1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2015 Nexenta Systems, Inc. All rights reserved. 25 * Copyright 2019 Joyent, Inc. 26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved. 27 * Copyright 2023 Racktop Systems, Inc. 28 */ 29 30 /* 31 * Copyright (c) 2000 to 2010, LSI Corporation. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms of all code within 35 * this file that is exclusively owned by LSI, with or without 36 * modification, is permitted provided that, in addition to the CDDL 1.0 37 * License requirements, the following conditions are met: 38 * 39 * Neither the name of the author nor the names of its contributors may be 40 * used to endorse or promote products derived from this software without 41 * specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 46 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 47 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 50 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 54 * DAMAGE. 55 */ 56 57 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 58 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 59 60 #include <sys/byteorder.h> 61 #include <sys/queue.h> 62 #include <sys/refhash.h> 63 #include <sys/isa_defs.h> 64 #include <sys/sunmdi.h> 65 #include <sys/mdi_impldefs.h> 66 #include <sys/ddi_ufm.h> 67 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 68 #include <sys/scsi/adapters/mpi/mpi2_tool.h> 69 #include <sys/scsi/adapters/mpi/mpi2_cnfg.h> 70 71 #ifdef __cplusplus 72 extern "C" { 73 #endif 74 75 /* 76 * Compile options 77 */ 78 #ifdef DEBUG 79 #define MPTSAS_DEBUG /* turn on debugging code */ 80 #endif /* DEBUG */ 81 82 #define MPTSAS_INITIAL_SOFT_SPACE 4 83 84 /* 85 * Note below macro definition and data type definition 86 * are used for phy mask handling, it should be changed 87 * simultaneously. 88 */ 89 #define MPTSAS_MAX_PHYS 24 90 typedef uint32_t mptsas_phymask_t; 91 92 #define MPTSAS_INVALID_DEVHDL 0xffff 93 #define MPTSAS_SATA_GUID "sata-guid" 94 95 /* 96 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP 97 * targets. There's no need to go overboard here, as the ordinary paths for 98 * I/O do not normally require hashed target lookups. These should be good 99 * enough and then some for any fabric within the hardware's capabilities. 100 */ 101 #define MPTSAS_SMP_BUCKET_COUNT 23 102 #define MPTSAS_TARGET_BUCKET_COUNT 97 103 #define MPTSAS_TMP_TARGET_BUCKET_COUNT 13 104 105 /* 106 * MPT HW defines 107 */ 108 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 109 #define MPTSAS_MAX_DISKS_IN_VOL 10 110 #define MPTSAS_MAX_HOTSPARES 2 111 #define MPTSAS_MAX_RAIDVOLS 2 112 #define MPTSAS_MAX_RAIDCONFIGS 5 113 114 /* 115 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 116 * plus two means the prefix 'w' and end of the string '\0'. 117 */ 118 #define MPTSAS_WWN_STRLEN (16 + 2) 119 #define MPTSAS_MAX_GUID_LEN 64 120 121 /* 122 * DMA routine flags 123 */ 124 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 125 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 126 #define MPTSAS_DMA_HANDLE_BOUND 0x8 127 128 /* 129 * If the HBA supports DMA or bus-mastering, you may have your own 130 * scatter-gather list for physically non-contiguous memory in one 131 * I/O operation; if so, there's probably a size for that list. 132 * It must be placed in the ddi_dma_lim_t structure, so that the system 133 * DMA-support routines can use it to break up the I/O request, so we 134 * define it here. 135 */ 136 #if defined(__sparc) 137 #define MPTSAS_MAX_DMA_SEGS 1 138 #define MPTSAS_MAX_CMD_SEGS 1 139 #else 140 #define MPTSAS_MAX_DMA_SEGS 256 141 #define MPTSAS_MAX_CMD_SEGS 257 142 #endif 143 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 144 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 145 146 #define MPTSAS_SGE_SIZE(mpt) \ 147 ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \ 148 sizeof (MPI2_SGE_SIMPLE64)) 149 150 /* 151 * Calculating how many 64-bit DMA simple elements can be stored in the first 152 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 153 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 154 * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words 155 * (16 bytes). 156 */ 157 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 158 ((mpt->m_req_frame_size - \ 159 sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \ 160 MPTSAS_SGE_SIZE(mpt)) 161 162 /* 163 * Scatter-gather list structure defined by HBA hardware 164 */ 165 typedef struct NcrTableIndirect { /* Table Indirect entries */ 166 uint32_t count; /* 24 bit count */ 167 union { 168 uint32_t address32; /* 32 bit address */ 169 struct { 170 uint32_t Low; 171 uint32_t High; 172 } address64; /* 64 bit address */ 173 } addr; 174 } mptti_t; 175 176 /* 177 * preferred pkt_private length in 64-bit quantities 178 */ 179 #ifdef _LP64 180 #define PKT_PRIV_SIZE 2 181 #define PKT_PRIV_LEN 16 /* in bytes */ 182 #else /* _ILP32 */ 183 #define PKT_PRIV_SIZE 1 184 #define PKT_PRIV_LEN 8 /* in bytes */ 185 #endif 186 187 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 188 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 189 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 190 191 /* 192 * get offset of item in structure 193 */ 194 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 195 196 /* 197 * WWID provided by LSI firmware is generated by firmware but the WWID is not 198 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 199 * address. According LSI's confirmation, the top nibble of RAID WWID is 200 * meanless, so the consensus between Solaris and OBP is to replace top nibble 201 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 202 * format unit address. 203 */ 204 #define MPTSAS_RAID_WWID(wwid) \ 205 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 206 207 typedef struct mptsas_target_addr { 208 uint64_t mta_wwn; 209 mptsas_phymask_t mta_phymask; 210 } mptsas_target_addr_t; 211 212 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd); 213 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t; 214 215 typedef struct mptsas_target { 216 mptsas_target_addr_t m_addr; 217 refhash_link_t m_link; 218 uint8_t m_dr_flag; 219 uint16_t m_devhdl; 220 uint32_t m_deviceinfo; 221 uint8_t m_phynum; 222 uint32_t m_dups; 223 mptsas_active_cmdq_t m_active_cmdq; 224 int32_t m_t_throttle; 225 int32_t m_t_ncmds; 226 int32_t m_reset_delay; 227 int32_t m_t_nwait; 228 229 uint16_t m_qfull_retry_interval; 230 uint8_t m_qfull_retries; 231 uint16_t m_io_flags; 232 uint16_t m_enclosure; 233 uint16_t m_slot_num; 234 uint32_t m_tgt_unconfigured; 235 } mptsas_target_t; 236 237 /* 238 * If you change this structure, be sure that mptsas_smp_target_copy() 239 * does the right thing. 240 */ 241 typedef struct mptsas_smp { 242 mptsas_target_addr_t m_addr; 243 refhash_link_t m_link; 244 uint16_t m_devhdl; 245 uint32_t m_deviceinfo; 246 uint16_t m_pdevhdl; 247 uint32_t m_pdevinfo; 248 } mptsas_smp_t; 249 250 /* 251 * This represents a single enclosure. Targets point to an enclosure through 252 * their m_enclosure member. 253 */ 254 typedef struct mptsas_enclosure { 255 list_node_t me_link; 256 uint16_t me_enchdl; 257 uint16_t me_flags; 258 uint16_t me_nslots; 259 uint16_t me_fslot; 260 uint8_t *me_slotleds; 261 } mptsas_enclosure_t; 262 263 typedef struct mptsas_cache_frames { 264 ddi_dma_handle_t m_dma_hdl; 265 ddi_acc_handle_t m_acc_hdl; 266 caddr_t m_frames_addr; 267 uint64_t m_phys_addr; 268 } mptsas_cache_frames_t; 269 270 typedef struct mptsas_cmd { 271 uint_t cmd_flags; /* flags from scsi_init_pkt */ 272 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 273 ddi_dma_cookie_t cmd_cookie; 274 uint_t cmd_cookiec; 275 uint_t cmd_winindex; 276 uint_t cmd_nwin; 277 uint_t cmd_cur_cookie; 278 off_t cmd_dma_offset; 279 size_t cmd_dma_len; 280 uint32_t cmd_totaldmacount; 281 caddr_t cmd_arq_buf; 282 283 int cmd_pkt_flags; 284 285 /* pending expiration time for command in active slot */ 286 hrtime_t cmd_active_expiration; 287 TAILQ_ENTRY(mptsas_cmd) cmd_active_link; 288 289 struct scsi_pkt *cmd_pkt; 290 struct scsi_arq_status cmd_scb; 291 uchar_t cmd_cdblen; /* length of cdb */ 292 uchar_t cmd_rqslen; /* len of requested rqsense */ 293 uchar_t cmd_privlen; 294 uint16_t cmd_extrqslen; /* len of extended rqsense */ 295 uint16_t cmd_extrqschunks; /* len in map chunks */ 296 uint16_t cmd_extrqsidx; /* Index into map */ 297 uint_t cmd_scblen; 298 uint32_t cmd_dmacount; 299 uint64_t cmd_dma_addr; 300 uchar_t cmd_age; 301 ushort_t cmd_qfull_retries; 302 uchar_t cmd_queued; /* true if queued */ 303 struct mptsas_cmd *cmd_linkp; 304 mptti_t *cmd_sg; /* Scatter/Gather structure */ 305 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 306 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 307 uint32_t cmd_slot; 308 uint32_t ioc_cmd_slot; 309 310 mptsas_cache_frames_t *cmd_extra_frames; 311 312 uint32_t cmd_rfm; 313 mptsas_target_t *cmd_tgt_addr; 314 } mptsas_cmd_t; 315 316 /* 317 * These are the defined cmd_flags for this structure. 318 */ 319 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 320 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 321 #define CFLAG_FINISHED 0x000004 /* command completed */ 322 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 323 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 324 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 325 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 326 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 327 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 328 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 329 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 330 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 331 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 332 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 333 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 334 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 335 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 336 #define CFLAG_FREE 0x010000 /* packet is on free list */ 337 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 338 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 339 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 340 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 341 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 342 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 343 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 344 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 345 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 346 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 347 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 348 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 349 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 350 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 351 352 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 353 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 354 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 355 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 356 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 357 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 358 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 359 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 360 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 361 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 362 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 363 364 #define MPTSAS_HASH_ARRAY_SIZE 16 365 /* 366 * hash table definition 367 */ 368 369 #define MPTSAS_HASH_FIRST 0xffff 370 #define MPTSAS_HASH_NEXT 0x0000 371 372 typedef struct mptsas_dma_alloc_state 373 { 374 ddi_dma_handle_t handle; 375 caddr_t memp; 376 size_t size; 377 ddi_acc_handle_t accessp; 378 ddi_dma_cookie_t cookie; 379 } mptsas_dma_alloc_state_t; 380 381 /* 382 * passthrough request structure 383 */ 384 typedef struct mptsas_pt_request { 385 uint8_t *request; 386 uint32_t request_size; 387 uint32_t data_size; 388 uint32_t dataout_size; 389 uint32_t direction; 390 uint8_t simple; 391 uint16_t sgl_offset; 392 ddi_dma_cookie_t data_cookie; 393 ddi_dma_cookie_t dataout_cookie; 394 } mptsas_pt_request_t; 395 396 /* 397 * config page request structure 398 */ 399 typedef struct mptsas_config_request { 400 uint32_t page_address; 401 uint8_t action; 402 uint8_t page_type; 403 uint8_t page_number; 404 uint8_t page_length; 405 uint8_t page_version; 406 uint8_t ext_page_type; 407 uint16_t ext_page_length; 408 } mptsas_config_request_t; 409 410 typedef struct mptsas_fw_diagnostic_buffer { 411 mptsas_dma_alloc_state_t buffer_data; 412 uint8_t extended_type; 413 uint8_t buffer_type; 414 uint8_t force_release; 415 uint32_t product_specific[23]; 416 uint8_t immediate; 417 uint8_t enabled; 418 uint8_t valid_data; 419 uint8_t owned_by_firmware; 420 uint32_t unique_id; 421 } mptsas_fw_diagnostic_buffer_t; 422 423 /* 424 * FW diag request structure 425 */ 426 typedef struct mptsas_diag_request { 427 mptsas_fw_diagnostic_buffer_t *pBuffer; 428 uint8_t function; 429 } mptsas_diag_request_t; 430 431 typedef struct mptsas_hash_node { 432 void *data; 433 struct mptsas_hash_node *next; 434 } mptsas_hash_node_t; 435 436 typedef struct mptsas_hash_table { 437 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 438 /* 439 * last position in traverse 440 */ 441 struct mptsas_hash_node *cur; 442 uint16_t line; 443 444 } mptsas_hash_table_t; 445 446 /* 447 * RAID volume information 448 */ 449 typedef struct mptsas_raidvol { 450 ushort_t m_israid; 451 uint16_t m_raidhandle; 452 uint64_t m_raidwwid; 453 uint8_t m_state; 454 uint32_t m_statusflags; 455 uint32_t m_settings; 456 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 457 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 458 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 459 uint64_t m_raidsize; 460 int m_raidlevel; 461 int m_ndisks; 462 mptsas_target_t *m_raidtgt; 463 } mptsas_raidvol_t; 464 465 /* 466 * RAID configurations 467 */ 468 typedef struct mptsas_raidconfig { 469 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 470 uint16_t m_physdisk_devhdl[ 471 MPTSAS_MAX_DISKS_IN_CONFIG]; 472 uint8_t m_native; 473 } m_raidconfig_t; 474 475 /* 476 * Track outstanding commands. The index into the m_slot array is the SMID 477 * (system message ID) of the outstanding command. SMID 0 is reserved by the 478 * software/firmware protocol and is never used for any command we generate; 479 * as such, the assertion m_slot[0] == NULL is universally true. The last 480 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for 481 * task management commands. No normal SCSI or ATA command will ever occupy 482 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any 483 * time that a consistent view of the target array is obtainable. 484 * 485 * As such, m_n_normal is the maximum number of slots available to ordinary 486 * commands, and the relationship: 487 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2 488 * always holds after initialisation. 489 */ 490 typedef struct mptsas_slots { 491 size_t m_size; /* size of struct, bytes */ 492 uint_t m_n_normal; /* see above */ 493 uint_t m_rotor; /* next slot idx to consider */ 494 mptsas_cmd_t *m_slot[1]; 495 } mptsas_slots_t; 496 497 /* 498 * Structure to hold command and packets for event ack 499 * and task management commands. 500 */ 501 typedef struct m_event_struct { 502 struct mptsas_cmd m_event_cmd; 503 struct m_event_struct *m_event_linkp; 504 /* 505 * event member record the failure event and eventcntx 506 * event member would be used in send ack pending process 507 */ 508 uint32_t m_event; 509 uint32_t m_eventcntx; 510 uint_t in_use; 511 struct scsi_pkt m_event_pkt; /* must be last */ 512 /* ... scsi_pkt_size() */ 513 } m_event_struct_t; 514 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 515 sizeof (struct scsi_pkt) + scsi_pkt_size()) 516 517 #define MAX_IOC_COMMANDS 8 518 519 /* 520 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 521 * A new event ack command requests mptsas_cmd and scsi_pkt structures 522 * from this pool, and returns it back when done. 523 */ 524 525 typedef struct m_replyh_arg { 526 void *mpt; 527 uint32_t rfm; 528 } m_replyh_arg_t; 529 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 530 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 531 532 /* 533 * Flags for DR handler topology change 534 */ 535 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 536 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 537 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 538 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 539 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 540 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 541 542 typedef struct mptsas_topo_change_list { 543 void *mpt; 544 uint_t event; 545 union { 546 uint8_t physport; 547 mptsas_phymask_t phymask; 548 } un; 549 uint16_t devhdl; 550 void *object; 551 uint8_t flags; 552 struct mptsas_topo_change_list *next; 553 } mptsas_topo_change_list_t; 554 555 556 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 557 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 558 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 559 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 560 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 561 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 562 563 /* 564 * Status types when calling mptsas_get_target_device_info 565 */ 566 #define DEV_INFO_SUCCESS 0x0 567 #define DEV_INFO_FAIL_PAGE0 0x1 568 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 569 #define DEV_INFO_PHYS_DISK 0x3 570 #define DEV_INFO_FAIL_ALLOC 0x4 571 #define DEV_INFO_FAIL_GUID 0x5 572 573 /* 574 * mpt hotplug event defines 575 */ 576 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 577 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 578 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 579 580 /* 581 * SMP target hotplug events 582 */ 583 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 584 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 585 #define MPTSAS_DR_EVENT_MASK 0x3F 586 587 /* 588 * mpt hotplug status definition for m_dr_flag 589 */ 590 591 /* 592 * MPTSAS_DR_INACTIVE 593 * 594 * The target is in a normal operating state. 595 * No dynamic reconfiguration operation is in progress. 596 */ 597 #define MPTSAS_DR_INACTIVE 0x0 598 /* 599 * MPTSAS_DR_INTRANSITION 600 * 601 * The target is in a transition mode since 602 * hotplug event happens and offline procedure has not 603 * been finished 604 */ 605 #define MPTSAS_DR_INTRANSITION 0x1 606 607 typedef struct mptsas_tgt_private { 608 int t_lun; 609 struct mptsas_target *t_private; 610 } mptsas_tgt_private_t; 611 612 /* 613 * The following defines are used in mptsas_set_init_mode to track the current 614 * state as we progress through reprogramming the HBA from target mode into 615 * initiator mode. 616 */ 617 618 #define IOUC_READ_PAGE0 0x00000100 619 #define IOUC_READ_PAGE1 0x00000200 620 #define IOUC_WRITE_PAGE1 0x00000400 621 #define IOUC_DONE 0x00000800 622 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 623 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 624 625 /* 626 * Last allocated slot is used for TM requests. Since only m_max_requests 627 * frames are allocated, the last SMID will be m_max_requests - 1. 628 */ 629 #define MPTSAS_SLOTS_SIZE(mpt) \ 630 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 631 mpt->m_max_requests)) 632 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 633 634 /* 635 * Macro for phy_flags 636 */ 637 638 typedef struct smhba_info { 639 kmutex_t phy_mutex; 640 uint8_t phy_id; 641 uint64_t sas_addr; 642 char path[8]; 643 uint16_t owner_devhdl; 644 uint16_t attached_devhdl; 645 uint8_t attached_phy_identify; 646 uint32_t attached_phy_info; 647 uint8_t programmed_link_rate; 648 uint8_t hw_link_rate; 649 uint8_t change_count; 650 uint32_t phy_info; 651 uint8_t negotiated_link_rate; 652 uint8_t port_num; 653 kstat_t *phy_stats; 654 uint32_t invalid_dword_count; 655 uint32_t running_disparity_error_count; 656 uint32_t loss_of_dword_sync_count; 657 uint32_t phy_reset_problem_count; 658 void *mpt; 659 } smhba_info_t; 660 661 typedef struct mptsas_phy_info { 662 uint8_t port_num; 663 uint8_t port_flags; 664 uint16_t ctrl_devhdl; 665 uint32_t phy_device_type; 666 uint16_t attached_devhdl; 667 mptsas_phymask_t phy_mask; 668 smhba_info_t smhba_info; 669 } mptsas_phy_info_t; 670 671 672 typedef struct mptsas_doneq_thread_arg { 673 void *mpt; 674 uint64_t t; 675 } mptsas_doneq_thread_arg_t; 676 677 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 678 typedef struct mptsas_doneq_thread_list { 679 mptsas_cmd_t *doneq; 680 mptsas_cmd_t **donetail; 681 kthread_t *threadp; 682 kcondvar_t cv; 683 ushort_t reserv1; 684 uint32_t reserv2; 685 kmutex_t mutex; 686 uint32_t flag; 687 uint32_t len; 688 mptsas_doneq_thread_arg_t arg; 689 } mptsas_doneq_thread_list_t; 690 691 typedef struct mptsas { 692 int m_instance; 693 694 struct mptsas *m_next; 695 696 scsi_hba_tran_t *m_tran; 697 smp_hba_tran_t *m_smptran; 698 kmutex_t m_mutex; 699 kmutex_t m_passthru_mutex; 700 kcondvar_t m_cv; 701 kcondvar_t m_passthru_cv; 702 kcondvar_t m_fw_cv; 703 kcondvar_t m_config_cv; 704 kcondvar_t m_fw_diag_cv; 705 dev_info_t *m_dip; 706 707 /* 708 * soft state flags 709 */ 710 uint_t m_softstate; 711 712 refhash_t *m_targets; 713 refhash_t *m_smp_targets; 714 list_t m_enclosures; 715 refhash_t *m_tmp_targets; 716 717 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 718 uint8_t m_num_raid_configs; 719 720 struct mptsas_slots *m_active; /* outstanding cmds */ 721 722 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 723 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 724 725 kmutex_t m_tx_waitq_mutex; 726 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */ 727 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */ 728 int m_tx_draining; /* TX queue draining flag */ 729 730 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 731 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 732 733 /* 734 * variables for helper threads (fan-out interrupts) 735 */ 736 mptsas_doneq_thread_list_t *m_doneq_thread_id; 737 uint32_t m_doneq_thread_n; 738 uint32_t m_doneq_thread_threshold; 739 uint32_t m_doneq_length_threshold; 740 uint32_t m_doneq_len; 741 kcondvar_t m_doneq_thread_cv; 742 kmutex_t m_doneq_mutex; 743 744 int m_ncmds; /* number of outstanding commands */ 745 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 746 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 747 748 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 749 750 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 751 752 ushort_t m_devid; /* device id of chip. */ 753 uchar_t m_revid; /* revision of chip. */ 754 uint16_t m_svid; /* subsystem Vendor ID of chip */ 755 uint16_t m_ssid; /* subsystem Device ID of chip */ 756 757 uchar_t m_sync_offset; /* default offset for this chip. */ 758 759 timeout_id_t m_quiesce_timeid; 760 761 ddi_dma_handle_t m_dma_req_frame_hdl; 762 ddi_acc_handle_t m_acc_req_frame_hdl; 763 ddi_dma_handle_t m_dma_req_sense_hdl; 764 ddi_acc_handle_t m_acc_req_sense_hdl; 765 ddi_dma_handle_t m_dma_reply_frame_hdl; 766 ddi_acc_handle_t m_acc_reply_frame_hdl; 767 ddi_dma_handle_t m_dma_free_queue_hdl; 768 ddi_acc_handle_t m_acc_free_queue_hdl; 769 ddi_dma_handle_t m_dma_post_queue_hdl; 770 ddi_acc_handle_t m_acc_post_queue_hdl; 771 772 /* 773 * list of reset notification requests 774 */ 775 struct scsi_reset_notify_entry *m_reset_notify_listf; 776 777 /* 778 * qfull handling 779 */ 780 timeout_id_t m_restart_cmd_timeid; 781 782 /* 783 * scsi reset delay per bus 784 */ 785 uint_t m_scsi_reset_delay; 786 787 int m_pm_idle_delay; 788 789 uchar_t m_polled_intr; /* intr was polled. */ 790 uchar_t m_suspended; /* true if driver is suspended */ 791 792 struct kmem_cache *m_kmem_cache; 793 struct kmem_cache *m_cache_frames; 794 795 /* 796 * hba options. 797 */ 798 uint_t m_options; 799 800 int m_in_callback; 801 802 int m_power_level; /* current power level */ 803 804 int m_busy; /* power management busy state */ 805 806 off_t m_pmcsr_offset; /* PMCSR offset */ 807 808 ddi_acc_handle_t m_config_handle; 809 810 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 811 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 812 ddi_device_acc_attr_t m_dev_acc_attr; 813 ddi_device_acc_attr_t m_reg_acc_attr; 814 815 /* 816 * request/reply variables 817 */ 818 caddr_t m_req_frame; 819 uint64_t m_req_frame_dma_addr; 820 caddr_t m_req_sense; 821 caddr_t m_extreq_sense; 822 uint_t m_extreq_sense_refcount; 823 kcondvar_t m_extreq_sense_refcount_cv; 824 uint64_t m_req_sense_dma_addr; 825 caddr_t m_reply_frame; 826 uint64_t m_reply_frame_dma_addr; 827 caddr_t m_free_queue; 828 uint64_t m_free_queue_dma_addr; 829 caddr_t m_post_queue; 830 uint64_t m_post_queue_dma_addr; 831 struct map *m_erqsense_map; 832 833 m_replyh_arg_t *m_replyh_args; 834 835 uint16_t m_max_requests; 836 uint16_t m_req_frame_size; 837 uint16_t m_req_sense_size; 838 839 /* 840 * Max frames per request reprted in IOC Facts 841 */ 842 uint8_t m_max_chain_depth; 843 /* 844 * Max frames per request which is used in reality. It's adjusted 845 * according DMA SG length attribute, and shall not exceed the 846 * m_max_chain_depth. 847 */ 848 uint8_t m_max_request_frames; 849 850 uint16_t m_free_queue_depth; 851 uint16_t m_post_queue_depth; 852 uint16_t m_max_replies; 853 uint32_t m_free_index; 854 uint32_t m_post_index; 855 uint8_t m_reply_frame_size; 856 uint32_t m_ioc_capabilities; 857 858 /* 859 * indicates if the firmware was upload by the driver 860 * at boot time 861 */ 862 ushort_t m_fwupload; 863 864 uint16_t m_productid; 865 866 /* 867 * per instance data structures for dma memory resources for 868 * MPI handshake protocol. only one handshake cmd can run at a time. 869 */ 870 ddi_dma_handle_t m_hshk_dma_hdl; 871 ddi_acc_handle_t m_hshk_acc_hdl; 872 caddr_t m_hshk_memp; 873 size_t m_hshk_dma_size; 874 875 /* Firmware version on the card at boot time */ 876 uint32_t m_fwversion; 877 878 /* MSI specific fields */ 879 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 880 int m_intr_type; /* What type of interrupt */ 881 int m_intr_cnt; /* # of intrs count returned */ 882 size_t m_intr_size; /* Size of intr array */ 883 uint_t m_intr_pri; /* Interrupt priority */ 884 int m_intr_cap; /* Interrupt capabilities */ 885 ddi_taskq_t *m_event_taskq; 886 887 /* SAS specific information */ 888 889 union { 890 uint64_t m_base_wwid; /* Base WWID */ 891 struct { 892 #ifdef _BIG_ENDIAN 893 uint32_t m_base_wwid_hi; 894 uint32_t m_base_wwid_lo; 895 #else 896 uint32_t m_base_wwid_lo; 897 uint32_t m_base_wwid_hi; 898 #endif 899 } sasaddr; 900 } un; 901 902 uint8_t m_num_phys; /* # of PHYs */ 903 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 904 uint8_t m_port_chng; /* initiator port changes */ 905 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 906 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 907 908 /* FMA Capabilities */ 909 int m_fm_capabilities; 910 ddi_taskq_t *m_dr_taskq; 911 int m_mpxio_enable; 912 uint8_t m_done_traverse_dev; 913 uint8_t m_done_traverse_smp; 914 uint8_t m_done_traverse_enc; 915 int m_diag_action_in_progress; 916 uint16_t m_dev_handle; 917 uint16_t m_smp_devhdl; 918 919 /* DDI UFM Handle */ 920 ddi_ufm_handle_t *m_ufmh; 921 922 /* 923 * Event recording 924 */ 925 uint8_t m_event_index; 926 uint32_t m_event_number; 927 uint32_t m_event_mask[4]; 928 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 929 930 /* 931 * FW diag Buffer List 932 */ 933 mptsas_fw_diagnostic_buffer_t 934 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 935 936 /* IOC type flags */ 937 uint8_t m_is_sea_ioc; 938 uint8_t m_is_gen35_ioc; 939 940 /* GEN3 support */ 941 uint8_t m_MPI25; 942 943 /* 944 * Event Replay flag (MUR support) 945 */ 946 uint8_t m_event_replay; 947 948 /* 949 * IR Capable flag 950 */ 951 uint8_t m_ir_capable; 952 953 /* 954 * Is HBA processing a diag reset? 955 */ 956 uint8_t m_in_reset; 957 958 /* 959 * index for the pci memory BAR 960 */ 961 uint8_t m_mem_bar; 962 963 /* 964 * per instance cmd data structures for task management cmds 965 */ 966 m_event_struct_t m_event_task_mgmt; /* must be last */ 967 /* ... scsi_pkt_size */ 968 } mptsas_t; 969 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 970 sizeof (struct scsi_pkt) + scsi_pkt_size()) 971 /* 972 * Only one of below two conditions is satisfied, we 973 * think the target is associated to the iport and 974 * allow call into mptsas_probe_lun(). 975 * 1. physicalsport == physport 976 * 2. (phymask & (1 << physport)) == 0 977 * The condition #2 is because LSI uses lowest PHY 978 * number as the value of physical port when auto port 979 * configuration. 980 */ 981 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 982 ((physicalport == physport) || (dynamicport && (phymask & \ 983 (1 << physport)))) 984 985 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 986 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 987 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 988 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 989 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 990 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 991 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 992 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 993 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 994 995 /* 996 * These should eventually migrate into the mpt header files 997 * that may become the /kernel/misc/mpt module... 998 */ 999 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 1000 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 1001 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 1002 mptsas_put_msg_Function(hdl, mp, Function); \ 1003 mptsas_put_msg_Lun(hdl, mp, Lun) 1004 1005 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 1006 ddi_put16(hdl, &(mp)->DevHandle, (val)) 1007 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 1008 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 1009 #define mptsas_put_msg_Function(hdl, mp, val) \ 1010 ddi_put8(hdl, &(mp)->Function, (val)) 1011 #define mptsas_put_msg_Lun(hdl, mp, val) \ 1012 ddi_put8(hdl, &(mp)->LUN[1], (val)) 1013 1014 #define mptsas_get_msg_Function(hdl, mp) \ 1015 ddi_get8(hdl, &(mp)->Function) 1016 1017 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 1018 ddi_get8(hdl, &(mp)->MsgFlags) 1019 1020 #define MPTSAS_ENABLE_DRWE(hdl) \ 1021 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1022 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 1023 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1024 MPI2_WRSEQ_1ST_KEY_VALUE); \ 1025 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1026 MPI2_WRSEQ_2ND_KEY_VALUE); \ 1027 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1028 MPI2_WRSEQ_3RD_KEY_VALUE); \ 1029 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1030 MPI2_WRSEQ_4TH_KEY_VALUE); \ 1031 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1032 MPI2_WRSEQ_5TH_KEY_VALUE); \ 1033 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1034 MPI2_WRSEQ_6TH_KEY_VALUE); 1035 1036 /* 1037 * m_options flags 1038 */ 1039 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 1040 1041 /* 1042 * m_softstate flags 1043 */ 1044 #define MPTSAS_SS_DRAINING 0x02 1045 #define MPTSAS_SS_QUIESCED 0x04 1046 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 1047 #define MPTSAS_DID_MSG_UNIT_RESET 0x10 1048 1049 /* 1050 * regspec defines. 1051 */ 1052 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 1053 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 1054 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 1055 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 1056 1057 /* 1058 * Handy constants 1059 */ 1060 #define FALSE 0 1061 #define TRUE 1 1062 #define UNDEFINED -1 1063 #define FAILED -2 1064 1065 /* 1066 * power management. 1067 */ 1068 #define MPTSAS_POWER_ON(mpt) { \ 1069 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1070 PCI_PMCSR_D0); \ 1071 delay(drv_usectohz(10000)); \ 1072 (void) pci_restore_config_regs(mpt->m_dip); \ 1073 mptsas_setup_cmd_reg(mpt); \ 1074 } 1075 1076 #define MPTSAS_POWER_OFF(mpt) { \ 1077 (void) pci_save_config_regs(mpt->m_dip); \ 1078 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1079 PCI_PMCSR_D3HOT); \ 1080 mpt->m_power_level = PM_LEVEL_D3; \ 1081 } 1082 1083 /* 1084 * inq_dtype: 1085 * Bits 5 through 7 are the Peripheral Device Qualifier 1086 * 001b: device not connected to the LUN 1087 * Bits 0 through 4 are the Peripheral Device Type 1088 * 1fh: Unknown or no device type 1089 * 1090 * Although the inquiry may return success, the following value 1091 * means no valid LUN connected. 1092 */ 1093 #define MPTSAS_VALID_LUN(sd_inq) \ 1094 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1095 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1096 1097 /* 1098 * Default is to have 10 retries on receiving QFULL status and 1099 * each retry to be after 100 ms. 1100 */ 1101 #define QFULL_RETRIES 10 1102 #define QFULL_RETRY_INTERVAL 100 1103 1104 /* 1105 * Handy macros 1106 */ 1107 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1108 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1109 1110 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1111 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1112 1113 /* 1114 * poll time for mptsas_pollret() and mptsas_wait_intr() 1115 */ 1116 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1117 1118 /* 1119 * default time for mptsas_do_passthru 1120 */ 1121 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1122 1123 /* 1124 * macro to return the effective address of a given per-target field 1125 */ 1126 #define EFF_ADDR(start, offset) ((start) + (offset)) 1127 1128 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1129 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1130 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1131 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1132 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1133 1134 1135 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1136 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1137 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1138 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1139 1140 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1141 1142 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1143 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1144 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1145 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1146 1147 #define MPTSAS_GET_ISTAT(mpt) (mptsas_hirrd((mpt), \ 1148 &(mpt)->m_reg->HostInterruptStatus)) 1149 1150 #define MPTSAS_SET_SIGP(P) \ 1151 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1152 1153 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1154 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1155 1156 #define MPTSAS_GET_INTCODE(P) (mptsas_hirrd(mpt, \ 1157 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1158 1159 1160 #define MPTSAS_START_CMD(mpt, req_desc) \ 1161 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow, \ 1162 req_desc & 0xffffffffu); \ 1163 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh, \ 1164 (req_desc >> 32) & 0xffffffffu); 1165 1166 #define INTPENDING(mpt) \ 1167 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1168 1169 /* 1170 * Mask all interrupts to disable 1171 */ 1172 #define MPTSAS_DISABLE_INTR(mpt) \ 1173 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1174 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1175 1176 /* 1177 * Mask Doorbell and Reset interrupts to enable reply desc int. 1178 */ 1179 #define MPTSAS_ENABLE_INTR(mpt) \ 1180 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1181 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1182 1183 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1184 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1185 1186 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1187 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1188 1189 #define ClrSetBits32(hdl, reg, clr, set) \ 1190 ddi_put32(hdl, (reg), \ 1191 ((mptsas_hirrd(mpt, (reg)) & ~(clr)) | (set))) 1192 1193 #define ClrSetBits(reg, clr, set) \ 1194 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1195 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1196 1197 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1198 if ((cmdp = mpt->m_waitq) != NULL) { \ 1199 /* If the queue is now empty fix the tail pointer */ \ 1200 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1201 mpt->m_waitqtail = &mpt->m_waitq; \ 1202 cmdp->cmd_linkp = NULL; \ 1203 cmdp->cmd_queued = FALSE; \ 1204 } 1205 1206 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1207 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1208 /* If the queue is now empty fix the tail pointer */ \ 1209 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1210 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1211 cmdp->cmd_linkp = NULL; \ 1212 cmdp->cmd_queued = FALSE; \ 1213 } 1214 1215 /* 1216 * defaults for the global properties 1217 */ 1218 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1219 #define DEFAULT_TAG_AGE_LIMIT 2 1220 #define DEFAULT_WD_TICK 1 1221 1222 /* 1223 * invalid hostid. 1224 */ 1225 #define MPTSAS_INVALID_HOSTID -1 1226 1227 /* 1228 * Get/Set hostid from SCSI port configuration page 1229 */ 1230 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1231 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1232 1233 /* 1234 * Config space. 1235 */ 1236 #define MPTSAS_LATENCY_TIMER 0x40 1237 1238 /* 1239 * Offset to firmware version 1240 */ 1241 #define MPTSAS_FW_VERSION_OFFSET 9 1242 1243 /* 1244 * Offset and masks to get at the ProductId field 1245 */ 1246 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1247 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1248 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1249 1250 /* 1251 * Subsystem ID for HBAs. 1252 */ 1253 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1254 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1255 1256 /* 1257 * reset delay tick 1258 */ 1259 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1260 1261 /* 1262 * Ioc reset return values 1263 */ 1264 #define MPTSAS_RESET_FAIL -1 1265 #define MPTSAS_NO_RESET 0 1266 #define MPTSAS_SUCCESS_HARDRESET 1 1267 #define MPTSAS_SUCCESS_MUR 2 1268 1269 /* 1270 * throttle support. 1271 */ 1272 #define MAX_THROTTLE 32 1273 #define HOLD_THROTTLE 0 1274 #define DRAIN_THROTTLE -1 1275 #define QFULL_THROTTLE -2 1276 1277 /* 1278 * Passthrough/config request flags 1279 */ 1280 #define MPTSAS_DATA_ALLOCATED 0x0001 1281 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1282 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1283 #define MPTSAS_ADDRESS_REPLY 0x0008 1284 #define MPTSAS_CMD_TIMEOUT 0x0010 1285 1286 /* 1287 * response code tlr flag 1288 */ 1289 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1290 1291 /* 1292 * System Events 1293 */ 1294 #ifndef DDI_VENDOR_LSI 1295 #define DDI_VENDOR_LSI "LSI" 1296 #endif /* DDI_VENDOR_LSI */ 1297 1298 /* 1299 * Shared functions 1300 */ 1301 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1302 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1303 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1304 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1305 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1306 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1307 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1308 uint8_t type, int mode); 1309 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1310 uint8_t type, int mode); 1311 int mptsas_download_firmware(); 1312 int mptsas_can_download_firmware(); 1313 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1314 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1315 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1316 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1317 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1318 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1319 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1320 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 1321 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 1322 uint32_t alloc_size, ddi_dma_cookie_t *cookiep); 1323 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *); 1324 uint32_t mptsas_hirrd(mptsas_t *mpt, uint32_t *regaddr); 1325 1326 /* 1327 * impl functions 1328 */ 1329 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1330 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1331 int mptsas_ioc_reset(mptsas_t *mpt, int); 1332 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1333 ddi_acc_handle_t accessp); 1334 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1335 ddi_acc_handle_t accessp); 1336 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1337 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1338 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1339 uint64_t SGEaddress); 1340 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1341 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1342 uint8_t pageversion, uint16_t extpagelength, 1343 uint32_t SGEflagslength, uint64_t SGEaddress); 1344 1345 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1346 struct scsi_pkt **pkt); 1347 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1348 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1349 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1350 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1351 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1352 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1353 1354 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1355 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1356 int mode); 1357 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1358 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1359 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1360 int mptsas_restart_ioc(mptsas_t *mpt); 1361 void mptsas_update_driver_data(struct mptsas *mpt); 1362 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1363 1364 /* 1365 * init functions 1366 */ 1367 int mptsas_ioc_get_facts(mptsas_t *mpt); 1368 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1369 int mptsas_ioc_enable_port(mptsas_t *mpt); 1370 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1371 int mptsas_ioc_init(mptsas_t *mpt); 1372 1373 /* 1374 * configuration pages operation 1375 */ 1376 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1377 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1378 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1379 uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags); 1380 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1381 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1382 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1383 mptsas_smp_t *info); 1384 int mptsas_set_ioc_params(mptsas_t *mpt); 1385 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1386 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1387 uint64_t *sas_wwn, uint8_t *portwidth); 1388 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1389 int mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1390 smhba_info_t *info); 1391 int mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1392 smhba_info_t *info); 1393 int mptsas_get_manufacture_page0(mptsas_t *mpt); 1394 int mptsas_get_enclosure_page0(mptsas_t *mpt, uint32_t page_address, 1395 mptsas_enclosure_t *mpe); 1396 void mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1397 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1398 int mptsas_smhba_phy_init(mptsas_t *mpt); 1399 /* 1400 * RAID functions 1401 */ 1402 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1403 int mptsas_get_raid_info(mptsas_t *mpt); 1404 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1405 uint8_t physdisknum); 1406 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1407 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1408 1409 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1410 /* 1411 * debugging. 1412 * MPTSAS_DBGLOG_LINECNT must be a power of 2. 1413 */ 1414 #define MPTSAS_DBGLOG_LINECNT 128 1415 #define MPTSAS_DBGLOG_LINELEN 256 1416 #define MPTSAS_DBGLOG_BUFSIZE (MPTSAS_DBGLOG_LINECNT * MPTSAS_DBGLOG_LINELEN) 1417 1418 #if defined(MPTSAS_DEBUG) 1419 1420 extern uint32_t mptsas_debugprt_flags; 1421 extern uint32_t mptsas_debuglog_flags; 1422 1423 void mptsas_printf(char *fmt, ...); 1424 void mptsas_debug_log(char *fmt, ...); 1425 1426 #define MPTSAS_DBGPR(m, args) \ 1427 if (mptsas_debugprt_flags & (m)) \ 1428 mptsas_printf args; \ 1429 if (mptsas_debuglog_flags & (m)) \ 1430 mptsas_debug_log args 1431 #else /* ! defined(MPTSAS_DEBUG) */ 1432 #define MPTSAS_DBGPR(m, args) 1433 #endif /* defined(MPTSAS_DEBUG) */ 1434 1435 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1436 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1437 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1438 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1439 1440 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1441 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1442 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1443 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1444 1445 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1446 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1447 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1448 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1449 1450 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1451 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1452 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1453 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */ 1454 1455 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */ 1456 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1457 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1458 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1459 1460 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1461 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1462 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1463 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1464 1465 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1466 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1467 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1468 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) /* passthrough */ 1469 1470 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1471 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1472 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1473 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1474 1475 /* 1476 * auto request sense 1477 */ 1478 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1479 (pkt)->pkt_flags = (flag), \ 1480 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1481 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1482 (pkt)->pkt_address.a_lun 1483 1484 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1485 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1486 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1487 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1488 1489 1490 #ifdef __cplusplus 1491 } 1492 #endif 1493 1494 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1495