1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2001 Scott Long <scottl@freebsd.org>
5 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Maestro-3/Allegro FreeBSD pcm sound driver
32 *
33 * executive status summary:
34 * (+) /dev/dsp multiple concurrent play channels.
35 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit).
36 * (+) /dev/mixer sets left/right volumes.
37 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel
38 * (+) apm suspend/resume works, and works properly!.
39 * (-) hardware volme controls don't work =-(
40 * (-) setblocksize() does nothing.
41 *
42 * The real credit goes to:
43 *
44 * Zach Brown for his Linux driver core and helpful technical comments.
45 * <zab@zabbo.net>, http://www.zabbo.net/maestro3
46 *
47 * Cameron Grant created the pcm framework used here nearly verbatim.
48 * <cg@freebsd.org>, https://people.freebsd.org/~cg/template.c
49 *
50 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference.
51 * <taku@cent.saitama-u.ac.jp>
52 *
53 * ESS docs explained a few magic registers and numbers.
54 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz
55 */
56
57 #ifdef HAVE_KERNEL_OPTION_HEADERS
58 #include "opt_snd.h"
59 #endif
60
61 #include <dev/sound/pcm/sound.h>
62 #include <dev/sound/pcm/ac97.h>
63
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66
67 #define M3_MODEL 1
68
69 #include <dev/sound/pci/allegro_reg.h>
70 #include <dev/sound/pci/allegro_code.h>
71
72 /* -------------------------------------------------------------------- */
73
74 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
75 #ifndef M3_DEBUG_LEVEL
76 #define M3_DEBUG_LEVEL NONE
77 #endif
78 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}}
79
80 /* -------------------------------------------------------------------- */
81 enum {
82 ESS_ALLEGRO_1,
83 ESS_MAESTRO3
84 };
85
86 static struct m3_card_type {
87 u_int32_t pci_id; int which; int delay1; int delay2; char *name;
88 } m3_card_types[] = {
89 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" },
90 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
91 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
92 { 0, 0, 0, 0, NULL }
93 };
94
95 #define M3_BUFSIZE_MIN 4096
96 #define M3_BUFSIZE_MAX 65536
97 #define M3_BUFSIZE_DEFAULT 4096
98 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
99 #define M3_RCHANS 1
100 #define M3_MAXADDR ((1 << 27) - 1)
101 #define M3_DEFAULT_VOL 0x6800
102
103 struct sc_info;
104
105 struct sc_pchinfo {
106 u_int32_t spd;
107 u_int32_t fmt;
108 struct snd_dbuf *buffer;
109 struct pcm_channel *channel;
110 struct sc_info *parent;
111 u_int32_t bufsize;
112 u_int32_t dac_data;
113 u_int32_t dac_idx;
114 u_int32_t active;
115 u_int32_t ptr;
116 u_int32_t prevptr;
117 };
118
119 struct sc_rchinfo {
120 u_int32_t spd;
121 u_int32_t fmt;
122 struct snd_dbuf *buffer;
123 struct pcm_channel *channel;
124 struct sc_info *parent;
125 u_int32_t bufsize;
126 u_int32_t adc_data;
127 u_int32_t adc_idx;
128 u_int32_t active;
129 u_int32_t ptr;
130 u_int32_t prevptr;
131 };
132
133 struct sc_info {
134 device_t dev;
135 u_int32_t type;
136 int which;
137 int delay1;
138 int delay2;
139
140 bus_space_tag_t st;
141 bus_space_handle_t sh;
142 bus_dma_tag_t parent_dmat;
143
144 struct resource *reg;
145 struct resource *irq;
146 int regtype;
147 int regid;
148 int irqid;
149 void *ih;
150
151 struct sc_pchinfo pch[M3_PCHANS];
152 struct sc_rchinfo rch[M3_RCHANS];
153 int pch_cnt;
154 int rch_cnt;
155 int pch_active_cnt;
156 unsigned int bufsz;
157 u_int16_t *savemem;
158
159 struct mtx *sc_lock;
160 };
161
162 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock)
163 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock)
164 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock)
165
166 /* -------------------------------------------------------------------- */
167
168 /* play channel interface */
169 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
170 static int m3_pchan_free(kobj_t, void *);
171 static int m3_pchan_setformat(kobj_t, void *, u_int32_t);
172 static u_int32_t m3_pchan_setspeed(kobj_t, void *, u_int32_t);
173 static u_int32_t m3_pchan_setblocksize(kobj_t, void *, u_int32_t);
174 static int m3_pchan_trigger(kobj_t, void *, int);
175 static int m3_pchan_trigger_locked(kobj_t, void *, int);
176 static u_int32_t m3_pchan_getptr_internal(struct sc_pchinfo *);
177 static u_int32_t m3_pchan_getptr(kobj_t, void *);
178 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *);
179
180 /* record channel interface */
181 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
182 static int m3_rchan_free(kobj_t, void *);
183 static int m3_rchan_setformat(kobj_t, void *, u_int32_t);
184 static u_int32_t m3_rchan_setspeed(kobj_t, void *, u_int32_t);
185 static u_int32_t m3_rchan_setblocksize(kobj_t, void *, u_int32_t);
186 static int m3_rchan_trigger(kobj_t, void *, int);
187 static int m3_rchan_trigger_locked(kobj_t, void *, int);
188 static u_int32_t m3_rchan_getptr_internal(struct sc_rchinfo *);
189 static u_int32_t m3_rchan_getptr(kobj_t, void *);
190 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *);
191
192 static int m3_chan_active(struct sc_info *);
193
194 /* talk to the codec - called from ac97.c */
195 static u_int32_t m3_initcd(kobj_t, void *);
196 static int m3_rdcd(kobj_t, void *, int);
197 static int m3_wrcd(kobj_t, void *, int, u_int32_t);
198
199 /* stuff */
200 static void m3_intr(void *);
201 static int m3_power(struct sc_info *, int);
202 static int m3_init(struct sc_info *);
203 static int m3_uninit(struct sc_info *);
204 static u_int8_t m3_assp_halt(struct sc_info *);
205 static void m3_config(struct sc_info *);
206 static void m3_amp_enable(struct sc_info *);
207 static void m3_enable_ints(struct sc_info *);
208 static void m3_codec_reset(struct sc_info *);
209
210 /* -------------------------------------------------------------------- */
211 /* Codec descriptor */
212 static kobj_method_t m3_codec_methods[] = {
213 KOBJMETHOD(ac97_init, m3_initcd),
214 KOBJMETHOD(ac97_read, m3_rdcd),
215 KOBJMETHOD(ac97_write, m3_wrcd),
216 KOBJMETHOD_END
217 };
218 AC97_DECLARE(m3_codec);
219
220 /* -------------------------------------------------------------------- */
221 /* channel descriptors */
222
223 static u_int32_t m3_playfmt[] = {
224 SND_FORMAT(AFMT_U8, 1, 0),
225 SND_FORMAT(AFMT_U8, 2, 0),
226 SND_FORMAT(AFMT_S16_LE, 1, 0),
227 SND_FORMAT(AFMT_S16_LE, 2, 0),
228 0
229 };
230 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0};
231
232 static kobj_method_t m3_pch_methods[] = {
233 KOBJMETHOD(channel_init, m3_pchan_init),
234 KOBJMETHOD(channel_setformat, m3_pchan_setformat),
235 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed),
236 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize),
237 KOBJMETHOD(channel_trigger, m3_pchan_trigger),
238 KOBJMETHOD(channel_getptr, m3_pchan_getptr),
239 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps),
240 KOBJMETHOD(channel_free, m3_pchan_free),
241 KOBJMETHOD_END
242 };
243 CHANNEL_DECLARE(m3_pch);
244
245 static u_int32_t m3_recfmt[] = {
246 SND_FORMAT(AFMT_U8, 1, 0),
247 SND_FORMAT(AFMT_U8, 2, 0),
248 SND_FORMAT(AFMT_S16_LE, 1, 0),
249 SND_FORMAT(AFMT_S16_LE, 2, 0),
250 0
251 };
252 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0};
253
254 static kobj_method_t m3_rch_methods[] = {
255 KOBJMETHOD(channel_init, m3_rchan_init),
256 KOBJMETHOD(channel_setformat, m3_rchan_setformat),
257 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed),
258 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize),
259 KOBJMETHOD(channel_trigger, m3_rchan_trigger),
260 KOBJMETHOD(channel_getptr, m3_rchan_getptr),
261 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps),
262 KOBJMETHOD(channel_free, m3_rchan_free),
263 KOBJMETHOD_END
264 };
265 CHANNEL_DECLARE(m3_rch);
266
267 /* -------------------------------------------------------------------- */
268 /* some i/o convenience functions */
269
270 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno)
271 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno)
272 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno)
273 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data)
274 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data)
275 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data)
276 #define m3_rd_assp_code(sc, index) \
277 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index)
278 #define m3_wr_assp_code(sc, index, data) \
279 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data)
280 #define m3_rd_assp_data(sc, index) \
281 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index)
282 #define m3_wr_assp_data(sc, index, data) \
283 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data)
284
285 static __inline u_int16_t
m3_rd_assp(struct sc_info * sc,u_int16_t region,u_int16_t index)286 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index)
287 {
288 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
289 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
290 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA);
291 }
292
293 static __inline void
m3_wr_assp(struct sc_info * sc,u_int16_t region,u_int16_t index,u_int16_t data)294 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index,
295 u_int16_t data)
296 {
297 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
298 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
299 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data);
300 }
301
302 static __inline int
m3_wait(struct sc_info * sc)303 m3_wait(struct sc_info *sc)
304 {
305 int i;
306
307 for (i=0 ; i<20 ; i++) {
308 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) {
309 return 0;
310 }
311 DELAY(2);
312 }
313 return -1;
314 }
315
316 /* -------------------------------------------------------------------- */
317 /* ac97 codec */
318
319 static u_int32_t
m3_initcd(kobj_t kobj,void * devinfo)320 m3_initcd(kobj_t kobj, void *devinfo)
321 {
322 struct sc_info *sc = (struct sc_info *)devinfo;
323 u_int32_t data;
324
325 M3_DEBUG(CALL, ("m3_initcd\n"));
326
327 /* init ac-link */
328
329 data = m3_rd_1(sc, CODEC_COMMAND);
330 return ((data & 0x1) ? 0 : 1);
331 }
332
333 static int
m3_rdcd(kobj_t kobj,void * devinfo,int regno)334 m3_rdcd(kobj_t kobj, void *devinfo, int regno)
335 {
336 struct sc_info *sc = (struct sc_info *)devinfo;
337 u_int32_t data;
338
339 if (m3_wait(sc)) {
340 device_printf(sc->dev, "m3_rdcd timed out.\n");
341 return -1;
342 }
343 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80);
344 DELAY(50); /* ac97 cycle = 20.8 usec */
345 if (m3_wait(sc)) {
346 device_printf(sc->dev, "m3_rdcd timed out.\n");
347 return -1;
348 }
349 data = m3_rd_2(sc, CODEC_DATA);
350 return data;
351 }
352
353 static int
m3_wrcd(kobj_t kobj,void * devinfo,int regno,u_int32_t data)354 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data)
355 {
356 struct sc_info *sc = (struct sc_info *)devinfo;
357 if (m3_wait(sc)) {
358 device_printf(sc->dev, "m3_wrcd timed out.\n");
359 return -1;
360 }
361 m3_wr_2(sc, CODEC_DATA, data);
362 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f);
363 DELAY(50); /* ac97 cycle = 20.8 usec */
364 return 0;
365 }
366
367 /* -------------------------------------------------------------------- */
368 /* play channel interface */
369
370 #define LO(x) (((x) & 0x0000ffff) )
371 #define HI(x) (((x) & 0xffff0000) >> 16)
372
373 static void *
m3_pchan_init(kobj_t kobj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)374 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
375 {
376 struct sc_info *sc = devinfo;
377 struct sc_pchinfo *ch;
378 u_int32_t bus_addr, i;
379 int idx, data_bytes, dac_data;
380 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
381
382 struct data_word {
383 u_int16_t addr, val;
384 } pv[] = {
385 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL},
386 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL},
387 {SRC3_DIRECTION_OFFSET, 0} ,
388 {SRC3_DIRECTION_OFFSET + 3, 0x0000},
389 {SRC3_DIRECTION_OFFSET + 4, 0},
390 {SRC3_DIRECTION_OFFSET + 5, 0},
391 {SRC3_DIRECTION_OFFSET + 6, 0},
392 {SRC3_DIRECTION_OFFSET + 7, 0},
393 {SRC3_DIRECTION_OFFSET + 8, 0},
394 {SRC3_DIRECTION_OFFSET + 9, 0},
395 {SRC3_DIRECTION_OFFSET + 10, 0x8000},
396 {SRC3_DIRECTION_OFFSET + 11, 0xFF00},
397 {SRC3_DIRECTION_OFFSET + 13, 0},
398 {SRC3_DIRECTION_OFFSET + 14, 0},
399 {SRC3_DIRECTION_OFFSET + 15, 0},
400 {SRC3_DIRECTION_OFFSET + 16, 8},
401 {SRC3_DIRECTION_OFFSET + 17, 50*2},
402 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1},
403 {SRC3_DIRECTION_OFFSET + 20, 0},
404 {SRC3_DIRECTION_OFFSET + 21, 0}
405 };
406
407 M3_LOCK(sc);
408 idx = sc->pch_cnt; /* dac instance number, no active reuse! */
409 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx));
410
411 if (dir != PCMDIR_PLAY) {
412 M3_UNLOCK(sc);
413 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
414 return (NULL);
415 }
416
417 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
418 (MINISRC_IN_BUFFER_SIZE & ~1) +
419 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
420 dac_data = 0x1100 + (data_bytes * idx);
421
422 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
423 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
424 dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2);
425 dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1;
426
427 ch = &sc->pch[idx];
428 ch->dac_idx = idx;
429 ch->dac_data = dac_data;
430 if (ch->dac_data + data_bytes/2 >= 0x1c00) {
431 M3_UNLOCK(sc);
432 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n");
433 return (NULL);
434 }
435
436 ch->buffer = b;
437 ch->parent = sc;
438 ch->channel = c;
439 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
440 ch->spd = DSP_DEFAULT_SPEED;
441 M3_UNLOCK(sc); /* XXX */
442 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
443 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n");
444 return (NULL);
445 }
446 M3_LOCK(sc);
447 ch->bufsize = sndbuf_getsize(ch->buffer);
448
449 /* host dma buffer pointers */
450 bus_addr = sndbuf_getbufaddr(ch->buffer);
451 if (bus_addr & 3) {
452 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n");
453 bus_addr = (bus_addr + 4) & ~3;
454 }
455 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
456 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
457 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L,
458 LO(bus_addr + ch->bufsize));
459 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H,
460 HI(bus_addr + ch->bufsize));
461 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL,
462 LO(bus_addr));
463 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH,
464 HI(bus_addr));
465
466 /* dsp buffers */
467 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
468 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1,
469 dsp_in_buf + dsp_in_size/2);
470 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
471 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
472 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
473 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1,
474 dsp_out_buf + dsp_out_size/2);
475 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
476 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
477
478 /* some per client initializers */
479 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12,
480 ch->dac_data + 40 + 8);
481 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19,
482 0x400 + MINISRC_COEF_LOC);
483 /* enable or disable low pass filter? (0xff if rate> 45000) */
484 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0);
485 /* tell it which way dma is going? */
486 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL,
487 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR +
488 DMAC_BLOCKF_SELECTOR);
489
490 /* set an armload of static initializers */
491 for(i = 0 ; i < nitems(pv); i++) {
492 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val);
493 }
494
495 /* put us in the packed task lists */
496 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
497 (sc->pch_cnt + sc->rch_cnt),
498 ch->dac_data >> DP_SHIFT_COUNT);
499 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
500 ch->dac_data >> DP_SHIFT_COUNT);
501 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt,
502 ch->dac_data >> DP_SHIFT_COUNT);
503
504 /* gotta start before stop */
505 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_START);
506 /* silence noise on load */
507 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
508
509 sc->pch_cnt++;
510 M3_UNLOCK(sc);
511
512 return (ch);
513 }
514
515 static int
m3_pchan_free(kobj_t kobj,void * chdata)516 m3_pchan_free(kobj_t kobj, void *chdata)
517 {
518 struct sc_pchinfo *ch = chdata;
519 struct sc_info *sc = ch->parent;
520
521 M3_LOCK(sc);
522 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx));
523
524 /*
525 * should remove this exact instance from the packed lists, but all
526 * are released at once (and in a stopped state) so this is ok.
527 */
528 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
529 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
530 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
531 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
532 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0);
533 sc->pch_cnt--;
534 M3_UNLOCK(sc);
535
536 return (0);
537 }
538
539 static int
m3_pchan_setformat(kobj_t kobj,void * chdata,u_int32_t format)540 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
541 {
542 struct sc_pchinfo *ch = chdata;
543 struct sc_info *sc = ch->parent;
544 u_int32_t data;
545
546 M3_LOCK(sc);
547 M3_DEBUG(CHANGE,
548 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
549 ch->dac_idx, format,
550 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
551 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO"));
552
553 /* mono word */
554 data = (AFMT_CHANNEL(format) > 1)? 0 : 1;
555 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data);
556
557 /* 8bit word */
558 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
559 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data);
560
561 ch->fmt = format;
562 M3_UNLOCK(sc);
563
564 return (0);
565 }
566
567 static u_int32_t
m3_pchan_setspeed(kobj_t kobj,void * chdata,u_int32_t speed)568 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
569 {
570 struct sc_pchinfo *ch = chdata;
571 struct sc_info *sc = ch->parent;
572 u_int32_t freq;
573
574 M3_LOCK(sc);
575 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n",
576 ch->dac_idx, speed));
577
578 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
579 freq--;
580 }
581
582 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq);
583 ch->spd = speed;
584 M3_UNLOCK(sc);
585
586 /* return closest possible speed */
587 return (speed);
588 }
589
590 static u_int32_t
m3_pchan_setblocksize(kobj_t kobj,void * chdata,u_int32_t blocksize)591 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
592 {
593 struct sc_pchinfo *ch = chdata;
594
595 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n",
596 ch->dac_idx, blocksize));
597
598 return (sndbuf_getblksz(ch->buffer));
599 }
600
601 static int
m3_pchan_trigger(kobj_t kobj,void * chdata,int go)602 m3_pchan_trigger(kobj_t kobj, void *chdata, int go)
603 {
604 struct sc_pchinfo *ch = chdata;
605 struct sc_info *sc = ch->parent;
606 int ret;
607
608 if (!PCMTRIG_COMMON(go))
609 return (0);
610
611 M3_LOCK(sc);
612 ret = m3_pchan_trigger_locked(kobj, chdata, go);
613 M3_UNLOCK(sc);
614
615 return (ret);
616 }
617
618 static int
m3_chan_active(struct sc_info * sc)619 m3_chan_active(struct sc_info *sc)
620 {
621 int i, ret;
622
623 ret = 0;
624
625 for (i = 0; i < sc->pch_cnt; i++)
626 ret += sc->pch[i].active;
627
628 for (i = 0; i < sc->rch_cnt; i++)
629 ret += sc->rch[i].active;
630
631 return (ret);
632 }
633
634 static int
m3_pchan_trigger_locked(kobj_t kobj,void * chdata,int go)635 m3_pchan_trigger_locked(kobj_t kobj, void *chdata, int go)
636 {
637 struct sc_pchinfo *ch = chdata;
638 struct sc_info *sc = ch->parent;
639 u_int32_t data;
640
641 M3_LOCK_ASSERT(sc);
642 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
643 go == PCMTRIG_STOP ? CHANGE :
644 go == PCMTRIG_ABORT ? CHANGE :
645 CALL,
646 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go,
647 go == PCMTRIG_START ? "PCMTRIG_START" :
648 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
649 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
650
651 switch(go) {
652 case PCMTRIG_START:
653 if (ch->active) {
654 return 0;
655 }
656 ch->active = 1;
657 ch->ptr = 0;
658 ch->prevptr = 0;
659 sc->pch_active_cnt++;
660
661 /*[[inc_timer_users]]*/
662 if (m3_chan_active(sc) == 1) {
663 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
664 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
665 data = m3_rd_2(sc, HOST_INT_CTRL);
666 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
667 }
668
669 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1);
670 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
671 sc->pch_active_cnt);
672 break;
673
674 case PCMTRIG_STOP:
675 case PCMTRIG_ABORT:
676 if (ch->active == 0) {
677 return 0;
678 }
679 ch->active = 0;
680 sc->pch_active_cnt--;
681
682 /* XXX should the channel be drained? */
683 /*[[dec_timer_users]]*/
684 if (m3_chan_active(sc) == 0) {
685 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
686 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
687 data = m3_rd_2(sc, HOST_INT_CTRL);
688 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
689 }
690
691 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0);
692 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
693 sc->pch_active_cnt);
694 break;
695
696 case PCMTRIG_EMLDMAWR:
697 /* got play irq, transfer next buffer - ignore if using dma */
698 case PCMTRIG_EMLDMARD:
699 /* got rec irq, transfer next buffer - ignore if using dma */
700 default:
701 break;
702 }
703 return 0;
704 }
705
706 static u_int32_t
m3_pchan_getptr_internal(struct sc_pchinfo * ch)707 m3_pchan_getptr_internal(struct sc_pchinfo *ch)
708 {
709 struct sc_info *sc = ch->parent;
710 u_int32_t hi, lo, bus_base, bus_crnt;
711
712 bus_base = sndbuf_getbufaddr(ch->buffer);
713 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH);
714 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL);
715 bus_crnt = lo | (hi << 16);
716
717 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n",
718 ch->dac_idx, bus_crnt - bus_base));
719
720 return (bus_crnt - bus_base); /* current byte offset of channel */
721 }
722
723 static u_int32_t
m3_pchan_getptr(kobj_t kobj,void * chdata)724 m3_pchan_getptr(kobj_t kobj, void *chdata)
725 {
726 struct sc_pchinfo *ch = chdata;
727 struct sc_info *sc = ch->parent;
728 u_int32_t ptr;
729
730 M3_LOCK(sc);
731 ptr = ch->ptr;
732 M3_UNLOCK(sc);
733
734 return (ptr);
735 }
736
737 static struct pcmchan_caps *
m3_pchan_getcaps(kobj_t kobj,void * chdata)738 m3_pchan_getcaps(kobj_t kobj, void *chdata)
739 {
740 struct sc_pchinfo *ch = chdata;
741
742 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx));
743
744 return &m3_playcaps;
745 }
746
747 /* -------------------------------------------------------------------- */
748 /* rec channel interface */
749
750 static void *
m3_rchan_init(kobj_t kobj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)751 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
752 {
753 struct sc_info *sc = devinfo;
754 struct sc_rchinfo *ch;
755 u_int32_t bus_addr, i;
756
757 int idx, data_bytes, adc_data;
758 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
759
760 struct data_word {
761 u_int16_t addr, val;
762 } rv[] = {
763 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL},
764 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL},
765 {SRC3_DIRECTION_OFFSET, 1},
766 {SRC3_DIRECTION_OFFSET + 3, 0x0000},
767 {SRC3_DIRECTION_OFFSET + 4, 0},
768 {SRC3_DIRECTION_OFFSET + 5, 0},
769 {SRC3_DIRECTION_OFFSET + 6, 0},
770 {SRC3_DIRECTION_OFFSET + 7, 0},
771 {SRC3_DIRECTION_OFFSET + 8, 0},
772 {SRC3_DIRECTION_OFFSET + 9, 0},
773 {SRC3_DIRECTION_OFFSET + 10, 0x8000},
774 {SRC3_DIRECTION_OFFSET + 11, 0xFF00},
775 {SRC3_DIRECTION_OFFSET + 13, 0},
776 {SRC3_DIRECTION_OFFSET + 14, 0},
777 {SRC3_DIRECTION_OFFSET + 15, 0},
778 {SRC3_DIRECTION_OFFSET + 16, 50},
779 {SRC3_DIRECTION_OFFSET + 17, 8},
780 {SRC3_DIRECTION_OFFSET + 18, 0},
781 {SRC3_DIRECTION_OFFSET + 19, 0},
782 {SRC3_DIRECTION_OFFSET + 20, 0},
783 {SRC3_DIRECTION_OFFSET + 21, 0},
784 {SRC3_DIRECTION_OFFSET + 22, 0xff}
785 };
786
787 M3_LOCK(sc);
788 idx = sc->rch_cnt; /* adc instance number, no active reuse! */
789 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx));
790
791 if (dir != PCMDIR_REC) {
792 M3_UNLOCK(sc);
793 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
794 return (NULL);
795 }
796
797 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
798 (MINISRC_IN_BUFFER_SIZE & ~1) +
799 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
800 adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2;
801 dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
802 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
803 dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2);
804 dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1;
805
806 ch = &sc->rch[idx];
807 ch->adc_idx = idx;
808 ch->adc_data = adc_data;
809 if (ch->adc_data + data_bytes/2 >= 0x1c00) {
810 M3_UNLOCK(sc);
811 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n");
812 return (NULL);
813 }
814
815 ch->buffer = b;
816 ch->parent = sc;
817 ch->channel = c;
818 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
819 ch->spd = DSP_DEFAULT_SPEED;
820 M3_UNLOCK(sc); /* XXX */
821 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
822 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n");
823 return (NULL);
824 }
825 M3_LOCK(sc);
826 ch->bufsize = sndbuf_getsize(ch->buffer);
827
828 /* host dma buffer pointers */
829 bus_addr = sndbuf_getbufaddr(ch->buffer);
830 if (bus_addr & 3) {
831 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n");
832 bus_addr = (bus_addr + 4) & ~3;
833 }
834 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
835 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
836 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L,
837 LO(bus_addr + ch->bufsize));
838 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H,
839 HI(bus_addr + ch->bufsize));
840 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL,
841 LO(bus_addr));
842 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH,
843 HI(bus_addr));
844
845 /* dsp buffers */
846 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
847 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1,
848 dsp_in_buf + dsp_in_size/2);
849 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
850 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
851 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
852 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1,
853 dsp_out_buf + dsp_out_size/2);
854 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
855 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
856
857 /* some per client initializers */
858 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12,
859 ch->adc_data + 40 + 8);
860 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL,
861 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
862 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
863
864 /* set an armload of static initializers */
865 for(i = 0 ; i < nitems(rv); i++) {
866 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val);
867 }
868
869 /* put us in the packed task lists */
870 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
871 (sc->pch_cnt + sc->rch_cnt),
872 ch->adc_data >> DP_SHIFT_COUNT);
873 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
874 ch->adc_data >> DP_SHIFT_COUNT);
875 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt,
876 ch->adc_data >> DP_SHIFT_COUNT);
877
878 /* gotta start before stop */
879 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_START);
880 /* stop on init */
881 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
882
883 sc->rch_cnt++;
884 M3_UNLOCK(sc);
885
886 return (ch);
887 }
888
889 static int
m3_rchan_free(kobj_t kobj,void * chdata)890 m3_rchan_free(kobj_t kobj, void *chdata)
891 {
892 struct sc_rchinfo *ch = chdata;
893 struct sc_info *sc = ch->parent;
894
895 M3_LOCK(sc);
896 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx));
897
898 /*
899 * should remove this exact instance from the packed lists, but all
900 * are released at once (and in a stopped state) so this is ok.
901 */
902 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
903 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
904 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
905 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
906 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0);
907 sc->rch_cnt--;
908 M3_UNLOCK(sc);
909
910 return (0);
911 }
912
913 static int
m3_rchan_setformat(kobj_t kobj,void * chdata,u_int32_t format)914 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
915 {
916 struct sc_rchinfo *ch = chdata;
917 struct sc_info *sc = ch->parent;
918 u_int32_t data;
919
920 M3_LOCK(sc);
921 M3_DEBUG(CHANGE,
922 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
923 ch->adc_idx, format,
924 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
925 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO"));
926
927 /* mono word */
928 data = (AFMT_CHANNEL(format) > 1) ? 0 : 1;
929 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data);
930
931 /* 8bit word */
932 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
933 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data);
934 ch->fmt = format;
935 M3_UNLOCK(sc);
936
937 return (0);
938 }
939
940 static u_int32_t
m3_rchan_setspeed(kobj_t kobj,void * chdata,u_int32_t speed)941 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
942 {
943 struct sc_rchinfo *ch = chdata;
944 struct sc_info *sc = ch->parent;
945 u_int32_t freq;
946
947 M3_LOCK(sc);
948 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n",
949 ch->adc_idx, speed));
950
951 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
952 freq--;
953 }
954
955 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq);
956 ch->spd = speed;
957 M3_UNLOCK(sc);
958
959 /* return closest possible speed */
960 return (speed);
961 }
962
963 static u_int32_t
m3_rchan_setblocksize(kobj_t kobj,void * chdata,u_int32_t blocksize)964 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
965 {
966 struct sc_rchinfo *ch = chdata;
967
968 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n",
969 ch->adc_idx, blocksize));
970
971 return (sndbuf_getblksz(ch->buffer));
972 }
973
974 static int
m3_rchan_trigger(kobj_t kobj,void * chdata,int go)975 m3_rchan_trigger(kobj_t kobj, void *chdata, int go)
976 {
977 struct sc_rchinfo *ch = chdata;
978 struct sc_info *sc = ch->parent;
979 int ret;
980
981 if (!PCMTRIG_COMMON(go))
982 return (0);
983
984 M3_LOCK(sc);
985 ret = m3_rchan_trigger_locked(kobj, chdata, go);
986 M3_UNLOCK(sc);
987
988 return (ret);
989 }
990
991 static int
m3_rchan_trigger_locked(kobj_t kobj,void * chdata,int go)992 m3_rchan_trigger_locked(kobj_t kobj, void *chdata, int go)
993 {
994 struct sc_rchinfo *ch = chdata;
995 struct sc_info *sc = ch->parent;
996 u_int32_t data;
997
998 M3_LOCK_ASSERT(sc);
999 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
1000 go == PCMTRIG_STOP ? CHANGE :
1001 go == PCMTRIG_ABORT ? CHANGE :
1002 CALL,
1003 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go,
1004 go == PCMTRIG_START ? "PCMTRIG_START" :
1005 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
1006 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
1007
1008 switch(go) {
1009 case PCMTRIG_START:
1010 if (ch->active) {
1011 return 0;
1012 }
1013 ch->active = 1;
1014 ch->ptr = 0;
1015 ch->prevptr = 0;
1016
1017 /*[[inc_timer_users]]*/
1018 if (m3_chan_active(sc) == 1) {
1019 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
1020 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
1021 data = m3_rd_2(sc, HOST_INT_CTRL);
1022 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
1023 }
1024
1025 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1);
1026 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1);
1027 break;
1028
1029 case PCMTRIG_STOP:
1030 case PCMTRIG_ABORT:
1031 if (ch->active == 0) {
1032 return 0;
1033 }
1034 ch->active = 0;
1035
1036 /*[[dec_timer_users]]*/
1037 if (m3_chan_active(sc) == 0) {
1038 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
1039 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
1040 data = m3_rd_2(sc, HOST_INT_CTRL);
1041 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
1042 }
1043
1044 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0);
1045 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0);
1046 break;
1047
1048 case PCMTRIG_EMLDMAWR:
1049 /* got play irq, transfer next buffer - ignore if using dma */
1050 case PCMTRIG_EMLDMARD:
1051 /* got rec irq, transfer next buffer - ignore if using dma */
1052 default:
1053 break;
1054 }
1055 return 0;
1056 }
1057
1058 static u_int32_t
m3_rchan_getptr_internal(struct sc_rchinfo * ch)1059 m3_rchan_getptr_internal(struct sc_rchinfo *ch)
1060 {
1061 struct sc_info *sc = ch->parent;
1062 u_int32_t hi, lo, bus_base, bus_crnt;
1063
1064 bus_base = sndbuf_getbufaddr(ch->buffer);
1065 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH);
1066 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL);
1067 bus_crnt = lo | (hi << 16);
1068
1069 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n",
1070 ch->adc_idx, bus_crnt - bus_base));
1071
1072 return (bus_crnt - bus_base); /* current byte offset of channel */
1073 }
1074
1075 static u_int32_t
m3_rchan_getptr(kobj_t kobj,void * chdata)1076 m3_rchan_getptr(kobj_t kobj, void *chdata)
1077 {
1078 struct sc_rchinfo *ch = chdata;
1079 struct sc_info *sc = ch->parent;
1080 u_int32_t ptr;
1081
1082 M3_LOCK(sc);
1083 ptr = ch->ptr;
1084 M3_UNLOCK(sc);
1085
1086 return (ptr);
1087 }
1088
1089 static struct pcmchan_caps *
m3_rchan_getcaps(kobj_t kobj,void * chdata)1090 m3_rchan_getcaps(kobj_t kobj, void *chdata)
1091 {
1092 struct sc_rchinfo *ch = chdata;
1093
1094 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx));
1095
1096 return &m3_reccaps;
1097 }
1098
1099 /* -------------------------------------------------------------------- */
1100 /* The interrupt handler */
1101
1102 static void
m3_intr(void * p)1103 m3_intr(void *p)
1104 {
1105 struct sc_info *sc = (struct sc_info *)p;
1106 struct sc_pchinfo *pch;
1107 struct sc_rchinfo *rch;
1108 u_int32_t status, ctl, i, delta;
1109
1110 M3_DEBUG(INTR, ("m3_intr\n"));
1111
1112 M3_LOCK(sc);
1113 status = m3_rd_1(sc, HOST_INT_STATUS);
1114 if (!status) {
1115 M3_UNLOCK(sc);
1116 return;
1117 }
1118
1119 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */
1120
1121 if (status & HV_INT_PENDING) {
1122 u_int8_t event;
1123
1124 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER);
1125 switch (event) {
1126 case 0x99:
1127 mixer_hwvol_mute(sc->dev);
1128 break;
1129 case 0xaa:
1130 mixer_hwvol_step(sc->dev, 1, 1);
1131 break;
1132 case 0x66:
1133 mixer_hwvol_step(sc->dev, -1, -1);
1134 break;
1135 case 0x88:
1136 break;
1137 default:
1138 device_printf(sc->dev, "Unknown HWVOL event\n");
1139 }
1140 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88);
1141 }
1142
1143 if (status & ASSP_INT_PENDING) {
1144 ctl = m3_rd_1(sc, ASSP_CONTROL_B);
1145 if (!(ctl & STOP_ASSP_CLOCK)) {
1146 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS);
1147 if (ctl & DSP2HOST_REQ_TIMER) {
1148 m3_wr_1(sc, ASSP_HOST_INT_STATUS,
1149 DSP2HOST_REQ_TIMER);
1150 /*[[ess_update_ptr]]*/
1151 goto m3_handle_channel_intr;
1152 }
1153 }
1154 }
1155
1156 goto m3_handle_channel_intr_out;
1157
1158 m3_handle_channel_intr:
1159 for (i=0 ; i<sc->pch_cnt ; i++) {
1160 pch = &sc->pch[i];
1161 if (pch->active) {
1162 pch->ptr = m3_pchan_getptr_internal(pch);
1163 delta = pch->bufsize + pch->ptr - pch->prevptr;
1164 delta %= pch->bufsize;
1165 if (delta < sndbuf_getblksz(pch->buffer))
1166 continue;
1167 pch->prevptr = pch->ptr;
1168 M3_UNLOCK(sc);
1169 chn_intr(pch->channel);
1170 M3_LOCK(sc);
1171 }
1172 }
1173 for (i=0 ; i<sc->rch_cnt ; i++) {
1174 rch = &sc->rch[i];
1175 if (rch->active) {
1176 rch->ptr = m3_rchan_getptr_internal(rch);
1177 delta = rch->bufsize + rch->ptr - rch->prevptr;
1178 delta %= rch->bufsize;
1179 if (delta < sndbuf_getblksz(rch->buffer))
1180 continue;
1181 rch->prevptr = rch->ptr;
1182 M3_UNLOCK(sc);
1183 chn_intr(rch->channel);
1184 M3_LOCK(sc);
1185 }
1186 }
1187
1188 m3_handle_channel_intr_out:
1189 M3_UNLOCK(sc);
1190 }
1191
1192 /* -------------------------------------------------------------------- */
1193 /* stuff */
1194
1195 static int
m3_power(struct sc_info * sc,int state)1196 m3_power(struct sc_info *sc, int state)
1197 {
1198 u_int32_t data;
1199
1200 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state));
1201 M3_LOCK_ASSERT(sc);
1202
1203 data = pci_read_config(sc->dev, 0x34, 1);
1204 if (pci_read_config(sc->dev, data, 1) == 1) {
1205 pci_write_config(sc->dev, data + 4, state, 1);
1206 }
1207
1208 return 0;
1209 }
1210
1211 static int
m3_init(struct sc_info * sc)1212 m3_init(struct sc_info *sc)
1213 {
1214 u_int32_t data, i, size;
1215 u_int8_t reset_state;
1216
1217 M3_LOCK_ASSERT(sc);
1218 M3_DEBUG(CHANGE, ("m3_init\n"));
1219
1220 /* diable legacy emulations. */
1221 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2);
1222 data |= DISABLE_LEGACY;
1223 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2);
1224
1225 m3_config(sc);
1226
1227 reset_state = m3_assp_halt(sc);
1228
1229 m3_codec_reset(sc);
1230
1231 /* [m3_assp_init] */
1232 /* zero kernel data */
1233 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1234 for(i = 0 ; i < size / 2 ; i++) {
1235 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0);
1236 }
1237 /* zero mixer data? */
1238 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1239 for(i = 0 ; i < size / 2 ; i++) {
1240 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0);
1241 }
1242 /* init dma pointer */
1243 m3_wr_assp_data(sc, KDATA_CURRENT_DMA,
1244 KDATA_DMA_XFER0);
1245 /* write kernel into code memory */
1246 size = sizeof(gaw_kernel_vect_code);
1247 for(i = 0 ; i < size / 2; i++) {
1248 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i,
1249 gaw_kernel_vect_code[i]);
1250 }
1251 /*
1252 * We only have this one client and we know that 0x400 is free in
1253 * our kernel's mem map, so lets just drop it there. It seems that
1254 * the minisrc doesn't need vectors, so we won't bother with them..
1255 */
1256 size = sizeof(gaw_minisrc_code_0400);
1257 for(i = 0 ; i < size / 2; i++) {
1258 m3_wr_assp_code(sc, 0x400 + i, gaw_minisrc_code_0400[i]);
1259 }
1260 /* write the coefficients for the low pass filter? */
1261 size = sizeof(minisrc_lpf);
1262 for(i = 0; i < size / 2 ; i++) {
1263 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i,
1264 minisrc_lpf[i]);
1265 }
1266 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000);
1267 /* the minisrc is the only thing on our task list */
1268 m3_wr_assp_data(sc, KDATA_TASK0, 0x400);
1269 /* init the mixer number */
1270 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0);
1271 /* extreme kernel master volume */
1272 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, M3_DEFAULT_VOL);
1273 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, M3_DEFAULT_VOL);
1274
1275 m3_amp_enable(sc);
1276
1277 /* [m3_assp_client_init] (only one client at index 0) */
1278 for (i=0x1100 ; i<0x1c00 ; i++) {
1279 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */
1280 }
1281
1282 /* [m3_assp_continue] */
1283 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1284
1285 return 0;
1286 }
1287
1288 static int
m3_uninit(struct sc_info * sc)1289 m3_uninit(struct sc_info *sc)
1290 {
1291 M3_DEBUG(CHANGE, ("m3_uninit\n"));
1292 return 0;
1293 }
1294
1295 /* -------------------------------------------------------------------- */
1296 /* Probe and attach the card */
1297
1298 static int
m3_pci_probe(device_t dev)1299 m3_pci_probe(device_t dev)
1300 {
1301 struct m3_card_type *card;
1302
1303 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev)));
1304
1305 for (card = m3_card_types ; card->pci_id ; card++) {
1306 if (pci_get_devid(dev) == card->pci_id) {
1307 device_set_desc(dev, card->name);
1308 return BUS_PROBE_DEFAULT;
1309 }
1310 }
1311 return ENXIO;
1312 }
1313
1314 static int
m3_pci_attach(device_t dev)1315 m3_pci_attach(device_t dev)
1316 {
1317 struct sc_info *sc;
1318 struct ac97_info *codec = NULL;
1319 char status[SND_STATUSLEN];
1320 struct m3_card_type *card;
1321 int i, len, dacn, adcn;
1322
1323 M3_DEBUG(CALL, ("m3_pci_attach\n"));
1324
1325 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
1326 sc->dev = dev;
1327 sc->type = pci_get_devid(dev);
1328 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev),
1329 "snd_maestro3 softc");
1330 for (card = m3_card_types ; card->pci_id ; card++) {
1331 if (sc->type == card->pci_id) {
1332 sc->which = card->which;
1333 sc->delay1 = card->delay1;
1334 sc->delay2 = card->delay2;
1335 break;
1336 }
1337 }
1338
1339 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1340 "dac", &i) == 0) {
1341 if (i < 1)
1342 dacn = 1;
1343 else if (i > M3_PCHANS)
1344 dacn = M3_PCHANS;
1345 else
1346 dacn = i;
1347 } else
1348 dacn = M3_PCHANS;
1349
1350 adcn = M3_RCHANS;
1351
1352 pci_enable_busmaster(dev);
1353
1354 sc->regid = PCIR_BAR(0);
1355 sc->regtype = SYS_RES_MEMORY;
1356 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1357 RF_ACTIVE);
1358 if (!sc->reg) {
1359 sc->regtype = SYS_RES_IOPORT;
1360 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1361 RF_ACTIVE);
1362 }
1363 if (!sc->reg) {
1364 device_printf(dev, "unable to allocate register space\n");
1365 goto bad;
1366 }
1367 sc->st = rman_get_bustag(sc->reg);
1368 sc->sh = rman_get_bushandle(sc->reg);
1369
1370 sc->irqid = 0;
1371 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1372 RF_ACTIVE | RF_SHAREABLE);
1373 if (!sc->irq) {
1374 device_printf(dev, "unable to allocate interrupt\n");
1375 goto bad;
1376 }
1377
1378 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) {
1379 device_printf(dev, "unable to setup interrupt\n");
1380 goto bad;
1381 }
1382
1383 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT,
1384 M3_BUFSIZE_MAX);
1385
1386 if (bus_dma_tag_create(
1387 bus_get_dma_tag(dev), /* parent */
1388 2, 0, /* alignment, boundary */
1389 M3_MAXADDR, /* lowaddr */
1390 BUS_SPACE_MAXADDR, /* highaddr */
1391 NULL, NULL, /* filtfunc, filtfuncarg */
1392 sc->bufsz, /* maxsize */
1393 1, /* nsegments */
1394 0x3ffff, /* maxsegz */
1395 0, /* flags */
1396 NULL, /* lockfunc */
1397 NULL, /* lockfuncarg */
1398 &sc->parent_dmat) != 0) {
1399 device_printf(dev, "unable to create dma tag\n");
1400 goto bad;
1401 }
1402
1403 M3_LOCK(sc);
1404 m3_power(sc, 0); /* power up */
1405 /* init chip */
1406 i = m3_init(sc);
1407 M3_UNLOCK(sc);
1408 if (i == -1) {
1409 device_printf(dev, "unable to initialize the card\n");
1410 goto bad;
1411 }
1412
1413 /* create/init mixer */
1414 codec = AC97_CREATE(dev, sc, m3_codec);
1415 if (codec == NULL) {
1416 device_printf(dev, "ac97_create error\n");
1417 goto bad;
1418 }
1419 if (mixer_init(dev, ac97_getmixerclass(), codec)) {
1420 device_printf(dev, "mixer_init error\n");
1421 goto bad;
1422 }
1423
1424 m3_enable_ints(sc);
1425
1426 pcm_init(dev, sc);
1427 for (i=0 ; i<dacn ; i++) {
1428 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) {
1429 device_printf(dev, "pcm_addchan (play) error\n");
1430 goto bad;
1431 }
1432 }
1433 for (i=0 ; i<adcn ; i++) {
1434 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) {
1435 device_printf(dev, "pcm_addchan (rec) error\n");
1436 goto bad;
1437 }
1438 }
1439 snprintf(status, SND_STATUSLEN, "%s 0x%jx irq %jd on %s",
1440 (sc->regtype == SYS_RES_IOPORT)? "port" : "mem",
1441 rman_get_start(sc->reg), rman_get_start(sc->irq),
1442 device_get_nameunit(device_get_parent(dev)));
1443 if (pcm_register(dev, status)) {
1444 device_printf(dev, "pcm_register error\n");
1445 goto bad;
1446 }
1447
1448 mixer_hwvol_init(dev);
1449
1450 /* Create the buffer for saving the card state during suspend */
1451 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH +
1452 REV_B_DATA_MEMORY_LENGTH);
1453 sc->savemem = malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1454
1455 return 0;
1456
1457 bad:
1458 if (codec)
1459 ac97_destroy(codec);
1460 if (sc->ih)
1461 bus_teardown_intr(dev, sc->irq, sc->ih);
1462 if (sc->irq)
1463 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1464 if (sc->reg)
1465 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1466 if (sc->parent_dmat)
1467 bus_dma_tag_destroy(sc->parent_dmat);
1468 if (sc->sc_lock)
1469 snd_mtxfree(sc->sc_lock);
1470 free(sc, M_DEVBUF);
1471 return ENXIO;
1472 }
1473
1474 static int
m3_pci_detach(device_t dev)1475 m3_pci_detach(device_t dev)
1476 {
1477 struct sc_info *sc = pcm_getdevinfo(dev);
1478 int r;
1479
1480 M3_DEBUG(CALL, ("m3_pci_detach\n"));
1481
1482 if ((r = pcm_unregister(dev)) != 0) {
1483 return r;
1484 }
1485
1486 M3_LOCK(sc);
1487 m3_uninit(sc); /* shutdown chip */
1488 m3_power(sc, 3); /* power off */
1489 M3_UNLOCK(sc);
1490
1491 bus_teardown_intr(dev, sc->irq, sc->ih);
1492 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1493 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1494 bus_dma_tag_destroy(sc->parent_dmat);
1495
1496 free(sc->savemem, M_DEVBUF);
1497 snd_mtxfree(sc->sc_lock);
1498 free(sc, M_DEVBUF);
1499 return 0;
1500 }
1501
1502 static int
m3_pci_suspend(device_t dev)1503 m3_pci_suspend(device_t dev)
1504 {
1505 struct sc_info *sc = pcm_getdevinfo(dev);
1506 int i, index = 0;
1507
1508 M3_DEBUG(CHANGE, ("m3_pci_suspend\n"));
1509
1510 M3_LOCK(sc);
1511 for (i=0 ; i<sc->pch_cnt ; i++) {
1512 if (sc->pch[i].active) {
1513 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1514 PCMTRIG_STOP);
1515 }
1516 }
1517 for (i=0 ; i<sc->rch_cnt ; i++) {
1518 if (sc->rch[i].active) {
1519 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1520 PCMTRIG_STOP);
1521 }
1522 }
1523 DELAY(10 * 1000); /* give things a chance to stop */
1524
1525 /* Disable interrupts */
1526 m3_wr_2(sc, HOST_INT_CTRL, 0);
1527 m3_wr_1(sc, ASSP_CONTROL_C, 0);
1528
1529 m3_assp_halt(sc);
1530
1531 /* Save the state of the ASSP */
1532 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1533 sc->savemem[index++] = m3_rd_assp_code(sc, i);
1534 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1535 sc->savemem[index++] = m3_rd_assp_data(sc, i);
1536
1537 /* Power down the card to D3 state */
1538 m3_power(sc, 3);
1539 M3_UNLOCK(sc);
1540
1541 return 0;
1542 }
1543
1544 static int
m3_pci_resume(device_t dev)1545 m3_pci_resume(device_t dev)
1546 {
1547 struct sc_info *sc = pcm_getdevinfo(dev);
1548 int i, index = 0;
1549 u_int8_t reset_state;
1550
1551 M3_DEBUG(CHANGE, ("m3_pci_resume\n"));
1552
1553 M3_LOCK(sc);
1554 /* Power the card back to D0 */
1555 m3_power(sc, 0);
1556
1557 m3_config(sc);
1558
1559 reset_state = m3_assp_halt(sc);
1560
1561 m3_codec_reset(sc);
1562
1563 /* Restore the ASSP state */
1564 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1565 m3_wr_assp_code(sc, i, sc->savemem[index++]);
1566 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1567 m3_wr_assp_data(sc, i, sc->savemem[index++]);
1568
1569 /* Restart the DMA engine */
1570 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0);
1571
1572 /* [m3_assp_continue] */
1573 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1574
1575 m3_amp_enable(sc);
1576
1577 m3_enable_ints(sc);
1578
1579 M3_UNLOCK(sc); /* XXX */
1580 if (mixer_reinit(dev) == -1) {
1581 device_printf(dev, "unable to reinitialize the mixer\n");
1582 return (ENXIO);
1583 }
1584 M3_LOCK(sc);
1585
1586 /* Turn the channels back on */
1587 for (i=0 ; i<sc->pch_cnt ; i++) {
1588 if (sc->pch[i].active) {
1589 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1590 PCMTRIG_START);
1591 }
1592 }
1593 for (i=0 ; i<sc->rch_cnt ; i++) {
1594 if (sc->rch[i].active) {
1595 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1596 PCMTRIG_START);
1597 }
1598 }
1599
1600 M3_UNLOCK(sc);
1601 return 0;
1602 }
1603
1604 static int
m3_pci_shutdown(device_t dev)1605 m3_pci_shutdown(device_t dev)
1606 {
1607 struct sc_info *sc = pcm_getdevinfo(dev);
1608
1609 M3_DEBUG(CALL, ("m3_pci_shutdown\n"));
1610
1611 M3_LOCK(sc);
1612 m3_power(sc, 3); /* power off */
1613 M3_UNLOCK(sc);
1614
1615 return 0;
1616 }
1617
1618 static u_int8_t
m3_assp_halt(struct sc_info * sc)1619 m3_assp_halt(struct sc_info *sc)
1620 {
1621 u_int8_t data, reset_state;
1622
1623 M3_LOCK_ASSERT(sc);
1624
1625 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B);
1626 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */
1627 DELAY(10 * 1000);
1628 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET);
1629 DELAY(10 * 1000); /* necessary? */
1630
1631 return reset_state;
1632 }
1633
1634 static void
m3_config(struct sc_info * sc)1635 m3_config(struct sc_info *sc)
1636 {
1637 u_int32_t data, hv_cfg;
1638 int hint;
1639
1640 M3_LOCK_ASSERT(sc);
1641
1642 M3_UNLOCK(sc);
1643 /*
1644 * The volume buttons can be wired up via two different sets of pins.
1645 * This presents a problem since we can't tell which way it's
1646 * configured. Allow the user to set a hint in order to twiddle
1647 * the proper bits.
1648 */
1649 if (resource_int_value(device_get_name(sc->dev),
1650 device_get_unit(sc->dev),
1651 "hwvol_config", &hint) == 0)
1652 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0;
1653 else
1654 hv_cfg = HV_BUTTON_FROM_GD;
1655 M3_LOCK(sc);
1656
1657 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1658 data &= ~HV_BUTTON_FROM_GD;
1659 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg;
1660 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
1661 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1662
1663 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP);
1664 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1665 data &= ~INT_CLK_SELECT;
1666 if (sc->which == ESS_MAESTRO3) {
1667 data &= ~INT_CLK_MULT_ENABLE;
1668 data |= INT_CLK_SRC_NOT_PCI;
1669 }
1670 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2);
1671 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1672
1673 if (sc->which == ESS_ALLEGRO_1) {
1674 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4);
1675 data |= IN_CLK_12MHZ_SELECT;
1676 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4);
1677 }
1678
1679 data = m3_rd_1(sc, ASSP_CONTROL_A);
1680 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
1681 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/
1682 data |= ASSP_0_WS_ENABLE;
1683 m3_wr_1(sc, ASSP_CONTROL_A, data);
1684
1685 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP);
1686 }
1687
1688 static void
m3_enable_ints(struct sc_info * sc)1689 m3_enable_ints(struct sc_info *sc)
1690 {
1691 u_int8_t data;
1692
1693 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE);
1694 data = m3_rd_1(sc, ASSP_CONTROL_C);
1695 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE);
1696 }
1697
1698 static void
m3_amp_enable(struct sc_info * sc)1699 m3_amp_enable(struct sc_info *sc)
1700 {
1701 u_int32_t gpo, polarity_port, polarity;
1702 u_int16_t data;
1703
1704 M3_LOCK_ASSERT(sc);
1705
1706 switch (sc->which) {
1707 case ESS_ALLEGRO_1:
1708 polarity_port = 0x1800;
1709 break;
1710 case ESS_MAESTRO3:
1711 polarity_port = 0x1100;
1712 break;
1713 default:
1714 panic("bad sc->which");
1715 }
1716 gpo = (polarity_port >> 8) & 0x0f;
1717 polarity = polarity_port >> 12;
1718 polarity = !polarity; /* enable */
1719 polarity = polarity << gpo;
1720 gpo = 1 << gpo;
1721 m3_wr_2(sc, GPIO_MASK, ~gpo);
1722 data = m3_rd_2(sc, GPIO_DIRECTION);
1723 m3_wr_2(sc, GPIO_DIRECTION, data | gpo);
1724 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity;
1725 m3_wr_2(sc, GPIO_DATA, data);
1726 m3_wr_2(sc, GPIO_MASK, ~0);
1727 }
1728
1729 static void
m3_codec_reset(struct sc_info * sc)1730 m3_codec_reset(struct sc_info *sc)
1731 {
1732 u_int16_t data, dir;
1733 int retry = 0;
1734
1735 M3_LOCK_ASSERT(sc);
1736 do {
1737 data = m3_rd_2(sc, GPIO_DIRECTION);
1738 dir = data | 0x10; /* assuming pci bus master? */
1739
1740 /* [[remote_codec_config]] */
1741 data = m3_rd_2(sc, RING_BUS_CTRL_B);
1742 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK);
1743 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL);
1744 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT);
1745 data = m3_rd_2(sc, SDO_IN_DEST_CTRL);
1746 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN);
1747
1748 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE);
1749 DELAY(20);
1750
1751 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97);
1752 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97);
1753 m3_wr_2(sc, GPIO_DATA, 0);
1754 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97);
1755 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/
1756 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97);
1757 DELAY(5);
1758 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE |
1759 SERIAL_AC_LINK_ENABLE);
1760 m3_wr_2(sc, GPIO_MASK, ~0);
1761 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/
1762
1763 /* [[try read vendor]] */
1764 data = m3_rdcd(NULL, sc, 0x7c);
1765 if ((data == 0) || (data == 0xffff)) {
1766 retry++;
1767 if (retry > 3) {
1768 device_printf(sc->dev, "Codec reset failed\n");
1769 break;
1770 }
1771 device_printf(sc->dev, "Codec reset retry\n");
1772 } else retry = 0;
1773 } while (retry);
1774 }
1775
1776 static device_method_t m3_methods[] = {
1777 DEVMETHOD(device_probe, m3_pci_probe),
1778 DEVMETHOD(device_attach, m3_pci_attach),
1779 DEVMETHOD(device_detach, m3_pci_detach),
1780 DEVMETHOD(device_suspend, m3_pci_suspend),
1781 DEVMETHOD(device_resume, m3_pci_resume),
1782 DEVMETHOD(device_shutdown, m3_pci_shutdown),
1783 { 0, 0 }
1784 };
1785
1786 static driver_t m3_driver = {
1787 "pcm",
1788 m3_methods,
1789 PCM_SOFTC_SIZE,
1790 };
1791
1792 DRIVER_MODULE(snd_maestro3, pci, m3_driver, 0, 0);
1793 MODULE_DEPEND(snd_maestro3, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1794 MODULE_VERSION(snd_maestro3, 1);
1795