1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/reset/imx8mp-reset-audiomix.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interconnect/fsl,imx8mp.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/thermal/thermal.h> 15 16#include "imx8mp-pinfunc.h" 17 18/ { 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &fec; 25 ethernet1 = &eqos; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 i2c0 = &i2c1; 32 i2c1 = &i2c2; 33 i2c2 = &i2c3; 34 i2c3 = &i2c4; 35 i2c4 = &i2c5; 36 i2c5 = &i2c6; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 serial0 = &uart1; 41 serial1 = &uart2; 42 serial2 = &uart3; 43 serial3 = &uart4; 44 spi0 = &flexspi; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 idle-states { 52 entry-method = "psci"; 53 54 cpu_pd_wait: cpu-pd-wait { 55 compatible = "arm,idle-state"; 56 arm,psci-suspend-param = <0x0010033>; 57 local-timer-stop; 58 entry-latency-us = <1000>; 59 exit-latency-us = <700>; 60 min-residency-us = <2700>; 61 wakeup-latency-us = <1500>; 62 }; 63 }; 64 65 A53_0: cpu@0 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x0>; 69 clocks = <&clk IMX8MP_CLK_ARM>; 70 enable-method = "psci"; 71 i-cache-size = <0x8000>; 72 i-cache-line-size = <64>; 73 i-cache-sets = <256>; 74 d-cache-size = <0x8000>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <128>; 77 next-level-cache = <&A53_L2>; 78 nvmem-cells = <&cpu_speed_grade>; 79 nvmem-cell-names = "speed_grade"; 80 operating-points-v2 = <&a53_opp_table>; 81 #cooling-cells = <2>; 82 cpu-idle-states = <&cpu_pd_wait>; 83 }; 84 85 A53_1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x1>; 89 clocks = <&clk IMX8MP_CLK_ARM>; 90 enable-method = "psci"; 91 i-cache-size = <0x8000>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <0x8000>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <128>; 97 next-level-cache = <&A53_L2>; 98 operating-points-v2 = <&a53_opp_table>; 99 #cooling-cells = <2>; 100 cpu-idle-states = <&cpu_pd_wait>; 101 }; 102 103 A53_2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x2>; 107 clocks = <&clk IMX8MP_CLK_ARM>; 108 enable-method = "psci"; 109 i-cache-size = <0x8000>; 110 i-cache-line-size = <64>; 111 i-cache-sets = <256>; 112 d-cache-size = <0x8000>; 113 d-cache-line-size = <64>; 114 d-cache-sets = <128>; 115 next-level-cache = <&A53_L2>; 116 operating-points-v2 = <&a53_opp_table>; 117 #cooling-cells = <2>; 118 cpu-idle-states = <&cpu_pd_wait>; 119 }; 120 121 A53_3: cpu@3 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a53"; 124 reg = <0x3>; 125 clocks = <&clk IMX8MP_CLK_ARM>; 126 enable-method = "psci"; 127 i-cache-size = <0x8000>; 128 i-cache-line-size = <64>; 129 i-cache-sets = <256>; 130 d-cache-size = <0x8000>; 131 d-cache-line-size = <64>; 132 d-cache-sets = <128>; 133 next-level-cache = <&A53_L2>; 134 operating-points-v2 = <&a53_opp_table>; 135 #cooling-cells = <2>; 136 cpu-idle-states = <&cpu_pd_wait>; 137 }; 138 139 A53_L2: l2-cache0 { 140 compatible = "cache"; 141 cache-unified; 142 cache-level = <2>; 143 cache-size = <0x80000>; 144 cache-line-size = <64>; 145 cache-sets = <512>; 146 }; 147 }; 148 149 a53_opp_table: opp-table { 150 compatible = "operating-points-v2"; 151 opp-shared; 152 153 opp-1200000000 { 154 opp-hz = /bits/ 64 <1200000000>; 155 opp-microvolt = <850000>; 156 opp-supported-hw = <0x8a0>, <0x7>; 157 clock-latency-ns = <150000>; 158 opp-suspend; 159 }; 160 161 opp-1600000000 { 162 opp-hz = /bits/ 64 <1600000000>; 163 opp-microvolt = <950000>; 164 opp-supported-hw = <0xa0>, <0x7>; 165 clock-latency-ns = <150000>; 166 opp-suspend; 167 }; 168 169 opp-1800000000 { 170 opp-hz = /bits/ 64 <1800000000>; 171 opp-microvolt = <1000000>; 172 opp-supported-hw = <0x20>, <0x3>; 173 clock-latency-ns = <150000>; 174 opp-suspend; 175 }; 176 }; 177 178 osc_32k: clock-osc-32k { 179 compatible = "fixed-clock"; 180 #clock-cells = <0>; 181 clock-frequency = <32768>; 182 clock-output-names = "osc_32k"; 183 }; 184 185 osc_24m: clock-osc-24m { 186 compatible = "fixed-clock"; 187 #clock-cells = <0>; 188 clock-frequency = <24000000>; 189 clock-output-names = "osc_24m"; 190 }; 191 192 clk_ext1: clock-ext1 { 193 compatible = "fixed-clock"; 194 #clock-cells = <0>; 195 clock-frequency = <133000000>; 196 clock-output-names = "clk_ext1"; 197 }; 198 199 clk_ext2: clock-ext2 { 200 compatible = "fixed-clock"; 201 #clock-cells = <0>; 202 clock-frequency = <133000000>; 203 clock-output-names = "clk_ext2"; 204 }; 205 206 clk_ext3: clock-ext3 { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <133000000>; 210 clock-output-names = "clk_ext3"; 211 }; 212 213 clk_ext4: clock-ext4 { 214 compatible = "fixed-clock"; 215 #clock-cells = <0>; 216 clock-frequency = <133000000>; 217 clock-output-names = "clk_ext4"; 218 }; 219 220 funnel { 221 /* 222 * non-configurable funnel don't show up on the AMBA 223 * bus. As such no need to add "arm,primecell". 224 */ 225 compatible = "arm,coresight-static-funnel"; 226 227 in-ports { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 port@0 { 232 reg = <0>; 233 234 ca_funnel_in_port0: endpoint { 235 remote-endpoint = <&etm0_out_port>; 236 }; 237 }; 238 239 port@1 { 240 reg = <1>; 241 242 ca_funnel_in_port1: endpoint { 243 remote-endpoint = <&etm1_out_port>; 244 }; 245 }; 246 247 port@2 { 248 reg = <2>; 249 250 ca_funnel_in_port2: endpoint { 251 remote-endpoint = <&etm2_out_port>; 252 }; 253 }; 254 255 port@3 { 256 reg = <3>; 257 258 ca_funnel_in_port3: endpoint { 259 remote-endpoint = <&etm3_out_port>; 260 }; 261 }; 262 }; 263 264 out-ports { 265 port { 266 267 ca_funnel_out_port0: endpoint { 268 remote-endpoint = <&hugo_funnel_in_port0>; 269 }; 270 }; 271 }; 272 }; 273 274 reserved-memory { 275 #address-cells = <2>; 276 #size-cells = <2>; 277 ranges; 278 279 dsp_reserved: dsp@92400000 { 280 reg = <0 0x92400000 0 0x1000000>; 281 no-map; 282 status = "disabled"; 283 }; 284 }; 285 286 pmu { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts = <GIC_PPI 7 289 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 290 }; 291 292 psci { 293 compatible = "arm,psci-1.0"; 294 method = "smc"; 295 }; 296 297 thermal-zones { 298 cpu-thermal { 299 polling-delay-passive = <250>; 300 polling-delay = <2000>; 301 thermal-sensors = <&tmu 0>; 302 trips { 303 cpu_alert0: trip0 { 304 temperature = <85000>; 305 hysteresis = <2000>; 306 type = "passive"; 307 }; 308 309 cpu_crit0: trip1 { 310 temperature = <95000>; 311 hysteresis = <2000>; 312 type = "critical"; 313 }; 314 }; 315 316 cooling-maps { 317 map0 { 318 trip = <&cpu_alert0>; 319 cooling-device = 320 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 321 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 322 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 323 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 324 }; 325 }; 326 }; 327 328 soc-thermal { 329 polling-delay-passive = <250>; 330 polling-delay = <2000>; 331 thermal-sensors = <&tmu 1>; 332 trips { 333 soc_alert0: trip0 { 334 temperature = <85000>; 335 hysteresis = <2000>; 336 type = "passive"; 337 }; 338 339 soc_crit0: trip1 { 340 temperature = <95000>; 341 hysteresis = <2000>; 342 type = "critical"; 343 }; 344 }; 345 346 cooling-maps { 347 map0 { 348 trip = <&soc_alert0>; 349 cooling-device = 350 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 351 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 352 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 353 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 354 }; 355 }; 356 }; 357 }; 358 359 timer { 360 compatible = "arm,armv8-timer"; 361 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 362 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 363 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 364 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 365 clock-frequency = <8000000>; 366 arm,no-tick-in-suspend; 367 }; 368 369 soc: soc@0 { 370 compatible = "fsl,imx8mp-soc", "simple-bus"; 371 #address-cells = <1>; 372 #size-cells = <1>; 373 ranges = <0x0 0x0 0x0 0x3e000000>; 374 nvmem-cells = <&imx8mp_uid>; 375 nvmem-cell-names = "soc_unique_id"; 376 377 etm0: etm@28440000 { 378 compatible = "arm,coresight-etm4x", "arm,primecell"; 379 reg = <0x28440000 0x1000>; 380 cpu = <&A53_0>; 381 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 382 clock-names = "apb_pclk"; 383 384 out-ports { 385 port { 386 etm0_out_port: endpoint { 387 remote-endpoint = <&ca_funnel_in_port0>; 388 }; 389 }; 390 }; 391 }; 392 393 etm1: etm@28540000 { 394 compatible = "arm,coresight-etm4x", "arm,primecell"; 395 reg = <0x28540000 0x1000>; 396 cpu = <&A53_1>; 397 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 398 clock-names = "apb_pclk"; 399 400 out-ports { 401 port { 402 etm1_out_port: endpoint { 403 remote-endpoint = <&ca_funnel_in_port1>; 404 }; 405 }; 406 }; 407 }; 408 409 etm2: etm@28640000 { 410 compatible = "arm,coresight-etm4x", "arm,primecell"; 411 reg = <0x28640000 0x1000>; 412 cpu = <&A53_2>; 413 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 414 clock-names = "apb_pclk"; 415 416 out-ports { 417 port { 418 etm2_out_port: endpoint { 419 remote-endpoint = <&ca_funnel_in_port2>; 420 }; 421 }; 422 }; 423 }; 424 425 etm3: etm@28740000 { 426 compatible = "arm,coresight-etm4x", "arm,primecell"; 427 reg = <0x28740000 0x1000>; 428 cpu = <&A53_3>; 429 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 430 clock-names = "apb_pclk"; 431 432 out-ports { 433 port { 434 etm3_out_port: endpoint { 435 remote-endpoint = <&ca_funnel_in_port3>; 436 }; 437 }; 438 }; 439 }; 440 441 funnel@28c03000 { 442 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 443 reg = <0x28c03000 0x1000>; 444 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 445 clock-names = "apb_pclk"; 446 447 in-ports { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 451 port@0 { 452 reg = <0>; 453 454 hugo_funnel_in_port0: endpoint { 455 remote-endpoint = <&ca_funnel_out_port0>; 456 }; 457 }; 458 459 port@1 { 460 reg = <1>; 461 462 hugo_funnel_in_port1: endpoint { 463 /* M7 input */ 464 }; 465 }; 466 467 port@2 { 468 reg = <2>; 469 470 hugo_funnel_in_port2: endpoint { 471 /* DSP input */ 472 }; 473 }; 474 /* the other input ports are not connect to anything */ 475 }; 476 477 out-ports { 478 port { 479 hugo_funnel_out_port0: endpoint { 480 remote-endpoint = <&etf_in_port>; 481 }; 482 }; 483 }; 484 }; 485 486 etf@28c04000 { 487 compatible = "arm,coresight-tmc", "arm,primecell"; 488 reg = <0x28c04000 0x1000>; 489 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 490 clock-names = "apb_pclk"; 491 492 in-ports { 493 port { 494 etf_in_port: endpoint { 495 remote-endpoint = <&hugo_funnel_out_port0>; 496 }; 497 }; 498 }; 499 500 out-ports { 501 port { 502 etf_out_port: endpoint { 503 remote-endpoint = <&etr_in_port>; 504 }; 505 }; 506 }; 507 }; 508 509 etr@28c06000 { 510 compatible = "arm,coresight-tmc", "arm,primecell"; 511 reg = <0x28c06000 0x1000>; 512 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 513 clock-names = "apb_pclk"; 514 515 in-ports { 516 port { 517 etr_in_port: endpoint { 518 remote-endpoint = <&etf_out_port>; 519 }; 520 }; 521 }; 522 }; 523 524 aips1: bus@30000000 { 525 compatible = "fsl,aips-bus", "simple-bus"; 526 reg = <0x30000000 0x400000>; 527 #address-cells = <1>; 528 #size-cells = <1>; 529 ranges; 530 531 gpio1: gpio@30200000 { 532 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 533 reg = <0x30200000 0x10000>; 534 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 537 gpio-controller; 538 #gpio-cells = <2>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 gpio-ranges = <&iomuxc 0 5 30>; 542 }; 543 544 gpio2: gpio@30210000 { 545 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 546 reg = <0x30210000 0x10000>; 547 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 550 gpio-controller; 551 #gpio-cells = <2>; 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 gpio-ranges = <&iomuxc 0 35 21>; 555 }; 556 557 gpio3: gpio@30220000 { 558 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 559 reg = <0x30220000 0x10000>; 560 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 563 gpio-controller; 564 #gpio-cells = <2>; 565 interrupt-controller; 566 #interrupt-cells = <2>; 567 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 568 }; 569 570 gpio4: gpio@30230000 { 571 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 572 reg = <0x30230000 0x10000>; 573 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 576 gpio-controller; 577 #gpio-cells = <2>; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 gpio-ranges = <&iomuxc 0 82 32>; 581 }; 582 583 gpio5: gpio@30240000 { 584 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 585 reg = <0x30240000 0x10000>; 586 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 589 gpio-controller; 590 #gpio-cells = <2>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 gpio-ranges = <&iomuxc 0 114 30>; 594 }; 595 596 tmu: tmu@30260000 { 597 compatible = "fsl,imx8mp-tmu"; 598 reg = <0x30260000 0x10000>; 599 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 600 nvmem-cells = <&tmu_calib>; 601 nvmem-cell-names = "calib"; 602 #thermal-sensor-cells = <1>; 603 }; 604 605 wdog1: watchdog@30280000 { 606 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 607 reg = <0x30280000 0x10000>; 608 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 610 status = "disabled"; 611 }; 612 613 wdog2: watchdog@30290000 { 614 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 615 reg = <0x30290000 0x10000>; 616 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 618 status = "disabled"; 619 }; 620 621 wdog3: watchdog@302a0000 { 622 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 623 reg = <0x302a0000 0x10000>; 624 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 626 status = "disabled"; 627 }; 628 629 gpt1: timer@302d0000 { 630 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 631 reg = <0x302d0000 0x10000>; 632 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 634 clock-names = "ipg", "per"; 635 }; 636 637 gpt2: timer@302e0000 { 638 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 639 reg = <0x302e0000 0x10000>; 640 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 642 clock-names = "ipg", "per"; 643 }; 644 645 gpt3: timer@302f0000 { 646 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 647 reg = <0x302f0000 0x10000>; 648 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 650 clock-names = "ipg", "per"; 651 }; 652 653 iomuxc: pinctrl@30330000 { 654 compatible = "fsl,imx8mp-iomuxc"; 655 reg = <0x30330000 0x10000>; 656 }; 657 658 gpr: syscon@30340000 { 659 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 660 reg = <0x30340000 0x10000>; 661 }; 662 663 ocotp: efuse@30350000 { 664 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 665 reg = <0x30350000 0x10000>; 666 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 667 /* For nvmem subnodes */ 668 #address-cells = <1>; 669 #size-cells = <1>; 670 671 /* 672 * The register address below maps to the MX8M 673 * Fusemap Description Table entries this way. 674 * Assuming 675 * reg = <ADDR SIZE>; 676 * then 677 * Fuse Address = (ADDR * 4) + 0x400 678 * Note that if SIZE is greater than 4, then 679 * each subsequent fuse is located at offset 680 * +0x10 in Fusemap Description Table (e.g. 681 * reg = <0x8 0x8> describes fuses 0x420 and 682 * 0x430). 683 */ 684 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 685 reg = <0x8 0x8>; 686 }; 687 688 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 689 reg = <0x10 4>; 690 }; 691 692 eth_mac1: mac-address@90 { /* 0x640 */ 693 reg = <0x90 6>; 694 }; 695 696 eth_mac2: mac-address@96 { /* 0x658 */ 697 reg = <0x96 6>; 698 }; 699 700 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 701 reg = <0x264 0x10>; 702 }; 703 }; 704 705 anatop: clock-controller@30360000 { 706 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 707 reg = <0x30360000 0x10000>; 708 #clock-cells = <1>; 709 }; 710 711 snvs: snvs@30370000 { 712 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 713 reg = <0x30370000 0x10000>; 714 715 snvs_rtc: snvs-rtc-lp { 716 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 717 regmap = <&snvs>; 718 offset = <0x34>; 719 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 722 clock-names = "snvs-rtc"; 723 }; 724 725 snvs_pwrkey: snvs-powerkey { 726 compatible = "fsl,sec-v4.0-pwrkey"; 727 regmap = <&snvs>; 728 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 730 clock-names = "snvs-pwrkey"; 731 linux,keycode = <KEY_POWER>; 732 wakeup-source; 733 status = "disabled"; 734 }; 735 736 snvs_lpgpr: snvs-lpgpr { 737 compatible = "fsl,imx8mp-snvs-lpgpr", 738 "fsl,imx7d-snvs-lpgpr"; 739 }; 740 }; 741 742 clk: clock-controller@30380000 { 743 compatible = "fsl,imx8mp-ccm"; 744 reg = <0x30380000 0x10000>; 745 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 747 #clock-cells = <1>; 748 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 749 <&clk_ext3>, <&clk_ext4>; 750 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 751 "clk_ext3", "clk_ext4"; 752 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 753 <&clk IMX8MP_CLK_A53_CORE>, 754 <&clk IMX8MP_CLK_NOC>, 755 <&clk IMX8MP_CLK_NOC_IO>, 756 <&clk IMX8MP_CLK_GIC>; 757 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 758 <&clk IMX8MP_ARM_PLL_OUT>, 759 <&clk IMX8MP_SYS_PLL2_1000M>, 760 <&clk IMX8MP_SYS_PLL1_800M>, 761 <&clk IMX8MP_SYS_PLL2_500M>; 762 assigned-clock-rates = <0>, <0>, 763 <1000000000>, 764 <800000000>, 765 <500000000>; 766 }; 767 768 src: reset-controller@30390000 { 769 compatible = "fsl,imx8mp-src", "syscon"; 770 reg = <0x30390000 0x10000>; 771 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 772 #reset-cells = <1>; 773 }; 774 775 gpc: gpc@303a0000 { 776 compatible = "fsl,imx8mp-gpc"; 777 reg = <0x303a0000 0x1000>; 778 interrupt-parent = <&gic>; 779 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 780 interrupt-controller; 781 #interrupt-cells = <3>; 782 783 pgc { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 787 pgc_mipi_phy1: power-domain@0 { 788 #power-domain-cells = <0>; 789 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 790 }; 791 792 pgc_pcie_phy: power-domain@1 { 793 #power-domain-cells = <0>; 794 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 795 }; 796 797 pgc_usb1_phy: power-domain@2 { 798 #power-domain-cells = <0>; 799 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 800 }; 801 802 pgc_usb2_phy: power-domain@3 { 803 #power-domain-cells = <0>; 804 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 805 }; 806 807 pgc_mlmix: power-domain@4 { 808 #power-domain-cells = <0>; 809 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 810 clocks = <&clk IMX8MP_CLK_ML_AXI>, 811 <&clk IMX8MP_CLK_ML_AHB>, 812 <&clk IMX8MP_CLK_NPU_ROOT>; 813 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 814 <&clk IMX8MP_CLK_ML_AXI>, 815 <&clk IMX8MP_CLK_ML_AHB>; 816 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 817 <&clk IMX8MP_SYS_PLL1_800M>, 818 <&clk IMX8MP_SYS_PLL1_800M>; 819 assigned-clock-rates = <1000000000>, 820 <800000000>, 821 <400000000>; 822 }; 823 824 pgc_audio: power-domain@5 { 825 #power-domain-cells = <0>; 826 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; 827 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 828 <&clk IMX8MP_CLK_AUDIO_AXI>; 829 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, 830 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; 831 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 832 <&clk IMX8MP_SYS_PLL1_800M>; 833 assigned-clock-rates = <400000000>, 834 <800000000>; 835 }; 836 837 pgc_gpu2d: power-domain@6 { 838 #power-domain-cells = <0>; 839 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 840 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 841 power-domains = <&pgc_gpumix>; 842 }; 843 844 pgc_gpumix: power-domain@7 { 845 #power-domain-cells = <0>; 846 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 847 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 848 <&clk IMX8MP_CLK_GPU_AHB>; 849 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 850 <&clk IMX8MP_CLK_GPU_AHB>; 851 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 852 <&clk IMX8MP_SYS_PLL1_800M>; 853 assigned-clock-rates = <800000000>, <400000000>; 854 }; 855 856 pgc_vpumix: power-domain@8 { 857 #power-domain-cells = <0>; 858 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 859 clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 860 }; 861 862 pgc_gpu3d: power-domain@9 { 863 #power-domain-cells = <0>; 864 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 865 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 866 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 867 power-domains = <&pgc_gpumix>; 868 }; 869 870 pgc_mediamix: power-domain@10 { 871 #power-domain-cells = <0>; 872 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 873 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 874 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 875 }; 876 877 pgc_vpu_g1: power-domain@11 { 878 #power-domain-cells = <0>; 879 power-domains = <&pgc_vpumix>; 880 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 881 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 882 }; 883 884 pgc_vpu_g2: power-domain@12 { 885 #power-domain-cells = <0>; 886 power-domains = <&pgc_vpumix>; 887 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 888 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 889 890 }; 891 892 pgc_vpu_vc8000e: power-domain@13 { 893 #power-domain-cells = <0>; 894 power-domains = <&pgc_vpumix>; 895 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 896 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 897 }; 898 899 pgc_hdmimix: power-domain@14 { 900 #power-domain-cells = <0>; 901 reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; 902 clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, 903 <&clk IMX8MP_CLK_HDMI_APB>; 904 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, 905 <&clk IMX8MP_CLK_HDMI_APB>; 906 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, 907 <&clk IMX8MP_SYS_PLL1_133M>; 908 assigned-clock-rates = <500000000>, <133000000>; 909 }; 910 911 pgc_hdmi_phy: power-domain@15 { 912 #power-domain-cells = <0>; 913 reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; 914 }; 915 916 pgc_mipi_phy2: power-domain@16 { 917 #power-domain-cells = <0>; 918 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 919 }; 920 921 pgc_hsiomix: power-domain@17 { 922 #power-domain-cells = <0>; 923 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 924 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 925 <&clk IMX8MP_CLK_HSIO_ROOT>; 926 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 927 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 928 assigned-clock-rates = <500000000>; 929 }; 930 931 pgc_ispdwp: power-domain@18 { 932 #power-domain-cells = <0>; 933 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 934 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 935 }; 936 }; 937 }; 938 }; 939 940 aips2: bus@30400000 { 941 compatible = "fsl,aips-bus", "simple-bus"; 942 reg = <0x30400000 0x400000>; 943 #address-cells = <1>; 944 #size-cells = <1>; 945 ranges; 946 947 pwm1: pwm@30660000 { 948 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 949 reg = <0x30660000 0x10000>; 950 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 952 <&clk IMX8MP_CLK_PWM1_ROOT>; 953 clock-names = "ipg", "per"; 954 #pwm-cells = <3>; 955 status = "disabled"; 956 }; 957 958 pwm2: pwm@30670000 { 959 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 960 reg = <0x30670000 0x10000>; 961 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 963 <&clk IMX8MP_CLK_PWM2_ROOT>; 964 clock-names = "ipg", "per"; 965 #pwm-cells = <3>; 966 status = "disabled"; 967 }; 968 969 pwm3: pwm@30680000 { 970 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 971 reg = <0x30680000 0x10000>; 972 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 974 <&clk IMX8MP_CLK_PWM3_ROOT>; 975 clock-names = "ipg", "per"; 976 #pwm-cells = <3>; 977 status = "disabled"; 978 }; 979 980 pwm4: pwm@30690000 { 981 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 982 reg = <0x30690000 0x10000>; 983 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 985 <&clk IMX8MP_CLK_PWM4_ROOT>; 986 clock-names = "ipg", "per"; 987 #pwm-cells = <3>; 988 status = "disabled"; 989 }; 990 991 system_counter: timer@306a0000 { 992 compatible = "nxp,sysctr-timer"; 993 reg = <0x306a0000 0x20000>; 994 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&osc_24m>; 996 clock-names = "per"; 997 }; 998 999 gpt6: timer@306e0000 { 1000 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1001 reg = <0x306e0000 0x10000>; 1002 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 1004 clock-names = "ipg", "per"; 1005 }; 1006 1007 gpt5: timer@306f0000 { 1008 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1009 reg = <0x306f0000 0x10000>; 1010 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 1012 clock-names = "ipg", "per"; 1013 }; 1014 1015 gpt4: timer@30700000 { 1016 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1017 reg = <0x30700000 0x10000>; 1018 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 1020 clock-names = "ipg", "per"; 1021 }; 1022 }; 1023 1024 aips3: bus@30800000 { 1025 compatible = "fsl,aips-bus", "simple-bus"; 1026 reg = <0x30800000 0x400000>; 1027 #address-cells = <1>; 1028 #size-cells = <1>; 1029 ranges; 1030 1031 spba-bus@30800000 { 1032 compatible = "fsl,spba-bus", "simple-bus"; 1033 reg = <0x30800000 0x100000>; 1034 #address-cells = <1>; 1035 #size-cells = <1>; 1036 ranges; 1037 1038 ecspi1: spi@30820000 { 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1042 reg = <0x30820000 0x10000>; 1043 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 1045 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 1046 clock-names = "ipg", "per"; 1047 assigned-clock-rates = <80000000>; 1048 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 1049 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1050 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 1051 dma-names = "rx", "tx"; 1052 status = "disabled"; 1053 }; 1054 1055 ecspi2: spi@30830000 { 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1059 reg = <0x30830000 0x10000>; 1060 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 1062 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 1063 clock-names = "ipg", "per"; 1064 assigned-clock-rates = <80000000>; 1065 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 1066 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1067 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1068 dma-names = "rx", "tx"; 1069 status = "disabled"; 1070 }; 1071 1072 ecspi3: spi@30840000 { 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1076 reg = <0x30840000 0x10000>; 1077 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 1079 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 1080 clock-names = "ipg", "per"; 1081 assigned-clock-rates = <80000000>; 1082 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 1083 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1084 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1085 dma-names = "rx", "tx"; 1086 status = "disabled"; 1087 }; 1088 1089 uart1: serial@30860000 { 1090 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1091 reg = <0x30860000 0x10000>; 1092 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 1094 <&clk IMX8MP_CLK_UART1_ROOT>; 1095 clock-names = "ipg", "per"; 1096 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1097 dma-names = "rx", "tx"; 1098 status = "disabled"; 1099 }; 1100 1101 uart3: serial@30880000 { 1102 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1103 reg = <0x30880000 0x10000>; 1104 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 1106 <&clk IMX8MP_CLK_UART3_ROOT>; 1107 clock-names = "ipg", "per"; 1108 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1109 dma-names = "rx", "tx"; 1110 status = "disabled"; 1111 }; 1112 1113 uart2: serial@30890000 { 1114 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1115 reg = <0x30890000 0x10000>; 1116 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 1118 <&clk IMX8MP_CLK_UART2_ROOT>; 1119 clock-names = "ipg", "per"; 1120 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1121 dma-names = "rx", "tx"; 1122 status = "disabled"; 1123 }; 1124 1125 flexcan1: can@308c0000 { 1126 compatible = "fsl,imx8mp-flexcan"; 1127 reg = <0x308c0000 0x10000>; 1128 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1130 <&clk IMX8MP_CLK_CAN1_ROOT>; 1131 clock-names = "ipg", "per"; 1132 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 1133 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1134 assigned-clock-rates = <40000000>; 1135 fsl,clk-source = /bits/ 8 <0>; 1136 fsl,stop-mode = <&gpr 0x10 4>; 1137 status = "disabled"; 1138 }; 1139 1140 flexcan2: can@308d0000 { 1141 compatible = "fsl,imx8mp-flexcan"; 1142 reg = <0x308d0000 0x10000>; 1143 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1145 <&clk IMX8MP_CLK_CAN2_ROOT>; 1146 clock-names = "ipg", "per"; 1147 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 1148 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1149 assigned-clock-rates = <40000000>; 1150 fsl,clk-source = /bits/ 8 <0>; 1151 fsl,stop-mode = <&gpr 0x10 5>; 1152 status = "disabled"; 1153 }; 1154 }; 1155 1156 crypto: crypto@30900000 { 1157 compatible = "fsl,sec-v4.0"; 1158 #address-cells = <1>; 1159 #size-cells = <1>; 1160 reg = <0x30900000 0x40000>; 1161 ranges = <0 0x30900000 0x40000>; 1162 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&clk IMX8MP_CLK_AHB>, 1164 <&clk IMX8MP_CLK_IPG_ROOT>; 1165 clock-names = "aclk", "ipg"; 1166 1167 sec_jr0: jr@1000 { 1168 compatible = "fsl,sec-v4.0-job-ring"; 1169 reg = <0x1000 0x1000>; 1170 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1171 status = "disabled"; 1172 }; 1173 1174 sec_jr1: jr@2000 { 1175 compatible = "fsl,sec-v4.0-job-ring"; 1176 reg = <0x2000 0x1000>; 1177 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1178 }; 1179 1180 sec_jr2: jr@3000 { 1181 compatible = "fsl,sec-v4.0-job-ring"; 1182 reg = <0x3000 0x1000>; 1183 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1184 }; 1185 }; 1186 1187 i2c1: i2c@30a20000 { 1188 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 reg = <0x30a20000 0x10000>; 1192 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 1194 status = "disabled"; 1195 }; 1196 1197 i2c2: i2c@30a30000 { 1198 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 reg = <0x30a30000 0x10000>; 1202 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 1204 status = "disabled"; 1205 }; 1206 1207 i2c3: i2c@30a40000 { 1208 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 reg = <0x30a40000 0x10000>; 1212 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 1214 status = "disabled"; 1215 }; 1216 1217 i2c4: i2c@30a50000 { 1218 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 reg = <0x30a50000 0x10000>; 1222 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 1224 status = "disabled"; 1225 }; 1226 1227 uart4: serial@30a60000 { 1228 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1229 reg = <0x30a60000 0x10000>; 1230 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 1232 <&clk IMX8MP_CLK_UART4_ROOT>; 1233 clock-names = "ipg", "per"; 1234 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1235 dma-names = "rx", "tx"; 1236 status = "disabled"; 1237 }; 1238 1239 mu: mailbox@30aa0000 { 1240 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1241 reg = <0x30aa0000 0x10000>; 1242 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1243 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 1244 #mbox-cells = <2>; 1245 }; 1246 1247 mu2: mailbox@30e60000 { 1248 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1249 reg = <0x30e60000 0x10000>; 1250 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1251 #mbox-cells = <2>; 1252 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; 1253 status = "disabled"; 1254 }; 1255 1256 i2c5: i2c@30ad0000 { 1257 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 reg = <0x30ad0000 0x10000>; 1261 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1263 status = "disabled"; 1264 }; 1265 1266 i2c6: i2c@30ae0000 { 1267 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 reg = <0x30ae0000 0x10000>; 1271 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1272 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1273 status = "disabled"; 1274 }; 1275 1276 usdhc1: mmc@30b40000 { 1277 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1278 reg = <0x30b40000 0x10000>; 1279 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1280 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1281 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1282 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1283 clock-names = "ipg", "ahb", "per"; 1284 fsl,tuning-start-tap = <20>; 1285 fsl,tuning-step = <2>; 1286 bus-width = <4>; 1287 status = "disabled"; 1288 }; 1289 1290 usdhc2: mmc@30b50000 { 1291 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1292 reg = <0x30b50000 0x10000>; 1293 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1295 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1296 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1297 clock-names = "ipg", "ahb", "per"; 1298 fsl,tuning-start-tap = <20>; 1299 fsl,tuning-step = <2>; 1300 bus-width = <4>; 1301 status = "disabled"; 1302 }; 1303 1304 usdhc3: mmc@30b60000 { 1305 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1306 reg = <0x30b60000 0x10000>; 1307 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1309 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1310 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1311 clock-names = "ipg", "ahb", "per"; 1312 fsl,tuning-start-tap = <20>; 1313 fsl,tuning-step = <2>; 1314 bus-width = <4>; 1315 status = "disabled"; 1316 }; 1317 1318 flexspi: spi@30bb0000 { 1319 compatible = "nxp,imx8mp-fspi"; 1320 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1321 reg-names = "fspi_base", "fspi_mmap"; 1322 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1323 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1324 <&clk IMX8MP_CLK_QSPI_ROOT>; 1325 clock-names = "fspi_en", "fspi"; 1326 assigned-clock-rates = <80000000>; 1327 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 sdma1: dma-controller@30bd0000 { 1334 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1335 reg = <0x30bd0000 0x10000>; 1336 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1337 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1338 <&clk IMX8MP_CLK_AHB>; 1339 clock-names = "ipg", "ahb"; 1340 #dma-cells = <3>; 1341 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1342 }; 1343 1344 fec: ethernet@30be0000 { 1345 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1346 reg = <0x30be0000 0x10000>; 1347 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1351 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1352 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1353 <&clk IMX8MP_CLK_ENET_TIMER>, 1354 <&clk IMX8MP_CLK_ENET_REF>, 1355 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1356 clock-names = "ipg", "ahb", "ptp", 1357 "enet_clk_ref", "enet_out"; 1358 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1359 <&clk IMX8MP_CLK_ENET_TIMER>, 1360 <&clk IMX8MP_CLK_ENET_REF>, 1361 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1362 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1363 <&clk IMX8MP_SYS_PLL2_100M>, 1364 <&clk IMX8MP_SYS_PLL2_125M>, 1365 <&clk IMX8MP_SYS_PLL2_50M>; 1366 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1367 fsl,num-tx-queues = <3>; 1368 fsl,num-rx-queues = <3>; 1369 nvmem-cells = <ð_mac1>; 1370 nvmem-cell-names = "mac-address"; 1371 fsl,stop-mode = <&gpr 0x10 3>; 1372 status = "disabled"; 1373 }; 1374 1375 eqos: ethernet@30bf0000 { 1376 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1377 reg = <0x30bf0000 0x10000>; 1378 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1380 interrupt-names = "macirq", "eth_wake_irq"; 1381 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1382 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1383 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1384 <&clk IMX8MP_CLK_ENET_QOS>; 1385 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1386 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1387 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1388 <&clk IMX8MP_CLK_ENET_QOS>; 1389 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1390 <&clk IMX8MP_SYS_PLL2_100M>, 1391 <&clk IMX8MP_SYS_PLL2_125M>; 1392 assigned-clock-rates = <0>, <100000000>, <125000000>; 1393 nvmem-cells = <ð_mac2>; 1394 nvmem-cell-names = "mac-address"; 1395 intf_mode = <&gpr 0x4>; 1396 status = "disabled"; 1397 }; 1398 }; 1399 1400 aips5: bus@30c00000 { 1401 compatible = "fsl,aips-bus", "simple-bus"; 1402 reg = <0x30c00000 0x400000>; 1403 #address-cells = <1>; 1404 #size-cells = <1>; 1405 ranges; 1406 1407 spba-bus@30c00000 { 1408 compatible = "fsl,spba-bus", "simple-bus"; 1409 reg = <0x30c00000 0x100000>; 1410 #address-cells = <1>; 1411 #size-cells = <1>; 1412 ranges; 1413 1414 sai1: sai@30c10000 { 1415 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1416 reg = <0x30c10000 0x10000>; 1417 #sound-dai-cells = <0>; 1418 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, 1419 <&clk IMX8MP_CLK_DUMMY>, 1420 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, 1421 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, 1422 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; 1423 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1424 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 1425 dma-names = "rx", "tx"; 1426 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1427 status = "disabled"; 1428 }; 1429 1430 sai2: sai@30c20000 { 1431 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1432 reg = <0x30c20000 0x10000>; 1433 #sound-dai-cells = <0>; 1434 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, 1435 <&clk IMX8MP_CLK_DUMMY>, 1436 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, 1437 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, 1438 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; 1439 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1440 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 1441 dma-names = "rx", "tx"; 1442 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1443 status = "disabled"; 1444 }; 1445 1446 sai3: sai@30c30000 { 1447 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1448 reg = <0x30c30000 0x10000>; 1449 #sound-dai-cells = <0>; 1450 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 1451 <&clk IMX8MP_CLK_DUMMY>, 1452 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 1453 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, 1454 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; 1455 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1456 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 1457 dma-names = "rx", "tx"; 1458 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1459 status = "disabled"; 1460 }; 1461 1462 sai5: sai@30c50000 { 1463 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1464 reg = <0x30c50000 0x10000>; 1465 #sound-dai-cells = <0>; 1466 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, 1467 <&clk IMX8MP_CLK_DUMMY>, 1468 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, 1469 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, 1470 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; 1471 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1472 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 1473 dma-names = "rx", "tx"; 1474 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1475 status = "disabled"; 1476 }; 1477 1478 sai6: sai@30c60000 { 1479 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1480 reg = <0x30c60000 0x10000>; 1481 #sound-dai-cells = <0>; 1482 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, 1483 <&clk IMX8MP_CLK_DUMMY>, 1484 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, 1485 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, 1486 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; 1487 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1488 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 1489 dma-names = "rx", "tx"; 1490 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1491 status = "disabled"; 1492 }; 1493 1494 sai7: sai@30c80000 { 1495 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1496 reg = <0x30c80000 0x10000>; 1497 #sound-dai-cells = <0>; 1498 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, 1499 <&clk IMX8MP_CLK_DUMMY>, 1500 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, 1501 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, 1502 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; 1503 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1504 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 1505 dma-names = "rx", "tx"; 1506 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1507 status = "disabled"; 1508 }; 1509 1510 easrc: easrc@30c90000 { 1511 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; 1512 reg = <0x30c90000 0x10000>; 1513 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1514 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; 1515 clock-names = "mem"; 1516 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 1517 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 1518 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 1519 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 1520 dma-names = "ctx0_rx", "ctx0_tx", 1521 "ctx1_rx", "ctx1_tx", 1522 "ctx2_rx", "ctx2_tx", 1523 "ctx3_rx", "ctx3_tx"; 1524 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 1525 fsl,asrc-rate = <8000>; 1526 fsl,asrc-format = <2>; 1527 status = "disabled"; 1528 }; 1529 1530 micfil: audio-controller@30ca0000 { 1531 compatible = "fsl,imx8mp-micfil"; 1532 reg = <0x30ca0000 0x10000>; 1533 #sound-dai-cells = <0>; 1534 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1538 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, 1539 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, 1540 <&clk IMX8MP_AUDIO_PLL1_OUT>, 1541 <&clk IMX8MP_AUDIO_PLL2_OUT>, 1542 <&clk IMX8MP_CLK_EXT3>; 1543 clock-names = "ipg_clk", "ipg_clk_app", 1544 "pll8k", "pll11k", "clkext3"; 1545 dmas = <&sdma2 24 25 0x80000000>; 1546 dma-names = "rx"; 1547 status = "disabled"; 1548 }; 1549 1550 aud2htx: aud2htx@30cb0000 { 1551 compatible = "fsl,imx8mp-aud2htx"; 1552 reg = <0x30cb0000 0x10000>; 1553 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; 1555 clock-names = "bus"; 1556 dmas = <&sdma2 26 2 0>; 1557 dma-names = "tx"; 1558 status = "disabled"; 1559 }; 1560 1561 xcvr: xcvr@30cc0000 { 1562 compatible = "fsl,imx8mp-xcvr"; 1563 reg = <0x30cc0000 0x800>, 1564 <0x30cc0800 0x400>, 1565 <0x30cc0c00 0x080>, 1566 <0x30cc0e00 0x080>; 1567 reg-names = "ram", "regs", "rxfifo", 1568 "txfifo"; 1569 interrupts = /* XCVR IRQ 0 */ 1570 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1571 /* XCVR IRQ 1 */ 1572 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1573 /* XCVR PHY - SPDIF wakeup IRQ */ 1574 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1575 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>, 1576 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>, 1577 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, 1578 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; 1579 clock-names = "ipg", "phy", "spba", "pll_ipg"; 1580 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; 1581 dma-names = "rx", "tx"; 1582 resets = <&audio_blk_ctrl 0>; 1583 status = "disabled"; 1584 }; 1585 }; 1586 1587 sdma3: dma-controller@30e00000 { 1588 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1589 reg = <0x30e00000 0x10000>; 1590 #dma-cells = <3>; 1591 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, 1592 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1593 clock-names = "ipg", "ahb"; 1594 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1595 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1596 }; 1597 1598 sdma2: dma-controller@30e10000 { 1599 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1600 reg = <0x30e10000 0x10000>; 1601 #dma-cells = <3>; 1602 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, 1603 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1604 clock-names = "ipg", "ahb"; 1605 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1606 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1607 }; 1608 1609 audio_blk_ctrl: clock-controller@30e20000 { 1610 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1611 reg = <0x30e20000 0x10000>; 1612 #clock-cells = <1>; 1613 #reset-cells = <1>; 1614 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1615 <&clk IMX8MP_CLK_SAI1>, 1616 <&clk IMX8MP_CLK_SAI2>, 1617 <&clk IMX8MP_CLK_SAI3>, 1618 <&clk IMX8MP_CLK_SAI5>, 1619 <&clk IMX8MP_CLK_SAI6>, 1620 <&clk IMX8MP_CLK_SAI7>, 1621 <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; 1622 clock-names = "ahb", 1623 "sai1", "sai2", "sai3", 1624 "sai5", "sai6", "sai7", "axi"; 1625 power-domains = <&pgc_audio>; 1626 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, 1627 <&clk IMX8MP_AUDIO_PLL2>; 1628 assigned-clock-rates = <393216000>, <361267200>; 1629 }; 1630 }; 1631 1632 noc: interconnect@32700000 { 1633 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1634 reg = <0x32700000 0x100000>; 1635 clocks = <&clk IMX8MP_CLK_NOC>; 1636 #interconnect-cells = <1>; 1637 operating-points-v2 = <&noc_opp_table>; 1638 1639 noc_opp_table: opp-table { 1640 compatible = "operating-points-v2"; 1641 1642 opp-200000000 { 1643 opp-hz = /bits/ 64 <200000000>; 1644 }; 1645 1646 /* Nominal drive mode maximum */ 1647 opp-800000000 { 1648 opp-hz = /bits/ 64 <800000000>; 1649 }; 1650 1651 /* Overdrive mode maximum */ 1652 opp-1000000000 { 1653 opp-hz = /bits/ 64 <1000000000>; 1654 }; 1655 }; 1656 }; 1657 1658 aips4: bus@32c00000 { 1659 compatible = "fsl,aips-bus", "simple-bus"; 1660 reg = <0x32c00000 0x400000>; 1661 #address-cells = <1>; 1662 #size-cells = <1>; 1663 ranges; 1664 1665 isi_0: isi@32e00000 { 1666 compatible = "fsl,imx8mp-isi"; 1667 reg = <0x32e00000 0x4000>; 1668 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1670 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1671 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1672 clock-names = "axi", "apb"; 1673 fsl,blk-ctrl = <&media_blk_ctrl>; 1674 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; 1675 status = "disabled"; 1676 1677 ports { 1678 #address-cells = <1>; 1679 #size-cells = <0>; 1680 1681 port@0 { 1682 reg = <0>; 1683 1684 isi_in_0: endpoint { 1685 remote-endpoint = <&mipi_csi_0_out>; 1686 }; 1687 }; 1688 1689 port@1 { 1690 reg = <1>; 1691 1692 isi_in_1: endpoint { 1693 remote-endpoint = <&mipi_csi_1_out>; 1694 }; 1695 }; 1696 }; 1697 }; 1698 1699 isp_0: isp@32e10000 { 1700 compatible = "fsl,imx8mp-isp"; 1701 reg = <0x32e10000 0x10000>; 1702 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1703 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1704 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1705 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1706 clock-names = "isp", "aclk", "hclk"; 1707 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; 1708 fsl,blk-ctrl = <&media_blk_ctrl 0>; 1709 status = "disabled"; 1710 1711 ports { 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 1715 port@1 { 1716 reg = <1>; 1717 }; 1718 }; 1719 }; 1720 1721 isp_1: isp@32e20000 { 1722 compatible = "fsl,imx8mp-isp"; 1723 reg = <0x32e20000 0x10000>; 1724 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1725 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1726 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1727 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1728 clock-names = "isp", "aclk", "hclk"; 1729 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; 1730 fsl,blk-ctrl = <&media_blk_ctrl 1>; 1731 status = "disabled"; 1732 1733 ports { 1734 #address-cells = <1>; 1735 #size-cells = <0>; 1736 1737 port@1 { 1738 reg = <1>; 1739 }; 1740 }; 1741 }; 1742 1743 dewarp: dwe@32e30000 { 1744 compatible = "nxp,imx8mp-dw100"; 1745 reg = <0x32e30000 0x10000>; 1746 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1747 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1748 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1749 clock-names = "axi", "ahb"; 1750 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; 1751 }; 1752 1753 mipi_csi_0: csi@32e40000 { 1754 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1755 reg = <0x32e40000 0x10000>; 1756 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1757 clock-frequency = <250000000>; 1758 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1759 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1760 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1761 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1762 clock-names = "pclk", "wrap", "phy", "axi"; 1763 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, 1764 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1765 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, 1766 <&clk IMX8MP_CLK_24M>; 1767 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1768 status = "disabled"; 1769 1770 ports { 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 1774 port@0 { 1775 reg = <0>; 1776 }; 1777 1778 port@1 { 1779 reg = <1>; 1780 1781 mipi_csi_0_out: endpoint { 1782 remote-endpoint = <&isi_in_0>; 1783 }; 1784 }; 1785 }; 1786 }; 1787 1788 mipi_csi_1: csi@32e50000 { 1789 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1790 reg = <0x32e50000 0x10000>; 1791 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1792 clock-frequency = <250000000>; 1793 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1794 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1795 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1796 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1797 clock-names = "pclk", "wrap", "phy", "axi"; 1798 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, 1799 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1800 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, 1801 <&clk IMX8MP_CLK_24M>; 1802 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1803 status = "disabled"; 1804 1805 ports { 1806 #address-cells = <1>; 1807 #size-cells = <0>; 1808 1809 port@0 { 1810 reg = <0>; 1811 }; 1812 1813 port@1 { 1814 reg = <1>; 1815 1816 mipi_csi_1_out: endpoint { 1817 remote-endpoint = <&isi_in_1>; 1818 }; 1819 }; 1820 }; 1821 }; 1822 1823 mipi_dsi: dsi@32e60000 { 1824 compatible = "fsl,imx8mp-mipi-dsim"; 1825 reg = <0x32e60000 0x400>; 1826 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1827 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1828 clock-names = "bus_clk", "sclk_mipi"; 1829 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1830 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1831 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1832 <&clk IMX8MP_CLK_24M>; 1833 assigned-clock-rates = <200000000>, <24000000>; 1834 samsung,pll-clock-frequency = <24000000>; 1835 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1836 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1837 status = "disabled"; 1838 1839 ports { 1840 #address-cells = <1>; 1841 #size-cells = <0>; 1842 1843 port@0 { 1844 reg = <0>; 1845 1846 dsim_from_lcdif1: endpoint { 1847 remote-endpoint = <&lcdif1_to_dsim>; 1848 }; 1849 }; 1850 1851 port@1 { 1852 reg = <1>; 1853 1854 mipi_dsi_out: endpoint { 1855 }; 1856 }; 1857 }; 1858 }; 1859 1860 lcdif1: display-controller@32e80000 { 1861 compatible = "fsl,imx8mp-lcdif"; 1862 reg = <0x32e80000 0x10000>; 1863 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1864 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1865 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1866 clock-names = "pix", "axi", "disp_axi"; 1867 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1868 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1869 status = "disabled"; 1870 1871 port { 1872 lcdif1_to_dsim: endpoint { 1873 remote-endpoint = <&dsim_from_lcdif1>; 1874 }; 1875 }; 1876 }; 1877 1878 lcdif2: display-controller@32e90000 { 1879 compatible = "fsl,imx8mp-lcdif"; 1880 reg = <0x32e90000 0x10000>; 1881 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1882 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1883 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1884 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1885 clock-names = "pix", "axi", "disp_axi"; 1886 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1887 status = "disabled"; 1888 1889 port { 1890 lcdif2_to_ldb: endpoint { 1891 remote-endpoint = <&ldb_from_lcdif2>; 1892 }; 1893 }; 1894 }; 1895 1896 media_blk_ctrl: blk-ctrl@32ec0000 { 1897 compatible = "fsl,imx8mp-media-blk-ctrl", 1898 "syscon"; 1899 reg = <0x32ec0000 0x10000>; 1900 #address-cells = <1>; 1901 #size-cells = <1>; 1902 power-domains = <&pgc_mediamix>, 1903 <&pgc_mipi_phy1>, 1904 <&pgc_mipi_phy1>, 1905 <&pgc_mediamix>, 1906 <&pgc_mediamix>, 1907 <&pgc_mipi_phy2>, 1908 <&pgc_mediamix>, 1909 <&pgc_ispdwp>, 1910 <&pgc_ispdwp>, 1911 <&pgc_mipi_phy2>; 1912 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1913 "lcdif1", "isi", "mipi-csi2", 1914 "lcdif2", "isp", "dwe", 1915 "mipi-dsi2"; 1916 interconnects = 1917 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1918 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1919 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1920 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1921 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1922 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1923 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1924 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1925 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1926 "isi1", "isi2", "isp0", "isp1", 1927 "dwe"; 1928 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1929 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1930 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1931 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1932 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1933 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1934 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1935 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1936 clock-names = "apb", "axi", "cam1", "cam2", 1937 "disp1", "disp2", "isp", "phy"; 1938 1939 /* 1940 * The ISP maximum frequency is 400MHz in normal mode 1941 * and 500MHz in overdrive mode. The 400MHz operating 1942 * point hasn't been successfully tested yet, so set 1943 * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. 1944 */ 1945 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1946 <&clk IMX8MP_CLK_MEDIA_APB>, 1947 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1948 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1949 <&clk IMX8MP_CLK_MEDIA_ISP>, 1950 <&clk IMX8MP_VIDEO_PLL1>; 1951 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1952 <&clk IMX8MP_SYS_PLL1_800M>, 1953 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1954 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1955 <&clk IMX8MP_SYS_PLL2_500M>; 1956 assigned-clock-rates = <500000000>, <200000000>, 1957 <0>, <0>, <500000000>, 1958 <1039500000>; 1959 #power-domain-cells = <1>; 1960 1961 lvds_bridge: bridge@5c { 1962 compatible = "fsl,imx8mp-ldb"; 1963 reg = <0x5c 0x4>, <0x128 0x4>; 1964 reg-names = "ldb", "lvds"; 1965 clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; 1966 clock-names = "ldb"; 1967 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1968 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1969 status = "disabled"; 1970 1971 ports { 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 1975 port@0 { 1976 reg = <0>; 1977 1978 ldb_from_lcdif2: endpoint { 1979 remote-endpoint = <&lcdif2_to_ldb>; 1980 }; 1981 }; 1982 1983 port@1 { 1984 reg = <1>; 1985 1986 ldb_lvds_ch0: endpoint { 1987 }; 1988 }; 1989 1990 port@2 { 1991 reg = <2>; 1992 1993 ldb_lvds_ch1: endpoint { 1994 }; 1995 }; 1996 }; 1997 }; 1998 }; 1999 2000 pcie_phy: pcie-phy@32f00000 { 2001 compatible = "fsl,imx8mp-pcie-phy"; 2002 reg = <0x32f00000 0x10000>; 2003 resets = <&src IMX8MP_RESET_PCIEPHY>, 2004 <&src IMX8MP_RESET_PCIEPHY_PERST>; 2005 reset-names = "pciephy", "perst"; 2006 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 2007 #phy-cells = <0>; 2008 status = "disabled"; 2009 }; 2010 2011 hsio_blk_ctrl: blk-ctrl@32f10000 { 2012 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 2013 reg = <0x32f10000 0x24>; 2014 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2015 <&clk IMX8MP_CLK_PCIE_ROOT>; 2016 clock-names = "usb", "pcie"; 2017 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 2018 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 2019 <&pgc_hsiomix>, <&pgc_pcie_phy>; 2020 power-domain-names = "bus", "usb", "usb-phy1", 2021 "usb-phy2", "pcie", "pcie-phy"; 2022 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 2023 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 2024 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 2025 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 2026 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 2027 #power-domain-cells = <1>; 2028 #clock-cells = <0>; 2029 }; 2030 2031 hdmi_blk_ctrl: blk-ctrl@32fc0000 { 2032 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; 2033 reg = <0x32fc0000 0x1000>; 2034 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2035 <&clk IMX8MP_CLK_HDMI_ROOT>, 2036 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2037 <&clk IMX8MP_CLK_HDMI_24M>, 2038 <&clk IMX8MP_CLK_HDMI_FDCC_TST>; 2039 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; 2040 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, 2041 <&pgc_hdmimix>, <&pgc_hdmimix>, 2042 <&pgc_hdmimix>, <&pgc_hdmimix>, 2043 <&pgc_hdmimix>, <&pgc_hdmi_phy>, 2044 <&pgc_hdmimix>, <&pgc_hdmimix>; 2045 power-domain-names = "bus", "irqsteer", "lcdif", 2046 "pai", "pvi", "trng", 2047 "hdmi-tx", "hdmi-tx-phy", 2048 "hdcp", "hrv"; 2049 #power-domain-cells = <1>; 2050 }; 2051 2052 irqsteer_hdmi: interrupt-controller@32fc2000 { 2053 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer"; 2054 reg = <0x32fc2000 0x1000>; 2055 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 2056 interrupt-controller; 2057 #interrupt-cells = <1>; 2058 fsl,channel = <1>; 2059 fsl,num-irqs = <64>; 2060 clocks = <&clk IMX8MP_CLK_HDMI_APB>; 2061 clock-names = "ipg"; 2062 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; 2063 }; 2064 2065 hdmi_pvi: display-bridge@32fc4000 { 2066 compatible = "fsl,imx8mp-hdmi-pvi"; 2067 reg = <0x32fc4000 0x1000>; 2068 interrupt-parent = <&irqsteer_hdmi>; 2069 interrupts = <12>; 2070 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; 2071 status = "disabled"; 2072 2073 ports { 2074 #address-cells = <1>; 2075 #size-cells = <0>; 2076 2077 port@0 { 2078 reg = <0>; 2079 pvi_from_lcdif3: endpoint { 2080 remote-endpoint = <&lcdif3_to_pvi>; 2081 }; 2082 }; 2083 2084 port@1 { 2085 reg = <1>; 2086 pvi_to_hdmi_tx: endpoint { 2087 remote-endpoint = <&hdmi_tx_from_pvi>; 2088 }; 2089 }; 2090 }; 2091 }; 2092 2093 lcdif3: display-controller@32fc6000 { 2094 compatible = "fsl,imx8mp-lcdif"; 2095 reg = <0x32fc6000 0x1000>; 2096 interrupt-parent = <&irqsteer_hdmi>; 2097 interrupts = <8>; 2098 clocks = <&hdmi_tx_phy>, 2099 <&clk IMX8MP_CLK_HDMI_APB>, 2100 <&clk IMX8MP_CLK_HDMI_ROOT>; 2101 clock-names = "pix", "axi", "disp_axi"; 2102 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; 2103 status = "disabled"; 2104 2105 port { 2106 lcdif3_to_pvi: endpoint { 2107 remote-endpoint = <&pvi_from_lcdif3>; 2108 }; 2109 }; 2110 }; 2111 2112 hdmi_tx: hdmi@32fd8000 { 2113 compatible = "fsl,imx8mp-hdmi-tx"; 2114 reg = <0x32fd8000 0x7eff>; 2115 interrupt-parent = <&irqsteer_hdmi>; 2116 interrupts = <0>; 2117 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2118 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2119 <&clk IMX8MP_CLK_32K>, 2120 <&hdmi_tx_phy>; 2121 clock-names = "iahb", "isfr", "cec", "pix"; 2122 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; 2123 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; 2124 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; 2125 reg-io-width = <1>; 2126 status = "disabled"; 2127 2128 ports { 2129 #address-cells = <1>; 2130 #size-cells = <0>; 2131 2132 port@0 { 2133 reg = <0>; 2134 2135 hdmi_tx_from_pvi: endpoint { 2136 remote-endpoint = <&pvi_to_hdmi_tx>; 2137 }; 2138 }; 2139 2140 port@1 { 2141 reg = <1>; 2142 /* Point endpoint to the HDMI connector */ 2143 }; 2144 }; 2145 }; 2146 2147 hdmi_tx_phy: phy@32fdff00 { 2148 compatible = "fsl,imx8mp-hdmi-phy"; 2149 reg = <0x32fdff00 0x100>; 2150 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2151 <&clk IMX8MP_CLK_HDMI_24M>; 2152 clock-names = "apb", "ref"; 2153 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; 2154 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2155 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; 2156 #clock-cells = <0>; 2157 #phy-cells = <0>; 2158 status = "disabled"; 2159 }; 2160 }; 2161 2162 pcie0: pcie: pcie@33800000 { 2163 compatible = "fsl,imx8mp-pcie"; 2164 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 2165 reg-names = "dbi", "config"; 2166 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2167 <&clk IMX8MP_CLK_HSIO_AXI>, 2168 <&clk IMX8MP_CLK_PCIE_ROOT>; 2169 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2170 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2171 assigned-clock-rates = <10000000>; 2172 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2173 #address-cells = <3>; 2174 #size-cells = <2>; 2175 device_type = "pci"; 2176 bus-range = <0x00 0xff>; 2177 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 2178 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 2179 num-lanes = <1>; 2180 num-viewport = <4>; 2181 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2182 interrupt-names = "msi"; 2183 #interrupt-cells = <1>; 2184 interrupt-map-mask = <0 0 0 0x7>; 2185 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2186 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2187 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2188 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2189 fsl,max-link-speed = <3>; 2190 linux,pci-domain = <0>; 2191 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2192 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2193 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2194 reset-names = "apps", "turnoff"; 2195 phys = <&pcie_phy>; 2196 phy-names = "pcie-phy"; 2197 status = "disabled"; 2198 }; 2199 2200 pcie0_ep: pcie_ep: pcie-ep@33800000 { 2201 compatible = "fsl,imx8mp-pcie-ep"; 2202 reg = <0x33800000 0x100000>, 2203 <0x18000000 0x8000000>, 2204 <0x33900000 0x100000>, 2205 <0x33b00000 0x100000>; 2206 reg-names = "dbi", "addr_space", "dbi2", "atu"; 2207 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2208 <&clk IMX8MP_CLK_HSIO_AXI>, 2209 <&clk IMX8MP_CLK_PCIE_ROOT>; 2210 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2211 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2212 assigned-clock-rates = <10000000>; 2213 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2214 num-lanes = <1>; 2215 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 2216 interrupt-names = "dma"; 2217 fsl,max-link-speed = <3>; 2218 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2219 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2220 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2221 reset-names = "apps", "turnoff"; 2222 phys = <&pcie_phy>; 2223 phy-names = "pcie-phy"; 2224 num-ib-windows = <4>; 2225 num-ob-windows = <4>; 2226 status = "disabled"; 2227 }; 2228 2229 gpu3d: gpu@38000000 { 2230 compatible = "vivante,gc"; 2231 reg = <0x38000000 0x8000>; 2232 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2233 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 2234 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 2235 <&clk IMX8MP_CLK_GPU_ROOT>, 2236 <&clk IMX8MP_CLK_GPU_AHB>; 2237 clock-names = "core", "shader", "bus", "reg"; 2238 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 2239 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 2240 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 2241 <&clk IMX8MP_SYS_PLL2_1000M>; 2242 assigned-clock-rates = <1000000000>, <1000000000>; 2243 power-domains = <&pgc_gpu3d>; 2244 }; 2245 2246 gpu2d: gpu@38008000 { 2247 compatible = "vivante,gc"; 2248 reg = <0x38008000 0x8000>; 2249 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2250 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 2251 <&clk IMX8MP_CLK_GPU_ROOT>, 2252 <&clk IMX8MP_CLK_GPU_AHB>; 2253 clock-names = "core", "bus", "reg"; 2254 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 2255 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 2256 assigned-clock-rates = <1000000000>; 2257 power-domains = <&pgc_gpu2d>; 2258 }; 2259 2260 vpu_g1: video-codec@38300000 { 2261 compatible = "nxp,imx8mm-vpu-g1"; 2262 reg = <0x38300000 0x10000>; 2263 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2264 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 2265 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 2266 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2267 assigned-clock-rates = <600000000>; 2268 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 2269 }; 2270 2271 vpu_g2: video-codec@38310000 { 2272 compatible = "nxp,imx8mq-vpu-g2"; 2273 reg = <0x38310000 0x10000>; 2274 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2275 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 2276 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 2277 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 2278 assigned-clock-rates = <500000000>; 2279 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 2280 }; 2281 2282 vpumix_blk_ctrl: blk-ctrl@38330000 { 2283 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 2284 reg = <0x38330000 0x100>; 2285 #power-domain-cells = <1>; 2286 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 2287 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 2288 power-domain-names = "bus", "g1", "g2", "vc8000e"; 2289 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 2290 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 2291 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 2292 clock-names = "g1", "g2", "vc8000e"; 2293 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 2294 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2295 assigned-clock-rates = <600000000>, <600000000>; 2296 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 2297 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 2298 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 2299 interconnect-names = "g1", "g2", "vc8000e"; 2300 }; 2301 2302 npu: npu@38500000 { 2303 compatible = "vivante,gc"; 2304 reg = <0x38500000 0x200000>; 2305 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2306 clocks = <&clk IMX8MP_CLK_NPU_ROOT>, 2307 <&clk IMX8MP_CLK_NPU_ROOT>, 2308 <&clk IMX8MP_CLK_ML_AXI>, 2309 <&clk IMX8MP_CLK_ML_AHB>; 2310 clock-names = "core", "shader", "bus", "reg"; 2311 power-domains = <&pgc_mlmix>; 2312 }; 2313 2314 gic: interrupt-controller@38800000 { 2315 compatible = "arm,gic-v3"; 2316 reg = <0x38800000 0x10000>, 2317 <0x38880000 0xc0000>; 2318 #interrupt-cells = <3>; 2319 interrupt-controller; 2320 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2321 interrupt-parent = <&gic>; 2322 }; 2323 2324 edacmc: memory-controller@3d400000 { 2325 compatible = "snps,ddrc-3.80a"; 2326 reg = <0x3d400000 0x400000>; 2327 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2328 }; 2329 2330 ddr-pmu@3d800000 { 2331 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 2332 reg = <0x3d800000 0x400000>; 2333 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2334 }; 2335 2336 usb3_phy0: usb-phy@381f0040 { 2337 compatible = "fsl,imx8mp-usb-phy"; 2338 reg = <0x381f0040 0x40>; 2339 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2340 clock-names = "phy"; 2341 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2342 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2343 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 2344 #phy-cells = <0>; 2345 status = "disabled"; 2346 }; 2347 2348 usb3_0: usb@32f10100 { 2349 compatible = "fsl,imx8mp-dwc3"; 2350 reg = <0x32f10100 0x8>, 2351 <0x381f0000 0x20>; 2352 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2353 <&clk IMX8MP_CLK_USB_SUSP>; 2354 clock-names = "hsio", "suspend"; 2355 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2356 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2357 #address-cells = <1>; 2358 #size-cells = <1>; 2359 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2360 ranges; 2361 status = "disabled"; 2362 2363 usb_dwc3_0: usb@38100000 { 2364 compatible = "snps,dwc3"; 2365 reg = <0x38100000 0x10000>; 2366 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2367 <&clk IMX8MP_CLK_USB_CORE_REF>, 2368 <&clk IMX8MP_CLK_USB_SUSP>; 2369 clock-names = "bus_early", "ref", "suspend"; 2370 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2371 phys = <&usb3_phy0>, <&usb3_phy0>; 2372 phy-names = "usb2-phy", "usb3-phy"; 2373 snps,gfladj-refclk-lpm-sel-quirk; 2374 snps,parkmode-disable-ss-quirk; 2375 }; 2376 2377 }; 2378 2379 usb3_phy1: usb-phy@382f0040 { 2380 compatible = "fsl,imx8mp-usb-phy"; 2381 reg = <0x382f0040 0x40>; 2382 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2383 clock-names = "phy"; 2384 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2385 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2386 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 2387 #phy-cells = <0>; 2388 status = "disabled"; 2389 }; 2390 2391 usb3_1: usb@32f10108 { 2392 compatible = "fsl,imx8mp-dwc3"; 2393 reg = <0x32f10108 0x8>, 2394 <0x382f0000 0x20>; 2395 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2396 <&clk IMX8MP_CLK_USB_SUSP>; 2397 clock-names = "hsio", "suspend"; 2398 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2399 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2400 #address-cells = <1>; 2401 #size-cells = <1>; 2402 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2403 ranges; 2404 status = "disabled"; 2405 2406 usb_dwc3_1: usb@38200000 { 2407 compatible = "snps,dwc3"; 2408 reg = <0x38200000 0x10000>; 2409 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2410 <&clk IMX8MP_CLK_USB_CORE_REF>, 2411 <&clk IMX8MP_CLK_USB_SUSP>; 2412 clock-names = "bus_early", "ref", "suspend"; 2413 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 2414 phys = <&usb3_phy1>, <&usb3_phy1>; 2415 phy-names = "usb2-phy", "usb3-phy"; 2416 snps,gfladj-refclk-lpm-sel-quirk; 2417 snps,parkmode-disable-ss-quirk; 2418 }; 2419 }; 2420 2421 dsp: dsp@3b6e8000 { 2422 compatible = "fsl,imx8mp-hifi4"; 2423 reg = <0x3b6e8000 0x88000>; 2424 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, 2425 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, 2426 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, 2427 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>; 2428 clock-names = "ipg", "ocram", "core", "debug"; 2429 power-domains = <&pgc_audio>; 2430 mbox-names = "tx", "rx", "rxdb"; 2431 mboxes = <&mu2 0 0>, <&mu2 1 0>, <&mu2 3 0>; 2432 firmware-name = "imx/dsp/hifi4.bin"; 2433 resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; 2434 reset-names = "runstall"; 2435 status = "disabled"; 2436 }; 2437 }; 2438}; 2439