xref: /linux/include/linux/nvme.h (revision 8a61cb6e150ea907b580a1b5e705decb0a3ffc86)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Definitions for the NVM Express interface
4  * Copyright (c) 2011-2014, Intel Corporation.
5  */
6 
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9 
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
13 
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN	256
16 
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE		223
19 
20 #define NVMF_TRSVCID_SIZE	32
21 #define NVMF_TRADDR_SIZE	256
22 #define NVMF_TSAS_SIZE		256
23 
24 #define NVME_DISC_SUBSYS_NAME	"nqn.2014-08.org.nvmexpress.discovery"
25 
26 #define NVME_NSID_ALL		0xffffffff
27 
28 /* Special NSSR value, 'NVMe' */
29 #define NVME_SUBSYS_RESET	0x4E564D65
30 
31 enum nvme_subsys_type {
32 	/* Referral to another discovery type target subsystem */
33 	NVME_NQN_DISC	= 1,
34 
35 	/* NVME type target subsystem */
36 	NVME_NQN_NVME	= 2,
37 
38 	/* Current discovery type target subsystem */
39 	NVME_NQN_CURR	= 3,
40 };
41 
42 enum nvme_ctrl_type {
43 	NVME_CTRL_IO	= 1,		/* I/O controller */
44 	NVME_CTRL_DISC	= 2,		/* Discovery controller */
45 	NVME_CTRL_ADMIN	= 3,		/* Administrative controller */
46 };
47 
48 enum nvme_dctype {
49 	NVME_DCTYPE_NOT_REPORTED	= 0,
50 	NVME_DCTYPE_DDC			= 1, /* Direct Discovery Controller */
51 	NVME_DCTYPE_CDC			= 2, /* Central Discovery Controller */
52 };
53 
54 /* Address Family codes for Discovery Log Page entry ADRFAM field */
55 enum {
56 	NVMF_ADDR_FAMILY_PCI	= 0,	/* PCIe */
57 	NVMF_ADDR_FAMILY_IP4	= 1,	/* IP4 */
58 	NVMF_ADDR_FAMILY_IP6	= 2,	/* IP6 */
59 	NVMF_ADDR_FAMILY_IB	= 3,	/* InfiniBand */
60 	NVMF_ADDR_FAMILY_FC	= 4,	/* Fibre Channel */
61 	NVMF_ADDR_FAMILY_LOOP	= 254,	/* Reserved for host usage */
62 	NVMF_ADDR_FAMILY_MAX,
63 };
64 
65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
66 enum {
67 	NVMF_TRTYPE_PCI		= 0,	/* PCI */
68 	NVMF_TRTYPE_RDMA	= 1,	/* RDMA */
69 	NVMF_TRTYPE_FC		= 2,	/* Fibre Channel */
70 	NVMF_TRTYPE_TCP		= 3,	/* TCP/IP */
71 	NVMF_TRTYPE_LOOP	= 254,	/* Reserved for host usage */
72 	NVMF_TRTYPE_MAX,
73 };
74 
75 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
76 enum {
77 	NVMF_TREQ_NOT_SPECIFIED	= 0,		/* Not specified */
78 	NVMF_TREQ_REQUIRED	= 1,		/* Required */
79 	NVMF_TREQ_NOT_REQUIRED	= 2,		/* Not Required */
80 #define NVME_TREQ_SECURE_CHANNEL_MASK \
81 	(NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
82 
83 	NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),	/* Supports SQ flow control disable */
84 };
85 
86 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
87  * RDMA_QPTYPE field
88  */
89 enum {
90 	NVMF_RDMA_QPTYPE_CONNECTED	= 1, /* Reliable Connected */
91 	NVMF_RDMA_QPTYPE_DATAGRAM	= 2, /* Reliable Datagram */
92 	NVMF_RDMA_QPTYPE_INVALID	= 0xff,
93 };
94 
95 /* RDMA Provider Type codes for Discovery Log Page entry TSAS
96  * RDMA_PRTYPE field
97  */
98 enum {
99 	NVMF_RDMA_PRTYPE_NOT_SPECIFIED	= 1, /* No Provider Specified */
100 	NVMF_RDMA_PRTYPE_IB		= 2, /* InfiniBand */
101 	NVMF_RDMA_PRTYPE_ROCE		= 3, /* InfiniBand RoCE */
102 	NVMF_RDMA_PRTYPE_ROCEV2		= 4, /* InfiniBand RoCEV2 */
103 	NVMF_RDMA_PRTYPE_IWARP		= 5, /* IWARP */
104 };
105 
106 /* RDMA Connection Management Service Type codes for Discovery Log Page
107  * entry TSAS RDMA_CMS field
108  */
109 enum {
110 	NVMF_RDMA_CMS_RDMA_CM	= 1, /* Sockets based endpoint addressing */
111 };
112 
113 /* TSAS SECTYPE for TCP transport */
114 enum {
115 	NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
116 	NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
117 	NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
118 	NVMF_TCP_SECTYPE_INVALID = 0xff,
119 };
120 
121 #define NVME_AQ_DEPTH		32
122 #define NVME_NR_AEN_COMMANDS	1
123 #define NVME_AQ_BLK_MQ_DEPTH	(NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
124 
125 /*
126  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
127  * NVM-Express 1.2 specification, section 4.1.2.
128  */
129 #define NVME_AQ_MQ_TAG_DEPTH	(NVME_AQ_BLK_MQ_DEPTH - 1)
130 
131 enum {
132 	NVME_REG_CAP	= 0x0000,	/* Controller Capabilities */
133 	NVME_REG_VS	= 0x0008,	/* Version */
134 	NVME_REG_INTMS	= 0x000c,	/* Interrupt Mask Set */
135 	NVME_REG_INTMC	= 0x0010,	/* Interrupt Mask Clear */
136 	NVME_REG_CC	= 0x0014,	/* Controller Configuration */
137 	NVME_REG_CSTS	= 0x001c,	/* Controller Status */
138 	NVME_REG_NSSR	= 0x0020,	/* NVM Subsystem Reset */
139 	NVME_REG_AQA	= 0x0024,	/* Admin Queue Attributes */
140 	NVME_REG_ASQ	= 0x0028,	/* Admin SQ Base Address */
141 	NVME_REG_ACQ	= 0x0030,	/* Admin CQ Base Address */
142 	NVME_REG_CMBLOC	= 0x0038,	/* Controller Memory Buffer Location */
143 	NVME_REG_CMBSZ	= 0x003c,	/* Controller Memory Buffer Size */
144 	NVME_REG_BPINFO	= 0x0040,	/* Boot Partition Information */
145 	NVME_REG_BPRSEL	= 0x0044,	/* Boot Partition Read Select */
146 	NVME_REG_BPMBL	= 0x0048,	/* Boot Partition Memory Buffer
147 					 * Location
148 					 */
149 	NVME_REG_CMBMSC = 0x0050,	/* Controller Memory Buffer Memory
150 					 * Space Control
151 					 */
152 	NVME_REG_CRTO	= 0x0068,	/* Controller Ready Timeouts */
153 	NVME_REG_PMRCAP	= 0x0e00,	/* Persistent Memory Capabilities */
154 	NVME_REG_PMRCTL	= 0x0e04,	/* Persistent Memory Region Control */
155 	NVME_REG_PMRSTS	= 0x0e08,	/* Persistent Memory Region Status */
156 	NVME_REG_PMREBS	= 0x0e0c,	/* Persistent Memory Region Elasticity
157 					 * Buffer Size
158 					 */
159 	NVME_REG_PMRSWTP = 0x0e10,	/* Persistent Memory Region Sustained
160 					 * Write Throughput
161 					 */
162 	NVME_REG_DBS	= 0x1000,	/* SQ 0 Tail Doorbell */
163 };
164 
165 #define NVME_CAP_MQES(cap)	((cap) & 0xffff)
166 #define NVME_CAP_TIMEOUT(cap)	(((cap) >> 24) & 0xff)
167 #define NVME_CAP_STRIDE(cap)	(((cap) >> 32) & 0xf)
168 #define NVME_CAP_NSSRC(cap)	(((cap) >> 36) & 0x1)
169 #define NVME_CAP_CSS(cap)	(((cap) >> 37) & 0xff)
170 #define NVME_CAP_MPSMIN(cap)	(((cap) >> 48) & 0xf)
171 #define NVME_CAP_MPSMAX(cap)	(((cap) >> 52) & 0xf)
172 #define NVME_CAP_CMBS(cap)	(((cap) >> 57) & 0x1)
173 
174 #define NVME_CMB_BIR(cmbloc)	((cmbloc) & 0x7)
175 #define NVME_CMB_OFST(cmbloc)	(((cmbloc) >> 12) & 0xfffff)
176 
177 #define NVME_CRTO_CRIMT(crto)	((crto) >> 16)
178 #define NVME_CRTO_CRWMT(crto)	((crto) & 0xffff)
179 
180 enum {
181 	NVME_CMBSZ_SQS		= 1 << 0,
182 	NVME_CMBSZ_CQS		= 1 << 1,
183 	NVME_CMBSZ_LISTS	= 1 << 2,
184 	NVME_CMBSZ_RDS		= 1 << 3,
185 	NVME_CMBSZ_WDS		= 1 << 4,
186 
187 	NVME_CMBSZ_SZ_SHIFT	= 12,
188 	NVME_CMBSZ_SZ_MASK	= 0xfffff,
189 
190 	NVME_CMBSZ_SZU_SHIFT	= 8,
191 	NVME_CMBSZ_SZU_MASK	= 0xf,
192 };
193 
194 /*
195  * Submission and Completion Queue Entry Sizes for the NVM command set.
196  * (In bytes and specified as a power of two (2^n)).
197  */
198 #define NVME_ADM_SQES       6
199 #define NVME_NVM_IOSQES		6
200 #define NVME_NVM_IOCQES		4
201 
202 /*
203  * Controller Configuration (CC) register (Offset 14h)
204  */
205 enum {
206 	/* Enable (EN): bit 0 */
207 	NVME_CC_ENABLE		= 1 << 0,
208 	NVME_CC_EN_SHIFT	= 0,
209 
210 	/* Bits 03:01 are reserved (NVMe Base Specification rev 2.1) */
211 
212 	/* I/O Command Set Selected (CSS): bits 06:04 */
213 	NVME_CC_CSS_SHIFT	= 4,
214 	NVME_CC_CSS_MASK	= 7 << NVME_CC_CSS_SHIFT,
215 	NVME_CC_CSS_NVM		= 0 << NVME_CC_CSS_SHIFT,
216 	NVME_CC_CSS_CSI		= 6 << NVME_CC_CSS_SHIFT,
217 
218 	/* Memory Page Size (MPS): bits 10:07 */
219 	NVME_CC_MPS_SHIFT	= 7,
220 	NVME_CC_MPS_MASK	= 0xf << NVME_CC_MPS_SHIFT,
221 
222 	/* Arbitration Mechanism Selected (AMS): bits 13:11 */
223 	NVME_CC_AMS_SHIFT	= 11,
224 	NVME_CC_AMS_MASK	= 7 << NVME_CC_AMS_SHIFT,
225 	NVME_CC_AMS_RR		= 0 << NVME_CC_AMS_SHIFT,
226 	NVME_CC_AMS_WRRU	= 1 << NVME_CC_AMS_SHIFT,
227 	NVME_CC_AMS_VS		= 7 << NVME_CC_AMS_SHIFT,
228 
229 	/* Shutdown Notification (SHN): bits 15:14 */
230 	NVME_CC_SHN_SHIFT	= 14,
231 	NVME_CC_SHN_MASK	= 3 << NVME_CC_SHN_SHIFT,
232 	NVME_CC_SHN_NONE	= 0 << NVME_CC_SHN_SHIFT,
233 	NVME_CC_SHN_NORMAL	= 1 << NVME_CC_SHN_SHIFT,
234 	NVME_CC_SHN_ABRUPT	= 2 << NVME_CC_SHN_SHIFT,
235 
236 	/* I/O Submission Queue Entry Size (IOSQES): bits 19:16 */
237 	NVME_CC_IOSQES_SHIFT	= 16,
238 	NVME_CC_IOSQES_MASK	= 0xf << NVME_CC_IOSQES_SHIFT,
239 	NVME_CC_IOSQES		= NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
240 
241 	/* I/O Completion Queue Entry Size (IOCQES): bits 23:20 */
242 	NVME_CC_IOCQES_SHIFT	= 20,
243 	NVME_CC_IOCQES_MASK	= 0xf << NVME_CC_IOCQES_SHIFT,
244 	NVME_CC_IOCQES		= NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
245 
246 	/* Controller Ready Independent of Media Enable (CRIME): bit 24 */
247 	NVME_CC_CRIME		= 1 << 24,
248 
249 	/* Bits 25:31 are reserved (NVMe Base Specification rev 2.1) */
250 };
251 
252 enum {
253 	NVME_CSTS_RDY		= 1 << 0,
254 	NVME_CSTS_CFS		= 1 << 1,
255 	NVME_CSTS_NSSRO		= 1 << 4,
256 	NVME_CSTS_PP		= 1 << 5,
257 	NVME_CSTS_SHST_NORMAL	= 0 << 2,
258 	NVME_CSTS_SHST_OCCUR	= 1 << 2,
259 	NVME_CSTS_SHST_CMPLT	= 2 << 2,
260 	NVME_CSTS_SHST_MASK	= 3 << 2,
261 };
262 
263 enum {
264 	NVME_CMBMSC_CRE		= 1 << 0,
265 	NVME_CMBMSC_CMSE	= 1 << 1,
266 };
267 
268 enum {
269 	NVME_CAP_CSS_NVM	= 1 << 0,
270 	NVME_CAP_CSS_CSI	= 1 << 6,
271 };
272 
273 enum {
274 	NVME_CAP_CRMS_CRWMS	= 1ULL << 59,
275 	NVME_CAP_CRMS_CRIMS	= 1ULL << 60,
276 };
277 
278 struct nvme_id_power_state {
279 	__le16			max_power;	/* centiwatts */
280 	__u8			rsvd2;
281 	__u8			flags;
282 	__le32			entry_lat;	/* microseconds */
283 	__le32			exit_lat;	/* microseconds */
284 	__u8			read_tput;
285 	__u8			read_lat;
286 	__u8			write_tput;
287 	__u8			write_lat;
288 	__le16			idle_power;
289 	__u8			idle_scale;
290 	__u8			rsvd19;
291 	__le16			active_power;
292 	__u8			active_work_scale;
293 	__u8			rsvd23[9];
294 };
295 
296 enum {
297 	NVME_PS_FLAGS_MAX_POWER_SCALE	= 1 << 0,
298 	NVME_PS_FLAGS_NON_OP_STATE	= 1 << 1,
299 };
300 
301 enum nvme_ctrl_attr {
302 	NVME_CTRL_ATTR_HID_128_BIT	= (1 << 0),
303 	NVME_CTRL_ATTR_TBKAS		= (1 << 6),
304 	NVME_CTRL_ATTR_ELBAS		= (1 << 15),
305 	NVME_CTRL_ATTR_RHII		= (1 << 18),
306 };
307 
308 struct nvme_id_ctrl {
309 	__le16			vid;
310 	__le16			ssvid;
311 	char			sn[20];
312 	char			mn[40];
313 	char			fr[8];
314 	__u8			rab;
315 	__u8			ieee[3];
316 	__u8			cmic;
317 	__u8			mdts;
318 	__le16			cntlid;
319 	__le32			ver;
320 	__le32			rtd3r;
321 	__le32			rtd3e;
322 	__le32			oaes;
323 	__le32			ctratt;
324 	__u8			rsvd100[11];
325 	__u8			cntrltype;
326 	__u8			fguid[16];
327 	__le16			crdt1;
328 	__le16			crdt2;
329 	__le16			crdt3;
330 	__u8			rsvd134[122];
331 	__le16			oacs;
332 	__u8			acl;
333 	__u8			aerl;
334 	__u8			frmw;
335 	__u8			lpa;
336 	__u8			elpe;
337 	__u8			npss;
338 	__u8			avscc;
339 	__u8			apsta;
340 	__le16			wctemp;
341 	__le16			cctemp;
342 	__le16			mtfa;
343 	__le32			hmpre;
344 	__le32			hmmin;
345 	__u8			tnvmcap[16];
346 	__u8			unvmcap[16];
347 	__le32			rpmbs;
348 	__le16			edstt;
349 	__u8			dsto;
350 	__u8			fwug;
351 	__le16			kas;
352 	__le16			hctma;
353 	__le16			mntmt;
354 	__le16			mxtmt;
355 	__le32			sanicap;
356 	__le32			hmminds;
357 	__le16			hmmaxd;
358 	__le16			nvmsetidmax;
359 	__le16			endgidmax;
360 	__u8			anatt;
361 	__u8			anacap;
362 	__le32			anagrpmax;
363 	__le32			nanagrpid;
364 	__u8			rsvd352[160];
365 	__u8			sqes;
366 	__u8			cqes;
367 	__le16			maxcmd;
368 	__le32			nn;
369 	__le16			oncs;
370 	__le16			fuses;
371 	__u8			fna;
372 	__u8			vwc;
373 	__le16			awun;
374 	__le16			awupf;
375 	__u8			nvscc;
376 	__u8			nwpc;
377 	__le16			acwu;
378 	__u8			rsvd534[2];
379 	__le32			sgls;
380 	__le32			mnan;
381 	__u8			rsvd544[224];
382 	char			subnqn[256];
383 	__u8			rsvd1024[768];
384 	__le32			ioccsz;
385 	__le32			iorcsz;
386 	__le16			icdoff;
387 	__u8			ctrattr;
388 	__u8			msdbd;
389 	__u8			rsvd1804[2];
390 	__u8			dctype;
391 	__u8			rsvd1807[241];
392 	struct nvme_id_power_state	psd[32];
393 	__u8			vs[1024];
394 };
395 
396 enum {
397 	NVME_CTRL_CMIC_MULTI_PORT		= 1 << 0,
398 	NVME_CTRL_CMIC_MULTI_CTRL		= 1 << 1,
399 	NVME_CTRL_CMIC_ANA			= 1 << 3,
400 	NVME_CTRL_ONCS_COMPARE			= 1 << 0,
401 	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE	= 1 << 1,
402 	NVME_CTRL_ONCS_DSM			= 1 << 2,
403 	NVME_CTRL_ONCS_WRITE_ZEROES		= 1 << 3,
404 	NVME_CTRL_ONCS_RESERVATIONS		= 1 << 5,
405 	NVME_CTRL_ONCS_TIMESTAMP		= 1 << 6,
406 	NVME_CTRL_VWC_PRESENT			= 1 << 0,
407 	NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
408 	NVME_CTRL_OACS_NS_MNGT_SUPP		= 1 << 3,
409 	NVME_CTRL_OACS_DIRECTIVES		= 1 << 5,
410 	NVME_CTRL_OACS_DBBUF_SUPP		= 1 << 8,
411 	NVME_CTRL_LPA_CMD_EFFECTS_LOG		= 1 << 1,
412 	NVME_CTRL_CTRATT_128_ID			= 1 << 0,
413 	NVME_CTRL_CTRATT_NON_OP_PSP		= 1 << 1,
414 	NVME_CTRL_CTRATT_NVM_SETS		= 1 << 2,
415 	NVME_CTRL_CTRATT_READ_RECV_LVLS		= 1 << 3,
416 	NVME_CTRL_CTRATT_ENDURANCE_GROUPS	= 1 << 4,
417 	NVME_CTRL_CTRATT_PREDICTABLE_LAT	= 1 << 5,
418 	NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY	= 1 << 7,
419 	NVME_CTRL_CTRATT_UUID_LIST		= 1 << 9,
420 	NVME_CTRL_SGLS_BYTE_ALIGNED             = 1,
421 	NVME_CTRL_SGLS_DWORD_ALIGNED            = 2,
422 	NVME_CTRL_SGLS_KSDBDS			= 1 << 2,
423 	NVME_CTRL_SGLS_MSDS                     = 1 << 19,
424 	NVME_CTRL_SGLS_SAOS                     = 1 << 20,
425 };
426 
427 struct nvme_lbaf {
428 	__le16			ms;
429 	__u8			ds;
430 	__u8			rp;
431 };
432 
433 struct nvme_id_ns {
434 	__le64			nsze;
435 	__le64			ncap;
436 	__le64			nuse;
437 	__u8			nsfeat;
438 	__u8			nlbaf;
439 	__u8			flbas;
440 	__u8			mc;
441 	__u8			dpc;
442 	__u8			dps;
443 	__u8			nmic;
444 	__u8			rescap;
445 	__u8			fpi;
446 	__u8			dlfeat;
447 	__le16			nawun;
448 	__le16			nawupf;
449 	__le16			nacwu;
450 	__le16			nabsn;
451 	__le16			nabo;
452 	__le16			nabspf;
453 	__le16			noiob;
454 	__u8			nvmcap[16];
455 	__le16			npwg;
456 	__le16			npwa;
457 	__le16			npdg;
458 	__le16			npda;
459 	__le16			nows;
460 	__u8			rsvd74[18];
461 	__le32			anagrpid;
462 	__u8			rsvd96[3];
463 	__u8			nsattr;
464 	__le16			nvmsetid;
465 	__le16			endgid;
466 	__u8			nguid[16];
467 	__u8			eui64[8];
468 	struct nvme_lbaf	lbaf[64];
469 	__u8			vs[3712];
470 };
471 
472 /* I/O Command Set Independent Identify Namespace Data Structure */
473 struct nvme_id_ns_cs_indep {
474 	__u8			nsfeat;
475 	__u8			nmic;
476 	__u8			rescap;
477 	__u8			fpi;
478 	__le32			anagrpid;
479 	__u8			nsattr;
480 	__u8			rsvd9;
481 	__le16			nvmsetid;
482 	__le16			endgid;
483 	__u8			nstat;
484 	__u8			rsvd15[4081];
485 };
486 
487 struct nvme_zns_lbafe {
488 	__le64			zsze;
489 	__u8			zdes;
490 	__u8			rsvd9[7];
491 };
492 
493 struct nvme_id_ns_zns {
494 	__le16			zoc;
495 	__le16			ozcs;
496 	__le32			mar;
497 	__le32			mor;
498 	__le32			rrl;
499 	__le32			frl;
500 	__u8			rsvd20[2796];
501 	struct nvme_zns_lbafe	lbafe[64];
502 	__u8			vs[256];
503 };
504 
505 struct nvme_id_ctrl_zns {
506 	__u8	zasl;
507 	__u8	rsvd1[4095];
508 };
509 
510 struct nvme_id_ns_nvm {
511 	__le64	lbstm;
512 	__u8	pic;
513 	__u8	rsvd9[3];
514 	__le32	elbaf[64];
515 	__u8	rsvd268[3828];
516 };
517 
518 enum {
519 	NVME_ID_NS_NVM_STS_MASK		= 0x7f,
520 	NVME_ID_NS_NVM_GUARD_SHIFT	= 7,
521 	NVME_ID_NS_NVM_GUARD_MASK	= 0x3,
522 	NVME_ID_NS_NVM_QPIF_SHIFT	= 9,
523 	NVME_ID_NS_NVM_QPIF_MASK	= 0xf,
524 	NVME_ID_NS_NVM_QPIFS		= 1 << 3,
525 };
526 
nvme_elbaf_sts(__u32 elbaf)527 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
528 {
529 	return elbaf & NVME_ID_NS_NVM_STS_MASK;
530 }
531 
nvme_elbaf_guard_type(__u32 elbaf)532 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
533 {
534 	return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
535 }
536 
nvme_elbaf_qualified_guard_type(__u32 elbaf)537 static inline __u8 nvme_elbaf_qualified_guard_type(__u32 elbaf)
538 {
539 	return (elbaf >> NVME_ID_NS_NVM_QPIF_SHIFT) & NVME_ID_NS_NVM_QPIF_MASK;
540 }
541 
542 struct nvme_id_ctrl_nvm {
543 	__u8	vsl;
544 	__u8	wzsl;
545 	__u8	wusl;
546 	__u8	dmrl;
547 	__le32	dmrsl;
548 	__le64	dmsl;
549 	__u8	rsvd16[4080];
550 };
551 
552 enum {
553 	NVME_ID_CNS_NS			= 0x00,
554 	NVME_ID_CNS_CTRL		= 0x01,
555 	NVME_ID_CNS_NS_ACTIVE_LIST	= 0x02,
556 	NVME_ID_CNS_NS_DESC_LIST	= 0x03,
557 	NVME_ID_CNS_CS_NS		= 0x05,
558 	NVME_ID_CNS_CS_CTRL		= 0x06,
559 	NVME_ID_CNS_NS_ACTIVE_LIST_CS	= 0x07,
560 	NVME_ID_CNS_NS_CS_INDEP		= 0x08,
561 	NVME_ID_CNS_NS_PRESENT_LIST	= 0x10,
562 	NVME_ID_CNS_NS_PRESENT		= 0x11,
563 	NVME_ID_CNS_CTRL_NS_LIST	= 0x12,
564 	NVME_ID_CNS_CTRL_LIST		= 0x13,
565 	NVME_ID_CNS_SCNDRY_CTRL_LIST	= 0x15,
566 	NVME_ID_CNS_NS_GRANULARITY	= 0x16,
567 	NVME_ID_CNS_UUID_LIST		= 0x17,
568 	NVME_ID_CNS_ENDGRP_LIST		= 0x19,
569 };
570 
571 enum {
572 	NVME_CSI_NVM			= 0,
573 	NVME_CSI_ZNS			= 2,
574 };
575 
576 enum {
577 	NVME_DIR_IDENTIFY		= 0x00,
578 	NVME_DIR_STREAMS		= 0x01,
579 	NVME_DIR_SND_ID_OP_ENABLE	= 0x01,
580 	NVME_DIR_SND_ST_OP_REL_ID	= 0x01,
581 	NVME_DIR_SND_ST_OP_REL_RSC	= 0x02,
582 	NVME_DIR_RCV_ID_OP_PARAM	= 0x01,
583 	NVME_DIR_RCV_ST_OP_PARAM	= 0x01,
584 	NVME_DIR_RCV_ST_OP_STATUS	= 0x02,
585 	NVME_DIR_RCV_ST_OP_RESOURCE	= 0x03,
586 	NVME_DIR_ENDIR			= 0x01,
587 };
588 
589 enum {
590 	NVME_NS_FEAT_THIN	= 1 << 0,
591 	NVME_NS_FEAT_ATOMICS	= 1 << 1,
592 	NVME_NS_FEAT_IO_OPT	= 1 << 4,
593 	NVME_NS_ATTR_RO		= 1 << 0,
594 	NVME_NS_FLBAS_LBA_MASK	= 0xf,
595 	NVME_NS_FLBAS_LBA_UMASK	= 0x60,
596 	NVME_NS_FLBAS_LBA_SHIFT	= 1,
597 	NVME_NS_FLBAS_META_EXT	= 0x10,
598 	NVME_NS_NMIC_SHARED	= 1 << 0,
599 	NVME_NS_ROTATIONAL	= 1 << 4,
600 	NVME_NS_VWC_NOT_PRESENT = 1 << 5,
601 	NVME_LBAF_RP_BEST	= 0,
602 	NVME_LBAF_RP_BETTER	= 1,
603 	NVME_LBAF_RP_GOOD	= 2,
604 	NVME_LBAF_RP_DEGRADED	= 3,
605 	NVME_NS_DPC_PI_LAST	= 1 << 4,
606 	NVME_NS_DPC_PI_FIRST	= 1 << 3,
607 	NVME_NS_DPC_PI_TYPE3	= 1 << 2,
608 	NVME_NS_DPC_PI_TYPE2	= 1 << 1,
609 	NVME_NS_DPC_PI_TYPE1	= 1 << 0,
610 	NVME_NS_DPS_PI_FIRST	= 1 << 3,
611 	NVME_NS_DPS_PI_MASK	= 0x7,
612 	NVME_NS_DPS_PI_TYPE1	= 1,
613 	NVME_NS_DPS_PI_TYPE2	= 2,
614 	NVME_NS_DPS_PI_TYPE3	= 3,
615 };
616 
617 enum {
618 	NVME_NSTAT_NRDY		= 1 << 0,
619 };
620 
621 enum {
622 	NVME_NVM_NS_16B_GUARD	= 0,
623 	NVME_NVM_NS_32B_GUARD	= 1,
624 	NVME_NVM_NS_64B_GUARD	= 2,
625 	NVME_NVM_NS_QTYPE_GUARD	= 3,
626 };
627 
nvme_lbaf_index(__u8 flbas)628 static inline __u8 nvme_lbaf_index(__u8 flbas)
629 {
630 	return (flbas & NVME_NS_FLBAS_LBA_MASK) |
631 		((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
632 }
633 
634 /* Identify Namespace Metadata Capabilities (MC): */
635 enum {
636 	NVME_MC_EXTENDED_LBA	= (1 << 0),
637 	NVME_MC_METADATA_PTR	= (1 << 1),
638 };
639 
640 struct nvme_ns_id_desc {
641 	__u8 nidt;
642 	__u8 nidl;
643 	__le16 reserved;
644 };
645 
646 #define NVME_NIDT_EUI64_LEN	8
647 #define NVME_NIDT_NGUID_LEN	16
648 #define NVME_NIDT_UUID_LEN	16
649 #define NVME_NIDT_CSI_LEN	1
650 
651 enum {
652 	NVME_NIDT_EUI64		= 0x01,
653 	NVME_NIDT_NGUID		= 0x02,
654 	NVME_NIDT_UUID		= 0x03,
655 	NVME_NIDT_CSI		= 0x04,
656 };
657 
658 struct nvme_endurance_group_log {
659 	__u8	egcw;
660 	__u8	egfeat;
661 	__u8	rsvd2;
662 	__u8	avsp;
663 	__u8	avspt;
664 	__u8	pused;
665 	__le16	did;
666 	__u8	rsvd8[24];
667 	__u8	ee[16];
668 	__u8	dur[16];
669 	__u8	duw[16];
670 	__u8	muw[16];
671 	__u8	hrc[16];
672 	__u8	hwc[16];
673 	__u8	mdie[16];
674 	__u8	neile[16];
675 	__u8	tegcap[16];
676 	__u8	uegcap[16];
677 	__u8	rsvd192[320];
678 };
679 
680 struct nvme_rotational_media_log {
681 	__le16	endgid;
682 	__le16	numa;
683 	__le16	nrs;
684 	__u8	rsvd6[2];
685 	__le32	spinc;
686 	__le32	fspinc;
687 	__le32	ldc;
688 	__le32	fldc;
689 	__u8	rsvd24[488];
690 };
691 
692 struct nvme_smart_log {
693 	__u8			critical_warning;
694 	__u8			temperature[2];
695 	__u8			avail_spare;
696 	__u8			spare_thresh;
697 	__u8			percent_used;
698 	__u8			endu_grp_crit_warn_sumry;
699 	__u8			rsvd7[25];
700 	__u8			data_units_read[16];
701 	__u8			data_units_written[16];
702 	__u8			host_reads[16];
703 	__u8			host_writes[16];
704 	__u8			ctrl_busy_time[16];
705 	__u8			power_cycles[16];
706 	__u8			power_on_hours[16];
707 	__u8			unsafe_shutdowns[16];
708 	__u8			media_errors[16];
709 	__u8			num_err_log_entries[16];
710 	__le32			warning_temp_time;
711 	__le32			critical_comp_time;
712 	__le16			temp_sensor[8];
713 	__le32			thm_temp1_trans_count;
714 	__le32			thm_temp2_trans_count;
715 	__le32			thm_temp1_total_time;
716 	__le32			thm_temp2_total_time;
717 	__u8			rsvd232[280];
718 };
719 
720 struct nvme_fw_slot_info_log {
721 	__u8			afi;
722 	__u8			rsvd1[7];
723 	__le64			frs[7];
724 	__u8			rsvd64[448];
725 };
726 
727 enum {
728 	NVME_CMD_EFFECTS_CSUPP		= 1 << 0,
729 	NVME_CMD_EFFECTS_LBCC		= 1 << 1,
730 	NVME_CMD_EFFECTS_NCC		= 1 << 2,
731 	NVME_CMD_EFFECTS_NIC		= 1 << 3,
732 	NVME_CMD_EFFECTS_CCC		= 1 << 4,
733 	NVME_CMD_EFFECTS_CSER_MASK	= GENMASK(15, 14),
734 	NVME_CMD_EFFECTS_CSE_MASK	= GENMASK(18, 16),
735 	NVME_CMD_EFFECTS_UUID_SEL	= 1 << 19,
736 	NVME_CMD_EFFECTS_SCOPE_MASK	= GENMASK(31, 20),
737 };
738 
739 struct nvme_effects_log {
740 	__le32 acs[256];
741 	__le32 iocs[256];
742 	__u8   resv[2048];
743 };
744 
745 enum nvme_ana_state {
746 	NVME_ANA_OPTIMIZED		= 0x01,
747 	NVME_ANA_NONOPTIMIZED		= 0x02,
748 	NVME_ANA_INACCESSIBLE		= 0x03,
749 	NVME_ANA_PERSISTENT_LOSS	= 0x04,
750 	NVME_ANA_CHANGE			= 0x0f,
751 };
752 
753 struct nvme_ana_group_desc {
754 	__le32	grpid;
755 	__le32	nnsids;
756 	__le64	chgcnt;
757 	__u8	state;
758 	__u8	rsvd17[15];
759 	__le32	nsids[];
760 };
761 
762 /* flag for the log specific field of the ANA log */
763 #define NVME_ANA_LOG_RGO	(1 << 0)
764 
765 struct nvme_ana_rsp_hdr {
766 	__le64	chgcnt;
767 	__le16	ngrps;
768 	__le16	rsvd10[3];
769 };
770 
771 struct nvme_zone_descriptor {
772 	__u8		zt;
773 	__u8		zs;
774 	__u8		za;
775 	__u8		rsvd3[5];
776 	__le64		zcap;
777 	__le64		zslba;
778 	__le64		wp;
779 	__u8		rsvd32[32];
780 };
781 
782 enum {
783 	NVME_ZONE_TYPE_SEQWRITE_REQ	= 0x2,
784 };
785 
786 struct nvme_zone_report {
787 	__le64		nr_zones;
788 	__u8		resv8[56];
789 	struct nvme_zone_descriptor entries[];
790 };
791 
792 enum {
793 	NVME_SMART_CRIT_SPARE		= 1 << 0,
794 	NVME_SMART_CRIT_TEMPERATURE	= 1 << 1,
795 	NVME_SMART_CRIT_RELIABILITY	= 1 << 2,
796 	NVME_SMART_CRIT_MEDIA		= 1 << 3,
797 	NVME_SMART_CRIT_VOLATILE_MEMORY	= 1 << 4,
798 };
799 
800 enum {
801 	NVME_AER_ERROR			= 0,
802 	NVME_AER_SMART			= 1,
803 	NVME_AER_NOTICE			= 2,
804 	NVME_AER_CSS			= 6,
805 	NVME_AER_VS			= 7,
806 };
807 
808 enum {
809 	NVME_AER_ERROR_PERSIST_INT_ERR	= 0x03,
810 };
811 
812 enum {
813 	NVME_AER_NOTICE_NS_CHANGED	= 0x00,
814 	NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
815 	NVME_AER_NOTICE_ANA		= 0x03,
816 	NVME_AER_NOTICE_DISC_CHANGED	= 0xf0,
817 };
818 
819 enum {
820 	NVME_AEN_BIT_NS_ATTR		= 8,
821 	NVME_AEN_BIT_FW_ACT		= 9,
822 	NVME_AEN_BIT_ANA_CHANGE		= 11,
823 	NVME_AEN_BIT_DISC_CHANGE	= 31,
824 };
825 
826 enum {
827 	NVME_AEN_CFG_NS_ATTR		= 1 << NVME_AEN_BIT_NS_ATTR,
828 	NVME_AEN_CFG_FW_ACT		= 1 << NVME_AEN_BIT_FW_ACT,
829 	NVME_AEN_CFG_ANA_CHANGE		= 1 << NVME_AEN_BIT_ANA_CHANGE,
830 	NVME_AEN_CFG_DISC_CHANGE	= 1 << NVME_AEN_BIT_DISC_CHANGE,
831 };
832 
833 struct nvme_lba_range_type {
834 	__u8			type;
835 	__u8			attributes;
836 	__u8			rsvd2[14];
837 	__le64			slba;
838 	__le64			nlb;
839 	__u8			guid[16];
840 	__u8			rsvd48[16];
841 };
842 
843 enum {
844 	NVME_LBART_TYPE_FS	= 0x01,
845 	NVME_LBART_TYPE_RAID	= 0x02,
846 	NVME_LBART_TYPE_CACHE	= 0x03,
847 	NVME_LBART_TYPE_SWAP	= 0x04,
848 
849 	NVME_LBART_ATTRIB_TEMP	= 1 << 0,
850 	NVME_LBART_ATTRIB_HIDE	= 1 << 1,
851 };
852 
853 enum nvme_pr_type {
854 	NVME_PR_WRITE_EXCLUSIVE			= 1,
855 	NVME_PR_EXCLUSIVE_ACCESS		= 2,
856 	NVME_PR_WRITE_EXCLUSIVE_REG_ONLY	= 3,
857 	NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY	= 4,
858 	NVME_PR_WRITE_EXCLUSIVE_ALL_REGS	= 5,
859 	NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS	= 6,
860 };
861 
862 enum nvme_eds {
863 	NVME_EXTENDED_DATA_STRUCT	= 0x1,
864 };
865 
866 struct nvme_registered_ctrl {
867 	__le16	cntlid;
868 	__u8	rcsts;
869 	__u8	rsvd3[5];
870 	__le64	hostid;
871 	__le64	rkey;
872 };
873 
874 struct nvme_reservation_status {
875 	__le32	gen;
876 	__u8	rtype;
877 	__u8	regctl[2];
878 	__u8	resv5[2];
879 	__u8	ptpls;
880 	__u8	resv10[14];
881 	struct nvme_registered_ctrl regctl_ds[];
882 };
883 
884 struct nvme_registered_ctrl_ext {
885 	__le16	cntlid;
886 	__u8	rcsts;
887 	__u8	rsvd3[5];
888 	__le64	rkey;
889 	__u8	hostid[16];
890 	__u8	rsvd32[32];
891 };
892 
893 struct nvme_reservation_status_ext {
894 	__le32	gen;
895 	__u8	rtype;
896 	__u8	regctl[2];
897 	__u8	resv5[2];
898 	__u8	ptpls;
899 	__u8	resv10[14];
900 	__u8	rsvd24[40];
901 	struct nvme_registered_ctrl_ext regctl_eds[];
902 };
903 
904 /* I/O commands */
905 
906 enum nvme_opcode {
907 	nvme_cmd_flush		= 0x00,
908 	nvme_cmd_write		= 0x01,
909 	nvme_cmd_read		= 0x02,
910 	nvme_cmd_write_uncor	= 0x04,
911 	nvme_cmd_compare	= 0x05,
912 	nvme_cmd_write_zeroes	= 0x08,
913 	nvme_cmd_dsm		= 0x09,
914 	nvme_cmd_verify		= 0x0c,
915 	nvme_cmd_resv_register	= 0x0d,
916 	nvme_cmd_resv_report	= 0x0e,
917 	nvme_cmd_resv_acquire	= 0x11,
918 	nvme_cmd_resv_release	= 0x15,
919 	nvme_cmd_zone_mgmt_send	= 0x79,
920 	nvme_cmd_zone_mgmt_recv	= 0x7a,
921 	nvme_cmd_zone_append	= 0x7d,
922 	nvme_cmd_vendor_start	= 0x80,
923 };
924 
925 #define nvme_opcode_name(opcode)	{ opcode, #opcode }
926 #define show_nvm_opcode_name(val)				\
927 	__print_symbolic(val,					\
928 		nvme_opcode_name(nvme_cmd_flush),		\
929 		nvme_opcode_name(nvme_cmd_write),		\
930 		nvme_opcode_name(nvme_cmd_read),		\
931 		nvme_opcode_name(nvme_cmd_write_uncor),		\
932 		nvme_opcode_name(nvme_cmd_compare),		\
933 		nvme_opcode_name(nvme_cmd_write_zeroes),	\
934 		nvme_opcode_name(nvme_cmd_dsm),			\
935 		nvme_opcode_name(nvme_cmd_verify),		\
936 		nvme_opcode_name(nvme_cmd_resv_register),	\
937 		nvme_opcode_name(nvme_cmd_resv_report),		\
938 		nvme_opcode_name(nvme_cmd_resv_acquire),	\
939 		nvme_opcode_name(nvme_cmd_resv_release),	\
940 		nvme_opcode_name(nvme_cmd_zone_mgmt_send),	\
941 		nvme_opcode_name(nvme_cmd_zone_mgmt_recv),	\
942 		nvme_opcode_name(nvme_cmd_zone_append))
943 
944 
945 
946 /*
947  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
948  *
949  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
950  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
951  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
952  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
953  *                            request subtype
954  */
955 enum {
956 	NVME_SGL_FMT_ADDRESS		= 0x00,
957 	NVME_SGL_FMT_OFFSET		= 0x01,
958 	NVME_SGL_FMT_TRANSPORT_A	= 0x0A,
959 	NVME_SGL_FMT_INVALIDATE		= 0x0f,
960 };
961 
962 /*
963  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
964  *
965  * For struct nvme_sgl_desc:
966  *   @NVME_SGL_FMT_DATA_DESC:		data block descriptor
967  *   @NVME_SGL_FMT_SEG_DESC:		sgl segment descriptor
968  *   @NVME_SGL_FMT_LAST_SEG_DESC:	last sgl segment descriptor
969  *
970  * For struct nvme_keyed_sgl_desc:
971  *   @NVME_KEY_SGL_FMT_DATA_DESC:	keyed data block descriptor
972  *
973  * Transport-specific SGL types:
974  *   @NVME_TRANSPORT_SGL_DATA_DESC:	Transport SGL data dlock descriptor
975  */
976 enum {
977 	NVME_SGL_FMT_DATA_DESC		= 0x00,
978 	NVME_SGL_FMT_SEG_DESC		= 0x02,
979 	NVME_SGL_FMT_LAST_SEG_DESC	= 0x03,
980 	NVME_KEY_SGL_FMT_DATA_DESC	= 0x04,
981 	NVME_TRANSPORT_SGL_DATA_DESC	= 0x05,
982 };
983 
984 struct nvme_sgl_desc {
985 	__le64	addr;
986 	__le32	length;
987 	__u8	rsvd[3];
988 	__u8	type;
989 };
990 
991 struct nvme_keyed_sgl_desc {
992 	__le64	addr;
993 	__u8	length[3];
994 	__u8	key[4];
995 	__u8	type;
996 };
997 
998 union nvme_data_ptr {
999 	struct {
1000 		__le64	prp1;
1001 		__le64	prp2;
1002 	};
1003 	struct nvme_sgl_desc	sgl;
1004 	struct nvme_keyed_sgl_desc ksgl;
1005 };
1006 
1007 /*
1008  * Lowest two bits of our flags field (FUSE field in the spec):
1009  *
1010  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
1011  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
1012  *
1013  * Highest two bits in our flags field (PSDT field in the spec):
1014  *
1015  * @NVME_CMD_PSDT_SGL_METABUF:	Use SGLS for this transfer,
1016  *	If used, MPTR contains addr of single physical buffer (byte aligned).
1017  * @NVME_CMD_PSDT_SGL_METASEG:	Use SGLS for this transfer,
1018  *	If used, MPTR contains an address of an SGL segment containing
1019  *	exactly 1 SGL descriptor (qword aligned).
1020  */
1021 enum {
1022 	NVME_CMD_FUSE_FIRST	= (1 << 0),
1023 	NVME_CMD_FUSE_SECOND	= (1 << 1),
1024 
1025 	NVME_CMD_SGL_METABUF	= (1 << 6),
1026 	NVME_CMD_SGL_METASEG	= (1 << 7),
1027 	NVME_CMD_SGL_ALL	= NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
1028 };
1029 
1030 struct nvme_common_command {
1031 	__u8			opcode;
1032 	__u8			flags;
1033 	__u16			command_id;
1034 	__le32			nsid;
1035 	__le32			cdw2[2];
1036 	__le64			metadata;
1037 	union nvme_data_ptr	dptr;
1038 	struct_group(cdws,
1039 	__le32			cdw10;
1040 	__le32			cdw11;
1041 	__le32			cdw12;
1042 	__le32			cdw13;
1043 	__le32			cdw14;
1044 	__le32			cdw15;
1045 	);
1046 };
1047 
1048 struct nvme_rw_command {
1049 	__u8			opcode;
1050 	__u8			flags;
1051 	__u16			command_id;
1052 	__le32			nsid;
1053 	__le32			cdw2;
1054 	__le32			cdw3;
1055 	__le64			metadata;
1056 	union nvme_data_ptr	dptr;
1057 	__le64			slba;
1058 	__le16			length;
1059 	__le16			control;
1060 	__le32			dsmgmt;
1061 	__le32			reftag;
1062 	__le16			lbat;
1063 	__le16			lbatm;
1064 };
1065 
1066 enum {
1067 	NVME_RW_LR			= 1 << 15,
1068 	NVME_RW_FUA			= 1 << 14,
1069 	NVME_RW_APPEND_PIREMAP		= 1 << 9,
1070 	NVME_RW_DSM_FREQ_UNSPEC		= 0,
1071 	NVME_RW_DSM_FREQ_TYPICAL	= 1,
1072 	NVME_RW_DSM_FREQ_RARE		= 2,
1073 	NVME_RW_DSM_FREQ_READS		= 3,
1074 	NVME_RW_DSM_FREQ_WRITES		= 4,
1075 	NVME_RW_DSM_FREQ_RW		= 5,
1076 	NVME_RW_DSM_FREQ_ONCE		= 6,
1077 	NVME_RW_DSM_FREQ_PREFETCH	= 7,
1078 	NVME_RW_DSM_FREQ_TEMP		= 8,
1079 	NVME_RW_DSM_LATENCY_NONE	= 0 << 4,
1080 	NVME_RW_DSM_LATENCY_IDLE	= 1 << 4,
1081 	NVME_RW_DSM_LATENCY_NORM	= 2 << 4,
1082 	NVME_RW_DSM_LATENCY_LOW		= 3 << 4,
1083 	NVME_RW_DSM_SEQ_REQ		= 1 << 6,
1084 	NVME_RW_DSM_COMPRESSED		= 1 << 7,
1085 	NVME_RW_PRINFO_PRCHK_REF	= 1 << 10,
1086 	NVME_RW_PRINFO_PRCHK_APP	= 1 << 11,
1087 	NVME_RW_PRINFO_PRCHK_GUARD	= 1 << 12,
1088 	NVME_RW_PRINFO_PRACT		= 1 << 13,
1089 	NVME_RW_DTYPE_STREAMS		= 1 << 4,
1090 	NVME_WZ_DEAC			= 1 << 9,
1091 };
1092 
1093 struct nvme_dsm_cmd {
1094 	__u8			opcode;
1095 	__u8			flags;
1096 	__u16			command_id;
1097 	__le32			nsid;
1098 	__u64			rsvd2[2];
1099 	union nvme_data_ptr	dptr;
1100 	__le32			nr;
1101 	__le32			attributes;
1102 	__u32			rsvd12[4];
1103 };
1104 
1105 enum {
1106 	NVME_DSMGMT_IDR		= 1 << 0,
1107 	NVME_DSMGMT_IDW		= 1 << 1,
1108 	NVME_DSMGMT_AD		= 1 << 2,
1109 };
1110 
1111 #define NVME_DSM_MAX_RANGES	256
1112 
1113 struct nvme_dsm_range {
1114 	__le32			cattr;
1115 	__le32			nlb;
1116 	__le64			slba;
1117 };
1118 
1119 struct nvme_write_zeroes_cmd {
1120 	__u8			opcode;
1121 	__u8			flags;
1122 	__u16			command_id;
1123 	__le32			nsid;
1124 	__u64			rsvd2;
1125 	__le64			metadata;
1126 	union nvme_data_ptr	dptr;
1127 	__le64			slba;
1128 	__le16			length;
1129 	__le16			control;
1130 	__le32			dsmgmt;
1131 	__le32			reftag;
1132 	__le16			lbat;
1133 	__le16			lbatm;
1134 };
1135 
1136 enum nvme_zone_mgmt_action {
1137 	NVME_ZONE_CLOSE		= 0x1,
1138 	NVME_ZONE_FINISH	= 0x2,
1139 	NVME_ZONE_OPEN		= 0x3,
1140 	NVME_ZONE_RESET		= 0x4,
1141 	NVME_ZONE_OFFLINE	= 0x5,
1142 	NVME_ZONE_SET_DESC_EXT	= 0x10,
1143 };
1144 
1145 struct nvme_zone_mgmt_send_cmd {
1146 	__u8			opcode;
1147 	__u8			flags;
1148 	__u16			command_id;
1149 	__le32			nsid;
1150 	__le32			cdw2[2];
1151 	__le64			metadata;
1152 	union nvme_data_ptr	dptr;
1153 	__le64			slba;
1154 	__le32			cdw12;
1155 	__u8			zsa;
1156 	__u8			select_all;
1157 	__u8			rsvd13[2];
1158 	__le32			cdw14[2];
1159 };
1160 
1161 struct nvme_zone_mgmt_recv_cmd {
1162 	__u8			opcode;
1163 	__u8			flags;
1164 	__u16			command_id;
1165 	__le32			nsid;
1166 	__le64			rsvd2[2];
1167 	union nvme_data_ptr	dptr;
1168 	__le64			slba;
1169 	__le32			numd;
1170 	__u8			zra;
1171 	__u8			zrasf;
1172 	__u8			pr;
1173 	__u8			rsvd13;
1174 	__le32			cdw14[2];
1175 };
1176 
1177 enum {
1178 	NVME_ZRA_ZONE_REPORT		= 0,
1179 	NVME_ZRASF_ZONE_REPORT_ALL	= 0,
1180 	NVME_ZRASF_ZONE_STATE_EMPTY	= 0x01,
1181 	NVME_ZRASF_ZONE_STATE_IMP_OPEN	= 0x02,
1182 	NVME_ZRASF_ZONE_STATE_EXP_OPEN	= 0x03,
1183 	NVME_ZRASF_ZONE_STATE_CLOSED	= 0x04,
1184 	NVME_ZRASF_ZONE_STATE_READONLY	= 0x05,
1185 	NVME_ZRASF_ZONE_STATE_FULL	= 0x06,
1186 	NVME_ZRASF_ZONE_STATE_OFFLINE	= 0x07,
1187 	NVME_REPORT_ZONE_PARTIAL	= 1,
1188 };
1189 
1190 /* Features */
1191 
1192 enum {
1193 	NVME_TEMP_THRESH_MASK		= 0xffff,
1194 	NVME_TEMP_THRESH_SELECT_SHIFT	= 16,
1195 	NVME_TEMP_THRESH_TYPE_UNDER	= 0x100000,
1196 };
1197 
1198 struct nvme_feat_auto_pst {
1199 	__le64 entries[32];
1200 };
1201 
1202 enum {
1203 	NVME_HOST_MEM_ENABLE	= (1 << 0),
1204 	NVME_HOST_MEM_RETURN	= (1 << 1),
1205 };
1206 
1207 struct nvme_feat_host_behavior {
1208 	__u8 acre;
1209 	__u8 etdas;
1210 	__u8 lbafee;
1211 	__u8 resv1[509];
1212 };
1213 
1214 enum {
1215 	NVME_ENABLE_ACRE	= 1,
1216 	NVME_ENABLE_LBAFEE	= 1,
1217 };
1218 
1219 /* Admin commands */
1220 
1221 enum nvme_admin_opcode {
1222 	nvme_admin_delete_sq		= 0x00,
1223 	nvme_admin_create_sq		= 0x01,
1224 	nvme_admin_get_log_page		= 0x02,
1225 	nvme_admin_delete_cq		= 0x04,
1226 	nvme_admin_create_cq		= 0x05,
1227 	nvme_admin_identify		= 0x06,
1228 	nvme_admin_abort_cmd		= 0x08,
1229 	nvme_admin_set_features		= 0x09,
1230 	nvme_admin_get_features		= 0x0a,
1231 	nvme_admin_async_event		= 0x0c,
1232 	nvme_admin_ns_mgmt		= 0x0d,
1233 	nvme_admin_activate_fw		= 0x10,
1234 	nvme_admin_download_fw		= 0x11,
1235 	nvme_admin_dev_self_test	= 0x14,
1236 	nvme_admin_ns_attach		= 0x15,
1237 	nvme_admin_keep_alive		= 0x18,
1238 	nvme_admin_directive_send	= 0x19,
1239 	nvme_admin_directive_recv	= 0x1a,
1240 	nvme_admin_virtual_mgmt		= 0x1c,
1241 	nvme_admin_nvme_mi_send		= 0x1d,
1242 	nvme_admin_nvme_mi_recv		= 0x1e,
1243 	nvme_admin_dbbuf		= 0x7C,
1244 	nvme_admin_format_nvm		= 0x80,
1245 	nvme_admin_security_send	= 0x81,
1246 	nvme_admin_security_recv	= 0x82,
1247 	nvme_admin_sanitize_nvm		= 0x84,
1248 	nvme_admin_get_lba_status	= 0x86,
1249 	nvme_admin_vendor_start		= 0xC0,
1250 };
1251 
1252 #define nvme_admin_opcode_name(opcode)	{ opcode, #opcode }
1253 #define show_admin_opcode_name(val)					\
1254 	__print_symbolic(val,						\
1255 		nvme_admin_opcode_name(nvme_admin_delete_sq),		\
1256 		nvme_admin_opcode_name(nvme_admin_create_sq),		\
1257 		nvme_admin_opcode_name(nvme_admin_get_log_page),	\
1258 		nvme_admin_opcode_name(nvme_admin_delete_cq),		\
1259 		nvme_admin_opcode_name(nvme_admin_create_cq),		\
1260 		nvme_admin_opcode_name(nvme_admin_identify),		\
1261 		nvme_admin_opcode_name(nvme_admin_abort_cmd),		\
1262 		nvme_admin_opcode_name(nvme_admin_set_features),	\
1263 		nvme_admin_opcode_name(nvme_admin_get_features),	\
1264 		nvme_admin_opcode_name(nvme_admin_async_event),		\
1265 		nvme_admin_opcode_name(nvme_admin_ns_mgmt),		\
1266 		nvme_admin_opcode_name(nvme_admin_activate_fw),		\
1267 		nvme_admin_opcode_name(nvme_admin_download_fw),		\
1268 		nvme_admin_opcode_name(nvme_admin_dev_self_test),	\
1269 		nvme_admin_opcode_name(nvme_admin_ns_attach),		\
1270 		nvme_admin_opcode_name(nvme_admin_keep_alive),		\
1271 		nvme_admin_opcode_name(nvme_admin_directive_send),	\
1272 		nvme_admin_opcode_name(nvme_admin_directive_recv),	\
1273 		nvme_admin_opcode_name(nvme_admin_virtual_mgmt),	\
1274 		nvme_admin_opcode_name(nvme_admin_nvme_mi_send),	\
1275 		nvme_admin_opcode_name(nvme_admin_nvme_mi_recv),	\
1276 		nvme_admin_opcode_name(nvme_admin_dbbuf),		\
1277 		nvme_admin_opcode_name(nvme_admin_format_nvm),		\
1278 		nvme_admin_opcode_name(nvme_admin_security_send),	\
1279 		nvme_admin_opcode_name(nvme_admin_security_recv),	\
1280 		nvme_admin_opcode_name(nvme_admin_sanitize_nvm),	\
1281 		nvme_admin_opcode_name(nvme_admin_get_lba_status))
1282 
1283 enum {
1284 	NVME_QUEUE_PHYS_CONTIG	= (1 << 0),
1285 	NVME_CQ_IRQ_ENABLED	= (1 << 1),
1286 	NVME_SQ_PRIO_URGENT	= (0 << 1),
1287 	NVME_SQ_PRIO_HIGH	= (1 << 1),
1288 	NVME_SQ_PRIO_MEDIUM	= (2 << 1),
1289 	NVME_SQ_PRIO_LOW	= (3 << 1),
1290 	NVME_FEAT_ARBITRATION	= 0x01,
1291 	NVME_FEAT_POWER_MGMT	= 0x02,
1292 	NVME_FEAT_LBA_RANGE	= 0x03,
1293 	NVME_FEAT_TEMP_THRESH	= 0x04,
1294 	NVME_FEAT_ERR_RECOVERY	= 0x05,
1295 	NVME_FEAT_VOLATILE_WC	= 0x06,
1296 	NVME_FEAT_NUM_QUEUES	= 0x07,
1297 	NVME_FEAT_IRQ_COALESCE	= 0x08,
1298 	NVME_FEAT_IRQ_CONFIG	= 0x09,
1299 	NVME_FEAT_WRITE_ATOMIC	= 0x0a,
1300 	NVME_FEAT_ASYNC_EVENT	= 0x0b,
1301 	NVME_FEAT_AUTO_PST	= 0x0c,
1302 	NVME_FEAT_HOST_MEM_BUF	= 0x0d,
1303 	NVME_FEAT_TIMESTAMP	= 0x0e,
1304 	NVME_FEAT_KATO		= 0x0f,
1305 	NVME_FEAT_HCTM		= 0x10,
1306 	NVME_FEAT_NOPSC		= 0x11,
1307 	NVME_FEAT_RRL		= 0x12,
1308 	NVME_FEAT_PLM_CONFIG	= 0x13,
1309 	NVME_FEAT_PLM_WINDOW	= 0x14,
1310 	NVME_FEAT_HOST_BEHAVIOR	= 0x16,
1311 	NVME_FEAT_SANITIZE	= 0x17,
1312 	NVME_FEAT_SW_PROGRESS	= 0x80,
1313 	NVME_FEAT_HOST_ID	= 0x81,
1314 	NVME_FEAT_RESV_MASK	= 0x82,
1315 	NVME_FEAT_RESV_PERSIST	= 0x83,
1316 	NVME_FEAT_WRITE_PROTECT	= 0x84,
1317 	NVME_FEAT_VENDOR_START	= 0xC0,
1318 	NVME_FEAT_VENDOR_END	= 0xFF,
1319 	NVME_LOG_SUPPORTED	= 0x00,
1320 	NVME_LOG_ERROR		= 0x01,
1321 	NVME_LOG_SMART		= 0x02,
1322 	NVME_LOG_FW_SLOT	= 0x03,
1323 	NVME_LOG_CHANGED_NS	= 0x04,
1324 	NVME_LOG_CMD_EFFECTS	= 0x05,
1325 	NVME_LOG_DEVICE_SELF_TEST = 0x06,
1326 	NVME_LOG_TELEMETRY_HOST = 0x07,
1327 	NVME_LOG_TELEMETRY_CTRL = 0x08,
1328 	NVME_LOG_ENDURANCE_GROUP = 0x09,
1329 	NVME_LOG_ANA		= 0x0c,
1330 	NVME_LOG_FEATURES	= 0x12,
1331 	NVME_LOG_RMI		= 0x16,
1332 	NVME_LOG_DISC		= 0x70,
1333 	NVME_LOG_RESERVATION	= 0x80,
1334 	NVME_FWACT_REPL		= (0 << 3),
1335 	NVME_FWACT_REPL_ACTV	= (1 << 3),
1336 	NVME_FWACT_ACTV		= (2 << 3),
1337 };
1338 
1339 struct nvme_supported_log {
1340 	__le32	lids[256];
1341 };
1342 
1343 enum {
1344 	NVME_LIDS_LSUPP	= 1 << 0,
1345 };
1346 
1347 struct nvme_supported_features_log {
1348 	__le32	fis[256];
1349 };
1350 
1351 enum {
1352 	NVME_FIS_FSUPP	= 1 << 0,
1353 	NVME_FIS_NSCPE	= 1 << 20,
1354 	NVME_FIS_CSCPE	= 1 << 21,
1355 };
1356 
1357 /* NVMe Namespace Write Protect State */
1358 enum {
1359 	NVME_NS_NO_WRITE_PROTECT = 0,
1360 	NVME_NS_WRITE_PROTECT,
1361 	NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1362 	NVME_NS_WRITE_PROTECT_PERMANENT,
1363 };
1364 
1365 #define NVME_MAX_CHANGED_NAMESPACES	1024
1366 
1367 struct nvme_identify {
1368 	__u8			opcode;
1369 	__u8			flags;
1370 	__u16			command_id;
1371 	__le32			nsid;
1372 	__u64			rsvd2[2];
1373 	union nvme_data_ptr	dptr;
1374 	__u8			cns;
1375 	__u8			rsvd3;
1376 	__le16			ctrlid;
1377 	__le16			cnssid;
1378 	__u8			rsvd11;
1379 	__u8			csi;
1380 	__u32			rsvd12[4];
1381 };
1382 
1383 #define NVME_IDENTIFY_DATA_SIZE 4096
1384 
1385 struct nvme_features {
1386 	__u8			opcode;
1387 	__u8			flags;
1388 	__u16			command_id;
1389 	__le32			nsid;
1390 	__u64			rsvd2[2];
1391 	union nvme_data_ptr	dptr;
1392 	__le32			fid;
1393 	__le32			dword11;
1394 	__le32                  dword12;
1395 	__le32                  dword13;
1396 	__le32                  dword14;
1397 	__le32                  dword15;
1398 };
1399 
1400 struct nvme_host_mem_buf_desc {
1401 	__le64			addr;
1402 	__le32			size;
1403 	__u32			rsvd;
1404 };
1405 
1406 struct nvme_create_cq {
1407 	__u8			opcode;
1408 	__u8			flags;
1409 	__u16			command_id;
1410 	__u32			rsvd1[5];
1411 	__le64			prp1;
1412 	__u64			rsvd8;
1413 	__le16			cqid;
1414 	__le16			qsize;
1415 	__le16			cq_flags;
1416 	__le16			irq_vector;
1417 	__u32			rsvd12[4];
1418 };
1419 
1420 struct nvme_create_sq {
1421 	__u8			opcode;
1422 	__u8			flags;
1423 	__u16			command_id;
1424 	__u32			rsvd1[5];
1425 	__le64			prp1;
1426 	__u64			rsvd8;
1427 	__le16			sqid;
1428 	__le16			qsize;
1429 	__le16			sq_flags;
1430 	__le16			cqid;
1431 	__u32			rsvd12[4];
1432 };
1433 
1434 struct nvme_delete_queue {
1435 	__u8			opcode;
1436 	__u8			flags;
1437 	__u16			command_id;
1438 	__u32			rsvd1[9];
1439 	__le16			qid;
1440 	__u16			rsvd10;
1441 	__u32			rsvd11[5];
1442 };
1443 
1444 struct nvme_abort_cmd {
1445 	__u8			opcode;
1446 	__u8			flags;
1447 	__u16			command_id;
1448 	__u32			rsvd1[9];
1449 	__le16			sqid;
1450 	__u16			cid;
1451 	__u32			rsvd11[5];
1452 };
1453 
1454 struct nvme_download_firmware {
1455 	__u8			opcode;
1456 	__u8			flags;
1457 	__u16			command_id;
1458 	__u32			rsvd1[5];
1459 	union nvme_data_ptr	dptr;
1460 	__le32			numd;
1461 	__le32			offset;
1462 	__u32			rsvd12[4];
1463 };
1464 
1465 struct nvme_format_cmd {
1466 	__u8			opcode;
1467 	__u8			flags;
1468 	__u16			command_id;
1469 	__le32			nsid;
1470 	__u64			rsvd2[4];
1471 	__le32			cdw10;
1472 	__u32			rsvd11[5];
1473 };
1474 
1475 struct nvme_get_log_page_command {
1476 	__u8			opcode;
1477 	__u8			flags;
1478 	__u16			command_id;
1479 	__le32			nsid;
1480 	__u64			rsvd2[2];
1481 	union nvme_data_ptr	dptr;
1482 	__u8			lid;
1483 	__u8			lsp; /* upper 4 bits reserved */
1484 	__le16			numdl;
1485 	__le16			numdu;
1486 	__le16			lsi;
1487 	union {
1488 		struct {
1489 			__le32 lpol;
1490 			__le32 lpou;
1491 		};
1492 		__le64 lpo;
1493 	};
1494 	__u8			rsvd14[3];
1495 	__u8			csi;
1496 	__u32			rsvd15;
1497 };
1498 
1499 struct nvme_directive_cmd {
1500 	__u8			opcode;
1501 	__u8			flags;
1502 	__u16			command_id;
1503 	__le32			nsid;
1504 	__u64			rsvd2[2];
1505 	union nvme_data_ptr	dptr;
1506 	__le32			numd;
1507 	__u8			doper;
1508 	__u8			dtype;
1509 	__le16			dspec;
1510 	__u8			endir;
1511 	__u8			tdtype;
1512 	__u16			rsvd15;
1513 
1514 	__u32			rsvd16[3];
1515 };
1516 
1517 /*
1518  * Fabrics subcommands.
1519  */
1520 enum nvmf_fabrics_opcode {
1521 	nvme_fabrics_command		= 0x7f,
1522 };
1523 
1524 enum nvmf_capsule_command {
1525 	nvme_fabrics_type_property_set	= 0x00,
1526 	nvme_fabrics_type_connect	= 0x01,
1527 	nvme_fabrics_type_property_get	= 0x04,
1528 	nvme_fabrics_type_auth_send	= 0x05,
1529 	nvme_fabrics_type_auth_receive	= 0x06,
1530 };
1531 
1532 #define nvme_fabrics_type_name(type)   { type, #type }
1533 #define show_fabrics_type_name(type)					\
1534 	__print_symbolic(type,						\
1535 		nvme_fabrics_type_name(nvme_fabrics_type_property_set),	\
1536 		nvme_fabrics_type_name(nvme_fabrics_type_connect),	\
1537 		nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1538 		nvme_fabrics_type_name(nvme_fabrics_type_auth_send),	\
1539 		nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1540 
1541 /*
1542  * If not fabrics command, fctype will be ignored.
1543  */
1544 #define show_opcode_name(qid, opcode, fctype)			\
1545 	((opcode) == nvme_fabrics_command ?			\
1546 	 show_fabrics_type_name(fctype) :			\
1547 	((qid) ?						\
1548 	 show_nvm_opcode_name(opcode) :				\
1549 	 show_admin_opcode_name(opcode)))
1550 
1551 struct nvmf_common_command {
1552 	__u8	opcode;
1553 	__u8	resv1;
1554 	__u16	command_id;
1555 	__u8	fctype;
1556 	__u8	resv2[35];
1557 	__u8	ts[24];
1558 };
1559 
1560 /*
1561  * The legal cntlid range a NVMe Target will provide.
1562  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1563  * Devices based on earlier specs did not have the subsystem concept;
1564  * therefore, those devices had their cntlid value set to 0 as a result.
1565  */
1566 #define NVME_CNTLID_MIN		1
1567 #define NVME_CNTLID_MAX		0xffef
1568 #define NVME_CNTLID_DYNAMIC	0xffff
1569 
1570 #define MAX_DISC_LOGS	255
1571 
1572 /* Discovery log page entry flags (EFLAGS): */
1573 enum {
1574 	NVME_DISC_EFLAGS_EPCSD		= (1 << 1),
1575 	NVME_DISC_EFLAGS_DUPRETINFO	= (1 << 0),
1576 };
1577 
1578 /* Discovery log page entry */
1579 struct nvmf_disc_rsp_page_entry {
1580 	__u8		trtype;
1581 	__u8		adrfam;
1582 	__u8		subtype;
1583 	__u8		treq;
1584 	__le16		portid;
1585 	__le16		cntlid;
1586 	__le16		asqsz;
1587 	__le16		eflags;
1588 	__u8		resv10[20];
1589 	char		trsvcid[NVMF_TRSVCID_SIZE];
1590 	__u8		resv64[192];
1591 	char		subnqn[NVMF_NQN_FIELD_LEN];
1592 	char		traddr[NVMF_TRADDR_SIZE];
1593 	union tsas {
1594 		char		common[NVMF_TSAS_SIZE];
1595 		struct rdma {
1596 			__u8	qptype;
1597 			__u8	prtype;
1598 			__u8	cms;
1599 			__u8	resv3[5];
1600 			__u16	pkey;
1601 			__u8	resv10[246];
1602 		} rdma;
1603 		struct tcp {
1604 			__u8	sectype;
1605 		} tcp;
1606 	} tsas;
1607 };
1608 
1609 /* Discovery log page header */
1610 struct nvmf_disc_rsp_page_hdr {
1611 	__le64		genctr;
1612 	__le64		numrec;
1613 	__le16		recfmt;
1614 	__u8		resv14[1006];
1615 	struct nvmf_disc_rsp_page_entry entries[];
1616 };
1617 
1618 enum {
1619 	NVME_CONNECT_DISABLE_SQFLOW	= (1 << 2),
1620 };
1621 
1622 struct nvmf_connect_command {
1623 	__u8		opcode;
1624 	__u8		resv1;
1625 	__u16		command_id;
1626 	__u8		fctype;
1627 	__u8		resv2[19];
1628 	union nvme_data_ptr dptr;
1629 	__le16		recfmt;
1630 	__le16		qid;
1631 	__le16		sqsize;
1632 	__u8		cattr;
1633 	__u8		resv3;
1634 	__le32		kato;
1635 	__u8		resv4[12];
1636 };
1637 
1638 enum {
1639 	NVME_CONNECT_AUTHREQ_ASCR	= (1U << 18),
1640 	NVME_CONNECT_AUTHREQ_ATR	= (1U << 17),
1641 };
1642 
1643 struct nvmf_connect_data {
1644 	uuid_t		hostid;
1645 	__le16		cntlid;
1646 	char		resv4[238];
1647 	char		subsysnqn[NVMF_NQN_FIELD_LEN];
1648 	char		hostnqn[NVMF_NQN_FIELD_LEN];
1649 	char		resv5[256];
1650 };
1651 
1652 struct nvmf_property_set_command {
1653 	__u8		opcode;
1654 	__u8		resv1;
1655 	__u16		command_id;
1656 	__u8		fctype;
1657 	__u8		resv2[35];
1658 	__u8		attrib;
1659 	__u8		resv3[3];
1660 	__le32		offset;
1661 	__le64		value;
1662 	__u8		resv4[8];
1663 };
1664 
1665 struct nvmf_property_get_command {
1666 	__u8		opcode;
1667 	__u8		resv1;
1668 	__u16		command_id;
1669 	__u8		fctype;
1670 	__u8		resv2[35];
1671 	__u8		attrib;
1672 	__u8		resv3[3];
1673 	__le32		offset;
1674 	__u8		resv4[16];
1675 };
1676 
1677 struct nvmf_auth_common_command {
1678 	__u8		opcode;
1679 	__u8		resv1;
1680 	__u16		command_id;
1681 	__u8		fctype;
1682 	__u8		resv2[19];
1683 	union nvme_data_ptr dptr;
1684 	__u8		resv3;
1685 	__u8		spsp0;
1686 	__u8		spsp1;
1687 	__u8		secp;
1688 	__le32		al_tl;
1689 	__u8		resv4[16];
1690 };
1691 
1692 struct nvmf_auth_send_command {
1693 	__u8		opcode;
1694 	__u8		resv1;
1695 	__u16		command_id;
1696 	__u8		fctype;
1697 	__u8		resv2[19];
1698 	union nvme_data_ptr dptr;
1699 	__u8		resv3;
1700 	__u8		spsp0;
1701 	__u8		spsp1;
1702 	__u8		secp;
1703 	__le32		tl;
1704 	__u8		resv4[16];
1705 };
1706 
1707 struct nvmf_auth_receive_command {
1708 	__u8		opcode;
1709 	__u8		resv1;
1710 	__u16		command_id;
1711 	__u8		fctype;
1712 	__u8		resv2[19];
1713 	union nvme_data_ptr dptr;
1714 	__u8		resv3;
1715 	__u8		spsp0;
1716 	__u8		spsp1;
1717 	__u8		secp;
1718 	__le32		al;
1719 	__u8		resv4[16];
1720 };
1721 
1722 /* Value for secp */
1723 enum {
1724 	NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER	= 0xe9,
1725 };
1726 
1727 /* Defined value for auth_type */
1728 enum {
1729 	NVME_AUTH_COMMON_MESSAGES	= 0x00,
1730 	NVME_AUTH_DHCHAP_MESSAGES	= 0x01,
1731 };
1732 
1733 /* Defined messages for auth_id */
1734 enum {
1735 	NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE	= 0x00,
1736 	NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE	= 0x01,
1737 	NVME_AUTH_DHCHAP_MESSAGE_REPLY		= 0x02,
1738 	NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1	= 0x03,
1739 	NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2	= 0x04,
1740 	NVME_AUTH_DHCHAP_MESSAGE_FAILURE2	= 0xf0,
1741 	NVME_AUTH_DHCHAP_MESSAGE_FAILURE1	= 0xf1,
1742 };
1743 
1744 struct nvmf_auth_dhchap_protocol_descriptor {
1745 	__u8		authid;
1746 	__u8		rsvd;
1747 	__u8		halen;
1748 	__u8		dhlen;
1749 	__u8		idlist[60];
1750 };
1751 
1752 enum {
1753 	NVME_AUTH_DHCHAP_AUTH_ID	= 0x01,
1754 };
1755 
1756 /* Defined hash functions for DH-HMAC-CHAP authentication */
1757 enum {
1758 	NVME_AUTH_HASH_SHA256	= 0x01,
1759 	NVME_AUTH_HASH_SHA384	= 0x02,
1760 	NVME_AUTH_HASH_SHA512	= 0x03,
1761 	NVME_AUTH_HASH_INVALID	= 0xff,
1762 };
1763 
1764 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1765 enum {
1766 	NVME_AUTH_DHGROUP_NULL		= 0x00,
1767 	NVME_AUTH_DHGROUP_2048		= 0x01,
1768 	NVME_AUTH_DHGROUP_3072		= 0x02,
1769 	NVME_AUTH_DHGROUP_4096		= 0x03,
1770 	NVME_AUTH_DHGROUP_6144		= 0x04,
1771 	NVME_AUTH_DHGROUP_8192		= 0x05,
1772 	NVME_AUTH_DHGROUP_INVALID	= 0xff,
1773 };
1774 
1775 union nvmf_auth_protocol {
1776 	struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1777 };
1778 
1779 struct nvmf_auth_dhchap_negotiate_data {
1780 	__u8		auth_type;
1781 	__u8		auth_id;
1782 	__le16		rsvd;
1783 	__le16		t_id;
1784 	__u8		sc_c;
1785 	__u8		napd;
1786 	union nvmf_auth_protocol auth_protocol[];
1787 };
1788 
1789 struct nvmf_auth_dhchap_challenge_data {
1790 	__u8		auth_type;
1791 	__u8		auth_id;
1792 	__u16		rsvd1;
1793 	__le16		t_id;
1794 	__u8		hl;
1795 	__u8		rsvd2;
1796 	__u8		hashid;
1797 	__u8		dhgid;
1798 	__le16		dhvlen;
1799 	__le32		seqnum;
1800 	/* 'hl' bytes of challenge value */
1801 	__u8		cval[];
1802 	/* followed by 'dhvlen' bytes of DH value */
1803 };
1804 
1805 struct nvmf_auth_dhchap_reply_data {
1806 	__u8		auth_type;
1807 	__u8		auth_id;
1808 	__le16		rsvd1;
1809 	__le16		t_id;
1810 	__u8		hl;
1811 	__u8		rsvd2;
1812 	__u8		cvalid;
1813 	__u8		rsvd3;
1814 	__le16		dhvlen;
1815 	__le32		seqnum;
1816 	/* 'hl' bytes of response data */
1817 	__u8		rval[];
1818 	/* followed by 'hl' bytes of Challenge value */
1819 	/* followed by 'dhvlen' bytes of DH value */
1820 };
1821 
1822 enum {
1823 	NVME_AUTH_DHCHAP_RESPONSE_VALID	= (1 << 0),
1824 };
1825 
1826 struct nvmf_auth_dhchap_success1_data {
1827 	__u8		auth_type;
1828 	__u8		auth_id;
1829 	__le16		rsvd1;
1830 	__le16		t_id;
1831 	__u8		hl;
1832 	__u8		rsvd2;
1833 	__u8		rvalid;
1834 	__u8		rsvd3[7];
1835 	/* 'hl' bytes of response value */
1836 	__u8		rval[];
1837 };
1838 
1839 struct nvmf_auth_dhchap_success2_data {
1840 	__u8		auth_type;
1841 	__u8		auth_id;
1842 	__le16		rsvd1;
1843 	__le16		t_id;
1844 	__u8		rsvd2[10];
1845 };
1846 
1847 struct nvmf_auth_dhchap_failure_data {
1848 	__u8		auth_type;
1849 	__u8		auth_id;
1850 	__le16		rsvd1;
1851 	__le16		t_id;
1852 	__u8		rescode;
1853 	__u8		rescode_exp;
1854 };
1855 
1856 enum {
1857 	NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED	= 0x01,
1858 };
1859 
1860 enum {
1861 	NVME_AUTH_DHCHAP_FAILURE_FAILED			= 0x01,
1862 	NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE		= 0x02,
1863 	NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH	= 0x03,
1864 	NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE		= 0x04,
1865 	NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE	= 0x05,
1866 	NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD	= 0x06,
1867 	NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE	= 0x07,
1868 };
1869 
1870 
1871 struct nvme_dbbuf {
1872 	__u8			opcode;
1873 	__u8			flags;
1874 	__u16			command_id;
1875 	__u32			rsvd1[5];
1876 	__le64			prp1;
1877 	__le64			prp2;
1878 	__u32			rsvd12[6];
1879 };
1880 
1881 struct streams_directive_params {
1882 	__le16	msl;
1883 	__le16	nssa;
1884 	__le16	nsso;
1885 	__u8	rsvd[10];
1886 	__le32	sws;
1887 	__le16	sgs;
1888 	__le16	nsa;
1889 	__le16	nso;
1890 	__u8	rsvd2[6];
1891 };
1892 
1893 struct nvme_command {
1894 	union {
1895 		struct nvme_common_command common;
1896 		struct nvme_rw_command rw;
1897 		struct nvme_identify identify;
1898 		struct nvme_features features;
1899 		struct nvme_create_cq create_cq;
1900 		struct nvme_create_sq create_sq;
1901 		struct nvme_delete_queue delete_queue;
1902 		struct nvme_download_firmware dlfw;
1903 		struct nvme_format_cmd format;
1904 		struct nvme_dsm_cmd dsm;
1905 		struct nvme_write_zeroes_cmd write_zeroes;
1906 		struct nvme_zone_mgmt_send_cmd zms;
1907 		struct nvme_zone_mgmt_recv_cmd zmr;
1908 		struct nvme_abort_cmd abort;
1909 		struct nvme_get_log_page_command get_log_page;
1910 		struct nvmf_common_command fabrics;
1911 		struct nvmf_connect_command connect;
1912 		struct nvmf_property_set_command prop_set;
1913 		struct nvmf_property_get_command prop_get;
1914 		struct nvmf_auth_common_command auth_common;
1915 		struct nvmf_auth_send_command auth_send;
1916 		struct nvmf_auth_receive_command auth_receive;
1917 		struct nvme_dbbuf dbbuf;
1918 		struct nvme_directive_cmd directive;
1919 	};
1920 };
1921 
nvme_is_fabrics(const struct nvme_command * cmd)1922 static inline bool nvme_is_fabrics(const struct nvme_command *cmd)
1923 {
1924 	return cmd->common.opcode == nvme_fabrics_command;
1925 }
1926 
1927 #ifdef CONFIG_NVME_VERBOSE_ERRORS
1928 const char *nvme_get_error_status_str(u16 status);
1929 const char *nvme_get_opcode_str(u8 opcode);
1930 const char *nvme_get_admin_opcode_str(u8 opcode);
1931 const char *nvme_get_fabrics_opcode_str(u8 opcode);
1932 #else /* CONFIG_NVME_VERBOSE_ERRORS */
nvme_get_error_status_str(u16 status)1933 static inline const char *nvme_get_error_status_str(u16 status)
1934 {
1935 	return "I/O Error";
1936 }
nvme_get_opcode_str(u8 opcode)1937 static inline const char *nvme_get_opcode_str(u8 opcode)
1938 {
1939 	return "I/O Cmd";
1940 }
nvme_get_admin_opcode_str(u8 opcode)1941 static inline const char *nvme_get_admin_opcode_str(u8 opcode)
1942 {
1943 	return "Admin Cmd";
1944 }
1945 
nvme_get_fabrics_opcode_str(u8 opcode)1946 static inline const char *nvme_get_fabrics_opcode_str(u8 opcode)
1947 {
1948 	return "Fabrics Cmd";
1949 }
1950 #endif /* CONFIG_NVME_VERBOSE_ERRORS */
1951 
nvme_opcode_str(int qid,u8 opcode)1952 static inline const char *nvme_opcode_str(int qid, u8 opcode)
1953 {
1954 	return qid ? nvme_get_opcode_str(opcode) :
1955 		nvme_get_admin_opcode_str(opcode);
1956 }
1957 
nvme_fabrics_opcode_str(int qid,const struct nvme_command * cmd)1958 static inline const char *nvme_fabrics_opcode_str(
1959 		int qid, const struct nvme_command *cmd)
1960 {
1961 	if (nvme_is_fabrics(cmd))
1962 		return nvme_get_fabrics_opcode_str(cmd->fabrics.fctype);
1963 
1964 	return nvme_opcode_str(qid, cmd->common.opcode);
1965 }
1966 
1967 struct nvme_error_slot {
1968 	__le64		error_count;
1969 	__le16		sqid;
1970 	__le16		cmdid;
1971 	__le16		status_field;
1972 	__le16		param_error_location;
1973 	__le64		lba;
1974 	__le32		nsid;
1975 	__u8		vs;
1976 	__u8		resv[3];
1977 	__le64		cs;
1978 	__u8		resv2[24];
1979 };
1980 
nvme_is_write(const struct nvme_command * cmd)1981 static inline bool nvme_is_write(const struct nvme_command *cmd)
1982 {
1983 	/*
1984 	 * What a mess...
1985 	 *
1986 	 * Why can't we simply have a Fabrics In and Fabrics out command?
1987 	 */
1988 	if (unlikely(nvme_is_fabrics(cmd)))
1989 		return cmd->fabrics.fctype & 1;
1990 	return cmd->common.opcode & 1;
1991 }
1992 
1993 enum {
1994 	/*
1995 	 * Generic Command Status:
1996 	 */
1997 	NVME_SCT_GENERIC		= 0x0,
1998 	NVME_SC_SUCCESS			= 0x0,
1999 	NVME_SC_INVALID_OPCODE		= 0x1,
2000 	NVME_SC_INVALID_FIELD		= 0x2,
2001 	NVME_SC_CMDID_CONFLICT		= 0x3,
2002 	NVME_SC_DATA_XFER_ERROR		= 0x4,
2003 	NVME_SC_POWER_LOSS		= 0x5,
2004 	NVME_SC_INTERNAL		= 0x6,
2005 	NVME_SC_ABORT_REQ		= 0x7,
2006 	NVME_SC_ABORT_QUEUE		= 0x8,
2007 	NVME_SC_FUSED_FAIL		= 0x9,
2008 	NVME_SC_FUSED_MISSING		= 0xa,
2009 	NVME_SC_INVALID_NS		= 0xb,
2010 	NVME_SC_CMD_SEQ_ERROR		= 0xc,
2011 	NVME_SC_SGL_INVALID_LAST	= 0xd,
2012 	NVME_SC_SGL_INVALID_COUNT	= 0xe,
2013 	NVME_SC_SGL_INVALID_DATA	= 0xf,
2014 	NVME_SC_SGL_INVALID_METADATA	= 0x10,
2015 	NVME_SC_SGL_INVALID_TYPE	= 0x11,
2016 	NVME_SC_CMB_INVALID_USE		= 0x12,
2017 	NVME_SC_PRP_INVALID_OFFSET	= 0x13,
2018 	NVME_SC_ATOMIC_WU_EXCEEDED	= 0x14,
2019 	NVME_SC_OP_DENIED		= 0x15,
2020 	NVME_SC_SGL_INVALID_OFFSET	= 0x16,
2021 	NVME_SC_RESERVED		= 0x17,
2022 	NVME_SC_HOST_ID_INCONSIST	= 0x18,
2023 	NVME_SC_KA_TIMEOUT_EXPIRED	= 0x19,
2024 	NVME_SC_KA_TIMEOUT_INVALID	= 0x1A,
2025 	NVME_SC_ABORTED_PREEMPT_ABORT	= 0x1B,
2026 	NVME_SC_SANITIZE_FAILED		= 0x1C,
2027 	NVME_SC_SANITIZE_IN_PROGRESS	= 0x1D,
2028 	NVME_SC_SGL_INVALID_GRANULARITY	= 0x1E,
2029 	NVME_SC_CMD_NOT_SUP_CMB_QUEUE	= 0x1F,
2030 	NVME_SC_NS_WRITE_PROTECTED	= 0x20,
2031 	NVME_SC_CMD_INTERRUPTED		= 0x21,
2032 	NVME_SC_TRANSIENT_TR_ERR	= 0x22,
2033 	NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
2034 	NVME_SC_INVALID_IO_CMD_SET	= 0x2C,
2035 
2036 	NVME_SC_LBA_RANGE		= 0x80,
2037 	NVME_SC_CAP_EXCEEDED		= 0x81,
2038 	NVME_SC_NS_NOT_READY		= 0x82,
2039 	NVME_SC_RESERVATION_CONFLICT	= 0x83,
2040 	NVME_SC_FORMAT_IN_PROGRESS	= 0x84,
2041 
2042 	/*
2043 	 * Command Specific Status:
2044 	 */
2045 	NVME_SCT_COMMAND_SPECIFIC	= 0x100,
2046 	NVME_SC_CQ_INVALID		= 0x100,
2047 	NVME_SC_QID_INVALID		= 0x101,
2048 	NVME_SC_QUEUE_SIZE		= 0x102,
2049 	NVME_SC_ABORT_LIMIT		= 0x103,
2050 	NVME_SC_ABORT_MISSING		= 0x104,
2051 	NVME_SC_ASYNC_LIMIT		= 0x105,
2052 	NVME_SC_FIRMWARE_SLOT		= 0x106,
2053 	NVME_SC_FIRMWARE_IMAGE		= 0x107,
2054 	NVME_SC_INVALID_VECTOR		= 0x108,
2055 	NVME_SC_INVALID_LOG_PAGE	= 0x109,
2056 	NVME_SC_INVALID_FORMAT		= 0x10a,
2057 	NVME_SC_FW_NEEDS_CONV_RESET	= 0x10b,
2058 	NVME_SC_INVALID_QUEUE		= 0x10c,
2059 	NVME_SC_FEATURE_NOT_SAVEABLE	= 0x10d,
2060 	NVME_SC_FEATURE_NOT_CHANGEABLE	= 0x10e,
2061 	NVME_SC_FEATURE_NOT_PER_NS	= 0x10f,
2062 	NVME_SC_FW_NEEDS_SUBSYS_RESET	= 0x110,
2063 	NVME_SC_FW_NEEDS_RESET		= 0x111,
2064 	NVME_SC_FW_NEEDS_MAX_TIME	= 0x112,
2065 	NVME_SC_FW_ACTIVATE_PROHIBITED	= 0x113,
2066 	NVME_SC_OVERLAPPING_RANGE	= 0x114,
2067 	NVME_SC_NS_INSUFFICIENT_CAP	= 0x115,
2068 	NVME_SC_NS_ID_UNAVAILABLE	= 0x116,
2069 	NVME_SC_NS_ALREADY_ATTACHED	= 0x118,
2070 	NVME_SC_NS_IS_PRIVATE		= 0x119,
2071 	NVME_SC_NS_NOT_ATTACHED		= 0x11a,
2072 	NVME_SC_THIN_PROV_NOT_SUPP	= 0x11b,
2073 	NVME_SC_CTRL_LIST_INVALID	= 0x11c,
2074 	NVME_SC_SELT_TEST_IN_PROGRESS	= 0x11d,
2075 	NVME_SC_BP_WRITE_PROHIBITED	= 0x11e,
2076 	NVME_SC_CTRL_ID_INVALID		= 0x11f,
2077 	NVME_SC_SEC_CTRL_STATE_INVALID	= 0x120,
2078 	NVME_SC_CTRL_RES_NUM_INVALID	= 0x121,
2079 	NVME_SC_RES_ID_INVALID		= 0x122,
2080 	NVME_SC_PMR_SAN_PROHIBITED	= 0x123,
2081 	NVME_SC_ANA_GROUP_ID_INVALID	= 0x124,
2082 	NVME_SC_ANA_ATTACH_FAILED	= 0x125,
2083 
2084 	/*
2085 	 * I/O Command Set Specific - NVM commands:
2086 	 */
2087 	NVME_SC_BAD_ATTRIBUTES		= 0x180,
2088 	NVME_SC_INVALID_PI		= 0x181,
2089 	NVME_SC_READ_ONLY		= 0x182,
2090 	NVME_SC_ONCS_NOT_SUPPORTED	= 0x183,
2091 
2092 	/*
2093 	 * I/O Command Set Specific - Fabrics commands:
2094 	 */
2095 	NVME_SC_CONNECT_FORMAT		= 0x180,
2096 	NVME_SC_CONNECT_CTRL_BUSY	= 0x181,
2097 	NVME_SC_CONNECT_INVALID_PARAM	= 0x182,
2098 	NVME_SC_CONNECT_RESTART_DISC	= 0x183,
2099 	NVME_SC_CONNECT_INVALID_HOST	= 0x184,
2100 
2101 	NVME_SC_DISCOVERY_RESTART	= 0x190,
2102 	NVME_SC_AUTH_REQUIRED		= 0x191,
2103 
2104 	/*
2105 	 * I/O Command Set Specific - Zoned commands:
2106 	 */
2107 	NVME_SC_ZONE_BOUNDARY_ERROR	= 0x1b8,
2108 	NVME_SC_ZONE_FULL		= 0x1b9,
2109 	NVME_SC_ZONE_READ_ONLY		= 0x1ba,
2110 	NVME_SC_ZONE_OFFLINE		= 0x1bb,
2111 	NVME_SC_ZONE_INVALID_WRITE	= 0x1bc,
2112 	NVME_SC_ZONE_TOO_MANY_ACTIVE	= 0x1bd,
2113 	NVME_SC_ZONE_TOO_MANY_OPEN	= 0x1be,
2114 	NVME_SC_ZONE_INVALID_TRANSITION	= 0x1bf,
2115 
2116 	/*
2117 	 * Media and Data Integrity Errors:
2118 	 */
2119 	NVME_SCT_MEDIA_ERROR		= 0x200,
2120 	NVME_SC_WRITE_FAULT		= 0x280,
2121 	NVME_SC_READ_ERROR		= 0x281,
2122 	NVME_SC_GUARD_CHECK		= 0x282,
2123 	NVME_SC_APPTAG_CHECK		= 0x283,
2124 	NVME_SC_REFTAG_CHECK		= 0x284,
2125 	NVME_SC_COMPARE_FAILED		= 0x285,
2126 	NVME_SC_ACCESS_DENIED		= 0x286,
2127 	NVME_SC_UNWRITTEN_BLOCK		= 0x287,
2128 
2129 	/*
2130 	 * Path-related Errors:
2131 	 */
2132 	NVME_SCT_PATH			= 0x300,
2133 	NVME_SC_INTERNAL_PATH_ERROR	= 0x300,
2134 	NVME_SC_ANA_PERSISTENT_LOSS	= 0x301,
2135 	NVME_SC_ANA_INACCESSIBLE	= 0x302,
2136 	NVME_SC_ANA_TRANSITION		= 0x303,
2137 	NVME_SC_CTRL_PATH_ERROR		= 0x360,
2138 	NVME_SC_HOST_PATH_ERROR		= 0x370,
2139 	NVME_SC_HOST_ABORTED_CMD	= 0x371,
2140 
2141 	NVME_SC_MASK			= 0x00ff, /* Status Code */
2142 	NVME_SCT_MASK			= 0x0700, /* Status Code Type */
2143 	NVME_SCT_SC_MASK		= NVME_SCT_MASK | NVME_SC_MASK,
2144 
2145 	NVME_STATUS_CRD			= 0x1800, /* Command Retry Delayed */
2146 	NVME_STATUS_MORE		= 0x2000,
2147 	NVME_STATUS_DNR			= 0x4000, /* Do Not Retry */
2148 };
2149 
2150 #define NVME_SCT(status) ((status) >> 8 & 7)
2151 
2152 struct nvme_completion {
2153 	/*
2154 	 * Used by Admin and Fabrics commands to return data:
2155 	 */
2156 	union nvme_result {
2157 		__le16	u16;
2158 		__le32	u32;
2159 		__le64	u64;
2160 	} result;
2161 	__le16	sq_head;	/* how much of this queue may be reclaimed */
2162 	__le16	sq_id;		/* submission queue that generated this entry */
2163 	__u16	command_id;	/* of the command which completed */
2164 	__le16	status;		/* did the command fail, and if so, why? */
2165 };
2166 
2167 #define NVME_VS(major, minor, tertiary) \
2168 	(((major) << 16) | ((minor) << 8) | (tertiary))
2169 
2170 #define NVME_MAJOR(ver)		((ver) >> 16)
2171 #define NVME_MINOR(ver)		(((ver) >> 8) & 0xff)
2172 #define NVME_TERTIARY(ver)	((ver) & 0xff)
2173 
2174 enum {
2175 	NVME_AEN_RESV_LOG_PAGE_AVALIABLE	= 0x00,
2176 };
2177 
2178 enum {
2179 	NVME_PR_LOG_EMPTY_LOG_PAGE			= 0x00,
2180 	NVME_PR_LOG_REGISTRATION_PREEMPTED		= 0x01,
2181 	NVME_PR_LOG_RESERVATION_RELEASED		= 0x02,
2182 	NVME_PR_LOG_RESERVATOIN_PREEMPTED		= 0x03,
2183 };
2184 
2185 enum {
2186 	NVME_PR_NOTIFY_BIT_REG_PREEMPTED		= 1,
2187 	NVME_PR_NOTIFY_BIT_RESV_RELEASED		= 2,
2188 	NVME_PR_NOTIFY_BIT_RESV_PREEMPTED		= 3,
2189 };
2190 
2191 struct nvme_pr_log {
2192 	__le64			count;
2193 	__u8			type;
2194 	__u8			nr_pages;
2195 	__u8			rsvd1[2];
2196 	__le32			nsid;
2197 	__u8			rsvd2[48];
2198 };
2199 
2200 struct nvmet_pr_register_data {
2201 	__le64	crkey;
2202 	__le64	nrkey;
2203 };
2204 
2205 struct nvmet_pr_acquire_data {
2206 	__le64	crkey;
2207 	__le64	prkey;
2208 };
2209 
2210 struct nvmet_pr_release_data {
2211 	__le64	crkey;
2212 };
2213 
2214 enum nvme_pr_capabilities {
2215 	NVME_PR_SUPPORT_PTPL				= 1,
2216 	NVME_PR_SUPPORT_WRITE_EXCLUSIVE			= 1 << 1,
2217 	NVME_PR_SUPPORT_EXCLUSIVE_ACCESS		= 1 << 2,
2218 	NVME_PR_SUPPORT_WRITE_EXCLUSIVE_REG_ONLY	= 1 << 3,
2219 	NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_REG_ONLY	= 1 << 4,
2220 	NVME_PR_SUPPORT_WRITE_EXCLUSIVE_ALL_REGS	= 1 << 5,
2221 	NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_ALL_REGS	= 1 << 6,
2222 	NVME_PR_SUPPORT_IEKEY_VER_1_3_DEF		= 1 << 7,
2223 };
2224 
2225 enum nvme_pr_register_action {
2226 	NVME_PR_REGISTER_ACT_REG		= 0,
2227 	NVME_PR_REGISTER_ACT_UNREG		= 1,
2228 	NVME_PR_REGISTER_ACT_REPLACE		= 1 << 1,
2229 };
2230 
2231 enum nvme_pr_acquire_action {
2232 	NVME_PR_ACQUIRE_ACT_ACQUIRE		= 0,
2233 	NVME_PR_ACQUIRE_ACT_PREEMPT		= 1,
2234 	NVME_PR_ACQUIRE_ACT_PREEMPT_AND_ABORT	= 1 << 1,
2235 };
2236 
2237 enum nvme_pr_release_action {
2238 	NVME_PR_RELEASE_ACT_RELEASE		= 0,
2239 	NVME_PR_RELEASE_ACT_CLEAR		= 1,
2240 };
2241 
2242 enum nvme_pr_change_ptpl {
2243 	NVME_PR_CPTPL_NO_CHANGE			= 0,
2244 	NVME_PR_CPTPL_RESV			= 1 << 30,
2245 	NVME_PR_CPTPL_CLEARED			= 2 << 30,
2246 	NVME_PR_CPTPL_PERSIST			= 3 << 30,
2247 };
2248 
2249 #define NVME_PR_IGNORE_KEY (1 << 3)
2250 
2251 #endif /* _LINUX_NVME_H */
2252