xref: /linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "amdgpu_dm_hdcp.h"
27 #include "amdgpu.h"
28 #include "amdgpu_dm.h"
29 #include "dm_helpers.h"
30 #include <drm/display/drm_hdcp_helper.h>
31 #include "hdcp_psp.h"
32 
33 /*
34  * If the SRM version being loaded is less than or equal to the
35  * currently loaded SRM, psp will return 0xFFFF as the version
36  */
37 #define PSP_SRM_VERSION_MAX 0xFFFF
38 
39 static bool
lp_write_i2c(void * handle,uint32_t address,const uint8_t * data,uint32_t size)40 lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
41 {
42 	struct dc_link *link = handle;
43 	struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };
44 	struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW,
45 				  link->dc->caps.i2c_speed_in_khz};
46 
47 	return dm_helpers_submit_i2c(link->ctx, link, &cmd);
48 }
49 
50 static bool
lp_read_i2c(void * handle,uint32_t address,uint8_t offset,uint8_t * data,uint32_t size)51 lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size)
52 {
53 	struct dc_link *link = handle;
54 
55 	struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset},
56 					     {false, address, size, data} };
57 	struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW,
58 				  link->dc->caps.i2c_speed_in_khz};
59 
60 	return dm_helpers_submit_i2c(link->ctx, link, &cmd);
61 }
62 
63 static bool
lp_write_dpcd(void * handle,uint32_t address,const uint8_t * data,uint32_t size)64 lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
65 {
66 	struct dc_link *link = handle;
67 
68 	return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size);
69 }
70 
71 static bool
lp_read_dpcd(void * handle,uint32_t address,uint8_t * data,uint32_t size)72 lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
73 {
74 	struct dc_link *link = handle;
75 
76 	return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size);
77 }
78 
psp_get_srm(struct psp_context * psp,uint32_t * srm_version,uint32_t * srm_size)79 static uint8_t *psp_get_srm(struct psp_context *psp, uint32_t *srm_version, uint32_t *srm_size)
80 {
81 	struct ta_hdcp_shared_memory *hdcp_cmd;
82 
83 	if (!psp->hdcp_context.context.initialized) {
84 		DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized.");
85 		return NULL;
86 	}
87 
88 	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;
89 	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
90 
91 	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_GET_SRM;
92 	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
93 
94 	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS)
95 		return NULL;
96 
97 	*srm_version = hdcp_cmd->out_msg.hdcp_get_srm.srm_version;
98 	*srm_size = hdcp_cmd->out_msg.hdcp_get_srm.srm_buf_size;
99 
100 	return hdcp_cmd->out_msg.hdcp_get_srm.srm_buf;
101 }
102 
psp_set_srm(struct psp_context * psp,u8 * srm,uint32_t srm_size,uint32_t * srm_version)103 static int psp_set_srm(struct psp_context *psp,
104 		       u8 *srm, uint32_t srm_size, uint32_t *srm_version)
105 {
106 	struct ta_hdcp_shared_memory *hdcp_cmd;
107 
108 	if (!psp->hdcp_context.context.initialized) {
109 		DRM_WARN("Failed to get hdcp srm. HDCP TA is not initialized.");
110 		return -EINVAL;
111 	}
112 
113 	hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;
114 	memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
115 
116 	memcpy(hdcp_cmd->in_msg.hdcp_set_srm.srm_buf, srm, srm_size);
117 	hdcp_cmd->in_msg.hdcp_set_srm.srm_buf_size = srm_size;
118 	hdcp_cmd->cmd_id = TA_HDCP_COMMAND__HDCP_SET_SRM;
119 
120 	psp_hdcp_invoke(psp, hdcp_cmd->cmd_id);
121 
122 	if (hdcp_cmd->hdcp_status != TA_HDCP_STATUS__SUCCESS ||
123 	    hdcp_cmd->out_msg.hdcp_set_srm.valid_signature != 1 ||
124 	    hdcp_cmd->out_msg.hdcp_set_srm.srm_version == PSP_SRM_VERSION_MAX)
125 		return -EINVAL;
126 
127 	*srm_version = hdcp_cmd->out_msg.hdcp_set_srm.srm_version;
128 	return 0;
129 }
130 
process_output(struct hdcp_workqueue * hdcp_work)131 static void process_output(struct hdcp_workqueue *hdcp_work)
132 {
133 	struct mod_hdcp_output output = hdcp_work->output;
134 
135 	if (output.callback_stop)
136 		cancel_delayed_work(&hdcp_work->callback_dwork);
137 
138 	if (output.callback_needed)
139 		schedule_delayed_work(&hdcp_work->callback_dwork,
140 				      msecs_to_jiffies(output.callback_delay));
141 
142 	if (output.watchdog_timer_stop)
143 		cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
144 
145 	if (output.watchdog_timer_needed)
146 		schedule_delayed_work(&hdcp_work->watchdog_timer_dwork,
147 				      msecs_to_jiffies(output.watchdog_timer_delay));
148 
149 	schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(0));
150 }
151 
link_lock(struct hdcp_workqueue * work,bool lock)152 static void link_lock(struct hdcp_workqueue *work, bool lock)
153 {
154 	int i = 0;
155 
156 	for (i = 0; i < work->max_link; i++) {
157 		if (lock)
158 			mutex_lock(&work[i].mutex);
159 		else
160 			mutex_unlock(&work[i].mutex);
161 	}
162 }
163 
hdcp_update_display(struct hdcp_workqueue * hdcp_work,unsigned int link_index,struct amdgpu_dm_connector * aconnector,u8 content_type,bool enable_encryption)164 void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
165 			 unsigned int link_index,
166 			 struct amdgpu_dm_connector *aconnector,
167 			 u8 content_type,
168 			 bool enable_encryption)
169 {
170 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
171 	struct mod_hdcp_link_adjustment link_adjust;
172 	struct mod_hdcp_display_adjustment display_adjust;
173 	unsigned int conn_index = aconnector->base.index;
174 
175 	mutex_lock(&hdcp_w->mutex);
176 	hdcp_w->aconnector[conn_index] = aconnector;
177 
178 	memset(&link_adjust, 0, sizeof(link_adjust));
179 	memset(&display_adjust, 0, sizeof(display_adjust));
180 
181 	if (enable_encryption) {
182 		/* Explicitly set the saved SRM as sysfs call will be after we already enabled hdcp
183 		 * (s3 resume case)
184 		 */
185 		if (hdcp_work->srm_size > 0)
186 			psp_set_srm(hdcp_work->hdcp.config.psp.handle, hdcp_work->srm,
187 				    hdcp_work->srm_size,
188 				    &hdcp_work->srm_version);
189 
190 		display_adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE;
191 
192 		link_adjust.auth_delay = 2;
193 
194 		if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) {
195 			link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
196 		} else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1) {
197 			link_adjust.hdcp1.disable = 1;
198 			link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1;
199 		}
200 
201 		schedule_delayed_work(&hdcp_w->property_validate_dwork,
202 				      msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
203 	} else {
204 		display_adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
205 		hdcp_w->encryption_status[conn_index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
206 		cancel_delayed_work(&hdcp_w->property_validate_dwork);
207 	}
208 
209 	mod_hdcp_update_display(&hdcp_w->hdcp, conn_index, &link_adjust, &display_adjust, &hdcp_w->output);
210 
211 	process_output(hdcp_w);
212 	mutex_unlock(&hdcp_w->mutex);
213 }
214 
hdcp_remove_display(struct hdcp_workqueue * hdcp_work,unsigned int link_index,struct amdgpu_dm_connector * aconnector)215 static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work,
216 				unsigned int link_index,
217 			 struct amdgpu_dm_connector *aconnector)
218 {
219 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
220 	struct drm_connector_state *conn_state = aconnector->base.state;
221 	unsigned int conn_index = aconnector->base.index;
222 
223 	mutex_lock(&hdcp_w->mutex);
224 	hdcp_w->aconnector[conn_index] = aconnector;
225 
226 	/* the removal of display will invoke auth reset -> hdcp destroy and
227 	 * we'd expect the Content Protection (CP) property changed back to
228 	 * DESIRED if at the time ENABLED. CP property change should occur
229 	 * before the element removed from linked list.
230 	 */
231 	if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
232 		conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
233 
234 		DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n",
235 				 aconnector->base.index, conn_state->hdcp_content_type,
236 				 aconnector->base.dpms);
237 	}
238 
239 	mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
240 
241 	process_output(hdcp_w);
242 	mutex_unlock(&hdcp_w->mutex);
243 }
244 
hdcp_reset_display(struct hdcp_workqueue * hdcp_work,unsigned int link_index)245 void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
246 {
247 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
248 	unsigned int conn_index;
249 
250 	mutex_lock(&hdcp_w->mutex);
251 
252 	mod_hdcp_reset_connection(&hdcp_w->hdcp,  &hdcp_w->output);
253 
254 	cancel_delayed_work(&hdcp_w->property_validate_dwork);
255 
256 	for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) {
257 		hdcp_w->encryption_status[conn_index] =
258 			MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
259 	}
260 
261 	process_output(hdcp_w);
262 
263 	mutex_unlock(&hdcp_w->mutex);
264 }
265 
hdcp_handle_cpirq(struct hdcp_workqueue * hdcp_work,unsigned int link_index)266 void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
267 {
268 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
269 
270 	schedule_work(&hdcp_w->cpirq_work);
271 }
272 
event_callback(struct work_struct * work)273 static void event_callback(struct work_struct *work)
274 {
275 	struct hdcp_workqueue *hdcp_work;
276 
277 	hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue,
278 				 callback_dwork);
279 
280 	mutex_lock(&hdcp_work->mutex);
281 
282 	cancel_delayed_work(&hdcp_work->callback_dwork);
283 
284 	mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CALLBACK,
285 			       &hdcp_work->output);
286 
287 	process_output(hdcp_work);
288 
289 	mutex_unlock(&hdcp_work->mutex);
290 }
291 
event_property_update(struct work_struct * work)292 static void event_property_update(struct work_struct *work)
293 {
294 	struct hdcp_workqueue *hdcp_work = container_of(work, struct hdcp_workqueue,
295 							property_update_work);
296 	struct amdgpu_dm_connector *aconnector = NULL;
297 	struct drm_device *dev;
298 	long ret;
299 	unsigned int conn_index;
300 	struct drm_connector *connector;
301 	struct drm_connector_state *conn_state;
302 
303 	for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) {
304 		aconnector = hdcp_work->aconnector[conn_index];
305 
306 		if (!aconnector)
307 			continue;
308 
309 		connector = &aconnector->base;
310 
311 		/* check if display connected */
312 		if (connector->status != connector_status_connected)
313 			continue;
314 
315 		conn_state = aconnector->base.state;
316 
317 		if (!conn_state)
318 			continue;
319 
320 		dev = connector->dev;
321 
322 		if (!dev)
323 			continue;
324 
325 		drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
326 		mutex_lock(&hdcp_work->mutex);
327 
328 		if (conn_state->commit) {
329 			ret = wait_for_completion_interruptible_timeout(&conn_state->commit->hw_done,
330 									10 * HZ);
331 			if (ret == 0) {
332 				DRM_ERROR("HDCP state unknown! Setting it to DESIRED\n");
333 				hdcp_work->encryption_status[conn_index] =
334 					MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
335 			}
336 		}
337 		if (hdcp_work->encryption_status[conn_index] !=
338 			MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) {
339 			if (conn_state->hdcp_content_type ==
340 				DRM_MODE_HDCP_CONTENT_TYPE0 &&
341 				hdcp_work->encryption_status[conn_index] <=
342 				MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON) {
343 				DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_ENABLED\n");
344 				drm_hdcp_update_content_protection(connector,
345 								   DRM_MODE_CONTENT_PROTECTION_ENABLED);
346 			} else if (conn_state->hdcp_content_type ==
347 					DRM_MODE_HDCP_CONTENT_TYPE1 &&
348 					hdcp_work->encryption_status[conn_index] ==
349 					MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON) {
350 				drm_hdcp_update_content_protection(connector,
351 								   DRM_MODE_CONTENT_PROTECTION_ENABLED);
352 			}
353 		} else {
354 			DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_DESIRED\n");
355 			drm_hdcp_update_content_protection(connector,
356 							   DRM_MODE_CONTENT_PROTECTION_DESIRED);
357 		}
358 		mutex_unlock(&hdcp_work->mutex);
359 		drm_modeset_unlock(&dev->mode_config.connection_mutex);
360 	}
361 }
362 
event_property_validate(struct work_struct * work)363 static void event_property_validate(struct work_struct *work)
364 {
365 	struct hdcp_workqueue *hdcp_work =
366 		container_of(to_delayed_work(work), struct hdcp_workqueue, property_validate_dwork);
367 	struct mod_hdcp_display_query query;
368 	struct amdgpu_dm_connector *aconnector;
369 	unsigned int conn_index;
370 
371 	mutex_lock(&hdcp_work->mutex);
372 
373 	for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX;
374 	     conn_index++) {
375 		aconnector = hdcp_work->aconnector[conn_index];
376 
377 		if (!aconnector)
378 			continue;
379 
380 		/* check if display connected */
381 		if (aconnector->base.status != connector_status_connected)
382 			continue;
383 
384 		if (!aconnector->base.state)
385 			continue;
386 
387 		query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
388 		mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index,
389 				       &query);
390 
391 		DRM_DEBUG_DRIVER("[HDCP_DM] disp %d, connector->CP %u, (query, work): (%d, %d)\n",
392 				 aconnector->base.index,
393 			aconnector->base.state->content_protection,
394 			query.encryption_status,
395 			hdcp_work->encryption_status[conn_index]);
396 
397 		if (query.encryption_status !=
398 		    hdcp_work->encryption_status[conn_index]) {
399 			DRM_DEBUG_DRIVER("[HDCP_DM] encryption_status change from %x to %x\n",
400 					 hdcp_work->encryption_status[conn_index],
401 					 query.encryption_status);
402 
403 			hdcp_work->encryption_status[conn_index] =
404 				query.encryption_status;
405 
406 			DRM_DEBUG_DRIVER("[HDCP_DM] trigger property_update_work\n");
407 
408 			schedule_work(&hdcp_work->property_update_work);
409 		}
410 	}
411 
412 	mutex_unlock(&hdcp_work->mutex);
413 }
414 
event_watchdog_timer(struct work_struct * work)415 static void event_watchdog_timer(struct work_struct *work)
416 {
417 	struct hdcp_workqueue *hdcp_work;
418 
419 	hdcp_work = container_of(to_delayed_work(work),
420 				 struct hdcp_workqueue,
421 				      watchdog_timer_dwork);
422 
423 	mutex_lock(&hdcp_work->mutex);
424 
425 	cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
426 
427 	mod_hdcp_process_event(&hdcp_work->hdcp,
428 			       MOD_HDCP_EVENT_WATCHDOG_TIMEOUT,
429 			       &hdcp_work->output);
430 
431 	process_output(hdcp_work);
432 
433 	mutex_unlock(&hdcp_work->mutex);
434 }
435 
event_cpirq(struct work_struct * work)436 static void event_cpirq(struct work_struct *work)
437 {
438 	struct hdcp_workqueue *hdcp_work;
439 
440 	hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work);
441 
442 	mutex_lock(&hdcp_work->mutex);
443 
444 	mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output);
445 
446 	process_output(hdcp_work);
447 
448 	mutex_unlock(&hdcp_work->mutex);
449 }
450 
hdcp_destroy(struct kobject * kobj,struct hdcp_workqueue * hdcp_work)451 void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *hdcp_work)
452 {
453 	int i = 0;
454 
455 	for (i = 0; i < hdcp_work->max_link; i++) {
456 		cancel_delayed_work_sync(&hdcp_work[i].callback_dwork);
457 		cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork);
458 	}
459 
460 	sysfs_remove_bin_file(kobj, &hdcp_work[0].attr);
461 	kfree(hdcp_work->srm);
462 	kfree(hdcp_work->srm_temp);
463 	kfree(hdcp_work);
464 }
465 
enable_assr(void * handle,struct dc_link * link)466 static bool enable_assr(void *handle, struct dc_link *link)
467 {
468 	struct hdcp_workqueue *hdcp_work = handle;
469 	struct mod_hdcp hdcp = hdcp_work->hdcp;
470 	struct psp_context *psp = hdcp.config.psp.handle;
471 	struct ta_dtm_shared_memory *dtm_cmd;
472 	bool res = true;
473 
474 	if (!psp->dtm_context.context.initialized) {
475 		DRM_INFO("Failed to enable ASSR, DTM TA is not initialized.");
476 		return false;
477 	}
478 
479 	dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.context.mem_context.shared_buf;
480 
481 	mutex_lock(&psp->dtm_context.mutex);
482 	memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
483 
484 	dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE;
485 	dtm_cmd->dtm_in_message.topology_assr_enable.display_topology_dig_be_index =
486 		link->link_enc_hw_inst;
487 	dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
488 
489 	psp_dtm_invoke(psp, dtm_cmd->cmd_id);
490 
491 	if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) {
492 		DRM_INFO("Failed to enable ASSR");
493 		res = false;
494 	}
495 
496 	mutex_unlock(&psp->dtm_context.mutex);
497 
498 	return res;
499 }
500 
update_config(void * handle,struct cp_psp_stream_config * config)501 static void update_config(void *handle, struct cp_psp_stream_config *config)
502 {
503 	struct hdcp_workqueue *hdcp_work = handle;
504 	struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx;
505 	int link_index = aconnector->dc_link->link_index;
506 	struct mod_hdcp_display *display = &hdcp_work[link_index].display;
507 	struct mod_hdcp_link *link = &hdcp_work[link_index].link;
508 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
509 	struct dc_sink *sink = NULL;
510 	bool link_is_hdcp14 = false;
511 
512 	if (config->dpms_off) {
513 		hdcp_remove_display(hdcp_work, link_index, aconnector);
514 		return;
515 	}
516 
517 	memset(display, 0, sizeof(*display));
518 	memset(link, 0, sizeof(*link));
519 
520 	display->index = aconnector->base.index;
521 	display->state = MOD_HDCP_DISPLAY_ACTIVE;
522 
523 	if (aconnector->dc_sink)
524 		sink = aconnector->dc_sink;
525 	else if (aconnector->dc_em_sink)
526 		sink = aconnector->dc_em_sink;
527 
528 	if (sink)
529 		link->mode = mod_hdcp_signal_type_to_operation_mode(sink->sink_signal);
530 
531 	display->controller = CONTROLLER_ID_D0 + config->otg_inst;
532 	display->dig_fe = config->dig_fe;
533 	link->dig_be = config->dig_be;
534 	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
535 	display->stream_enc_idx = config->stream_enc_idx;
536 	link->link_enc_idx = config->link_enc_idx;
537 	link->dio_output_id = config->dio_output_idx;
538 	link->phy_idx = config->phy_idx;
539 
540 	if (sink)
541 		link_is_hdcp14 = dc_link_is_hdcp14(aconnector->dc_link, sink->sink_signal);
542 	link->hdcp_supported_informational = link_is_hdcp14;
543 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
544 	link->dp.assr_enabled = config->assr_enabled;
545 	link->dp.mst_enabled = config->mst_enabled;
546 	link->dp.dp2_enabled = config->dp2_enabled;
547 	link->dp.usb4_enabled = config->usb4_enabled;
548 	display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
549 	link->adjust.auth_delay = 2;
550 	link->adjust.hdcp1.disable = 0;
551 	hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
552 
553 	DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index,
554 			 (!!aconnector->base.state) ?
555 			 aconnector->base.state->content_protection : -1,
556 			 (!!aconnector->base.state) ?
557 			 aconnector->base.state->hdcp_content_type : -1);
558 
559 	mutex_lock(&hdcp_w->mutex);
560 
561 	mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
562 
563 	process_output(hdcp_w);
564 	mutex_unlock(&hdcp_w->mutex);
565 
566 }
567 
568 /**
569  * DOC: Add sysfs interface for set/get srm
570  *
571  * NOTE: From the usermodes prospective you only need to call write *ONCE*, the kernel
572  *      will automatically call once or twice depending on the size
573  *
574  * call: "cat file > /sys/class/drm/card0/device/hdcp_srm" from usermode no matter what the size is
575  *
576  * The kernel can only send PAGE_SIZE at once and since MAX_SRM_FILE(5120) > PAGE_SIZE(4096),
577  * srm_data_write can be called multiple times.
578  *
579  * sysfs interface doesn't tell us the size we will get so we are sending partial SRMs to psp and on
580  * the last call we will send the full SRM. PSP will fail on every call before the last.
581  *
582  * This means we don't know if the SRM is good until the last call. And because of this
583  * limitation we cannot throw errors early as it will stop the kernel from writing to sysfs
584  *
585  * Example 1:
586  *	Good SRM size = 5096
587  *	first call to write 4096 -> PSP fails
588  *	Second call to write 1000 -> PSP Pass -> SRM is set
589  *
590  * Example 2:
591  *	Bad SRM size = 4096
592  *	first call to write 4096 -> PSP fails (This is the same as above, but we don't know if this
593  *	is the last call)
594  *
595  * Solution?:
596  *	1: Parse the SRM? -> It is signed so we don't know the EOF
597  *	2: We can have another sysfs that passes the size before calling set. -> simpler solution
598  *	below
599  *
600  * Easy Solution:
601  * Always call get after Set to verify if set was successful.
602  * +----------------------+
603  * |   Why it works:      |
604  * +----------------------+
605  * PSP will only update its srm if its older than the one we are trying to load.
606  * Always do set first than get.
607  *	-if we try to "1. SET" a older version PSP will reject it and we can "2. GET" the newer
608  *	version and save it
609  *
610  *	-if we try to "1. SET" a newer version PSP will accept it and we can "2. GET" the
611  *	same(newer) version back and save it
612  *
613  *	-if we try to "1. SET" a newer version and PSP rejects it. That means the format is
614  *	incorrect/corrupted and we should correct our SRM by getting it from PSP
615  */
srm_data_write(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buffer,loff_t pos,size_t count)616 static ssize_t srm_data_write(struct file *filp, struct kobject *kobj,
617 			      struct bin_attribute *bin_attr, char *buffer,
618 			      loff_t pos, size_t count)
619 {
620 	struct hdcp_workqueue *work;
621 	u32 srm_version = 0;
622 
623 	work = container_of(bin_attr, struct hdcp_workqueue, attr);
624 	link_lock(work, true);
625 
626 	memcpy(work->srm_temp + pos, buffer, count);
627 
628 	if (!psp_set_srm(work->hdcp.config.psp.handle, work->srm_temp, pos + count, &srm_version)) {
629 		DRM_DEBUG_DRIVER("HDCP SRM SET version 0x%X", srm_version);
630 		memcpy(work->srm, work->srm_temp, pos + count);
631 		work->srm_size = pos + count;
632 		work->srm_version = srm_version;
633 	}
634 
635 	link_lock(work, false);
636 
637 	return count;
638 }
639 
srm_data_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buffer,loff_t pos,size_t count)640 static ssize_t srm_data_read(struct file *filp, struct kobject *kobj,
641 			     struct bin_attribute *bin_attr, char *buffer,
642 			     loff_t pos, size_t count)
643 {
644 	struct hdcp_workqueue *work;
645 	u8 *srm = NULL;
646 	u32 srm_version;
647 	u32 srm_size;
648 	size_t ret = count;
649 
650 	work = container_of(bin_attr, struct hdcp_workqueue, attr);
651 
652 	link_lock(work, true);
653 
654 	srm = psp_get_srm(work->hdcp.config.psp.handle, &srm_version, &srm_size);
655 
656 	if (!srm) {
657 		ret = -EINVAL;
658 		goto ret;
659 	}
660 
661 	if (pos >= srm_size)
662 		ret = 0;
663 
664 	if (srm_size - pos < count) {
665 		memcpy(buffer, srm + pos, srm_size - pos);
666 		ret = srm_size - pos;
667 		goto ret;
668 	}
669 
670 	memcpy(buffer, srm + pos, count);
671 
672 ret:
673 	link_lock(work, false);
674 	return ret;
675 }
676 
677 /* From the hdcp spec (5.Renewability) SRM needs to be stored in a non-volatile memory.
678  *
679  * For example,
680  *	if Application "A" sets the SRM (ver 2) and we reboot/suspend and later when Application "B"
681  *	needs to use HDCP, the version in PSP should be SRM(ver 2). So SRM should be persistent
682  *	across boot/reboots/suspend/resume/shutdown
683  *
684  * Currently when the system goes down (suspend/shutdown) the SRM is cleared from PSP. For HDCP
685  * we need to make the SRM persistent.
686  *
687  * -PSP owns the checking of SRM but doesn't have the ability to store it in a non-volatile memory.
688  * -The kernel cannot write to the file systems.
689  * -So we need usermode to do this for us, which is why an interface for usermode is needed
690  *
691  *
692  *
693  * Usermode can read/write to/from PSP using the sysfs interface
694  * For example:
695  *	to save SRM from PSP to storage : cat /sys/class/drm/card0/device/hdcp_srm > srmfile
696  *	to load from storage to PSP: cat srmfile > /sys/class/drm/card0/device/hdcp_srm
697  */
698 static const struct bin_attribute data_attr = {
699 	.attr = {.name = "hdcp_srm", .mode = 0664},
700 	.size = PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, /* Limit SRM size */
701 	.write = srm_data_write,
702 	.read = srm_data_read,
703 };
704 
hdcp_create_workqueue(struct amdgpu_device * adev,struct cp_psp * cp_psp,struct dc * dc)705 struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev,
706 					     struct cp_psp *cp_psp, struct dc *dc)
707 {
708 	int max_caps = dc->caps.max_links;
709 	struct hdcp_workqueue *hdcp_work;
710 	int i = 0;
711 
712 	hdcp_work = kcalloc(max_caps, sizeof(*hdcp_work), GFP_KERNEL);
713 	if (ZERO_OR_NULL_PTR(hdcp_work))
714 		return NULL;
715 
716 	hdcp_work->srm = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE,
717 				 sizeof(*hdcp_work->srm), GFP_KERNEL);
718 
719 	if (!hdcp_work->srm)
720 		goto fail_alloc_context;
721 
722 	hdcp_work->srm_temp = kcalloc(PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE,
723 				      sizeof(*hdcp_work->srm_temp), GFP_KERNEL);
724 
725 	if (!hdcp_work->srm_temp)
726 		goto fail_alloc_context;
727 
728 	hdcp_work->max_link = max_caps;
729 
730 	for (i = 0; i < max_caps; i++) {
731 		mutex_init(&hdcp_work[i].mutex);
732 
733 		INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq);
734 		INIT_WORK(&hdcp_work[i].property_update_work, event_property_update);
735 		INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback);
736 		INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer);
737 		INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);
738 
739 		hdcp_work[i].hdcp.config.psp.handle = &adev->psp;
740 		if (dc->ctx->dce_version == DCN_VERSION_3_1 ||
741 		    dc->ctx->dce_version == DCN_VERSION_3_14 ||
742 		    dc->ctx->dce_version == DCN_VERSION_3_15 ||
743 		    dc->ctx->dce_version == DCN_VERSION_3_5 ||
744 		    dc->ctx->dce_version == DCN_VERSION_3_51 ||
745 		    dc->ctx->dce_version == DCN_VERSION_3_16)
746 			hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
747 		hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
748 		hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
749 		hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
750 		hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd;
751 		hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd;
752 
753 		memset(hdcp_work[i].aconnector, 0,
754 		       sizeof(struct amdgpu_dm_connector *) *
755 			       AMDGPU_DM_MAX_DISPLAY_INDEX);
756 		memset(hdcp_work[i].encryption_status, 0,
757 		       sizeof(enum mod_hdcp_encryption_status) *
758 			       AMDGPU_DM_MAX_DISPLAY_INDEX);
759 	}
760 
761 	cp_psp->funcs.update_stream_config = update_config;
762 	cp_psp->funcs.enable_assr = enable_assr;
763 	cp_psp->handle = hdcp_work;
764 
765 	/* File created at /sys/class/drm/card0/device/hdcp_srm*/
766 	hdcp_work[0].attr = data_attr;
767 	sysfs_bin_attr_init(&hdcp_work[0].attr);
768 
769 	if (sysfs_create_bin_file(&adev->dev->kobj, &hdcp_work[0].attr))
770 		DRM_WARN("Failed to create device file hdcp_srm");
771 
772 	return hdcp_work;
773 
774 fail_alloc_context:
775 	kfree(hdcp_work->srm);
776 	kfree(hdcp_work->srm_temp);
777 	kfree(hdcp_work);
778 
779 	return NULL;
780 }
781 
782