1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file manages link detection states and receiver states by using various
28 * link protocols. It also provides helper functions to interpret certain
29 * capabilities or status based on the states it manages or retrieve them
30 * directly from connected receivers.
31 */
32
33 #include "link_dpms.h"
34 #include "link_detection.h"
35 #include "link_hwss.h"
36 #include "protocols/link_edp_panel_control.h"
37 #include "protocols/link_ddc.h"
38 #include "protocols/link_hpd.h"
39 #include "protocols/link_dpcd.h"
40 #include "protocols/link_dp_capability.h"
41 #include "protocols/link_dp_dpia.h"
42 #include "protocols/link_dp_phy.h"
43 #include "protocols/link_dp_training.h"
44 #include "protocols/link_dp_dpia_bw.h"
45 #include "accessories/link_dp_trace.h"
46
47 #include "link_enc_cfg.h"
48 #include "dm_helpers.h"
49 #include "clk_mgr.h"
50
51 // Offset DPCD 050Eh == 0x5A
52 #define MST_HUB_ID_0x5A 0x5A
53
54 #define DC_LOGGER \
55 link->ctx->logger
56 #define DC_LOGGER_INIT(logger)
57
58 #define LINK_INFO(...) \
59 DC_LOG_HW_HOTPLUG( \
60 __VA_ARGS__)
61 /*
62 * Some receivers fail to train on first try and are good
63 * on subsequent tries. 2 retries should be plenty. If we
64 * don't have a successful training then we don't expect to
65 * ever get one.
66 */
67 #define LINK_TRAINING_MAX_VERIFY_RETRY 2
68
69 static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u";
70
71 static const u8 dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
72
get_ddc_transaction_type(enum signal_type sink_signal)73 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
74 {
75 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
76
77 switch (sink_signal) {
78 case SIGNAL_TYPE_DVI_SINGLE_LINK:
79 case SIGNAL_TYPE_DVI_DUAL_LINK:
80 case SIGNAL_TYPE_HDMI_TYPE_A:
81 case SIGNAL_TYPE_LVDS:
82 case SIGNAL_TYPE_RGB:
83 transaction_type = DDC_TRANSACTION_TYPE_I2C;
84 break;
85
86 case SIGNAL_TYPE_DISPLAY_PORT:
87 case SIGNAL_TYPE_EDP:
88 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
89 break;
90
91 case SIGNAL_TYPE_DISPLAY_PORT_MST:
92 /* MST does not use I2COverAux, but there is the
93 * SPECIAL use case for "immediate dwnstrm device
94 * access" (EPR#370830).
95 */
96 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
97 break;
98
99 default:
100 break;
101 }
102
103 return transaction_type;
104 }
105
get_basic_signal_type(struct graphics_object_id encoder,struct graphics_object_id downstream)106 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
107 struct graphics_object_id downstream)
108 {
109 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
110 switch (downstream.id) {
111 case CONNECTOR_ID_SINGLE_LINK_DVII:
112 switch (encoder.id) {
113 case ENCODER_ID_INTERNAL_DAC1:
114 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
115 case ENCODER_ID_INTERNAL_DAC2:
116 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
117 return SIGNAL_TYPE_RGB;
118 default:
119 return SIGNAL_TYPE_DVI_SINGLE_LINK;
120 }
121 break;
122 case CONNECTOR_ID_DUAL_LINK_DVII:
123 {
124 switch (encoder.id) {
125 case ENCODER_ID_INTERNAL_DAC1:
126 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
127 case ENCODER_ID_INTERNAL_DAC2:
128 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
129 return SIGNAL_TYPE_RGB;
130 default:
131 return SIGNAL_TYPE_DVI_DUAL_LINK;
132 }
133 }
134 break;
135 case CONNECTOR_ID_SINGLE_LINK_DVID:
136 return SIGNAL_TYPE_DVI_SINGLE_LINK;
137 case CONNECTOR_ID_DUAL_LINK_DVID:
138 return SIGNAL_TYPE_DVI_DUAL_LINK;
139 case CONNECTOR_ID_VGA:
140 return SIGNAL_TYPE_RGB;
141 case CONNECTOR_ID_HDMI_TYPE_A:
142 return SIGNAL_TYPE_HDMI_TYPE_A;
143 case CONNECTOR_ID_LVDS:
144 return SIGNAL_TYPE_LVDS;
145 case CONNECTOR_ID_DISPLAY_PORT:
146 case CONNECTOR_ID_USBC:
147 return SIGNAL_TYPE_DISPLAY_PORT;
148 case CONNECTOR_ID_EDP:
149 return SIGNAL_TYPE_EDP;
150 default:
151 return SIGNAL_TYPE_NONE;
152 }
153 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
154 switch (downstream.id) {
155 case ENCODER_ID_EXTERNAL_NUTMEG:
156 case ENCODER_ID_EXTERNAL_TRAVIS:
157 return SIGNAL_TYPE_DISPLAY_PORT;
158 default:
159 return SIGNAL_TYPE_NONE;
160 }
161 }
162
163 return SIGNAL_TYPE_NONE;
164 }
165
166 /*
167 * @brief
168 * Detect output sink type
169 */
link_detect_sink_signal_type(struct dc_link * link,enum dc_detect_reason reason)170 static enum signal_type link_detect_sink_signal_type(struct dc_link *link,
171 enum dc_detect_reason reason)
172 {
173 enum signal_type result;
174 struct graphics_object_id enc_id;
175
176 if (link->is_dig_mapping_flexible)
177 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
178 else
179 enc_id = link->link_enc->id;
180 result = get_basic_signal_type(enc_id, link->link_id);
181
182 /* Use basic signal type for link without physical connector. */
183 if (link->ep_type != DISPLAY_ENDPOINT_PHY)
184 return result;
185
186 /* Internal digital encoder will detect only dongles
187 * that require digital signal
188 */
189
190 /* Detection mechanism is different
191 * for different native connectors.
192 * LVDS connector supports only LVDS signal;
193 * PCIE is a bus slot, the actual connector needs to be detected first;
194 * eDP connector supports only eDP signal;
195 * HDMI should check straps for audio
196 */
197
198 /* PCIE detects the actual connector on add-on board */
199 if (link->link_id.id == CONNECTOR_ID_PCIE) {
200 /* ZAZTODO implement PCIE add-on card detection */
201 }
202
203 switch (link->link_id.id) {
204 case CONNECTOR_ID_HDMI_TYPE_A: {
205 /* check audio support:
206 * if native HDMI is not supported, switch to DVI
207 */
208 struct audio_support *aud_support =
209 &link->dc->res_pool->audio_support;
210
211 if (!aud_support->hdmi_audio_native)
212 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
213 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
214 }
215 break;
216 case CONNECTOR_ID_DISPLAY_PORT:
217 case CONNECTOR_ID_USBC: {
218 /* DP HPD short pulse. Passive DP dongle will not
219 * have short pulse
220 */
221 if (reason != DETECT_REASON_HPDRX) {
222 /* Check whether DP signal detected: if not -
223 * we assume signal is DVI; it could be corrected
224 * to HDMI after dongle detection
225 */
226 if (!dm_helpers_is_dp_sink_present(link))
227 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
228 }
229 }
230 break;
231 default:
232 break;
233 }
234
235 return result;
236 }
237
decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,struct audio_support * audio_support)238 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
239 struct audio_support *audio_support)
240 {
241 enum signal_type signal = SIGNAL_TYPE_NONE;
242
243 switch (dongle_type) {
244 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
245 if (audio_support->hdmi_audio_on_dongle)
246 signal = SIGNAL_TYPE_HDMI_TYPE_A;
247 else
248 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
249 break;
250 case DISPLAY_DONGLE_DP_DVI_DONGLE:
251 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
252 break;
253 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
254 if (audio_support->hdmi_audio_native)
255 signal = SIGNAL_TYPE_HDMI_TYPE_A;
256 else
257 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
258 break;
259 default:
260 signal = SIGNAL_TYPE_NONE;
261 break;
262 }
263
264 return signal;
265 }
266
read_scdc_caps(struct ddc_service * ddc_service,struct dc_sink * sink)267 static void read_scdc_caps(struct ddc_service *ddc_service,
268 struct dc_sink *sink)
269 {
270 uint8_t slave_address = HDMI_SCDC_ADDRESS;
271 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI;
272
273 if (ddc_service->link->local_sink &&
274 !ddc_service->link->local_sink->edid_caps.scdc_present)
275 return;
276
277 link_query_ddc_data(ddc_service, slave_address, &offset,
278 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte,
279 sizeof(sink->scdc_caps.manufacturer_OUI.byte));
280
281 offset = HDMI_SCDC_DEVICE_ID;
282
283 link_query_ddc_data(ddc_service, slave_address, &offset,
284 sizeof(offset), &(sink->scdc_caps.device_id.byte),
285 sizeof(sink->scdc_caps.device_id.byte));
286 }
287
i2c_read(struct ddc_service * ddc,uint32_t address,uint8_t * buffer,uint32_t len)288 static bool i2c_read(
289 struct ddc_service *ddc,
290 uint32_t address,
291 uint8_t *buffer,
292 uint32_t len)
293 {
294 uint8_t offs_data = 0;
295 struct i2c_payload payloads[2] = {
296 {
297 .write = true,
298 .address = address,
299 .length = 1,
300 .data = &offs_data },
301 {
302 .write = false,
303 .address = address,
304 .length = len,
305 .data = buffer } };
306
307 struct i2c_command command = {
308 .payloads = payloads,
309 .number_of_payloads = 2,
310 .engine = DDC_I2C_COMMAND_ENGINE,
311 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
312
313 return dm_helpers_submit_i2c(
314 ddc->ctx,
315 ddc->link,
316 &command);
317 }
318
319 enum {
320 DP_SINK_CAP_SIZE =
321 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
322 };
323
query_dp_dual_mode_adaptor(struct ddc_service * ddc,struct display_sink_capability * sink_cap)324 static void query_dp_dual_mode_adaptor(
325 struct ddc_service *ddc,
326 struct display_sink_capability *sink_cap)
327 {
328 uint8_t i;
329 bool is_valid_hdmi_signature;
330 enum display_dongle_type *dongle = &sink_cap->dongle_type;
331 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
332 bool is_type2_dongle = false;
333 int retry_count = 2;
334 struct dp_hdmi_dongle_signature_data *dongle_signature;
335 struct dc_link *link = ddc->link;
336
337 /* Assume we have no valid DP passive dongle connected */
338 *dongle = DISPLAY_DONGLE_NONE;
339 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
340
341 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
342 if (!i2c_read(
343 ddc,
344 DP_HDMI_DONGLE_ADDRESS,
345 type2_dongle_buf,
346 sizeof(type2_dongle_buf))) {
347 /* Passive HDMI dongles can sometimes fail here without retrying*/
348 while (retry_count > 0) {
349 if (i2c_read(ddc,
350 DP_HDMI_DONGLE_ADDRESS,
351 type2_dongle_buf,
352 sizeof(type2_dongle_buf)))
353 break;
354 retry_count--;
355 }
356 if (retry_count == 0) {
357 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
358 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
359
360 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
361 "DP-DVI passive dongle %dMhz: ",
362 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
363 return;
364 }
365 }
366
367 /* Check if Type 2 dongle.*/
368 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
369 is_type2_dongle = true;
370
371 dongle_signature =
372 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
373
374 is_valid_hdmi_signature = true;
375
376 /* Check EOT */
377 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
378 is_valid_hdmi_signature = false;
379 }
380
381 /* Check signature */
382 for (i = 0; i < sizeof(dongle_signature->id); ++i) {
383 /* If its not the right signature,
384 * skip mismatch in subversion byte.*/
385 if (dongle_signature->id[i] !=
386 dp_hdmi_dongle_signature_str[i] && i != 3) {
387
388 if (is_type2_dongle) {
389 is_valid_hdmi_signature = false;
390 break;
391 }
392
393 }
394 }
395
396 if (is_type2_dongle) {
397 uint32_t max_tmds_clk =
398 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
399
400 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
401
402 if (0 == max_tmds_clk ||
403 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
404 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
405 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
406
407 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
408 sizeof(type2_dongle_buf),
409 "DP-DVI passive dongle %dMhz: ",
410 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
411 } else {
412 if (is_valid_hdmi_signature == true) {
413 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
414
415 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
416 sizeof(type2_dongle_buf),
417 "Type 2 DP-HDMI passive dongle %dMhz: ",
418 max_tmds_clk);
419 } else {
420 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
421
422 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
423 sizeof(type2_dongle_buf),
424 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
425 max_tmds_clk);
426
427 }
428
429 /* Multiply by 1000 to convert to kHz. */
430 sink_cap->max_hdmi_pixel_clock =
431 max_tmds_clk * 1000;
432 }
433 sink_cap->is_dongle_type_one = false;
434
435 } else {
436 if (is_valid_hdmi_signature == true) {
437 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
438
439 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
440 sizeof(type2_dongle_buf),
441 "Type 1 DP-HDMI passive dongle %dMhz: ",
442 sink_cap->max_hdmi_pixel_clock / 1000);
443 } else {
444 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
445
446 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
447 sizeof(type2_dongle_buf),
448 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
449 sink_cap->max_hdmi_pixel_clock / 1000);
450 }
451 sink_cap->is_dongle_type_one = true;
452 }
453
454 return;
455 }
456
dp_passive_dongle_detection(struct ddc_service * ddc,struct display_sink_capability * sink_cap,struct audio_support * audio_support)457 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
458 struct display_sink_capability *sink_cap,
459 struct audio_support *audio_support)
460 {
461 query_dp_dual_mode_adaptor(ddc, sink_cap);
462
463 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
464 audio_support);
465 }
466
link_disconnect_sink(struct dc_link * link)467 static void link_disconnect_sink(struct dc_link *link)
468 {
469 if (link->local_sink) {
470 dc_sink_release(link->local_sink);
471 link->local_sink = NULL;
472 }
473
474 link->dpcd_sink_count = 0;
475 //link->dpcd_caps.dpcd_rev.raw = 0;
476 }
477
link_disconnect_remap(struct dc_sink * prev_sink,struct dc_link * link)478 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
479 {
480 dc_sink_release(link->local_sink);
481 link->local_sink = prev_sink;
482 }
483
query_hdcp_capability(enum signal_type signal,struct dc_link * link)484 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
485 {
486 struct hdcp_protection_message msg22;
487 struct hdcp_protection_message msg14;
488
489 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
490 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
491 memset(link->hdcp_caps.rx_caps.raw, 0,
492 sizeof(link->hdcp_caps.rx_caps.raw));
493
494 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
495 link->ddc->transaction_type ==
496 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
497 link->connector_signal == SIGNAL_TYPE_EDP) {
498 msg22.data = link->hdcp_caps.rx_caps.raw;
499 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
500 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
501 } else {
502 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
503 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
504 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
505 }
506 msg22.version = HDCP_VERSION_22;
507 msg22.link = HDCP_LINK_PRIMARY;
508 msg22.max_retries = 5;
509 dc_process_hdcp_msg(signal, link, &msg22);
510
511 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
512 msg14.data = &link->hdcp_caps.bcaps.raw;
513 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
514 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
515 msg14.version = HDCP_VERSION_14;
516 msg14.link = HDCP_LINK_PRIMARY;
517 msg14.max_retries = 5;
518
519 dc_process_hdcp_msg(signal, link, &msg14);
520 }
521
522 }
read_current_link_settings_on_detect(struct dc_link * link)523 static void read_current_link_settings_on_detect(struct dc_link *link)
524 {
525 union lane_count_set lane_count_set = {0};
526 uint8_t link_bw_set = 0;
527 uint8_t link_rate_set = 0;
528 uint32_t read_dpcd_retry_cnt = 10;
529 enum dc_status status = DC_ERROR_UNEXPECTED;
530 int i;
531 union max_down_spread max_down_spread = {0};
532
533 // Read DPCD 00101h to find out the number of lanes currently set
534 for (i = 0; i < read_dpcd_retry_cnt; i++) {
535 status = core_link_read_dpcd(link,
536 DP_LANE_COUNT_SET,
537 &lane_count_set.raw,
538 sizeof(lane_count_set));
539 /* First DPCD read after VDD ON can fail if the particular board
540 * does not have HPD pin wired correctly. So if DPCD read fails,
541 * which it should never happen, retry a few times. Target worst
542 * case scenario of 80 ms.
543 */
544 if (status == DC_OK) {
545 link->cur_link_settings.lane_count =
546 lane_count_set.bits.LANE_COUNT_SET;
547 break;
548 }
549
550 msleep(8);
551 }
552
553 // Read DPCD 00100h to find if standard link rates are set
554 core_link_read_dpcd(link, DP_LINK_BW_SET,
555 &link_bw_set, sizeof(link_bw_set));
556
557 if (link_bw_set == 0) {
558 if (link->connector_signal == SIGNAL_TYPE_EDP) {
559 /* If standard link rates are not being used,
560 * Read DPCD 00115h to find the edp link rate set used
561 */
562 core_link_read_dpcd(link, DP_LINK_RATE_SET,
563 &link_rate_set, sizeof(link_rate_set));
564
565 // edp_supported_link_rates_count = 0 for DP
566 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
567 link->cur_link_settings.link_rate =
568 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
569 link->cur_link_settings.link_rate_set = link_rate_set;
570 link->cur_link_settings.use_link_rate_set = true;
571 }
572 } else {
573 // Link Rate not found. Seamless boot may not work.
574 ASSERT(false);
575 }
576 } else {
577 link->cur_link_settings.link_rate = link_bw_set;
578 link->cur_link_settings.use_link_rate_set = false;
579 }
580 // Read DPCD 00003h to find the max down spread.
581 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
582 &max_down_spread.raw, sizeof(max_down_spread));
583 link->cur_link_settings.link_spread =
584 max_down_spread.bits.MAX_DOWN_SPREAD ?
585 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
586 }
587
detect_dp(struct dc_link * link,struct display_sink_capability * sink_caps,enum dc_detect_reason reason)588 static bool detect_dp(struct dc_link *link,
589 struct display_sink_capability *sink_caps,
590 enum dc_detect_reason reason)
591 {
592 struct audio_support *audio_support = &link->dc->res_pool->audio_support;
593
594 sink_caps->signal = link_detect_sink_signal_type(link, reason);
595 sink_caps->transaction_type =
596 get_ddc_transaction_type(sink_caps->signal);
597
598 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
599 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
600 if (!detect_dp_sink_caps(link)) {
601 return false;
602 }
603
604 if (is_dp_branch_device(link))
605 /* DP SST branch */
606 link->type = dc_connection_sst_branch;
607 } else {
608 if (link->dc->debug.disable_dp_plus_plus_wa &&
609 link->link_enc->features.flags.bits.IS_UHBR20_CAPABLE)
610 return false;
611
612 /* DP passive dongles */
613 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
614 sink_caps,
615 audio_support);
616 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
617 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
618 link->dpcd_caps.dpcd_rev.raw = 0;
619 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0;
620 }
621
622 return true;
623 }
624
is_same_edid(struct dc_edid * old_edid,struct dc_edid * new_edid)625 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
626 {
627 if (old_edid->length != new_edid->length)
628 return false;
629
630 if (new_edid->length == 0)
631 return false;
632
633 return (memcmp(old_edid->raw_edid,
634 new_edid->raw_edid, new_edid->length) == 0);
635 }
636
wait_for_entering_dp_alt_mode(struct dc_link * link)637 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
638 {
639
640 /**
641 * something is terribly wrong if time out is > 200ms. (5Hz)
642 * 500 microseconds * 400 tries us 200 ms
643 **/
644 unsigned int sleep_time_in_microseconds = 500;
645 unsigned int tries_allowed = 400;
646 bool is_in_alt_mode;
647 unsigned long long enter_timestamp;
648 unsigned long long finish_timestamp;
649 unsigned long long time_taken_in_ns;
650 int tries_taken;
651
652 DC_LOGGER_INIT(link->ctx->logger);
653
654 /**
655 * this function will only exist if we are on dcn21 (is_in_alt_mode is a
656 * function pointer, so checking to see if it is equal to 0 is the same
657 * as checking to see if it is null
658 **/
659 if (!link->link_enc->funcs->is_in_alt_mode)
660 return true;
661
662 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
663 DC_LOG_DC("DP Alt mode state on HPD: %d Link=%d\n", is_in_alt_mode, link->link_index);
664
665 if (is_in_alt_mode)
666 return true;
667
668 enter_timestamp = dm_get_timestamp(link->ctx);
669
670 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
671 udelay(sleep_time_in_microseconds);
672 /* ask the link if alt mode is enabled, if so return ok */
673 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
674 finish_timestamp = dm_get_timestamp(link->ctx);
675 time_taken_in_ns =
676 dm_get_elapse_time_in_ns(link->ctx,
677 finish_timestamp,
678 enter_timestamp);
679 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
680 div_u64(time_taken_in_ns, 1000000));
681 return true;
682 }
683 }
684 finish_timestamp = dm_get_timestamp(link->ctx);
685 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
686 enter_timestamp);
687 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
688 div_u64(time_taken_in_ns, 1000000));
689 return false;
690 }
691
apply_dpia_mst_dsc_always_on_wa(struct dc_link * link)692 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
693 {
694 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
695 * reports DSC support.
696 */
697 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
698 link->type == dc_connection_mst_branch &&
699 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
700 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
701 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
702 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
703 link->wa_flags.dpia_mst_dsc_always_on = true;
704
705 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
706 link->type == dc_connection_mst_branch &&
707 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
708 link->dpcd_caps.branch_vendor_specific_data[2] == MST_HUB_ID_0x5A &&
709 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
710 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) {
711 link->wa_flags.dpia_mst_dsc_always_on = true;
712 }
713 }
714
revert_dpia_mst_dsc_always_on_wa(struct dc_link * link)715 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
716 {
717 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
718 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
719 link->wa_flags.dpia_mst_dsc_always_on = false;
720 }
721
discover_dp_mst_topology(struct dc_link * link,enum dc_detect_reason reason)722 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
723 {
724 DC_LOGGER_INIT(link->ctx->logger);
725
726 LINK_INFO("link=%d, mst branch is now Connected\n",
727 link->link_index);
728
729 link->type = dc_connection_mst_branch;
730 apply_dpia_mst_dsc_always_on_wa(link);
731
732 dm_helpers_dp_update_branch_info(link->ctx, link);
733 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
734 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
735 link_disconnect_sink(link);
736 } else {
737 link->type = dc_connection_sst_branch;
738 }
739
740 return link->type == dc_connection_mst_branch;
741 }
742
link_reset_cur_dp_mst_topology(struct dc_link * link)743 bool link_reset_cur_dp_mst_topology(struct dc_link *link)
744 {
745 DC_LOGGER_INIT(link->ctx->logger);
746
747 LINK_INFO("link=%d, mst branch is now Disconnected\n",
748 link->link_index);
749
750 revert_dpia_mst_dsc_always_on_wa(link);
751 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
752 }
753
should_prepare_phy_clocks_for_link_verification(const struct dc * dc,enum dc_detect_reason reason)754 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
755 enum dc_detect_reason reason)
756 {
757 int i;
758 bool can_apply_seamless_boot = false;
759
760 for (i = 0; i < dc->current_state->stream_count; i++) {
761 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
762 can_apply_seamless_boot = true;
763 break;
764 }
765 }
766
767 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
768 }
769
prepare_phy_clocks_for_destructive_link_verification(const struct dc * dc)770 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
771 {
772 dc_z10_restore(dc);
773 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
774 }
775
restore_phy_clocks_for_destructive_link_verification(const struct dc * dc)776 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
777 {
778 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
779 }
780
verify_link_capability_destructive(struct dc_link * link,struct dc_sink * sink,enum dc_detect_reason reason)781 static void verify_link_capability_destructive(struct dc_link *link,
782 struct dc_sink *sink,
783 enum dc_detect_reason reason)
784 {
785 bool should_prepare_phy_clocks =
786 should_prepare_phy_clocks_for_link_verification(link->dc, reason);
787
788 if (should_prepare_phy_clocks)
789 prepare_phy_clocks_for_destructive_link_verification(link->dc);
790
791 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
792 struct dc_link_settings known_limit_link_setting =
793 dp_get_max_link_cap(link);
794 link_set_all_streams_dpms_off_for_link(link);
795 dp_verify_link_cap_with_retries(
796 link, &known_limit_link_setting,
797 LINK_TRAINING_MAX_VERIFY_RETRY);
798 } else {
799 ASSERT(0);
800 }
801
802 if (should_prepare_phy_clocks)
803 restore_phy_clocks_for_destructive_link_verification(link->dc);
804 }
805
verify_link_capability_non_destructive(struct dc_link * link)806 static void verify_link_capability_non_destructive(struct dc_link *link)
807 {
808 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
809 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
810 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
811 /* TODO - should we check link encoder's max link caps here?
812 * How do we know which link encoder to check from?
813 */
814 link->verified_link_cap = link->reported_link_cap;
815 else
816 link->verified_link_cap = dp_get_max_link_cap(link);
817 }
818 }
819
should_verify_link_capability_destructively(struct dc_link * link,enum dc_detect_reason reason)820 static bool should_verify_link_capability_destructively(struct dc_link *link,
821 enum dc_detect_reason reason)
822 {
823 bool destrictive = false;
824 struct dc_link_settings max_link_cap;
825 bool is_link_enc_unavailable = false;
826
827 if (!link->dc->config.unify_link_enc_assignment)
828 is_link_enc_unavailable = link->link_enc &&
829 link->dc->res_pool->funcs->link_encs_assign &&
830 !link_enc_cfg_is_link_enc_avail(
831 link->ctx->dc,
832 link->link_enc->preferred_engine,
833 link);
834
835 if (dc_is_dp_signal(link->local_sink->sink_signal)) {
836 max_link_cap = dp_get_max_link_cap(link);
837 destrictive = true;
838
839 if (link->dc->debug.skip_detection_link_training ||
840 dc_is_embedded_signal(link->local_sink->sink_signal) ||
841 (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
842 !link->dc->config.enable_dpia_pre_training)) {
843 destrictive = false;
844 } else if (link_dp_get_encoding_format(&max_link_cap) ==
845 DP_8b_10b_ENCODING) {
846 if (link->dpcd_caps.is_mst_capable ||
847 is_link_enc_unavailable) {
848 destrictive = false;
849 }
850 }
851 }
852
853 return destrictive;
854 }
855
verify_link_capability(struct dc_link * link,struct dc_sink * sink,enum dc_detect_reason reason)856 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
857 enum dc_detect_reason reason)
858 {
859 if (should_verify_link_capability_destructively(link, reason))
860 verify_link_capability_destructive(link, sink, reason);
861 else
862 verify_link_capability_non_destructive(link);
863 }
864
865 /**
866 * link_detect_evaluate_edid_header() - Evaluate if an EDID header is acceptable.
867 *
868 * Evaluates an 8-byte EDID header to check if it's good enough
869 * for the purpose of determining whether a display is connected
870 * without reading the full EDID.
871 *
872 * @edid_header: The first 8 bytes of the EDID read from DDC.
873 *
874 * Return: true if the header looks valid (>= 6 of 8 bytes match the
875 * expected 00/FF pattern), false otherwise.
876 */
link_detect_evaluate_edid_header(uint8_t edid_header[8])877 static bool link_detect_evaluate_edid_header(uint8_t edid_header[8])
878 {
879 int edid_header_score = 0;
880 int i;
881
882 for (i = 0; i < 8; ++i)
883 edid_header_score += edid_header[i] == ((i == 0 || i == 7) ? 0x00 : 0xff);
884
885 return edid_header_score >= 6;
886 }
887
888 /**
889 * link_detect_ddc_probe() - Probe the DDC to see if a display is connected.
890 *
891 * Detect whether a display is connected to DDC without reading full EDID.
892 * Reads only the EDID header (the first 8 bytes of EDID) from DDC and
893 * evaluates whether that matches.
894 *
895 * @link: DC link whose DDC/I2C is probed for the EDID header.
896 *
897 * Return: true if the EDID header was read and passes validation,
898 * false otherwise.
899 */
link_detect_ddc_probe(struct dc_link * link)900 static bool link_detect_ddc_probe(struct dc_link *link)
901 {
902 if (!link->ddc)
903 return false;
904
905 uint8_t edid_header[8] = {0};
906 bool ddc_probed = i2c_read(link->ddc, 0x50, edid_header, sizeof(edid_header));
907
908 if (!ddc_probed)
909 return false;
910
911 if (!link_detect_evaluate_edid_header(edid_header))
912 return false;
913
914 return true;
915 }
916
917 /**
918 * link_detect_dac_load_detect() - Performs DAC load detection.
919 *
920 * Load detection can be used to detect the presence of an
921 * analog display when we can't read DDC. This causes a visible
922 * visual glitch so it should be used sparingly.
923 *
924 * @link: DC link to test using the DAC load-detect path.
925 *
926 * Return: true if the VBIOS load-detect call reports OK, false
927 * otherwise.
928 */
link_detect_dac_load_detect(struct dc_link * link)929 static bool link_detect_dac_load_detect(struct dc_link *link)
930 {
931 struct dc_bios *bios = link->ctx->dc_bios;
932 struct link_encoder *link_enc = link->link_enc;
933 enum engine_id engine_id = link_enc->preferred_engine;
934 enum dal_device_type device_type = DEVICE_TYPE_CRT;
935 enum bp_result bp_result;
936 uint32_t enum_id;
937
938 switch (engine_id) {
939 case ENGINE_ID_DACB:
940 enum_id = 2;
941 break;
942 case ENGINE_ID_DACA:
943 default:
944 engine_id = ENGINE_ID_DACA;
945 enum_id = 1;
946 break;
947 }
948
949 bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id);
950 return bp_result == BP_RESULT_OK;
951 }
952
953 /*
954 * detect_link_and_local_sink() - Detect if a sink is attached to a given link
955 *
956 * link->local_sink is created or destroyed as needed.
957 *
958 * This does not create remote sinks.
959 */
detect_link_and_local_sink(struct dc_link * link,enum dc_detect_reason reason)960 static bool detect_link_and_local_sink(struct dc_link *link,
961 enum dc_detect_reason reason)
962 {
963 struct dc_sink_init_data sink_init_data = { 0 };
964 struct display_sink_capability sink_caps = { 0 };
965 uint32_t i;
966 bool converter_disable_audio = false;
967 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
968 bool same_edid = false;
969 enum dc_edid_status edid_status;
970 struct dc_context *dc_ctx = link->ctx;
971 struct dc *dc = dc_ctx->dc;
972 struct dc_sink *sink = NULL;
973 struct dc_sink *prev_sink = NULL;
974 struct dpcd_caps prev_dpcd_caps;
975 enum dc_connection_type new_connection_type = dc_connection_none;
976 const uint32_t post_oui_delay = 30; // 30ms
977
978 DC_LOGGER_INIT(link->ctx->logger);
979
980 if (dc_is_virtual_signal(link->connector_signal))
981 return false;
982
983 if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
984 link->connector_signal == SIGNAL_TYPE_EDP) &&
985 (!link->dc->config.allow_edp_hotplug_detection)) &&
986 link->local_sink) {
987 // need to re-write OUI and brightness in resume case
988 if (link->connector_signal == SIGNAL_TYPE_EDP &&
989 (link->dpcd_sink_ext_caps.bits.oled == 1)) {
990 dpcd_set_source_specific_data(link);
991 msleep(post_oui_delay);
992 set_default_brightness_aux(link);
993 }
994
995 return true;
996 }
997
998 if (!link_detect_connection_type(link, &new_connection_type)) {
999 BREAK_TO_DEBUGGER();
1000 return false;
1001 }
1002
1003 prev_sink = link->local_sink;
1004 if (prev_sink) {
1005 dc_sink_retain(prev_sink);
1006 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1007 }
1008
1009 link_disconnect_sink(link);
1010 if (new_connection_type != dc_connection_none) {
1011 link->type = new_connection_type;
1012 link->link_state_valid = false;
1013
1014 /* From Disconnected-to-Connected. */
1015 switch (link->connector_signal) {
1016 case SIGNAL_TYPE_HDMI_TYPE_A: {
1017 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1018 if (aud_support->hdmi_audio_native)
1019 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1020 else
1021 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1022 break;
1023 }
1024
1025 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1026 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1027 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1028 break;
1029 }
1030
1031 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1032 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1033 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1034 break;
1035 }
1036
1037 case SIGNAL_TYPE_RGB: {
1038 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1039 sink_caps.signal = SIGNAL_TYPE_RGB;
1040 break;
1041 }
1042
1043 case SIGNAL_TYPE_LVDS: {
1044 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1045 sink_caps.signal = SIGNAL_TYPE_LVDS;
1046 break;
1047 }
1048
1049 case SIGNAL_TYPE_EDP: {
1050 detect_edp_sink_caps(link);
1051 read_current_link_settings_on_detect(link);
1052
1053 /* Disable power sequence on MIPI panel + converter
1054 */
1055 if (dc->config.enable_mipi_converter_optimization &&
1056 dc_ctx->dce_version == DCN_VERSION_3_01 &&
1057 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
1058 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
1059 sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
1060 dc->config.edp_no_power_sequencing = true;
1061
1062 if (!link->dpcd_caps.set_power_state_capable_edp)
1063 link->wa_flags.dp_keep_receiver_powered = true;
1064 }
1065
1066 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1067 sink_caps.signal = SIGNAL_TYPE_EDP;
1068 break;
1069 }
1070
1071 case SIGNAL_TYPE_DISPLAY_PORT: {
1072
1073 /* wa HPD high coming too early*/
1074 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1075 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1076
1077 /* if alt mode times out, return false */
1078 if (!wait_for_entering_dp_alt_mode(link))
1079 return false;
1080 }
1081
1082 if (!detect_dp(link, &sink_caps, reason)) {
1083
1084 if (prev_sink)
1085 dc_sink_release(prev_sink);
1086 return false;
1087 }
1088
1089 /* Active SST downstream branch device unplug*/
1090 if (link->type == dc_connection_sst_branch &&
1091 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1092 if (prev_sink)
1093 /* Downstream unplug */
1094 dc_sink_release(prev_sink);
1095 return true;
1096 }
1097
1098 /* disable audio for non DP to HDMI active sst converter */
1099 if (link->type == dc_connection_sst_branch &&
1100 is_dp_active_dongle(link) &&
1101 (link->dpcd_caps.dongle_type !=
1102 DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1103 converter_disable_audio = true;
1104
1105 /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
1106 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1107 link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
1108 link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
1109
1110 if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
1111 && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
1112 && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) {
1113 if (link_dpia_enable_usb4_dp_bw_alloc_mode(link) == false)
1114 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false;
1115 }
1116 break;
1117 }
1118
1119 default:
1120 DC_ERROR("Invalid connector type! signal:%d\n",
1121 link->connector_signal);
1122 if (prev_sink)
1123 dc_sink_release(prev_sink);
1124 return false;
1125 } /* switch() */
1126
1127 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1128 link->dpcd_sink_count =
1129 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1130 else
1131 link->dpcd_sink_count = 1;
1132
1133 set_ddc_transaction_type(link->ddc,
1134 sink_caps.transaction_type);
1135
1136 link->aux_mode =
1137 link_is_in_aux_transaction_mode(link->ddc);
1138
1139 sink_init_data.link = link;
1140 sink_init_data.sink_signal = sink_caps.signal;
1141
1142 sink = dc_sink_create(&sink_init_data);
1143 if (!sink) {
1144 DC_ERROR("Failed to create sink!\n");
1145 if (prev_sink)
1146 dc_sink_release(prev_sink);
1147 return false;
1148 }
1149
1150 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1151 sink->converter_disable_audio = converter_disable_audio;
1152
1153 /* dc_sink_create returns a new reference */
1154 link->local_sink = sink;
1155
1156 edid_status = dm_helpers_read_local_edid(link->ctx,
1157 link, sink);
1158
1159 switch (edid_status) {
1160 case EDID_BAD_CHECKSUM:
1161 DC_LOG_ERROR("EDID checksum invalid.\n");
1162 break;
1163 case EDID_PARTIAL_VALID:
1164 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1165 break;
1166 case EDID_NO_RESPONSE:
1167 /* Analog connectors without EDID:
1168 * - old monitor that actually doesn't have EDID
1169 * - cheap DVI-A cable or adapter that doesn't connect DDC
1170 */
1171 if (dc_connector_supports_analog(link->link_id.id)) {
1172 /* If we didn't do DAC load detection yet, do it now
1173 * to verify there really is a display connected.
1174 */
1175 if (link->type != dc_connection_dac_load &&
1176 !link_detect_dac_load_detect(link)) {
1177 if (prev_sink)
1178 dc_sink_release(prev_sink);
1179 link_disconnect_sink(link);
1180 return false;
1181 }
1182
1183 DC_LOG_INFO("%s detected analog display without EDID\n", __func__);
1184 link->type = dc_connection_dac_load;
1185 sink->edid_caps.analog = true;
1186 break;
1187 }
1188
1189 DC_LOG_ERROR("No EDID read.\n");
1190
1191 /*
1192 * Abort detection for non-DP connectors if we have
1193 * no EDID
1194 *
1195 * DP needs to report as connected if HDP is high
1196 * even if we have no EDID in order to go to
1197 * fail-safe mode
1198 */
1199 if (dc_is_hdmi_signal(link->connector_signal) ||
1200 dc_is_dvi_signal(link->connector_signal)) {
1201 if (prev_sink)
1202 dc_sink_release(prev_sink);
1203
1204 return false;
1205 }
1206
1207 if (link->type == dc_connection_sst_branch &&
1208 link->dpcd_caps.dongle_type ==
1209 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1210 reason == DETECT_REASON_HPDRX) {
1211 /* Abort detection for DP-VGA adapters when EDID
1212 * can't be read and detection reason is VGA-side
1213 * hotplug
1214 */
1215 if (prev_sink)
1216 dc_sink_release(prev_sink);
1217 link_disconnect_sink(link);
1218
1219 return true;
1220 }
1221
1222 break;
1223 default:
1224 break;
1225 }
1226
1227 // Check if edid is the same
1228 if ((prev_sink) &&
1229 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1230 same_edid = is_same_edid(&prev_sink->dc_edid,
1231 &sink->dc_edid);
1232
1233 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1234 link->ctx->dc->debug.hdmi20_disable = true;
1235
1236 if (sink->edid_caps.panel_patch.remove_sink_ext_caps)
1237 link->dpcd_sink_ext_caps.raw = 0;
1238
1239 if (dc_is_hdmi_signal(link->connector_signal))
1240 read_scdc_caps(link->ddc, link->local_sink);
1241
1242 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1243 sink_caps.transaction_type ==
1244 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1245 /*
1246 * TODO debug why certain monitors don't like
1247 * two link trainings
1248 */
1249 query_hdcp_capability(sink->sink_signal, link);
1250 } else {
1251 // If edid is the same, then discard new sink and revert back to original sink
1252 if (same_edid) {
1253 link_disconnect_remap(prev_sink, link);
1254 sink = prev_sink;
1255 prev_sink = NULL;
1256 }
1257
1258 if (!sink->edid_caps.analog)
1259 query_hdcp_capability(sink->sink_signal, link);
1260 }
1261
1262 /* DVI-I connector connected to analog display. */
1263 if ((link->link_id.id == CONNECTOR_ID_DUAL_LINK_DVII ||
1264 link->link_id.id == CONNECTOR_ID_SINGLE_LINK_DVII) &&
1265 sink->edid_caps.analog)
1266 sink->sink_signal = SIGNAL_TYPE_RGB;
1267
1268 /* HDMI-DVI Dongle */
1269 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1270 !sink->edid_caps.edid_hdmi)
1271 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1272 else if (dc_is_dvi_signal(sink->sink_signal) &&
1273 dc_is_dvi_signal(link->connector_signal) &&
1274 aud_support->hdmi_audio_native &&
1275 sink->edid_caps.edid_hdmi)
1276 sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1277
1278 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1279 dp_trace_init(link);
1280
1281 /* Connectivity log: detection */
1282 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1283 CONN_DATA_DETECT(link,
1284 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1285 DC_EDID_BLOCK_SIZE,
1286 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1287 }
1288
1289 DC_LOG_DETECTION_EDID_PARSER("%s: "
1290 "manufacturer_id = %X, "
1291 "product_id = %X, "
1292 "serial_number = %X, "
1293 "manufacture_week = %d, "
1294 "manufacture_year = %d, "
1295 "display_name = %s, "
1296 "speaker_flag = %d, "
1297 "audio_mode_count = %d\n",
1298 __func__,
1299 sink->edid_caps.manufacturer_id,
1300 sink->edid_caps.product_id,
1301 sink->edid_caps.serial_number,
1302 sink->edid_caps.manufacture_week,
1303 sink->edid_caps.manufacture_year,
1304 sink->edid_caps.display_name,
1305 sink->edid_caps.speaker_flags,
1306 sink->edid_caps.audio_mode_count);
1307
1308 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1309 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1310 "format_code = %d, "
1311 "channel_count = %d, "
1312 "sample_rate = %d, "
1313 "sample_size = %d\n",
1314 __func__,
1315 i,
1316 sink->edid_caps.audio_modes[i].format_code,
1317 sink->edid_caps.audio_modes[i].channel_count,
1318 sink->edid_caps.audio_modes[i].sample_rate,
1319 sink->edid_caps.audio_modes[i].sample_size);
1320 }
1321
1322 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1323 // Init dc_panel_config by HW config
1324 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults)
1325 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config);
1326 // Pickup base DM settings
1327 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
1328 // Override dc_panel_config if system has specific settings
1329 dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
1330
1331 //sink only can use supported link rate table, we are foreced to enable it
1332 if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
1333 link->panel_config.ilr.optimize_edp_link_rate = true;
1334 link->reported_link_cap.link_rate = get_max_edp_link_rate(link);
1335 }
1336
1337 } else {
1338 /* From Connected-to-Disconnected. */
1339 link->type = dc_connection_none;
1340 sink_caps.signal = SIGNAL_TYPE_NONE;
1341 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps));
1342 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1343 * is not cleared. If we emulate a DP signal on this connection, it thinks
1344 * the dongle is still there and limits the number of modes we can emulate.
1345 * Clear dongle_max_pix_clk on disconnect to fix this
1346 */
1347 link->dongle_max_pix_clk = 0;
1348
1349 dc_link_clear_dprx_states(link);
1350 dp_trace_reset(link);
1351 }
1352
1353 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1354 link->link_index, sink,
1355 (sink_caps.signal ==
1356 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1357 prev_sink, same_edid);
1358
1359 if (prev_sink)
1360 dc_sink_release(prev_sink);
1361
1362 return true;
1363 }
1364
1365 /**
1366 * link_detect_analog() - Determines if an analog sink is connected.
1367 *
1368 * @link: DC link to evaluate (must support analog signalling).
1369 * @type: Updated with the detected connection type:
1370 * dc_connection_single (analog via DDC),
1371 * dc_connection_dac_load (via load-detect),
1372 * or dc_connection_none.
1373 *
1374 * Return: true if detection completed.
1375 */
link_detect_analog(struct dc_link * link,enum dc_connection_type * type)1376 static bool link_detect_analog(struct dc_link *link, enum dc_connection_type *type)
1377 {
1378 /* Don't care about connectors that don't support an analog signal. */
1379 ASSERT(dc_connector_supports_analog(link->link_id.id));
1380
1381 if (link_detect_ddc_probe(link)) {
1382 *type = dc_connection_single;
1383 return true;
1384 }
1385
1386 if (link_detect_dac_load_detect(link)) {
1387 *type = dc_connection_dac_load;
1388 return true;
1389 }
1390
1391 *type = dc_connection_none;
1392 return true;
1393 }
1394
1395 /*
1396 * link_detect_connection_type() - Determine if there is a sink connected
1397 *
1398 * @type: Returned connection type
1399 * Does not detect downstream devices, such as MST sinks
1400 * or display connected through active dongles
1401 */
link_detect_connection_type(struct dc_link * link,enum dc_connection_type * type)1402 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type)
1403 {
1404 uint32_t is_hpd_high = 0;
1405
1406 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
1407 *type = dc_connection_single;
1408 return true;
1409 }
1410
1411 /* Ignore the HPD pin (if any) for analog connectors.
1412 * Instead rely on DDC and DAC.
1413 *
1414 * - VGA connectors don't have any HPD at all.
1415 * - Some DVI-A cables don't connect the HPD pin.
1416 * - Some DVI-A cables pull up the HPD pin.
1417 * (So it's high even when no display is connected.)
1418 */
1419 if (dc_connector_supports_analog(link->link_id.id))
1420 return link_detect_analog(link, type);
1421
1422 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1423 /*in case it is not on*/
1424 if (!link->dc->config.edp_no_power_sequencing)
1425 link->dc->hwss.edp_power_control(link, true);
1426 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1427 }
1428
1429 /* Link may not have physical HPD pin. */
1430 if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
1431 if (link->is_hpd_pending || !dpia_query_hpd_status(link))
1432 *type = dc_connection_none;
1433 else
1434 *type = dc_connection_single;
1435
1436 return true;
1437 }
1438
1439
1440 if (!query_hpd_status(link, &is_hpd_high))
1441 goto hpd_gpio_failure;
1442
1443 if (is_hpd_high) {
1444 *type = dc_connection_single;
1445 /* TODO: need to do the actual detection */
1446 } else {
1447 *type = dc_connection_none;
1448 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1449 /* eDP is not connected, power down it */
1450 if (!link->dc->config.edp_no_power_sequencing)
1451 link->dc->hwss.edp_power_control(link, false);
1452 }
1453 }
1454
1455 return true;
1456
1457 hpd_gpio_failure:
1458 return false;
1459 }
1460
link_detect(struct dc_link * link,enum dc_detect_reason reason)1461 bool link_detect(struct dc_link *link, enum dc_detect_reason reason)
1462 {
1463 bool is_local_sink_detect_success;
1464 bool is_delegated_to_mst_top_mgr = false;
1465 enum dc_connection_type pre_link_type = link->type;
1466
1467 DC_LOGGER_INIT(link->ctx->logger);
1468
1469 is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1470
1471 if (is_local_sink_detect_success && link->local_sink)
1472 verify_link_capability(link, link->local_sink, reason);
1473
1474 DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__,
1475 link->link_index, is_local_sink_detect_success, pre_link_type, link->type);
1476
1477 if (is_local_sink_detect_success && link->local_sink &&
1478 dc_is_dp_signal(link->local_sink->sink_signal) &&
1479 link->dpcd_caps.is_mst_capable)
1480 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1481
1482 if (pre_link_type == dc_connection_mst_branch &&
1483 link->type != dc_connection_mst_branch)
1484 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link);
1485
1486 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1487 }
1488
link_clear_dprx_states(struct dc_link * link)1489 void link_clear_dprx_states(struct dc_link *link)
1490 {
1491 memset(&link->dprx_states, 0, sizeof(link->dprx_states));
1492 }
1493
link_is_hdcp14(struct dc_link * link,enum signal_type signal)1494 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal)
1495 {
1496 bool ret = false;
1497
1498 switch (signal) {
1499 case SIGNAL_TYPE_DISPLAY_PORT:
1500 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1501 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
1502 break;
1503 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1504 case SIGNAL_TYPE_DVI_DUAL_LINK:
1505 case SIGNAL_TYPE_HDMI_TYPE_A:
1506 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
1507 * we can poll for bksv but some displays have an issue with this. Since its so rare
1508 * for a display to not be 1.4 capable, this assumtion is ok
1509 */
1510 ret = true;
1511 break;
1512 default:
1513 break;
1514 }
1515 return ret;
1516 }
1517
link_is_hdcp22(struct dc_link * link,enum signal_type signal)1518 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal)
1519 {
1520 bool ret = false;
1521
1522 switch (signal) {
1523 case SIGNAL_TYPE_DISPLAY_PORT:
1524 case SIGNAL_TYPE_DISPLAY_PORT_MST:
1525 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
1526 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
1527 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
1528 break;
1529 case SIGNAL_TYPE_DVI_SINGLE_LINK:
1530 case SIGNAL_TYPE_DVI_DUAL_LINK:
1531 case SIGNAL_TYPE_HDMI_TYPE_A:
1532 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
1533 break;
1534 default:
1535 break;
1536 }
1537
1538 return ret;
1539 }
1540
link_get_status(const struct dc_link * link)1541 const struct dc_link_status *link_get_status(const struct dc_link *link)
1542 {
1543 return &link->link_status;
1544 }
1545
1546
link_add_remote_sink_helper(struct dc_link * dc_link,struct dc_sink * sink)1547 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
1548 {
1549 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1550 BREAK_TO_DEBUGGER();
1551 return false;
1552 }
1553
1554 dc_sink_retain(sink);
1555
1556 dc_link->remote_sinks[dc_link->sink_count] = sink;
1557 dc_link->sink_count++;
1558
1559 return true;
1560 }
1561
link_add_remote_sink(struct dc_link * link,const uint8_t * edid,int len,struct dc_sink_init_data * init_data)1562 struct dc_sink *link_add_remote_sink(
1563 struct dc_link *link,
1564 const uint8_t *edid,
1565 int len,
1566 struct dc_sink_init_data *init_data)
1567 {
1568 struct dc_sink *dc_sink;
1569 enum dc_edid_status edid_status;
1570
1571 if (len > DC_MAX_EDID_BUFFER_SIZE) {
1572 dm_error("Max EDID buffer size breached!\n");
1573 return NULL;
1574 }
1575
1576 if (!init_data) {
1577 BREAK_TO_DEBUGGER();
1578 return NULL;
1579 }
1580
1581 if (!init_data->link) {
1582 BREAK_TO_DEBUGGER();
1583 return NULL;
1584 }
1585
1586 dc_sink = dc_sink_create(init_data);
1587
1588 if (!dc_sink)
1589 return NULL;
1590
1591 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1592 dc_sink->dc_edid.length = len;
1593
1594 if (!link_add_remote_sink_helper(
1595 link,
1596 dc_sink))
1597 goto fail_add_sink;
1598
1599 edid_status = dm_helpers_parse_edid_caps(
1600 link,
1601 &dc_sink->dc_edid,
1602 &dc_sink->edid_caps);
1603
1604 /*
1605 * Treat device as no EDID device if EDID
1606 * parsing fails
1607 */
1608 if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) {
1609 dc_sink->dc_edid.length = 0;
1610 dm_error("Bad EDID, status%d!\n", edid_status);
1611 }
1612
1613 return dc_sink;
1614
1615 fail_add_sink:
1616 dc_sink_release(dc_sink);
1617 return NULL;
1618 }
1619
link_remove_remote_sink(struct dc_link * link,struct dc_sink * sink)1620 void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
1621 {
1622 int i;
1623
1624 if (!link->sink_count) {
1625 BREAK_TO_DEBUGGER();
1626 return;
1627 }
1628
1629 for (i = 0; i < link->sink_count; i++) {
1630 if (link->remote_sinks[i] == sink) {
1631 dc_sink_release(sink);
1632 link->remote_sinks[i] = NULL;
1633
1634 /* shrink array to remove empty place */
1635 while (i < link->sink_count - 1) {
1636 link->remote_sinks[i] = link->remote_sinks[i+1];
1637 i++;
1638 }
1639 link->remote_sinks[i] = NULL;
1640 link->sink_count--;
1641 return;
1642 }
1643 }
1644 }
1645