1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2000, 2001
6 * Bill Paul <william.paul@windriver.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 /*
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
40 *
41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44 * are three supported methods for data transfer between host and
45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46 * Propulsion Technology (tm) DMA. The latter mechanism is a form
47 * of double buffer DMA where the packet data is copied to a
48 * pre-allocated DMA buffer who's physical address has been loaded
49 * into a table at device initialization time. The rationale is that
50 * the virtual to physical address translation needed for normal
51 * scatter/gather DMA is more expensive than the data copy needed
52 * for double buffering. This may be true in Windows NT and the like,
53 * but it isn't true for us, at least on the x86 arch. This driver
54 * uses the scatter/gather I/O method for both TX and RX.
55 *
56 * The LXT1001 only supports TCP/IP checksum offload on receive.
57 * Also, the VLAN tagging is done using a 16-entry table which allows
58 * the chip to perform hardware filtering based on VLAN tags. Sadly,
59 * our vlan support doesn't currently play well with this kind of
60 * hardware support.
61 *
62 * Special thanks to:
63 * - Jeff James at Intel, for arranging to have the LXT1001 manual
64 * released (at long last)
65 * - Beny Chen at D-Link, for actually sending it to me
66 * - Brad Short and Keith Alexis at SMC, for sending me sample
67 * SMC9462SX and SMC9462TX adapters for testing
68 * - Paul Saab at Y!, for not killing me (though it remains to be seen
69 * if in fact he did me much of a favor)
70 */
71
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/sockio.h>
75 #include <sys/mbuf.h>
76 #include <sys/malloc.h>
77 #include <sys/kernel.h>
78 #include <sys/module.h>
79 #include <sys/socket.h>
80
81 #include <net/if.h>
82 #include <net/if_var.h>
83 #include <net/if_arp.h>
84 #include <net/ethernet.h>
85 #include <net/if_dl.h>
86 #include <net/if_media.h>
87 #include <net/if_types.h>
88
89 #include <net/bpf.h>
90
91 #include <vm/vm.h> /* for vtophys */
92 #include <vm/pmap.h> /* for vtophys */
93 #include <machine/bus.h>
94 #include <machine/resource.h>
95 #include <sys/bus.h>
96 #include <sys/rman.h>
97
98 #include <dev/mii/mii.h>
99 #include <dev/mii/miivar.h>
100
101 #include <dev/pci/pcireg.h>
102 #include <dev/pci/pcivar.h>
103
104 #define LGE_USEIOSPACE
105
106 #include <dev/lge/if_lgereg.h>
107
108 /* "device miibus" required. See GENERIC if you get errors here. */
109 #include "miibus_if.h"
110
111 /*
112 * Various supported device vendors/types and their names.
113 */
114 static const struct lge_type lge_devs[] = {
115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
116 { 0, 0, NULL }
117 };
118
119 static int lge_probe(device_t);
120 static int lge_attach(device_t);
121 static int lge_detach(device_t);
122
123 static int lge_alloc_jumbo_mem(struct lge_softc *);
124 static void lge_free_jumbo_mem(struct lge_softc *);
125 static void *lge_jalloc(struct lge_softc *);
126 static void lge_jfree(struct mbuf *);
127
128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
130 static void lge_rxeof(struct lge_softc *, int);
131 static void lge_rxeoc(struct lge_softc *);
132 static void lge_txeof(struct lge_softc *);
133 static void lge_intr(void *);
134 static void lge_tick(void *);
135 static void lge_start(if_t);
136 static void lge_start_locked(if_t);
137 static int lge_ioctl(if_t, u_long, caddr_t);
138 static void lge_init(void *);
139 static void lge_init_locked(struct lge_softc *);
140 static void lge_stop(struct lge_softc *);
141 static void lge_watchdog(struct lge_softc *);
142 static int lge_shutdown(device_t);
143 static int lge_ifmedia_upd(if_t);
144 static void lge_ifmedia_upd_locked(if_t);
145 static void lge_ifmedia_sts(if_t, struct ifmediareq *);
146
147 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
148 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
149
150 static int lge_miibus_readreg(device_t, int, int);
151 static int lge_miibus_writereg(device_t, int, int, int);
152 static void lge_miibus_statchg(device_t);
153
154 static void lge_setmulti(struct lge_softc *);
155 static void lge_reset(struct lge_softc *);
156 static int lge_list_rx_init(struct lge_softc *);
157 static int lge_list_tx_init(struct lge_softc *);
158
159 #ifdef LGE_USEIOSPACE
160 #define LGE_RES SYS_RES_IOPORT
161 #define LGE_RID LGE_PCI_LOIO
162 #else
163 #define LGE_RES SYS_RES_MEMORY
164 #define LGE_RID LGE_PCI_LOMEM
165 #endif
166
167 static device_method_t lge_methods[] = {
168 /* Device interface */
169 DEVMETHOD(device_probe, lge_probe),
170 DEVMETHOD(device_attach, lge_attach),
171 DEVMETHOD(device_detach, lge_detach),
172 DEVMETHOD(device_shutdown, lge_shutdown),
173
174 /* MII interface */
175 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
176 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
177 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
178
179 DEVMETHOD_END
180 };
181
182 static driver_t lge_driver = {
183 "lge",
184 lge_methods,
185 sizeof(struct lge_softc)
186 };
187
188 DRIVER_MODULE(lge, pci, lge_driver, 0, 0);
189 DRIVER_MODULE(miibus, lge, miibus_driver, 0, 0);
190 MODULE_DEPEND(lge, pci, 1, 1, 1);
191 MODULE_DEPEND(lge, ether, 1, 1, 1);
192 MODULE_DEPEND(lge, miibus, 1, 1, 1);
193
194 #define LGE_SETBIT(sc, reg, x) \
195 CSR_WRITE_4(sc, reg, \
196 CSR_READ_4(sc, reg) | (x))
197
198 #define LGE_CLRBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, \
200 CSR_READ_4(sc, reg) & ~(x))
201
202 #define SIO_SET(x) \
203 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
204
205 #define SIO_CLR(x) \
206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
207
208 /*
209 * Read a word of data stored in the EEPROM at address 'addr.'
210 */
211 static void
lge_eeprom_getword(struct lge_softc * sc,int addr,u_int16_t * dest)212 lge_eeprom_getword(struct lge_softc *sc, int addr, u_int16_t *dest)
213 {
214 int i;
215 u_int32_t val;
216
217 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
218 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
219
220 for (i = 0; i < LGE_TIMEOUT; i++)
221 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
222 break;
223
224 if (i == LGE_TIMEOUT) {
225 device_printf(sc->lge_dev, "EEPROM read timed out\n");
226 return;
227 }
228
229 val = CSR_READ_4(sc, LGE_EEDATA);
230
231 if (addr & 1)
232 *dest = (val >> 16) & 0xFFFF;
233 else
234 *dest = val & 0xFFFF;
235
236 return;
237 }
238
239 /*
240 * Read a sequence of words from the EEPROM.
241 */
242 static void
lge_read_eeprom(struct lge_softc * sc,caddr_t dest,int off,int cnt,int swap)243 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt, int swap)
244 {
245 int i;
246 u_int16_t word = 0, *ptr;
247
248 for (i = 0; i < cnt; i++) {
249 lge_eeprom_getword(sc, off + i, &word);
250 ptr = (u_int16_t *)(dest + (i * 2));
251 if (swap)
252 *ptr = ntohs(word);
253 else
254 *ptr = word;
255 }
256
257 return;
258 }
259
260 static int
lge_miibus_readreg(device_t dev,int phy,int reg)261 lge_miibus_readreg(device_t dev, int phy, int reg)
262 {
263 struct lge_softc *sc;
264 int i;
265
266 sc = device_get_softc(dev);
267
268 /*
269 * If we have a non-PCS PHY, pretend that the internal
270 * autoneg stuff at PHY address 0 isn't there so that
271 * the miibus code will find only the GMII PHY.
272 */
273 if (sc->lge_pcs == 0 && phy == 0)
274 return(0);
275
276 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
277
278 for (i = 0; i < LGE_TIMEOUT; i++)
279 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
280 break;
281
282 if (i == LGE_TIMEOUT) {
283 device_printf(sc->lge_dev, "PHY read timed out\n");
284 return(0);
285 }
286
287 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
288 }
289
290 static int
lge_miibus_writereg(device_t dev,int phy,int reg,int data)291 lge_miibus_writereg(device_t dev, int phy, int reg, int data)
292 {
293 struct lge_softc *sc;
294 int i;
295
296 sc = device_get_softc(dev);
297
298 CSR_WRITE_4(sc, LGE_GMIICTL,
299 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
300
301 for (i = 0; i < LGE_TIMEOUT; i++)
302 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
303 break;
304
305 if (i == LGE_TIMEOUT) {
306 device_printf(sc->lge_dev, "PHY write timed out\n");
307 return(0);
308 }
309
310 return(0);
311 }
312
313 static void
lge_miibus_statchg(device_t dev)314 lge_miibus_statchg(device_t dev)
315 {
316 struct lge_softc *sc;
317 struct mii_data *mii;
318
319 sc = device_get_softc(dev);
320 mii = device_get_softc(sc->lge_miibus);
321
322 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
323 switch (IFM_SUBTYPE(mii->mii_media_active)) {
324 case IFM_1000_T:
325 case IFM_1000_SX:
326 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
327 break;
328 case IFM_100_TX:
329 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
330 break;
331 case IFM_10_T:
332 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
333 break;
334 default:
335 /*
336 * Choose something, even if it's wrong. Clearing
337 * all the bits will hose autoneg on the internal
338 * PHY.
339 */
340 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
341 break;
342 }
343
344 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
345 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
346 } else {
347 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
348 }
349
350 return;
351 }
352
353 static u_int
lge_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int count)354 lge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int count)
355 {
356 uint32_t h, *hashes = arg;
357
358 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
359 if (h < 32)
360 hashes[0] |= (1 << h);
361 else
362 hashes[1] |= (1 << (h - 32));
363 return (1);
364 }
365
366 static void
lge_setmulti(struct lge_softc * sc)367 lge_setmulti(struct lge_softc *sc)
368 {
369 if_t ifp;
370 uint32_t hashes[2] = { 0, 0 };
371
372 ifp = sc->lge_ifp;
373 LGE_LOCK_ASSERT(sc);
374
375 /* Make sure multicast hash table is enabled. */
376 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
377
378 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
379 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
380 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
381 return;
382 }
383
384 /* first, zot all the existing hash bits */
385 CSR_WRITE_4(sc, LGE_MAR0, 0);
386 CSR_WRITE_4(sc, LGE_MAR1, 0);
387
388 /* now program new ones */
389 if_foreach_llmaddr(ifp, lge_hash_maddr, hashes);
390
391 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
392 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
393
394 return;
395 }
396
397 static void
lge_reset(struct lge_softc * sc)398 lge_reset(struct lge_softc *sc)
399 {
400 int i;
401
402 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
403
404 for (i = 0; i < LGE_TIMEOUT; i++) {
405 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
406 break;
407 }
408
409 if (i == LGE_TIMEOUT)
410 device_printf(sc->lge_dev, "reset never completed\n");
411
412 /* Wait a little while for the chip to get its brains in order. */
413 DELAY(1000);
414
415 return;
416 }
417
418 /*
419 * Probe for a Level 1 chip. Check the PCI vendor and device
420 * IDs against our list and return a device name if we find a match.
421 */
422 static int
lge_probe(device_t dev)423 lge_probe(device_t dev)
424 {
425 const struct lge_type *t;
426
427 t = lge_devs;
428
429 while(t->lge_name != NULL) {
430 if ((pci_get_vendor(dev) == t->lge_vid) &&
431 (pci_get_device(dev) == t->lge_did)) {
432 device_set_desc(dev, t->lge_name);
433 return(BUS_PROBE_DEFAULT);
434 }
435 t++;
436 }
437
438 return(ENXIO);
439 }
440
441 /*
442 * Attach the interface. Allocate softc structures, do ifmedia
443 * setup and ethernet/BPF attach.
444 */
445 static int
lge_attach(device_t dev)446 lge_attach(device_t dev)
447 {
448 u_char eaddr[ETHER_ADDR_LEN];
449 struct lge_softc *sc;
450 if_t ifp = NULL;
451 int error = 0, rid;
452
453 sc = device_get_softc(dev);
454 sc->lge_dev = dev;
455
456 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
457 MTX_DEF);
458 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0);
459
460 /*
461 * Map control/status registers.
462 */
463 pci_enable_busmaster(dev);
464
465 rid = LGE_RID;
466 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
467
468 if (sc->lge_res == NULL) {
469 device_printf(dev, "couldn't map ports/memory\n");
470 error = ENXIO;
471 goto fail;
472 }
473
474 sc->lge_btag = rman_get_bustag(sc->lge_res);
475 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
476
477 /* Allocate interrupt */
478 rid = 0;
479 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
480 RF_SHAREABLE | RF_ACTIVE);
481
482 if (sc->lge_irq == NULL) {
483 device_printf(dev, "couldn't map interrupt\n");
484 error = ENXIO;
485 goto fail;
486 }
487
488 /* Reset the adapter. */
489 lge_reset(sc);
490
491 /*
492 * Get station address from the EEPROM.
493 */
494 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
495 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
496 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
497
498 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
499 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
500
501 if (sc->lge_ldata == NULL) {
502 device_printf(dev, "no memory for list buffers!\n");
503 error = ENXIO;
504 goto fail;
505 }
506
507 /* Try to allocate memory for jumbo buffers. */
508 if (lge_alloc_jumbo_mem(sc)) {
509 device_printf(dev, "jumbo buffer allocation failed\n");
510 error = ENXIO;
511 goto fail;
512 }
513
514 ifp = sc->lge_ifp = if_alloc(IFT_ETHER);
515 if_setsoftc(ifp, sc);
516 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
517 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
518 if_setioctlfn(ifp, lge_ioctl);
519 if_setstartfn(ifp, lge_start);
520 if_setinitfn(ifp, lge_init);
521 if_setsendqlen(ifp, LGE_TX_LIST_CNT - 1);
522 if_setcapabilities(ifp, IFCAP_RXCSUM);
523 if_setcapenable(ifp, if_getcapabilities(ifp));
524
525 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
526 sc->lge_pcs = 1;
527 else
528 sc->lge_pcs = 0;
529
530 /*
531 * Do MII setup.
532 */
533 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd,
534 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
535 if (error != 0) {
536 device_printf(dev, "attaching PHYs failed\n");
537 goto fail;
538 }
539
540 /*
541 * Call MI attach routine.
542 */
543 ether_ifattach(ifp, eaddr);
544
545 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE,
546 NULL, lge_intr, sc, &sc->lge_intrhand);
547
548 if (error) {
549 ether_ifdetach(ifp);
550 device_printf(dev, "couldn't set up irq\n");
551 goto fail;
552 }
553 return (0);
554
555 fail:
556 lge_free_jumbo_mem(sc);
557 if (sc->lge_ldata)
558 free(sc->lge_ldata, M_DEVBUF);
559 if (ifp)
560 if_free(ifp);
561 if (sc->lge_irq)
562 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
563 if (sc->lge_res)
564 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
565 mtx_destroy(&sc->lge_mtx);
566 return(error);
567 }
568
569 static int
lge_detach(device_t dev)570 lge_detach(device_t dev)
571 {
572 struct lge_softc *sc;
573 if_t ifp;
574
575 sc = device_get_softc(dev);
576 ifp = sc->lge_ifp;
577
578 LGE_LOCK(sc);
579 lge_reset(sc);
580 lge_stop(sc);
581 LGE_UNLOCK(sc);
582 callout_drain(&sc->lge_stat_callout);
583 ether_ifdetach(ifp);
584
585 bus_generic_detach(dev);
586
587 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
589 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
590
591 free(sc->lge_ldata, M_DEVBUF);
592 if_free(ifp);
593 lge_free_jumbo_mem(sc);
594 mtx_destroy(&sc->lge_mtx);
595
596 return(0);
597 }
598
599 /*
600 * Initialize the transmit descriptors.
601 */
602 static int
lge_list_tx_init(struct lge_softc * sc)603 lge_list_tx_init(struct lge_softc *sc)
604 {
605 struct lge_list_data *ld;
606 struct lge_ring_data *cd;
607 int i;
608
609 cd = &sc->lge_cdata;
610 ld = sc->lge_ldata;
611 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
612 ld->lge_tx_list[i].lge_mbuf = NULL;
613 ld->lge_tx_list[i].lge_ctl = 0;
614 }
615
616 cd->lge_tx_prod = cd->lge_tx_cons = 0;
617
618 return(0);
619 }
620
621
622 /*
623 * Initialize the RX descriptors and allocate mbufs for them. Note that
624 * we arralge the descriptors in a closed ring, so that the last descriptor
625 * points back to the first.
626 */
627 static int
lge_list_rx_init(struct lge_softc * sc)628 lge_list_rx_init(struct lge_softc *sc)
629 {
630 struct lge_list_data *ld;
631 struct lge_ring_data *cd;
632 int i;
633
634 ld = sc->lge_ldata;
635 cd = &sc->lge_cdata;
636
637 cd->lge_rx_prod = cd->lge_rx_cons = 0;
638
639 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
640
641 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
642 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
643 break;
644 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
645 return(ENOBUFS);
646 }
647
648 /* Clear possible 'rx command queue empty' interrupt. */
649 CSR_READ_4(sc, LGE_ISR);
650
651 return(0);
652 }
653
654 /*
655 * Initialize an RX descriptor and attach an MBUF cluster.
656 */
657 static int
lge_newbuf(struct lge_softc * sc,struct lge_rx_desc * c,struct mbuf * m)658 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m)
659 {
660 struct mbuf *m_new = NULL;
661 char *buf = NULL;
662
663 if (m == NULL) {
664 MGETHDR(m_new, M_NOWAIT, MT_DATA);
665 if (m_new == NULL) {
666 device_printf(sc->lge_dev, "no memory for rx list "
667 "-- packet dropped!\n");
668 return(ENOBUFS);
669 }
670
671 /* Allocate the jumbo buffer */
672 buf = lge_jalloc(sc);
673 if (buf == NULL) {
674 #ifdef LGE_VERBOSE
675 device_printf(sc->lge_dev, "jumbo allocation failed "
676 "-- packet dropped!\n");
677 #endif
678 m_freem(m_new);
679 return(ENOBUFS);
680 }
681 /* Attach the buffer to the mbuf */
682 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
683 m_extadd(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, sc, NULL,
684 0, EXT_NET_DRV);
685 } else {
686 m_new = m;
687 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
688 m_new->m_data = m_new->m_ext.ext_buf;
689 }
690
691 /*
692 * Adjust alignment so packet payload begins on a
693 * longword boundary. Mandatory for Alpha, useful on
694 * x86 too.
695 */
696 m_adj(m_new, ETHER_ALIGN);
697
698 c->lge_mbuf = m_new;
699 c->lge_fragptr_hi = 0;
700 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
701 c->lge_fraglen = m_new->m_len;
702 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
703 c->lge_sts = 0;
704
705 /*
706 * Put this buffer in the RX command FIFO. To do this,
707 * we just write the physical address of the descriptor
708 * into the RX descriptor address registers. Note that
709 * there are two registers, one high DWORD and one low
710 * DWORD, which lets us specify a 64-bit address if
711 * desired. We only use a 32-bit address for now.
712 * Writing to the low DWORD register is what actually
713 * causes the command to be issued, so we do that
714 * last.
715 */
716 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
717 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
718
719 return(0);
720 }
721
722 static int
lge_alloc_jumbo_mem(struct lge_softc * sc)723 lge_alloc_jumbo_mem(struct lge_softc *sc)
724 {
725 caddr_t ptr;
726 int i;
727 struct lge_jpool_entry *entry;
728
729 /* Grab a big chunk o' storage. */
730 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
731 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
732
733 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
734 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n");
735 return(ENOBUFS);
736 }
737
738 SLIST_INIT(&sc->lge_jfree_listhead);
739 SLIST_INIT(&sc->lge_jinuse_listhead);
740
741 /*
742 * Now divide it up into 9K pieces and save the addresses
743 * in an array.
744 */
745 ptr = sc->lge_cdata.lge_jumbo_buf;
746 for (i = 0; i < LGE_JSLOTS; i++) {
747 sc->lge_cdata.lge_jslots[i] = ptr;
748 ptr += LGE_JLEN;
749 entry = malloc(sizeof(struct lge_jpool_entry),
750 M_DEVBUF, M_NOWAIT);
751 if (entry == NULL) {
752 device_printf(sc->lge_dev, "no memory for jumbo "
753 "buffer queue!\n");
754 return(ENOBUFS);
755 }
756 entry->slot = i;
757 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
758 entry, jpool_entries);
759 }
760
761 return(0);
762 }
763
764 static void
lge_free_jumbo_mem(struct lge_softc * sc)765 lge_free_jumbo_mem(struct lge_softc *sc)
766 {
767 struct lge_jpool_entry *entry;
768
769 if (sc->lge_cdata.lge_jumbo_buf == NULL)
770 return;
771
772 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) {
773 device_printf(sc->lge_dev,
774 "asked to free buffer that is in use!\n");
775 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
776 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry,
777 jpool_entries);
778 }
779 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) {
780 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
781 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
782 free(entry, M_DEVBUF);
783 }
784
785 free(sc->lge_cdata.lge_jumbo_buf, M_DEVBUF);
786
787 return;
788 }
789
790 /*
791 * Allocate a jumbo buffer.
792 */
793 static void *
lge_jalloc(struct lge_softc * sc)794 lge_jalloc(struct lge_softc *sc)
795 {
796 struct lge_jpool_entry *entry;
797
798 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
799
800 if (entry == NULL) {
801 #ifdef LGE_VERBOSE
802 device_printf(sc->lge_dev, "no free jumbo buffers\n");
803 #endif
804 return(NULL);
805 }
806
807 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
808 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
809 return(sc->lge_cdata.lge_jslots[entry->slot]);
810 }
811
812 /*
813 * Release a jumbo buffer.
814 */
815 static void
lge_jfree(struct mbuf * m)816 lge_jfree(struct mbuf *m)
817 {
818 struct lge_softc *sc;
819 int i;
820 struct lge_jpool_entry *entry;
821
822 /* Extract the softc struct pointer. */
823 sc = m->m_ext.ext_arg1;
824
825 if (sc == NULL)
826 panic("lge_jfree: can't find softc pointer!");
827
828 /* calculate the slot this buffer belongs to */
829 i = ((vm_offset_t)m->m_ext.ext_buf
830 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
831
832 if ((i < 0) || (i >= LGE_JSLOTS))
833 panic("lge_jfree: asked to free buffer that we don't manage!");
834
835 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
836 if (entry == NULL)
837 panic("lge_jfree: buffer not in use!");
838 entry->slot = i;
839 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
840 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
841 }
842
843 /*
844 * A frame has been uploaded: pass the resulting mbuf chain up to
845 * the higher level protocols.
846 */
847 static void
lge_rxeof(struct lge_softc * sc,int cnt)848 lge_rxeof(struct lge_softc *sc, int cnt)
849 {
850 struct mbuf *m;
851 if_t ifp;
852 struct lge_rx_desc *cur_rx;
853 int c, i, total_len = 0;
854 u_int32_t rxsts, rxctl;
855
856 ifp = sc->lge_ifp;
857
858 /* Find out how many frames were processed. */
859 c = cnt;
860 i = sc->lge_cdata.lge_rx_cons;
861
862 /* Suck them in. */
863 while(c) {
864 struct mbuf *m0 = NULL;
865
866 cur_rx = &sc->lge_ldata->lge_rx_list[i];
867 rxctl = cur_rx->lge_ctl;
868 rxsts = cur_rx->lge_sts;
869 m = cur_rx->lge_mbuf;
870 cur_rx->lge_mbuf = NULL;
871 total_len = LGE_RXBYTES(cur_rx);
872 LGE_INC(i, LGE_RX_LIST_CNT);
873 c--;
874
875 /*
876 * If an error occurs, update stats, clear the
877 * status word and leave the mbuf cluster in place:
878 * it should simply get re-used next time this descriptor
879 * comes up in the ring.
880 */
881 if (rxctl & LGE_RXCTL_ERRMASK) {
882 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
883 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
884 continue;
885 }
886
887 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
888 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
889 ifp, NULL);
890 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
891 if (m0 == NULL) {
892 device_printf(sc->lge_dev, "no receive buffers "
893 "available -- packet dropped!\n");
894 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
895 continue;
896 }
897 m = m0;
898 } else {
899 m->m_pkthdr.rcvif = ifp;
900 m->m_pkthdr.len = m->m_len = total_len;
901 }
902
903 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
904
905 /* Do IP checksum checking. */
906 if (rxsts & LGE_RXSTS_ISIP)
907 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
908 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
909 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
910 if ((rxsts & LGE_RXSTS_ISTCP &&
911 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
912 (rxsts & LGE_RXSTS_ISUDP &&
913 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
914 m->m_pkthdr.csum_flags |=
915 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
916 m->m_pkthdr.csum_data = 0xffff;
917 }
918
919 LGE_UNLOCK(sc);
920 if_input(ifp, m);
921 LGE_LOCK(sc);
922 }
923
924 sc->lge_cdata.lge_rx_cons = i;
925
926 return;
927 }
928
929 static void
lge_rxeoc(struct lge_softc * sc)930 lge_rxeoc(struct lge_softc *sc)
931 {
932 if_t ifp;
933
934 ifp = sc->lge_ifp;
935 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
936 lge_init_locked(sc);
937 return;
938 }
939
940 /*
941 * A frame was downloaded to the chip. It's safe for us to clean up
942 * the list buffers.
943 */
944
945 static void
lge_txeof(struct lge_softc * sc)946 lge_txeof(struct lge_softc *sc)
947 {
948 struct lge_tx_desc *cur_tx = NULL;
949 if_t ifp;
950 u_int32_t idx, txdone;
951
952 ifp = sc->lge_ifp;
953
954 /* Clear the timeout timer. */
955 sc->lge_timer = 0;
956
957 /*
958 * Go through our tx list and free mbufs for those
959 * frames that have been transmitted.
960 */
961 idx = sc->lge_cdata.lge_tx_cons;
962 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
963
964 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
965 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
966
967 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
968 if (cur_tx->lge_mbuf != NULL) {
969 m_freem(cur_tx->lge_mbuf);
970 cur_tx->lge_mbuf = NULL;
971 }
972 cur_tx->lge_ctl = 0;
973
974 txdone--;
975 LGE_INC(idx, LGE_TX_LIST_CNT);
976 sc->lge_timer = 0;
977 }
978
979 sc->lge_cdata.lge_tx_cons = idx;
980
981 if (cur_tx != NULL)
982 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
983
984 return;
985 }
986
987 static void
lge_tick(void * xsc)988 lge_tick(void *xsc)
989 {
990 struct lge_softc *sc;
991 struct mii_data *mii;
992 if_t ifp;
993
994 sc = xsc;
995 ifp = sc->lge_ifp;
996 LGE_LOCK_ASSERT(sc);
997
998 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
999 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1000 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1001 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1002
1003 if (!sc->lge_link) {
1004 mii = device_get_softc(sc->lge_miibus);
1005 mii_tick(mii);
1006 if (mii->mii_media_status & IFM_ACTIVE &&
1007 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1008 sc->lge_link++;
1009 if (bootverbose &&
1010 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1011 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T))
1012 device_printf(sc->lge_dev, "gigabit link up\n");
1013 if (!if_sendq_empty(ifp))
1014 lge_start_locked(ifp);
1015 }
1016 }
1017
1018 if (sc->lge_timer != 0 && --sc->lge_timer == 0)
1019 lge_watchdog(sc);
1020 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1021
1022 return;
1023 }
1024
1025 static void
lge_intr(void * arg)1026 lge_intr(void *arg)
1027 {
1028 struct lge_softc *sc;
1029 if_t ifp;
1030 u_int32_t status;
1031
1032 sc = arg;
1033 ifp = sc->lge_ifp;
1034 LGE_LOCK(sc);
1035
1036 /* Suppress unwanted interrupts */
1037 if (!(if_getflags(ifp) & IFF_UP)) {
1038 lge_stop(sc);
1039 LGE_UNLOCK(sc);
1040 return;
1041 }
1042
1043 for (;;) {
1044 /*
1045 * Reading the ISR register clears all interrupts, and
1046 * clears the 'interrupts enabled' bit in the IMR
1047 * register.
1048 */
1049 status = CSR_READ_4(sc, LGE_ISR);
1050
1051 if ((status & LGE_INTRS) == 0)
1052 break;
1053
1054 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1055 lge_txeof(sc);
1056
1057 if (status & LGE_ISR_RXDMA_DONE)
1058 lge_rxeof(sc, LGE_RX_DMACNT(status));
1059
1060 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1061 lge_rxeoc(sc);
1062
1063 if (status & LGE_ISR_PHY_INTR) {
1064 sc->lge_link = 0;
1065 callout_stop(&sc->lge_stat_callout);
1066 lge_tick(sc);
1067 }
1068 }
1069
1070 /* Re-enable interrupts. */
1071 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1072
1073 if (!if_sendq_empty(ifp))
1074 lge_start_locked(ifp);
1075
1076 LGE_UNLOCK(sc);
1077 return;
1078 }
1079
1080 /*
1081 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1082 * pointers to the fragment pointers.
1083 */
1084 static int
lge_encap(struct lge_softc * sc,struct mbuf * m_head,u_int32_t * txidx)1085 lge_encap(struct lge_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
1086 {
1087 struct lge_frag *f = NULL;
1088 struct lge_tx_desc *cur_tx;
1089 struct mbuf *m;
1090 int frag = 0, tot_len = 0;
1091
1092 /*
1093 * Start packing the mbufs in this chain into
1094 * the fragment pointers. Stop when we run out
1095 * of fragments or hit the end of the mbuf chain.
1096 */
1097 m = m_head;
1098 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1099 frag = 0;
1100
1101 for (m = m_head; m != NULL; m = m->m_next) {
1102 if (m->m_len != 0) {
1103 tot_len += m->m_len;
1104 f = &cur_tx->lge_frags[frag];
1105 f->lge_fraglen = m->m_len;
1106 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1107 f->lge_fragptr_hi = 0;
1108 frag++;
1109 }
1110 }
1111
1112 if (m != NULL)
1113 return(ENOBUFS);
1114
1115 cur_tx->lge_mbuf = m_head;
1116 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1117 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1118
1119 /* Queue for transmit */
1120 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1121
1122 return(0);
1123 }
1124
1125 /*
1126 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1127 * to the mbuf data regions directly in the transmit lists. We also save a
1128 * copy of the pointers since the transmit list fragment pointers are
1129 * physical addresses.
1130 */
1131
1132 static void
lge_start(if_t ifp)1133 lge_start(if_t ifp)
1134 {
1135 struct lge_softc *sc;
1136
1137 sc = if_getsoftc(ifp);
1138 LGE_LOCK(sc);
1139 lge_start_locked(ifp);
1140 LGE_UNLOCK(sc);
1141 }
1142
1143 static void
lge_start_locked(if_t ifp)1144 lge_start_locked(if_t ifp)
1145 {
1146 struct lge_softc *sc;
1147 struct mbuf *m_head = NULL;
1148 u_int32_t idx;
1149
1150 sc = if_getsoftc(ifp);
1151
1152 if (!sc->lge_link)
1153 return;
1154
1155 idx = sc->lge_cdata.lge_tx_prod;
1156
1157 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
1158 return;
1159
1160 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1161 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1162 break;
1163
1164 m_head = if_dequeue(ifp);
1165 if (m_head == NULL)
1166 break;
1167
1168 if (lge_encap(sc, m_head, &idx)) {
1169 if_sendq_prepend(ifp, m_head);
1170 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1171 break;
1172 }
1173
1174 /*
1175 * If there's a BPF listener, bounce a copy of this frame
1176 * to him.
1177 */
1178 BPF_MTAP(ifp, m_head);
1179 }
1180
1181 sc->lge_cdata.lge_tx_prod = idx;
1182
1183 /*
1184 * Set a timeout in case the chip goes out to lunch.
1185 */
1186 sc->lge_timer = 5;
1187
1188 return;
1189 }
1190
1191 static void
lge_init(void * xsc)1192 lge_init(void *xsc)
1193 {
1194 struct lge_softc *sc = xsc;
1195
1196 LGE_LOCK(sc);
1197 lge_init_locked(sc);
1198 LGE_UNLOCK(sc);
1199 }
1200
1201 static void
lge_init_locked(struct lge_softc * sc)1202 lge_init_locked(struct lge_softc *sc)
1203 {
1204 if_t ifp = sc->lge_ifp;
1205
1206 LGE_LOCK_ASSERT(sc);
1207 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1208 return;
1209
1210 /*
1211 * Cancel pending I/O and free all RX/TX buffers.
1212 */
1213 lge_stop(sc);
1214 lge_reset(sc);
1215
1216 /* Set MAC address */
1217 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[0]));
1218 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[4]));
1219
1220 /* Init circular RX list. */
1221 if (lge_list_rx_init(sc) == ENOBUFS) {
1222 device_printf(sc->lge_dev, "initialization failed: no "
1223 "memory for rx buffers\n");
1224 lge_stop(sc);
1225 return;
1226 }
1227
1228 /*
1229 * Init tx descriptors.
1230 */
1231 lge_list_tx_init(sc);
1232
1233 /* Set initial value for MODE1 register. */
1234 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1235 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1236 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1237 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1238
1239 /* If we want promiscuous mode, set the allframes bit. */
1240 if (if_getflags(ifp) & IFF_PROMISC) {
1241 CSR_WRITE_4(sc, LGE_MODE1,
1242 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1243 } else {
1244 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1245 }
1246
1247 /*
1248 * Set the capture broadcast bit to capture broadcast frames.
1249 */
1250 if (if_getflags(ifp) & IFF_BROADCAST) {
1251 CSR_WRITE_4(sc, LGE_MODE1,
1252 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1253 } else {
1254 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1255 }
1256
1257 /* Packet padding workaround? */
1258 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1259
1260 /* No error frames */
1261 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1262
1263 /* Receive large frames */
1264 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1265
1266 /* Workaround: disable RX/TX flow control */
1267 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1269
1270 /* Make sure to strip CRC from received frames */
1271 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1272
1273 /* Turn off magic packet mode */
1274 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1275
1276 /* Turn off all VLAN stuff */
1277 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1278 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1279
1280 /* Workarond: FIFO overflow */
1281 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1282 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1283
1284 /*
1285 * Load the multicast filter.
1286 */
1287 lge_setmulti(sc);
1288
1289 /*
1290 * Enable hardware checksum validation for all received IPv4
1291 * packets, do not reject packets with bad checksums.
1292 */
1293 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1294 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1295 LGE_MODE2_RX_ERRCSUM);
1296
1297 /*
1298 * Enable the delivery of PHY interrupts based on
1299 * link/speed/duplex status chalges.
1300 */
1301 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1302
1303 /* Enable receiver and transmitter. */
1304 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1305 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1306
1307 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1309
1310 /*
1311 * Enable interrupts.
1312 */
1313 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1314 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1315
1316 lge_ifmedia_upd_locked(ifp);
1317
1318 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1319 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1320
1321 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1322
1323 return;
1324 }
1325
1326 /*
1327 * Set media options.
1328 */
1329 static int
lge_ifmedia_upd(if_t ifp)1330 lge_ifmedia_upd(if_t ifp)
1331 {
1332 struct lge_softc *sc;
1333
1334 sc = if_getsoftc(ifp);
1335 LGE_LOCK(sc);
1336 lge_ifmedia_upd_locked(ifp);
1337 LGE_UNLOCK(sc);
1338
1339 return(0);
1340 }
1341
1342 static void
lge_ifmedia_upd_locked(if_t ifp)1343 lge_ifmedia_upd_locked(if_t ifp)
1344 {
1345 struct lge_softc *sc;
1346 struct mii_data *mii;
1347 struct mii_softc *miisc;
1348
1349 sc = if_getsoftc(ifp);
1350
1351 LGE_LOCK_ASSERT(sc);
1352 mii = device_get_softc(sc->lge_miibus);
1353 sc->lge_link = 0;
1354 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1355 PHY_RESET(miisc);
1356 mii_mediachg(mii);
1357 }
1358
1359 /*
1360 * Report current media status.
1361 */
1362 static void
lge_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1363 lge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1364 {
1365 struct lge_softc *sc;
1366 struct mii_data *mii;
1367
1368 sc = if_getsoftc(ifp);
1369
1370 LGE_LOCK(sc);
1371 mii = device_get_softc(sc->lge_miibus);
1372 mii_pollstat(mii);
1373 ifmr->ifm_active = mii->mii_media_active;
1374 ifmr->ifm_status = mii->mii_media_status;
1375 LGE_UNLOCK(sc);
1376
1377 return;
1378 }
1379
1380 static int
lge_ioctl(if_t ifp,u_long command,caddr_t data)1381 lge_ioctl(if_t ifp, u_long command, caddr_t data)
1382 {
1383 struct lge_softc *sc = if_getsoftc(ifp);
1384 struct ifreq *ifr = (struct ifreq *) data;
1385 struct mii_data *mii;
1386 int error = 0;
1387
1388 switch(command) {
1389 case SIOCSIFMTU:
1390 LGE_LOCK(sc);
1391 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1392 error = EINVAL;
1393 else
1394 if_setmtu(ifp, ifr->ifr_mtu);
1395 LGE_UNLOCK(sc);
1396 break;
1397 case SIOCSIFFLAGS:
1398 LGE_LOCK(sc);
1399 if (if_getflags(ifp) & IFF_UP) {
1400 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
1401 if_getflags(ifp) & IFF_PROMISC &&
1402 !(sc->lge_if_flags & IFF_PROMISC)) {
1403 CSR_WRITE_4(sc, LGE_MODE1,
1404 LGE_MODE1_SETRST_CTL1|
1405 LGE_MODE1_RX_PROMISC);
1406 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
1407 !(if_getflags(ifp) & IFF_PROMISC) &&
1408 sc->lge_if_flags & IFF_PROMISC) {
1409 CSR_WRITE_4(sc, LGE_MODE1,
1410 LGE_MODE1_RX_PROMISC);
1411 } else {
1412 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1413 lge_init_locked(sc);
1414 }
1415 } else {
1416 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1417 lge_stop(sc);
1418 }
1419 sc->lge_if_flags = if_getflags(ifp);
1420 LGE_UNLOCK(sc);
1421 error = 0;
1422 break;
1423 case SIOCADDMULTI:
1424 case SIOCDELMULTI:
1425 LGE_LOCK(sc);
1426 lge_setmulti(sc);
1427 LGE_UNLOCK(sc);
1428 error = 0;
1429 break;
1430 case SIOCGIFMEDIA:
1431 case SIOCSIFMEDIA:
1432 mii = device_get_softc(sc->lge_miibus);
1433 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1434 break;
1435 default:
1436 error = ether_ioctl(ifp, command, data);
1437 break;
1438 }
1439
1440 return(error);
1441 }
1442
1443 static void
lge_watchdog(struct lge_softc * sc)1444 lge_watchdog(struct lge_softc *sc)
1445 {
1446 if_t ifp;
1447
1448 LGE_LOCK_ASSERT(sc);
1449 ifp = sc->lge_ifp;
1450
1451 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1452 if_printf(ifp, "watchdog timeout\n");
1453
1454 lge_stop(sc);
1455 lge_reset(sc);
1456 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1457 lge_init_locked(sc);
1458
1459 if (!if_sendq_empty(ifp))
1460 lge_start_locked(ifp);
1461 }
1462
1463 /*
1464 * Stop the adapter and free any mbufs allocated to the
1465 * RX and TX lists.
1466 */
1467 static void
lge_stop(struct lge_softc * sc)1468 lge_stop(struct lge_softc *sc)
1469 {
1470 int i;
1471 if_t ifp;
1472
1473 LGE_LOCK_ASSERT(sc);
1474 ifp = sc->lge_ifp;
1475 sc->lge_timer = 0;
1476 callout_stop(&sc->lge_stat_callout);
1477 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1478
1479 /* Disable receiver and transmitter. */
1480 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1481 sc->lge_link = 0;
1482
1483 /*
1484 * Free data in the RX lists.
1485 */
1486 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1487 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1488 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1489 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1490 }
1491 }
1492 bzero((char *)&sc->lge_ldata->lge_rx_list,
1493 sizeof(sc->lge_ldata->lge_rx_list));
1494
1495 /*
1496 * Free the TX list buffers.
1497 */
1498 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1499 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1500 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1501 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1502 }
1503 }
1504
1505 bzero((char *)&sc->lge_ldata->lge_tx_list,
1506 sizeof(sc->lge_ldata->lge_tx_list));
1507
1508 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1509
1510 return;
1511 }
1512
1513 /*
1514 * Stop all chip I/O so that the kernel's probe routines don't
1515 * get confused by errant DMAs when rebooting.
1516 */
1517 static int
lge_shutdown(device_t dev)1518 lge_shutdown(device_t dev)
1519 {
1520 struct lge_softc *sc;
1521
1522 sc = device_get_softc(dev);
1523
1524 LGE_LOCK(sc);
1525 lge_reset(sc);
1526 lge_stop(sc);
1527 LGE_UNLOCK(sc);
1528
1529 return (0);
1530 }
1531