1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 6 * Bill Paul <william.paul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 42 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 44 * are three supported methods for data transfer between host and 45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 46 * Propulsion Technology (tm) DMA. The latter mechanism is a form 47 * of double buffer DMA where the packet data is copied to a 48 * pre-allocated DMA buffer who's physical address has been loaded 49 * into a table at device initialization time. The rationale is that 50 * the virtual to physical address translation needed for normal 51 * scatter/gather DMA is more expensive than the data copy needed 52 * for double buffering. This may be true in Windows NT and the like, 53 * but it isn't true for us, at least on the x86 arch. This driver 54 * uses the scatter/gather I/O method for both TX and RX. 55 * 56 * The LXT1001 only supports TCP/IP checksum offload on receive. 57 * Also, the VLAN tagging is done using a 16-entry table which allows 58 * the chip to perform hardware filtering based on VLAN tags. Sadly, 59 * our vlan support doesn't currently play well with this kind of 60 * hardware support. 61 * 62 * Special thanks to: 63 * - Jeff James at Intel, for arranging to have the LXT1001 manual 64 * released (at long last) 65 * - Beny Chen at D-Link, for actually sending it to me 66 * - Brad Short and Keith Alexis at SMC, for sending me sample 67 * SMC9462SX and SMC9462TX adapters for testing 68 * - Paul Saab at Y!, for not killing me (though it remains to be seen 69 * if in fact he did me much of a favor) 70 */ 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/sockio.h> 75 #include <sys/mbuf.h> 76 #include <sys/malloc.h> 77 #include <sys/kernel.h> 78 #include <sys/module.h> 79 #include <sys/socket.h> 80 81 #include <net/if.h> 82 #include <net/if_var.h> 83 #include <net/if_arp.h> 84 #include <net/ethernet.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 #include <net/if_types.h> 88 89 #include <net/bpf.h> 90 91 #include <vm/vm.h> /* for vtophys */ 92 #include <vm/pmap.h> /* for vtophys */ 93 #include <machine/bus.h> 94 #include <machine/resource.h> 95 #include <sys/bus.h> 96 #include <sys/rman.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 104 #define LGE_USEIOSPACE 105 106 #include <dev/lge/if_lgereg.h> 107 108 /* "device miibus" required. See GENERIC if you get errors here. */ 109 #include "miibus_if.h" 110 111 /* 112 * Various supported device vendors/types and their names. 113 */ 114 static const struct lge_type lge_devs[] = { 115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 116 { 0, 0, NULL } 117 }; 118 119 static int lge_probe(device_t); 120 static int lge_attach(device_t); 121 static int lge_detach(device_t); 122 123 static int lge_alloc_jumbo_mem(struct lge_softc *); 124 static void lge_free_jumbo_mem(struct lge_softc *); 125 static void *lge_jalloc(struct lge_softc *); 126 static void lge_jfree(struct mbuf *); 127 128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 130 static void lge_rxeof(struct lge_softc *, int); 131 static void lge_rxeoc(struct lge_softc *); 132 static void lge_txeof(struct lge_softc *); 133 static void lge_intr(void *); 134 static void lge_tick(void *); 135 static void lge_start(if_t); 136 static void lge_start_locked(if_t); 137 static int lge_ioctl(if_t, u_long, caddr_t); 138 static void lge_init(void *); 139 static void lge_init_locked(struct lge_softc *); 140 static void lge_stop(struct lge_softc *); 141 static void lge_watchdog(struct lge_softc *); 142 static int lge_shutdown(device_t); 143 static int lge_ifmedia_upd(if_t); 144 static void lge_ifmedia_upd_locked(if_t); 145 static void lge_ifmedia_sts(if_t, struct ifmediareq *); 146 147 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 148 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 149 150 static int lge_miibus_readreg(device_t, int, int); 151 static int lge_miibus_writereg(device_t, int, int, int); 152 static void lge_miibus_statchg(device_t); 153 154 static void lge_setmulti(struct lge_softc *); 155 static void lge_reset(struct lge_softc *); 156 static int lge_list_rx_init(struct lge_softc *); 157 static int lge_list_tx_init(struct lge_softc *); 158 159 #ifdef LGE_USEIOSPACE 160 #define LGE_RES SYS_RES_IOPORT 161 #define LGE_RID LGE_PCI_LOIO 162 #else 163 #define LGE_RES SYS_RES_MEMORY 164 #define LGE_RID LGE_PCI_LOMEM 165 #endif 166 167 static device_method_t lge_methods[] = { 168 /* Device interface */ 169 DEVMETHOD(device_probe, lge_probe), 170 DEVMETHOD(device_attach, lge_attach), 171 DEVMETHOD(device_detach, lge_detach), 172 DEVMETHOD(device_shutdown, lge_shutdown), 173 174 /* MII interface */ 175 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 176 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 177 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 178 179 DEVMETHOD_END 180 }; 181 182 static driver_t lge_driver = { 183 "lge", 184 lge_methods, 185 sizeof(struct lge_softc) 186 }; 187 188 DRIVER_MODULE(lge, pci, lge_driver, 0, 0); 189 DRIVER_MODULE(miibus, lge, miibus_driver, 0, 0); 190 MODULE_DEPEND(lge, pci, 1, 1, 1); 191 MODULE_DEPEND(lge, ether, 1, 1, 1); 192 MODULE_DEPEND(lge, miibus, 1, 1, 1); 193 194 #define LGE_SETBIT(sc, reg, x) \ 195 CSR_WRITE_4(sc, reg, \ 196 CSR_READ_4(sc, reg) | (x)) 197 198 #define LGE_CLRBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) & ~(x)) 201 202 #define SIO_SET(x) \ 203 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 204 205 #define SIO_CLR(x) \ 206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 207 208 /* 209 * Read a word of data stored in the EEPROM at address 'addr.' 210 */ 211 static void 212 lge_eeprom_getword(struct lge_softc *sc, int addr, u_int16_t *dest) 213 { 214 int i; 215 u_int32_t val; 216 217 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 218 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 219 220 for (i = 0; i < LGE_TIMEOUT; i++) 221 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 222 break; 223 224 if (i == LGE_TIMEOUT) { 225 device_printf(sc->lge_dev, "EEPROM read timed out\n"); 226 return; 227 } 228 229 val = CSR_READ_4(sc, LGE_EEDATA); 230 231 if (addr & 1) 232 *dest = (val >> 16) & 0xFFFF; 233 else 234 *dest = val & 0xFFFF; 235 236 return; 237 } 238 239 /* 240 * Read a sequence of words from the EEPROM. 241 */ 242 static void 243 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt, int swap) 244 { 245 int i; 246 u_int16_t word = 0, *ptr; 247 248 for (i = 0; i < cnt; i++) { 249 lge_eeprom_getword(sc, off + i, &word); 250 ptr = (u_int16_t *)(dest + (i * 2)); 251 if (swap) 252 *ptr = ntohs(word); 253 else 254 *ptr = word; 255 } 256 257 return; 258 } 259 260 static int 261 lge_miibus_readreg(device_t dev, int phy, int reg) 262 { 263 struct lge_softc *sc; 264 int i; 265 266 sc = device_get_softc(dev); 267 268 /* 269 * If we have a non-PCS PHY, pretend that the internal 270 * autoneg stuff at PHY address 0 isn't there so that 271 * the miibus code will find only the GMII PHY. 272 */ 273 if (sc->lge_pcs == 0 && phy == 0) 274 return(0); 275 276 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 277 278 for (i = 0; i < LGE_TIMEOUT; i++) 279 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 280 break; 281 282 if (i == LGE_TIMEOUT) { 283 device_printf(sc->lge_dev, "PHY read timed out\n"); 284 return(0); 285 } 286 287 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 288 } 289 290 static int 291 lge_miibus_writereg(device_t dev, int phy, int reg, int data) 292 { 293 struct lge_softc *sc; 294 int i; 295 296 sc = device_get_softc(dev); 297 298 CSR_WRITE_4(sc, LGE_GMIICTL, 299 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 300 301 for (i = 0; i < LGE_TIMEOUT; i++) 302 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 303 break; 304 305 if (i == LGE_TIMEOUT) { 306 device_printf(sc->lge_dev, "PHY write timed out\n"); 307 return(0); 308 } 309 310 return(0); 311 } 312 313 static void 314 lge_miibus_statchg(device_t dev) 315 { 316 struct lge_softc *sc; 317 struct mii_data *mii; 318 319 sc = device_get_softc(dev); 320 mii = device_get_softc(sc->lge_miibus); 321 322 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 323 switch (IFM_SUBTYPE(mii->mii_media_active)) { 324 case IFM_1000_T: 325 case IFM_1000_SX: 326 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 327 break; 328 case IFM_100_TX: 329 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 330 break; 331 case IFM_10_T: 332 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 333 break; 334 default: 335 /* 336 * Choose something, even if it's wrong. Clearing 337 * all the bits will hose autoneg on the internal 338 * PHY. 339 */ 340 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 341 break; 342 } 343 344 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 345 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 346 } else { 347 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 348 } 349 350 return; 351 } 352 353 static u_int 354 lge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int count) 355 { 356 uint32_t h, *hashes = arg; 357 358 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 359 if (h < 32) 360 hashes[0] |= (1 << h); 361 else 362 hashes[1] |= (1 << (h - 32)); 363 return (1); 364 } 365 366 static void 367 lge_setmulti(struct lge_softc *sc) 368 { 369 if_t ifp; 370 uint32_t hashes[2] = { 0, 0 }; 371 372 ifp = sc->lge_ifp; 373 LGE_LOCK_ASSERT(sc); 374 375 /* Make sure multicast hash table is enabled. */ 376 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 377 378 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 379 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 380 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 381 return; 382 } 383 384 /* first, zot all the existing hash bits */ 385 CSR_WRITE_4(sc, LGE_MAR0, 0); 386 CSR_WRITE_4(sc, LGE_MAR1, 0); 387 388 /* now program new ones */ 389 if_foreach_llmaddr(ifp, lge_hash_maddr, hashes); 390 391 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 392 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 393 394 return; 395 } 396 397 static void 398 lge_reset(struct lge_softc *sc) 399 { 400 int i; 401 402 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 403 404 for (i = 0; i < LGE_TIMEOUT; i++) { 405 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 406 break; 407 } 408 409 if (i == LGE_TIMEOUT) 410 device_printf(sc->lge_dev, "reset never completed\n"); 411 412 /* Wait a little while for the chip to get its brains in order. */ 413 DELAY(1000); 414 415 return; 416 } 417 418 /* 419 * Probe for a Level 1 chip. Check the PCI vendor and device 420 * IDs against our list and return a device name if we find a match. 421 */ 422 static int 423 lge_probe(device_t dev) 424 { 425 const struct lge_type *t; 426 427 t = lge_devs; 428 429 while(t->lge_name != NULL) { 430 if ((pci_get_vendor(dev) == t->lge_vid) && 431 (pci_get_device(dev) == t->lge_did)) { 432 device_set_desc(dev, t->lge_name); 433 return(BUS_PROBE_DEFAULT); 434 } 435 t++; 436 } 437 438 return(ENXIO); 439 } 440 441 /* 442 * Attach the interface. Allocate softc structures, do ifmedia 443 * setup and ethernet/BPF attach. 444 */ 445 static int 446 lge_attach(device_t dev) 447 { 448 u_char eaddr[ETHER_ADDR_LEN]; 449 struct lge_softc *sc; 450 if_t ifp = NULL; 451 int error = 0, rid; 452 453 sc = device_get_softc(dev); 454 sc->lge_dev = dev; 455 456 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 457 MTX_DEF); 458 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0); 459 460 /* 461 * Map control/status registers. 462 */ 463 pci_enable_busmaster(dev); 464 465 rid = LGE_RID; 466 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 467 468 if (sc->lge_res == NULL) { 469 device_printf(dev, "couldn't map ports/memory\n"); 470 error = ENXIO; 471 goto fail; 472 } 473 474 sc->lge_btag = rman_get_bustag(sc->lge_res); 475 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 476 477 /* Allocate interrupt */ 478 rid = 0; 479 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 480 RF_SHAREABLE | RF_ACTIVE); 481 482 if (sc->lge_irq == NULL) { 483 device_printf(dev, "couldn't map interrupt\n"); 484 error = ENXIO; 485 goto fail; 486 } 487 488 /* Reset the adapter. */ 489 lge_reset(sc); 490 491 /* 492 * Get station address from the EEPROM. 493 */ 494 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 495 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 496 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 497 498 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 499 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 500 501 if (sc->lge_ldata == NULL) { 502 device_printf(dev, "no memory for list buffers!\n"); 503 error = ENXIO; 504 goto fail; 505 } 506 507 /* Try to allocate memory for jumbo buffers. */ 508 if (lge_alloc_jumbo_mem(sc)) { 509 device_printf(dev, "jumbo buffer allocation failed\n"); 510 error = ENXIO; 511 goto fail; 512 } 513 514 ifp = sc->lge_ifp = if_alloc(IFT_ETHER); 515 if_setsoftc(ifp, sc); 516 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 517 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 518 if_setioctlfn(ifp, lge_ioctl); 519 if_setstartfn(ifp, lge_start); 520 if_setinitfn(ifp, lge_init); 521 if_setsendqlen(ifp, LGE_TX_LIST_CNT - 1); 522 if_setcapabilities(ifp, IFCAP_RXCSUM); 523 if_setcapenable(ifp, if_getcapabilities(ifp)); 524 525 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 526 sc->lge_pcs = 1; 527 else 528 sc->lge_pcs = 0; 529 530 /* 531 * Do MII setup. 532 */ 533 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd, 534 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 535 if (error != 0) { 536 device_printf(dev, "attaching PHYs failed\n"); 537 goto fail; 538 } 539 540 /* 541 * Call MI attach routine. 542 */ 543 ether_ifattach(ifp, eaddr); 544 545 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE, 546 NULL, lge_intr, sc, &sc->lge_intrhand); 547 548 if (error) { 549 ether_ifdetach(ifp); 550 device_printf(dev, "couldn't set up irq\n"); 551 goto fail; 552 } 553 return (0); 554 555 fail: 556 lge_free_jumbo_mem(sc); 557 if (sc->lge_ldata) 558 free(sc->lge_ldata, M_DEVBUF); 559 if (ifp) 560 if_free(ifp); 561 if (sc->lge_irq) 562 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 563 if (sc->lge_res) 564 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 565 mtx_destroy(&sc->lge_mtx); 566 return(error); 567 } 568 569 static int 570 lge_detach(device_t dev) 571 { 572 struct lge_softc *sc; 573 if_t ifp; 574 575 sc = device_get_softc(dev); 576 ifp = sc->lge_ifp; 577 578 LGE_LOCK(sc); 579 lge_reset(sc); 580 lge_stop(sc); 581 LGE_UNLOCK(sc); 582 callout_drain(&sc->lge_stat_callout); 583 ether_ifdetach(ifp); 584 585 bus_generic_detach(dev); 586 device_delete_child(dev, sc->lge_miibus); 587 588 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 589 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 590 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 591 592 free(sc->lge_ldata, M_DEVBUF); 593 if_free(ifp); 594 lge_free_jumbo_mem(sc); 595 mtx_destroy(&sc->lge_mtx); 596 597 return(0); 598 } 599 600 /* 601 * Initialize the transmit descriptors. 602 */ 603 static int 604 lge_list_tx_init(struct lge_softc *sc) 605 { 606 struct lge_list_data *ld; 607 struct lge_ring_data *cd; 608 int i; 609 610 cd = &sc->lge_cdata; 611 ld = sc->lge_ldata; 612 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 613 ld->lge_tx_list[i].lge_mbuf = NULL; 614 ld->lge_tx_list[i].lge_ctl = 0; 615 } 616 617 cd->lge_tx_prod = cd->lge_tx_cons = 0; 618 619 return(0); 620 } 621 622 623 /* 624 * Initialize the RX descriptors and allocate mbufs for them. Note that 625 * we arralge the descriptors in a closed ring, so that the last descriptor 626 * points back to the first. 627 */ 628 static int 629 lge_list_rx_init(struct lge_softc *sc) 630 { 631 struct lge_list_data *ld; 632 struct lge_ring_data *cd; 633 int i; 634 635 ld = sc->lge_ldata; 636 cd = &sc->lge_cdata; 637 638 cd->lge_rx_prod = cd->lge_rx_cons = 0; 639 640 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 641 642 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 643 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 644 break; 645 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 646 return(ENOBUFS); 647 } 648 649 /* Clear possible 'rx command queue empty' interrupt. */ 650 CSR_READ_4(sc, LGE_ISR); 651 652 return(0); 653 } 654 655 /* 656 * Initialize an RX descriptor and attach an MBUF cluster. 657 */ 658 static int 659 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 660 { 661 struct mbuf *m_new = NULL; 662 char *buf = NULL; 663 664 if (m == NULL) { 665 MGETHDR(m_new, M_NOWAIT, MT_DATA); 666 if (m_new == NULL) { 667 device_printf(sc->lge_dev, "no memory for rx list " 668 "-- packet dropped!\n"); 669 return(ENOBUFS); 670 } 671 672 /* Allocate the jumbo buffer */ 673 buf = lge_jalloc(sc); 674 if (buf == NULL) { 675 #ifdef LGE_VERBOSE 676 device_printf(sc->lge_dev, "jumbo allocation failed " 677 "-- packet dropped!\n"); 678 #endif 679 m_freem(m_new); 680 return(ENOBUFS); 681 } 682 /* Attach the buffer to the mbuf */ 683 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 684 m_extadd(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, sc, NULL, 685 0, EXT_NET_DRV); 686 } else { 687 m_new = m; 688 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 689 m_new->m_data = m_new->m_ext.ext_buf; 690 } 691 692 /* 693 * Adjust alignment so packet payload begins on a 694 * longword boundary. Mandatory for Alpha, useful on 695 * x86 too. 696 */ 697 m_adj(m_new, ETHER_ALIGN); 698 699 c->lge_mbuf = m_new; 700 c->lge_fragptr_hi = 0; 701 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 702 c->lge_fraglen = m_new->m_len; 703 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 704 c->lge_sts = 0; 705 706 /* 707 * Put this buffer in the RX command FIFO. To do this, 708 * we just write the physical address of the descriptor 709 * into the RX descriptor address registers. Note that 710 * there are two registers, one high DWORD and one low 711 * DWORD, which lets us specify a 64-bit address if 712 * desired. We only use a 32-bit address for now. 713 * Writing to the low DWORD register is what actually 714 * causes the command to be issued, so we do that 715 * last. 716 */ 717 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 718 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 719 720 return(0); 721 } 722 723 static int 724 lge_alloc_jumbo_mem(struct lge_softc *sc) 725 { 726 caddr_t ptr; 727 int i; 728 struct lge_jpool_entry *entry; 729 730 /* Grab a big chunk o' storage. */ 731 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 732 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 733 734 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 735 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n"); 736 return(ENOBUFS); 737 } 738 739 SLIST_INIT(&sc->lge_jfree_listhead); 740 SLIST_INIT(&sc->lge_jinuse_listhead); 741 742 /* 743 * Now divide it up into 9K pieces and save the addresses 744 * in an array. 745 */ 746 ptr = sc->lge_cdata.lge_jumbo_buf; 747 for (i = 0; i < LGE_JSLOTS; i++) { 748 sc->lge_cdata.lge_jslots[i] = ptr; 749 ptr += LGE_JLEN; 750 entry = malloc(sizeof(struct lge_jpool_entry), 751 M_DEVBUF, M_NOWAIT); 752 if (entry == NULL) { 753 device_printf(sc->lge_dev, "no memory for jumbo " 754 "buffer queue!\n"); 755 return(ENOBUFS); 756 } 757 entry->slot = i; 758 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 759 entry, jpool_entries); 760 } 761 762 return(0); 763 } 764 765 static void 766 lge_free_jumbo_mem(struct lge_softc *sc) 767 { 768 struct lge_jpool_entry *entry; 769 770 if (sc->lge_cdata.lge_jumbo_buf == NULL) 771 return; 772 773 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) { 774 device_printf(sc->lge_dev, 775 "asked to free buffer that is in use!\n"); 776 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 777 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, 778 jpool_entries); 779 } 780 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) { 781 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 782 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 783 free(entry, M_DEVBUF); 784 } 785 786 free(sc->lge_cdata.lge_jumbo_buf, M_DEVBUF); 787 788 return; 789 } 790 791 /* 792 * Allocate a jumbo buffer. 793 */ 794 static void * 795 lge_jalloc(struct lge_softc *sc) 796 { 797 struct lge_jpool_entry *entry; 798 799 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 800 801 if (entry == NULL) { 802 #ifdef LGE_VERBOSE 803 device_printf(sc->lge_dev, "no free jumbo buffers\n"); 804 #endif 805 return(NULL); 806 } 807 808 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 809 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 810 return(sc->lge_cdata.lge_jslots[entry->slot]); 811 } 812 813 /* 814 * Release a jumbo buffer. 815 */ 816 static void 817 lge_jfree(struct mbuf *m) 818 { 819 struct lge_softc *sc; 820 int i; 821 struct lge_jpool_entry *entry; 822 823 /* Extract the softc struct pointer. */ 824 sc = m->m_ext.ext_arg1; 825 826 if (sc == NULL) 827 panic("lge_jfree: can't find softc pointer!"); 828 829 /* calculate the slot this buffer belongs to */ 830 i = ((vm_offset_t)m->m_ext.ext_buf 831 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 832 833 if ((i < 0) || (i >= LGE_JSLOTS)) 834 panic("lge_jfree: asked to free buffer that we don't manage!"); 835 836 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 837 if (entry == NULL) 838 panic("lge_jfree: buffer not in use!"); 839 entry->slot = i; 840 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 841 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 842 } 843 844 /* 845 * A frame has been uploaded: pass the resulting mbuf chain up to 846 * the higher level protocols. 847 */ 848 static void 849 lge_rxeof(struct lge_softc *sc, int cnt) 850 { 851 struct mbuf *m; 852 if_t ifp; 853 struct lge_rx_desc *cur_rx; 854 int c, i, total_len = 0; 855 u_int32_t rxsts, rxctl; 856 857 ifp = sc->lge_ifp; 858 859 /* Find out how many frames were processed. */ 860 c = cnt; 861 i = sc->lge_cdata.lge_rx_cons; 862 863 /* Suck them in. */ 864 while(c) { 865 struct mbuf *m0 = NULL; 866 867 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 868 rxctl = cur_rx->lge_ctl; 869 rxsts = cur_rx->lge_sts; 870 m = cur_rx->lge_mbuf; 871 cur_rx->lge_mbuf = NULL; 872 total_len = LGE_RXBYTES(cur_rx); 873 LGE_INC(i, LGE_RX_LIST_CNT); 874 c--; 875 876 /* 877 * If an error occurs, update stats, clear the 878 * status word and leave the mbuf cluster in place: 879 * it should simply get re-used next time this descriptor 880 * comes up in the ring. 881 */ 882 if (rxctl & LGE_RXCTL_ERRMASK) { 883 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 884 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 885 continue; 886 } 887 888 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 889 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 890 ifp, NULL); 891 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 892 if (m0 == NULL) { 893 device_printf(sc->lge_dev, "no receive buffers " 894 "available -- packet dropped!\n"); 895 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 896 continue; 897 } 898 m = m0; 899 } else { 900 m->m_pkthdr.rcvif = ifp; 901 m->m_pkthdr.len = m->m_len = total_len; 902 } 903 904 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 905 906 /* Do IP checksum checking. */ 907 if (rxsts & LGE_RXSTS_ISIP) 908 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 909 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 910 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 911 if ((rxsts & LGE_RXSTS_ISTCP && 912 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 913 (rxsts & LGE_RXSTS_ISUDP && 914 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 915 m->m_pkthdr.csum_flags |= 916 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 917 m->m_pkthdr.csum_data = 0xffff; 918 } 919 920 LGE_UNLOCK(sc); 921 if_input(ifp, m); 922 LGE_LOCK(sc); 923 } 924 925 sc->lge_cdata.lge_rx_cons = i; 926 927 return; 928 } 929 930 static void 931 lge_rxeoc(struct lge_softc *sc) 932 { 933 if_t ifp; 934 935 ifp = sc->lge_ifp; 936 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 937 lge_init_locked(sc); 938 return; 939 } 940 941 /* 942 * A frame was downloaded to the chip. It's safe for us to clean up 943 * the list buffers. 944 */ 945 946 static void 947 lge_txeof(struct lge_softc *sc) 948 { 949 struct lge_tx_desc *cur_tx = NULL; 950 if_t ifp; 951 u_int32_t idx, txdone; 952 953 ifp = sc->lge_ifp; 954 955 /* Clear the timeout timer. */ 956 sc->lge_timer = 0; 957 958 /* 959 * Go through our tx list and free mbufs for those 960 * frames that have been transmitted. 961 */ 962 idx = sc->lge_cdata.lge_tx_cons; 963 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 964 965 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 966 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 967 968 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 969 if (cur_tx->lge_mbuf != NULL) { 970 m_freem(cur_tx->lge_mbuf); 971 cur_tx->lge_mbuf = NULL; 972 } 973 cur_tx->lge_ctl = 0; 974 975 txdone--; 976 LGE_INC(idx, LGE_TX_LIST_CNT); 977 sc->lge_timer = 0; 978 } 979 980 sc->lge_cdata.lge_tx_cons = idx; 981 982 if (cur_tx != NULL) 983 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 984 985 return; 986 } 987 988 static void 989 lge_tick(void *xsc) 990 { 991 struct lge_softc *sc; 992 struct mii_data *mii; 993 if_t ifp; 994 995 sc = xsc; 996 ifp = sc->lge_ifp; 997 LGE_LOCK_ASSERT(sc); 998 999 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1000 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1001 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1002 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL)); 1003 1004 if (!sc->lge_link) { 1005 mii = device_get_softc(sc->lge_miibus); 1006 mii_tick(mii); 1007 if (mii->mii_media_status & IFM_ACTIVE && 1008 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1009 sc->lge_link++; 1010 if (bootverbose && 1011 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1012 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)) 1013 device_printf(sc->lge_dev, "gigabit link up\n"); 1014 if (!if_sendq_empty(ifp)) 1015 lge_start_locked(ifp); 1016 } 1017 } 1018 1019 if (sc->lge_timer != 0 && --sc->lge_timer == 0) 1020 lge_watchdog(sc); 1021 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1022 1023 return; 1024 } 1025 1026 static void 1027 lge_intr(void *arg) 1028 { 1029 struct lge_softc *sc; 1030 if_t ifp; 1031 u_int32_t status; 1032 1033 sc = arg; 1034 ifp = sc->lge_ifp; 1035 LGE_LOCK(sc); 1036 1037 /* Suppress unwanted interrupts */ 1038 if (!(if_getflags(ifp) & IFF_UP)) { 1039 lge_stop(sc); 1040 LGE_UNLOCK(sc); 1041 return; 1042 } 1043 1044 for (;;) { 1045 /* 1046 * Reading the ISR register clears all interrupts, and 1047 * clears the 'interrupts enabled' bit in the IMR 1048 * register. 1049 */ 1050 status = CSR_READ_4(sc, LGE_ISR); 1051 1052 if ((status & LGE_INTRS) == 0) 1053 break; 1054 1055 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1056 lge_txeof(sc); 1057 1058 if (status & LGE_ISR_RXDMA_DONE) 1059 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1060 1061 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1062 lge_rxeoc(sc); 1063 1064 if (status & LGE_ISR_PHY_INTR) { 1065 sc->lge_link = 0; 1066 callout_stop(&sc->lge_stat_callout); 1067 lge_tick(sc); 1068 } 1069 } 1070 1071 /* Re-enable interrupts. */ 1072 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1073 1074 if (!if_sendq_empty(ifp)) 1075 lge_start_locked(ifp); 1076 1077 LGE_UNLOCK(sc); 1078 return; 1079 } 1080 1081 /* 1082 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1083 * pointers to the fragment pointers. 1084 */ 1085 static int 1086 lge_encap(struct lge_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1087 { 1088 struct lge_frag *f = NULL; 1089 struct lge_tx_desc *cur_tx; 1090 struct mbuf *m; 1091 int frag = 0, tot_len = 0; 1092 1093 /* 1094 * Start packing the mbufs in this chain into 1095 * the fragment pointers. Stop when we run out 1096 * of fragments or hit the end of the mbuf chain. 1097 */ 1098 m = m_head; 1099 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1100 frag = 0; 1101 1102 for (m = m_head; m != NULL; m = m->m_next) { 1103 if (m->m_len != 0) { 1104 tot_len += m->m_len; 1105 f = &cur_tx->lge_frags[frag]; 1106 f->lge_fraglen = m->m_len; 1107 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1108 f->lge_fragptr_hi = 0; 1109 frag++; 1110 } 1111 } 1112 1113 if (m != NULL) 1114 return(ENOBUFS); 1115 1116 cur_tx->lge_mbuf = m_head; 1117 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1118 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1119 1120 /* Queue for transmit */ 1121 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1122 1123 return(0); 1124 } 1125 1126 /* 1127 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1128 * to the mbuf data regions directly in the transmit lists. We also save a 1129 * copy of the pointers since the transmit list fragment pointers are 1130 * physical addresses. 1131 */ 1132 1133 static void 1134 lge_start(if_t ifp) 1135 { 1136 struct lge_softc *sc; 1137 1138 sc = if_getsoftc(ifp); 1139 LGE_LOCK(sc); 1140 lge_start_locked(ifp); 1141 LGE_UNLOCK(sc); 1142 } 1143 1144 static void 1145 lge_start_locked(if_t ifp) 1146 { 1147 struct lge_softc *sc; 1148 struct mbuf *m_head = NULL; 1149 u_int32_t idx; 1150 1151 sc = if_getsoftc(ifp); 1152 1153 if (!sc->lge_link) 1154 return; 1155 1156 idx = sc->lge_cdata.lge_tx_prod; 1157 1158 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 1159 return; 1160 1161 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1162 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1163 break; 1164 1165 m_head = if_dequeue(ifp); 1166 if (m_head == NULL) 1167 break; 1168 1169 if (lge_encap(sc, m_head, &idx)) { 1170 if_sendq_prepend(ifp, m_head); 1171 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1172 break; 1173 } 1174 1175 /* 1176 * If there's a BPF listener, bounce a copy of this frame 1177 * to him. 1178 */ 1179 BPF_MTAP(ifp, m_head); 1180 } 1181 1182 sc->lge_cdata.lge_tx_prod = idx; 1183 1184 /* 1185 * Set a timeout in case the chip goes out to lunch. 1186 */ 1187 sc->lge_timer = 5; 1188 1189 return; 1190 } 1191 1192 static void 1193 lge_init(void *xsc) 1194 { 1195 struct lge_softc *sc = xsc; 1196 1197 LGE_LOCK(sc); 1198 lge_init_locked(sc); 1199 LGE_UNLOCK(sc); 1200 } 1201 1202 static void 1203 lge_init_locked(struct lge_softc *sc) 1204 { 1205 if_t ifp = sc->lge_ifp; 1206 1207 LGE_LOCK_ASSERT(sc); 1208 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1209 return; 1210 1211 /* 1212 * Cancel pending I/O and free all RX/TX buffers. 1213 */ 1214 lge_stop(sc); 1215 lge_reset(sc); 1216 1217 /* Set MAC address */ 1218 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[0])); 1219 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[4])); 1220 1221 /* Init circular RX list. */ 1222 if (lge_list_rx_init(sc) == ENOBUFS) { 1223 device_printf(sc->lge_dev, "initialization failed: no " 1224 "memory for rx buffers\n"); 1225 lge_stop(sc); 1226 return; 1227 } 1228 1229 /* 1230 * Init tx descriptors. 1231 */ 1232 lge_list_tx_init(sc); 1233 1234 /* Set initial value for MODE1 register. */ 1235 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1236 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1237 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1238 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1239 1240 /* If we want promiscuous mode, set the allframes bit. */ 1241 if (if_getflags(ifp) & IFF_PROMISC) { 1242 CSR_WRITE_4(sc, LGE_MODE1, 1243 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1244 } else { 1245 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1246 } 1247 1248 /* 1249 * Set the capture broadcast bit to capture broadcast frames. 1250 */ 1251 if (if_getflags(ifp) & IFF_BROADCAST) { 1252 CSR_WRITE_4(sc, LGE_MODE1, 1253 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1254 } else { 1255 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1256 } 1257 1258 /* Packet padding workaround? */ 1259 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1260 1261 /* No error frames */ 1262 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1263 1264 /* Receive large frames */ 1265 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1266 1267 /* Workaround: disable RX/TX flow control */ 1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1269 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1270 1271 /* Make sure to strip CRC from received frames */ 1272 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1273 1274 /* Turn off magic packet mode */ 1275 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1276 1277 /* Turn off all VLAN stuff */ 1278 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1279 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1280 1281 /* Workarond: FIFO overflow */ 1282 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1283 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1284 1285 /* 1286 * Load the multicast filter. 1287 */ 1288 lge_setmulti(sc); 1289 1290 /* 1291 * Enable hardware checksum validation for all received IPv4 1292 * packets, do not reject packets with bad checksums. 1293 */ 1294 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1295 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1296 LGE_MODE2_RX_ERRCSUM); 1297 1298 /* 1299 * Enable the delivery of PHY interrupts based on 1300 * link/speed/duplex status chalges. 1301 */ 1302 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1303 1304 /* Enable receiver and transmitter. */ 1305 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1307 1308 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1309 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1310 1311 /* 1312 * Enable interrupts. 1313 */ 1314 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1315 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1316 1317 lge_ifmedia_upd_locked(ifp); 1318 1319 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1320 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1321 1322 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc); 1323 1324 return; 1325 } 1326 1327 /* 1328 * Set media options. 1329 */ 1330 static int 1331 lge_ifmedia_upd(if_t ifp) 1332 { 1333 struct lge_softc *sc; 1334 1335 sc = if_getsoftc(ifp); 1336 LGE_LOCK(sc); 1337 lge_ifmedia_upd_locked(ifp); 1338 LGE_UNLOCK(sc); 1339 1340 return(0); 1341 } 1342 1343 static void 1344 lge_ifmedia_upd_locked(if_t ifp) 1345 { 1346 struct lge_softc *sc; 1347 struct mii_data *mii; 1348 struct mii_softc *miisc; 1349 1350 sc = if_getsoftc(ifp); 1351 1352 LGE_LOCK_ASSERT(sc); 1353 mii = device_get_softc(sc->lge_miibus); 1354 sc->lge_link = 0; 1355 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1356 PHY_RESET(miisc); 1357 mii_mediachg(mii); 1358 } 1359 1360 /* 1361 * Report current media status. 1362 */ 1363 static void 1364 lge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1365 { 1366 struct lge_softc *sc; 1367 struct mii_data *mii; 1368 1369 sc = if_getsoftc(ifp); 1370 1371 LGE_LOCK(sc); 1372 mii = device_get_softc(sc->lge_miibus); 1373 mii_pollstat(mii); 1374 ifmr->ifm_active = mii->mii_media_active; 1375 ifmr->ifm_status = mii->mii_media_status; 1376 LGE_UNLOCK(sc); 1377 1378 return; 1379 } 1380 1381 static int 1382 lge_ioctl(if_t ifp, u_long command, caddr_t data) 1383 { 1384 struct lge_softc *sc = if_getsoftc(ifp); 1385 struct ifreq *ifr = (struct ifreq *) data; 1386 struct mii_data *mii; 1387 int error = 0; 1388 1389 switch(command) { 1390 case SIOCSIFMTU: 1391 LGE_LOCK(sc); 1392 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1393 error = EINVAL; 1394 else 1395 if_setmtu(ifp, ifr->ifr_mtu); 1396 LGE_UNLOCK(sc); 1397 break; 1398 case SIOCSIFFLAGS: 1399 LGE_LOCK(sc); 1400 if (if_getflags(ifp) & IFF_UP) { 1401 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 1402 if_getflags(ifp) & IFF_PROMISC && 1403 !(sc->lge_if_flags & IFF_PROMISC)) { 1404 CSR_WRITE_4(sc, LGE_MODE1, 1405 LGE_MODE1_SETRST_CTL1| 1406 LGE_MODE1_RX_PROMISC); 1407 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 1408 !(if_getflags(ifp) & IFF_PROMISC) && 1409 sc->lge_if_flags & IFF_PROMISC) { 1410 CSR_WRITE_4(sc, LGE_MODE1, 1411 LGE_MODE1_RX_PROMISC); 1412 } else { 1413 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1414 lge_init_locked(sc); 1415 } 1416 } else { 1417 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1418 lge_stop(sc); 1419 } 1420 sc->lge_if_flags = if_getflags(ifp); 1421 LGE_UNLOCK(sc); 1422 error = 0; 1423 break; 1424 case SIOCADDMULTI: 1425 case SIOCDELMULTI: 1426 LGE_LOCK(sc); 1427 lge_setmulti(sc); 1428 LGE_UNLOCK(sc); 1429 error = 0; 1430 break; 1431 case SIOCGIFMEDIA: 1432 case SIOCSIFMEDIA: 1433 mii = device_get_softc(sc->lge_miibus); 1434 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1435 break; 1436 default: 1437 error = ether_ioctl(ifp, command, data); 1438 break; 1439 } 1440 1441 return(error); 1442 } 1443 1444 static void 1445 lge_watchdog(struct lge_softc *sc) 1446 { 1447 if_t ifp; 1448 1449 LGE_LOCK_ASSERT(sc); 1450 ifp = sc->lge_ifp; 1451 1452 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1453 if_printf(ifp, "watchdog timeout\n"); 1454 1455 lge_stop(sc); 1456 lge_reset(sc); 1457 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1458 lge_init_locked(sc); 1459 1460 if (!if_sendq_empty(ifp)) 1461 lge_start_locked(ifp); 1462 } 1463 1464 /* 1465 * Stop the adapter and free any mbufs allocated to the 1466 * RX and TX lists. 1467 */ 1468 static void 1469 lge_stop(struct lge_softc *sc) 1470 { 1471 int i; 1472 if_t ifp; 1473 1474 LGE_LOCK_ASSERT(sc); 1475 ifp = sc->lge_ifp; 1476 sc->lge_timer = 0; 1477 callout_stop(&sc->lge_stat_callout); 1478 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1479 1480 /* Disable receiver and transmitter. */ 1481 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1482 sc->lge_link = 0; 1483 1484 /* 1485 * Free data in the RX lists. 1486 */ 1487 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1488 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1489 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1490 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1491 } 1492 } 1493 bzero((char *)&sc->lge_ldata->lge_rx_list, 1494 sizeof(sc->lge_ldata->lge_rx_list)); 1495 1496 /* 1497 * Free the TX list buffers. 1498 */ 1499 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1500 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1501 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1502 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1503 } 1504 } 1505 1506 bzero((char *)&sc->lge_ldata->lge_tx_list, 1507 sizeof(sc->lge_ldata->lge_tx_list)); 1508 1509 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1510 1511 return; 1512 } 1513 1514 /* 1515 * Stop all chip I/O so that the kernel's probe routines don't 1516 * get confused by errant DMAs when rebooting. 1517 */ 1518 static int 1519 lge_shutdown(device_t dev) 1520 { 1521 struct lge_softc *sc; 1522 1523 sc = device_get_softc(dev); 1524 1525 LGE_LOCK(sc); 1526 lge_reset(sc); 1527 lge_stop(sc); 1528 LGE_UNLOCK(sc); 1529 1530 return (0); 1531 } 1532