1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5668.c -- RT5668B ALSA SoC audio component driver
4 *
5 * Copyright 2018 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/mutex.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/rt5668.h>
30
31 #include "rl6231.h"
32 #include "rt5668.h"
33
34 #define RT5668_NUM_SUPPLIES 3
35
36 static const char *rt5668_supply_names[RT5668_NUM_SUPPLIES] = {
37 "AVDD",
38 "MICVDD",
39 "VBAT",
40 };
41
42 struct rt5668_priv {
43 struct snd_soc_component *component;
44 struct rt5668_platform_data pdata;
45 struct gpio_desc *ldo1_en;
46 struct regmap *regmap;
47 struct snd_soc_jack *hs_jack;
48 struct regulator_bulk_data supplies[RT5668_NUM_SUPPLIES];
49 struct delayed_work jack_detect_work;
50 struct delayed_work jd_check_work;
51 struct mutex calibrate_mutex;
52
53 int sysclk;
54 int sysclk_src;
55 int lrck[RT5668_AIFS];
56 int bclk[RT5668_AIFS];
57 int master[RT5668_AIFS];
58
59 int pll_src;
60 int pll_in;
61 int pll_out;
62
63 int jack_type;
64 };
65
66 static const struct reg_default rt5668_reg[] = {
67 {0x0002, 0x8080},
68 {0x0003, 0x8000},
69 {0x0005, 0x0000},
70 {0x0006, 0x0000},
71 {0x0008, 0x800f},
72 {0x000b, 0x0000},
73 {0x0010, 0x4040},
74 {0x0011, 0x0000},
75 {0x0012, 0x1404},
76 {0x0013, 0x1000},
77 {0x0014, 0xa00a},
78 {0x0015, 0x0404},
79 {0x0016, 0x0404},
80 {0x0019, 0xafaf},
81 {0x001c, 0x2f2f},
82 {0x001f, 0x0000},
83 {0x0022, 0x5757},
84 {0x0023, 0x0039},
85 {0x0024, 0x000b},
86 {0x0026, 0xc0c4},
87 {0x0029, 0x8080},
88 {0x002a, 0xa0a0},
89 {0x002b, 0x0300},
90 {0x0030, 0x0000},
91 {0x003c, 0x0080},
92 {0x0044, 0x0c0c},
93 {0x0049, 0x0000},
94 {0x0061, 0x0000},
95 {0x0062, 0x0000},
96 {0x0063, 0x003f},
97 {0x0064, 0x0000},
98 {0x0065, 0x0000},
99 {0x0066, 0x0030},
100 {0x0067, 0x0000},
101 {0x006b, 0x0000},
102 {0x006c, 0x0000},
103 {0x006d, 0x2200},
104 {0x006e, 0x0a10},
105 {0x0070, 0x8000},
106 {0x0071, 0x8000},
107 {0x0073, 0x0000},
108 {0x0074, 0x0000},
109 {0x0075, 0x0002},
110 {0x0076, 0x0001},
111 {0x0079, 0x0000},
112 {0x007a, 0x0000},
113 {0x007b, 0x0000},
114 {0x007c, 0x0100},
115 {0x007e, 0x0000},
116 {0x0080, 0x0000},
117 {0x0081, 0x0000},
118 {0x0082, 0x0000},
119 {0x0083, 0x0000},
120 {0x0084, 0x0000},
121 {0x0085, 0x0000},
122 {0x0086, 0x0005},
123 {0x0087, 0x0000},
124 {0x0088, 0x0000},
125 {0x008c, 0x0003},
126 {0x008d, 0x0000},
127 {0x008e, 0x0060},
128 {0x008f, 0x1000},
129 {0x0091, 0x0c26},
130 {0x0092, 0x0073},
131 {0x0093, 0x0000},
132 {0x0094, 0x0080},
133 {0x0098, 0x0000},
134 {0x009a, 0x0000},
135 {0x009b, 0x0000},
136 {0x009c, 0x0000},
137 {0x009d, 0x0000},
138 {0x009e, 0x100c},
139 {0x009f, 0x0000},
140 {0x00a0, 0x0000},
141 {0x00a3, 0x0002},
142 {0x00a4, 0x0001},
143 {0x00ae, 0x2040},
144 {0x00af, 0x0000},
145 {0x00b6, 0x0000},
146 {0x00b7, 0x0000},
147 {0x00b8, 0x0000},
148 {0x00b9, 0x0002},
149 {0x00be, 0x0000},
150 {0x00c0, 0x0160},
151 {0x00c1, 0x82a0},
152 {0x00c2, 0x0000},
153 {0x00d0, 0x0000},
154 {0x00d1, 0x2244},
155 {0x00d2, 0x3300},
156 {0x00d3, 0x2200},
157 {0x00d4, 0x0000},
158 {0x00d9, 0x0009},
159 {0x00da, 0x0000},
160 {0x00db, 0x0000},
161 {0x00dc, 0x00c0},
162 {0x00dd, 0x2220},
163 {0x00de, 0x3131},
164 {0x00df, 0x3131},
165 {0x00e0, 0x3131},
166 {0x00e2, 0x0000},
167 {0x00e3, 0x4000},
168 {0x00e4, 0x0aa0},
169 {0x00e5, 0x3131},
170 {0x00e6, 0x3131},
171 {0x00e7, 0x3131},
172 {0x00e8, 0x3131},
173 {0x00ea, 0xb320},
174 {0x00eb, 0x0000},
175 {0x00f0, 0x0000},
176 {0x00f1, 0x00d0},
177 {0x00f2, 0x00d0},
178 {0x00f6, 0x0000},
179 {0x00fa, 0x0000},
180 {0x00fb, 0x0000},
181 {0x00fc, 0x0000},
182 {0x00fd, 0x0000},
183 {0x00fe, 0x10ec},
184 {0x00ff, 0x6530},
185 {0x0100, 0xa0a0},
186 {0x010b, 0x0000},
187 {0x010c, 0xae00},
188 {0x010d, 0xaaa0},
189 {0x010e, 0x8aa2},
190 {0x010f, 0x02a2},
191 {0x0110, 0xc000},
192 {0x0111, 0x04a2},
193 {0x0112, 0x2800},
194 {0x0113, 0x0000},
195 {0x0117, 0x0100},
196 {0x0125, 0x0410},
197 {0x0132, 0x6026},
198 {0x0136, 0x5555},
199 {0x0138, 0x3700},
200 {0x013a, 0x2000},
201 {0x013b, 0x2000},
202 {0x013c, 0x2005},
203 {0x013f, 0x0000},
204 {0x0142, 0x0000},
205 {0x0145, 0x0002},
206 {0x0146, 0x0000},
207 {0x0147, 0x0000},
208 {0x0148, 0x0000},
209 {0x0149, 0x0000},
210 {0x0150, 0x79a1},
211 {0x0151, 0x0000},
212 {0x0160, 0x4ec0},
213 {0x0161, 0x0080},
214 {0x0162, 0x0200},
215 {0x0163, 0x0800},
216 {0x0164, 0x0000},
217 {0x0165, 0x0000},
218 {0x0166, 0x0000},
219 {0x0167, 0x000f},
220 {0x0168, 0x000f},
221 {0x0169, 0x0021},
222 {0x0190, 0x413d},
223 {0x0194, 0x0000},
224 {0x0195, 0x0000},
225 {0x0197, 0x0022},
226 {0x0198, 0x0000},
227 {0x0199, 0x0000},
228 {0x01af, 0x0000},
229 {0x01b0, 0x0400},
230 {0x01b1, 0x0000},
231 {0x01b2, 0x0000},
232 {0x01b3, 0x0000},
233 {0x01b4, 0x0000},
234 {0x01b5, 0x0000},
235 {0x01b6, 0x01c3},
236 {0x01b7, 0x02a0},
237 {0x01b8, 0x03e9},
238 {0x01b9, 0x1389},
239 {0x01ba, 0xc351},
240 {0x01bb, 0x0009},
241 {0x01bc, 0x0018},
242 {0x01bd, 0x002a},
243 {0x01be, 0x004c},
244 {0x01bf, 0x0097},
245 {0x01c0, 0x433d},
246 {0x01c1, 0x2800},
247 {0x01c2, 0x0000},
248 {0x01c3, 0x0000},
249 {0x01c4, 0x0000},
250 {0x01c5, 0x0000},
251 {0x01c6, 0x0000},
252 {0x01c7, 0x0000},
253 {0x01c8, 0x40af},
254 {0x01c9, 0x0702},
255 {0x01ca, 0x0000},
256 {0x01cb, 0x0000},
257 {0x01cc, 0x5757},
258 {0x01cd, 0x5757},
259 {0x01ce, 0x5757},
260 {0x01cf, 0x5757},
261 {0x01d0, 0x5757},
262 {0x01d1, 0x5757},
263 {0x01d2, 0x5757},
264 {0x01d3, 0x5757},
265 {0x01d4, 0x5757},
266 {0x01d5, 0x5757},
267 {0x01d6, 0x0000},
268 {0x01d7, 0x0008},
269 {0x01d8, 0x0029},
270 {0x01d9, 0x3333},
271 {0x01da, 0x0000},
272 {0x01db, 0x0004},
273 {0x01dc, 0x0000},
274 {0x01de, 0x7c00},
275 {0x01df, 0x0320},
276 {0x01e0, 0x06a1},
277 {0x01e1, 0x0000},
278 {0x01e2, 0x0000},
279 {0x01e3, 0x0000},
280 {0x01e4, 0x0000},
281 {0x01e6, 0x0001},
282 {0x01e7, 0x0000},
283 {0x01e8, 0x0000},
284 {0x01ea, 0x0000},
285 {0x01eb, 0x0000},
286 {0x01ec, 0x0000},
287 {0x01ed, 0x0000},
288 {0x01ee, 0x0000},
289 {0x01ef, 0x0000},
290 {0x01f0, 0x0000},
291 {0x01f1, 0x0000},
292 {0x01f2, 0x0000},
293 {0x01f3, 0x0000},
294 {0x01f4, 0x0000},
295 {0x0210, 0x6297},
296 {0x0211, 0xa005},
297 {0x0212, 0x824c},
298 {0x0213, 0xf7ff},
299 {0x0214, 0xf24c},
300 {0x0215, 0x0102},
301 {0x0216, 0x00a3},
302 {0x0217, 0x0048},
303 {0x0218, 0xa2c0},
304 {0x0219, 0x0400},
305 {0x021a, 0x00c8},
306 {0x021b, 0x00c0},
307 {0x021c, 0x0000},
308 {0x0250, 0x4500},
309 {0x0251, 0x40b3},
310 {0x0252, 0x0000},
311 {0x0253, 0x0000},
312 {0x0254, 0x0000},
313 {0x0255, 0x0000},
314 {0x0256, 0x0000},
315 {0x0257, 0x0000},
316 {0x0258, 0x0000},
317 {0x0259, 0x0000},
318 {0x025a, 0x0005},
319 {0x0270, 0x0000},
320 {0x02ff, 0x0110},
321 {0x0300, 0x001f},
322 {0x0301, 0x032c},
323 {0x0302, 0x5f21},
324 {0x0303, 0x4000},
325 {0x0304, 0x4000},
326 {0x0305, 0x06d5},
327 {0x0306, 0x8000},
328 {0x0307, 0x0700},
329 {0x0310, 0x4560},
330 {0x0311, 0xa4a8},
331 {0x0312, 0x7418},
332 {0x0313, 0x0000},
333 {0x0314, 0x0006},
334 {0x0315, 0xffff},
335 {0x0316, 0xc400},
336 {0x0317, 0x0000},
337 {0x03c0, 0x7e00},
338 {0x03c1, 0x8000},
339 {0x03c2, 0x8000},
340 {0x03c3, 0x8000},
341 {0x03c4, 0x8000},
342 {0x03c5, 0x8000},
343 {0x03c6, 0x8000},
344 {0x03c7, 0x8000},
345 {0x03c8, 0x8000},
346 {0x03c9, 0x8000},
347 {0x03ca, 0x8000},
348 {0x03cb, 0x8000},
349 {0x03cc, 0x8000},
350 {0x03d0, 0x0000},
351 {0x03d1, 0x0000},
352 {0x03d2, 0x0000},
353 {0x03d3, 0x0000},
354 {0x03d4, 0x2000},
355 {0x03d5, 0x2000},
356 {0x03d6, 0x0000},
357 {0x03d7, 0x0000},
358 {0x03d8, 0x2000},
359 {0x03d9, 0x2000},
360 {0x03da, 0x2000},
361 {0x03db, 0x2000},
362 {0x03dc, 0x0000},
363 {0x03dd, 0x0000},
364 {0x03de, 0x0000},
365 {0x03df, 0x2000},
366 {0x03e0, 0x0000},
367 {0x03e1, 0x0000},
368 {0x03e2, 0x0000},
369 {0x03e3, 0x0000},
370 {0x03e4, 0x0000},
371 {0x03e5, 0x0000},
372 {0x03e6, 0x0000},
373 {0x03e7, 0x0000},
374 {0x03e8, 0x0000},
375 {0x03e9, 0x0000},
376 {0x03ea, 0x0000},
377 {0x03eb, 0x0000},
378 {0x03ec, 0x0000},
379 {0x03ed, 0x0000},
380 {0x03ee, 0x0000},
381 {0x03ef, 0x0000},
382 {0x03f0, 0x0800},
383 {0x03f1, 0x0800},
384 {0x03f2, 0x0800},
385 {0x03f3, 0x0800},
386 };
387
rt5668_volatile_register(struct device * dev,unsigned int reg)388 static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
389 {
390 switch (reg) {
391 case RT5668_RESET:
392 case RT5668_CBJ_CTRL_2:
393 case RT5668_INT_ST_1:
394 case RT5668_4BTN_IL_CMD_1:
395 case RT5668_AJD1_CTRL:
396 case RT5668_HP_CALIB_CTRL_1:
397 case RT5668_DEVICE_ID:
398 case RT5668_I2C_MODE:
399 case RT5668_HP_CALIB_CTRL_10:
400 case RT5668_EFUSE_CTRL_2:
401 case RT5668_JD_TOP_VC_VTRL:
402 case RT5668_HP_IMP_SENS_CTRL_19:
403 case RT5668_IL_CMD_1:
404 case RT5668_SAR_IL_CMD_2:
405 case RT5668_SAR_IL_CMD_4:
406 case RT5668_SAR_IL_CMD_10:
407 case RT5668_SAR_IL_CMD_11:
408 case RT5668_EFUSE_CTRL_6...RT5668_EFUSE_CTRL_11:
409 case RT5668_HP_CALIB_STA_1...RT5668_HP_CALIB_STA_11:
410 return true;
411 default:
412 return false;
413 }
414 }
415
rt5668_readable_register(struct device * dev,unsigned int reg)416 static bool rt5668_readable_register(struct device *dev, unsigned int reg)
417 {
418 switch (reg) {
419 case RT5668_RESET:
420 case RT5668_VERSION_ID:
421 case RT5668_VENDOR_ID:
422 case RT5668_DEVICE_ID:
423 case RT5668_HP_CTRL_1:
424 case RT5668_HP_CTRL_2:
425 case RT5668_HPL_GAIN:
426 case RT5668_HPR_GAIN:
427 case RT5668_I2C_CTRL:
428 case RT5668_CBJ_BST_CTRL:
429 case RT5668_CBJ_CTRL_1:
430 case RT5668_CBJ_CTRL_2:
431 case RT5668_CBJ_CTRL_3:
432 case RT5668_CBJ_CTRL_4:
433 case RT5668_CBJ_CTRL_5:
434 case RT5668_CBJ_CTRL_6:
435 case RT5668_CBJ_CTRL_7:
436 case RT5668_DAC1_DIG_VOL:
437 case RT5668_STO1_ADC_DIG_VOL:
438 case RT5668_STO1_ADC_BOOST:
439 case RT5668_HP_IMP_GAIN_1:
440 case RT5668_HP_IMP_GAIN_2:
441 case RT5668_SIDETONE_CTRL:
442 case RT5668_STO1_ADC_MIXER:
443 case RT5668_AD_DA_MIXER:
444 case RT5668_STO1_DAC_MIXER:
445 case RT5668_A_DAC1_MUX:
446 case RT5668_DIG_INF2_DATA:
447 case RT5668_REC_MIXER:
448 case RT5668_CAL_REC:
449 case RT5668_ALC_BACK_GAIN:
450 case RT5668_PWR_DIG_1:
451 case RT5668_PWR_DIG_2:
452 case RT5668_PWR_ANLG_1:
453 case RT5668_PWR_ANLG_2:
454 case RT5668_PWR_ANLG_3:
455 case RT5668_PWR_MIXER:
456 case RT5668_PWR_VOL:
457 case RT5668_CLK_DET:
458 case RT5668_RESET_LPF_CTRL:
459 case RT5668_RESET_HPF_CTRL:
460 case RT5668_DMIC_CTRL_1:
461 case RT5668_I2S1_SDP:
462 case RT5668_I2S2_SDP:
463 case RT5668_ADDA_CLK_1:
464 case RT5668_ADDA_CLK_2:
465 case RT5668_I2S1_F_DIV_CTRL_1:
466 case RT5668_I2S1_F_DIV_CTRL_2:
467 case RT5668_TDM_CTRL:
468 case RT5668_TDM_ADDA_CTRL_1:
469 case RT5668_TDM_ADDA_CTRL_2:
470 case RT5668_DATA_SEL_CTRL_1:
471 case RT5668_TDM_TCON_CTRL:
472 case RT5668_GLB_CLK:
473 case RT5668_PLL_CTRL_1:
474 case RT5668_PLL_CTRL_2:
475 case RT5668_PLL_TRACK_1:
476 case RT5668_PLL_TRACK_2:
477 case RT5668_PLL_TRACK_3:
478 case RT5668_PLL_TRACK_4:
479 case RT5668_PLL_TRACK_5:
480 case RT5668_PLL_TRACK_6:
481 case RT5668_PLL_TRACK_11:
482 case RT5668_SDW_REF_CLK:
483 case RT5668_DEPOP_1:
484 case RT5668_DEPOP_2:
485 case RT5668_HP_CHARGE_PUMP_1:
486 case RT5668_HP_CHARGE_PUMP_2:
487 case RT5668_MICBIAS_1:
488 case RT5668_MICBIAS_2:
489 case RT5668_PLL_TRACK_12:
490 case RT5668_PLL_TRACK_14:
491 case RT5668_PLL2_CTRL_1:
492 case RT5668_PLL2_CTRL_2:
493 case RT5668_PLL2_CTRL_3:
494 case RT5668_PLL2_CTRL_4:
495 case RT5668_RC_CLK_CTRL:
496 case RT5668_I2S_M_CLK_CTRL_1:
497 case RT5668_I2S2_F_DIV_CTRL_1:
498 case RT5668_I2S2_F_DIV_CTRL_2:
499 case RT5668_EQ_CTRL_1:
500 case RT5668_EQ_CTRL_2:
501 case RT5668_IRQ_CTRL_1:
502 case RT5668_IRQ_CTRL_2:
503 case RT5668_IRQ_CTRL_3:
504 case RT5668_IRQ_CTRL_4:
505 case RT5668_INT_ST_1:
506 case RT5668_GPIO_CTRL_1:
507 case RT5668_GPIO_CTRL_2:
508 case RT5668_GPIO_CTRL_3:
509 case RT5668_HP_AMP_DET_CTRL_1:
510 case RT5668_HP_AMP_DET_CTRL_2:
511 case RT5668_MID_HP_AMP_DET:
512 case RT5668_LOW_HP_AMP_DET:
513 case RT5668_DELAY_BUF_CTRL:
514 case RT5668_SV_ZCD_1:
515 case RT5668_SV_ZCD_2:
516 case RT5668_IL_CMD_1:
517 case RT5668_IL_CMD_2:
518 case RT5668_IL_CMD_3:
519 case RT5668_IL_CMD_4:
520 case RT5668_IL_CMD_5:
521 case RT5668_IL_CMD_6:
522 case RT5668_4BTN_IL_CMD_1:
523 case RT5668_4BTN_IL_CMD_2:
524 case RT5668_4BTN_IL_CMD_3:
525 case RT5668_4BTN_IL_CMD_4:
526 case RT5668_4BTN_IL_CMD_5:
527 case RT5668_4BTN_IL_CMD_6:
528 case RT5668_4BTN_IL_CMD_7:
529 case RT5668_ADC_STO1_HP_CTRL_1:
530 case RT5668_ADC_STO1_HP_CTRL_2:
531 case RT5668_AJD1_CTRL:
532 case RT5668_JD1_THD:
533 case RT5668_JD2_THD:
534 case RT5668_JD_CTRL_1:
535 case RT5668_DUMMY_1:
536 case RT5668_DUMMY_2:
537 case RT5668_DUMMY_3:
538 case RT5668_DAC_ADC_DIG_VOL1:
539 case RT5668_BIAS_CUR_CTRL_2:
540 case RT5668_BIAS_CUR_CTRL_3:
541 case RT5668_BIAS_CUR_CTRL_4:
542 case RT5668_BIAS_CUR_CTRL_5:
543 case RT5668_BIAS_CUR_CTRL_6:
544 case RT5668_BIAS_CUR_CTRL_7:
545 case RT5668_BIAS_CUR_CTRL_8:
546 case RT5668_BIAS_CUR_CTRL_9:
547 case RT5668_BIAS_CUR_CTRL_10:
548 case RT5668_VREF_REC_OP_FB_CAP_CTRL:
549 case RT5668_CHARGE_PUMP_1:
550 case RT5668_DIG_IN_CTRL_1:
551 case RT5668_PAD_DRIVING_CTRL:
552 case RT5668_SOFT_RAMP_DEPOP:
553 case RT5668_CHOP_DAC:
554 case RT5668_CHOP_ADC:
555 case RT5668_CALIB_ADC_CTRL:
556 case RT5668_VOL_TEST:
557 case RT5668_SPKVDD_DET_STA:
558 case RT5668_TEST_MODE_CTRL_1:
559 case RT5668_TEST_MODE_CTRL_2:
560 case RT5668_TEST_MODE_CTRL_3:
561 case RT5668_TEST_MODE_CTRL_4:
562 case RT5668_TEST_MODE_CTRL_5:
563 case RT5668_PLL1_INTERNAL:
564 case RT5668_PLL2_INTERNAL:
565 case RT5668_STO_NG2_CTRL_1:
566 case RT5668_STO_NG2_CTRL_2:
567 case RT5668_STO_NG2_CTRL_3:
568 case RT5668_STO_NG2_CTRL_4:
569 case RT5668_STO_NG2_CTRL_5:
570 case RT5668_STO_NG2_CTRL_6:
571 case RT5668_STO_NG2_CTRL_7:
572 case RT5668_STO_NG2_CTRL_8:
573 case RT5668_STO_NG2_CTRL_9:
574 case RT5668_STO_NG2_CTRL_10:
575 case RT5668_STO1_DAC_SIL_DET:
576 case RT5668_SIL_PSV_CTRL1:
577 case RT5668_SIL_PSV_CTRL2:
578 case RT5668_SIL_PSV_CTRL3:
579 case RT5668_SIL_PSV_CTRL4:
580 case RT5668_SIL_PSV_CTRL5:
581 case RT5668_HP_IMP_SENS_CTRL_01:
582 case RT5668_HP_IMP_SENS_CTRL_02:
583 case RT5668_HP_IMP_SENS_CTRL_03:
584 case RT5668_HP_IMP_SENS_CTRL_04:
585 case RT5668_HP_IMP_SENS_CTRL_05:
586 case RT5668_HP_IMP_SENS_CTRL_06:
587 case RT5668_HP_IMP_SENS_CTRL_07:
588 case RT5668_HP_IMP_SENS_CTRL_08:
589 case RT5668_HP_IMP_SENS_CTRL_09:
590 case RT5668_HP_IMP_SENS_CTRL_10:
591 case RT5668_HP_IMP_SENS_CTRL_11:
592 case RT5668_HP_IMP_SENS_CTRL_12:
593 case RT5668_HP_IMP_SENS_CTRL_13:
594 case RT5668_HP_IMP_SENS_CTRL_14:
595 case RT5668_HP_IMP_SENS_CTRL_15:
596 case RT5668_HP_IMP_SENS_CTRL_16:
597 case RT5668_HP_IMP_SENS_CTRL_17:
598 case RT5668_HP_IMP_SENS_CTRL_18:
599 case RT5668_HP_IMP_SENS_CTRL_19:
600 case RT5668_HP_IMP_SENS_CTRL_20:
601 case RT5668_HP_IMP_SENS_CTRL_21:
602 case RT5668_HP_IMP_SENS_CTRL_22:
603 case RT5668_HP_IMP_SENS_CTRL_23:
604 case RT5668_HP_IMP_SENS_CTRL_24:
605 case RT5668_HP_IMP_SENS_CTRL_25:
606 case RT5668_HP_IMP_SENS_CTRL_26:
607 case RT5668_HP_IMP_SENS_CTRL_27:
608 case RT5668_HP_IMP_SENS_CTRL_28:
609 case RT5668_HP_IMP_SENS_CTRL_29:
610 case RT5668_HP_IMP_SENS_CTRL_30:
611 case RT5668_HP_IMP_SENS_CTRL_31:
612 case RT5668_HP_IMP_SENS_CTRL_32:
613 case RT5668_HP_IMP_SENS_CTRL_33:
614 case RT5668_HP_IMP_SENS_CTRL_34:
615 case RT5668_HP_IMP_SENS_CTRL_35:
616 case RT5668_HP_IMP_SENS_CTRL_36:
617 case RT5668_HP_IMP_SENS_CTRL_37:
618 case RT5668_HP_IMP_SENS_CTRL_38:
619 case RT5668_HP_IMP_SENS_CTRL_39:
620 case RT5668_HP_IMP_SENS_CTRL_40:
621 case RT5668_HP_IMP_SENS_CTRL_41:
622 case RT5668_HP_IMP_SENS_CTRL_42:
623 case RT5668_HP_IMP_SENS_CTRL_43:
624 case RT5668_HP_LOGIC_CTRL_1:
625 case RT5668_HP_LOGIC_CTRL_2:
626 case RT5668_HP_LOGIC_CTRL_3:
627 case RT5668_HP_CALIB_CTRL_1:
628 case RT5668_HP_CALIB_CTRL_2:
629 case RT5668_HP_CALIB_CTRL_3:
630 case RT5668_HP_CALIB_CTRL_4:
631 case RT5668_HP_CALIB_CTRL_5:
632 case RT5668_HP_CALIB_CTRL_6:
633 case RT5668_HP_CALIB_CTRL_7:
634 case RT5668_HP_CALIB_CTRL_9:
635 case RT5668_HP_CALIB_CTRL_10:
636 case RT5668_HP_CALIB_CTRL_11:
637 case RT5668_HP_CALIB_STA_1:
638 case RT5668_HP_CALIB_STA_2:
639 case RT5668_HP_CALIB_STA_3:
640 case RT5668_HP_CALIB_STA_4:
641 case RT5668_HP_CALIB_STA_5:
642 case RT5668_HP_CALIB_STA_6:
643 case RT5668_HP_CALIB_STA_7:
644 case RT5668_HP_CALIB_STA_8:
645 case RT5668_HP_CALIB_STA_9:
646 case RT5668_HP_CALIB_STA_10:
647 case RT5668_HP_CALIB_STA_11:
648 case RT5668_SAR_IL_CMD_1:
649 case RT5668_SAR_IL_CMD_2:
650 case RT5668_SAR_IL_CMD_3:
651 case RT5668_SAR_IL_CMD_4:
652 case RT5668_SAR_IL_CMD_5:
653 case RT5668_SAR_IL_CMD_6:
654 case RT5668_SAR_IL_CMD_7:
655 case RT5668_SAR_IL_CMD_8:
656 case RT5668_SAR_IL_CMD_9:
657 case RT5668_SAR_IL_CMD_10:
658 case RT5668_SAR_IL_CMD_11:
659 case RT5668_SAR_IL_CMD_12:
660 case RT5668_SAR_IL_CMD_13:
661 case RT5668_EFUSE_CTRL_1:
662 case RT5668_EFUSE_CTRL_2:
663 case RT5668_EFUSE_CTRL_3:
664 case RT5668_EFUSE_CTRL_4:
665 case RT5668_EFUSE_CTRL_5:
666 case RT5668_EFUSE_CTRL_6:
667 case RT5668_EFUSE_CTRL_7:
668 case RT5668_EFUSE_CTRL_8:
669 case RT5668_EFUSE_CTRL_9:
670 case RT5668_EFUSE_CTRL_10:
671 case RT5668_EFUSE_CTRL_11:
672 case RT5668_JD_TOP_VC_VTRL:
673 case RT5668_DRC1_CTRL_0:
674 case RT5668_DRC1_CTRL_1:
675 case RT5668_DRC1_CTRL_2:
676 case RT5668_DRC1_CTRL_3:
677 case RT5668_DRC1_CTRL_4:
678 case RT5668_DRC1_CTRL_5:
679 case RT5668_DRC1_CTRL_6:
680 case RT5668_DRC1_HARD_LMT_CTRL_1:
681 case RT5668_DRC1_HARD_LMT_CTRL_2:
682 case RT5668_DRC1_PRIV_1:
683 case RT5668_DRC1_PRIV_2:
684 case RT5668_DRC1_PRIV_3:
685 case RT5668_DRC1_PRIV_4:
686 case RT5668_DRC1_PRIV_5:
687 case RT5668_DRC1_PRIV_6:
688 case RT5668_DRC1_PRIV_7:
689 case RT5668_DRC1_PRIV_8:
690 case RT5668_EQ_AUTO_RCV_CTRL1:
691 case RT5668_EQ_AUTO_RCV_CTRL2:
692 case RT5668_EQ_AUTO_RCV_CTRL3:
693 case RT5668_EQ_AUTO_RCV_CTRL4:
694 case RT5668_EQ_AUTO_RCV_CTRL5:
695 case RT5668_EQ_AUTO_RCV_CTRL6:
696 case RT5668_EQ_AUTO_RCV_CTRL7:
697 case RT5668_EQ_AUTO_RCV_CTRL8:
698 case RT5668_EQ_AUTO_RCV_CTRL9:
699 case RT5668_EQ_AUTO_RCV_CTRL10:
700 case RT5668_EQ_AUTO_RCV_CTRL11:
701 case RT5668_EQ_AUTO_RCV_CTRL12:
702 case RT5668_EQ_AUTO_RCV_CTRL13:
703 case RT5668_ADC_L_EQ_LPF1_A1:
704 case RT5668_R_EQ_LPF1_A1:
705 case RT5668_L_EQ_LPF1_H0:
706 case RT5668_R_EQ_LPF1_H0:
707 case RT5668_L_EQ_BPF1_A1:
708 case RT5668_R_EQ_BPF1_A1:
709 case RT5668_L_EQ_BPF1_A2:
710 case RT5668_R_EQ_BPF1_A2:
711 case RT5668_L_EQ_BPF1_H0:
712 case RT5668_R_EQ_BPF1_H0:
713 case RT5668_L_EQ_BPF2_A1:
714 case RT5668_R_EQ_BPF2_A1:
715 case RT5668_L_EQ_BPF2_A2:
716 case RT5668_R_EQ_BPF2_A2:
717 case RT5668_L_EQ_BPF2_H0:
718 case RT5668_R_EQ_BPF2_H0:
719 case RT5668_L_EQ_BPF3_A1:
720 case RT5668_R_EQ_BPF3_A1:
721 case RT5668_L_EQ_BPF3_A2:
722 case RT5668_R_EQ_BPF3_A2:
723 case RT5668_L_EQ_BPF3_H0:
724 case RT5668_R_EQ_BPF3_H0:
725 case RT5668_L_EQ_BPF4_A1:
726 case RT5668_R_EQ_BPF4_A1:
727 case RT5668_L_EQ_BPF4_A2:
728 case RT5668_R_EQ_BPF4_A2:
729 case RT5668_L_EQ_BPF4_H0:
730 case RT5668_R_EQ_BPF4_H0:
731 case RT5668_L_EQ_HPF1_A1:
732 case RT5668_R_EQ_HPF1_A1:
733 case RT5668_L_EQ_HPF1_H0:
734 case RT5668_R_EQ_HPF1_H0:
735 case RT5668_L_EQ_PRE_VOL:
736 case RT5668_R_EQ_PRE_VOL:
737 case RT5668_L_EQ_POST_VOL:
738 case RT5668_R_EQ_POST_VOL:
739 case RT5668_I2C_MODE:
740 return true;
741 default:
742 return false;
743 }
744 }
745
746 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
747 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
748 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
749 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
750
751 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
752 static const DECLARE_TLV_DB_RANGE(bst_tlv,
753 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
754 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
755 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
756 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
757 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
758 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
759 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
760 );
761
762 /* Interface data select */
763 static const char * const rt5668_data_select[] = {
764 "L/R", "R/L", "L/L", "R/R"
765 };
766
767 static SOC_ENUM_SINGLE_DECL(rt5668_if2_adc_enum,
768 RT5668_DIG_INF2_DATA, RT5668_IF2_ADC_SEL_SFT, rt5668_data_select);
769
770 static SOC_ENUM_SINGLE_DECL(rt5668_if1_01_adc_enum,
771 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC1_SEL_SFT, rt5668_data_select);
772
773 static SOC_ENUM_SINGLE_DECL(rt5668_if1_23_adc_enum,
774 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC2_SEL_SFT, rt5668_data_select);
775
776 static SOC_ENUM_SINGLE_DECL(rt5668_if1_45_adc_enum,
777 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC3_SEL_SFT, rt5668_data_select);
778
779 static SOC_ENUM_SINGLE_DECL(rt5668_if1_67_adc_enum,
780 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC4_SEL_SFT, rt5668_data_select);
781
782 static const struct snd_kcontrol_new rt5668_if2_adc_swap_mux =
783 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5668_if2_adc_enum);
784
785 static const struct snd_kcontrol_new rt5668_if1_01_adc_swap_mux =
786 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5668_if1_01_adc_enum);
787
788 static const struct snd_kcontrol_new rt5668_if1_23_adc_swap_mux =
789 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5668_if1_23_adc_enum);
790
791 static const struct snd_kcontrol_new rt5668_if1_45_adc_swap_mux =
792 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5668_if1_45_adc_enum);
793
794 static const struct snd_kcontrol_new rt5668_if1_67_adc_swap_mux =
795 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5668_if1_67_adc_enum);
796
rt5668_reset(struct regmap * regmap)797 static void rt5668_reset(struct regmap *regmap)
798 {
799 regmap_write(regmap, RT5668_RESET, 0);
800 regmap_write(regmap, RT5668_I2C_MODE, 1);
801 }
802
rt5668_button_detect(struct snd_soc_component * component)803 static int rt5668_button_detect(struct snd_soc_component *component)
804 {
805 int btn_type, val;
806
807 val = snd_soc_component_read(component, RT5668_4BTN_IL_CMD_1);
808 btn_type = val & 0xfff0;
809 snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val);
810 pr_debug("%s btn_type=%x\n", __func__, btn_type);
811
812 return btn_type;
813 }
814
rt5668_enable_push_button_irq(struct snd_soc_component * component,bool enable)815 static void rt5668_enable_push_button_irq(struct snd_soc_component *component,
816 bool enable)
817 {
818 if (enable) {
819 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
820 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_EN);
821 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
822 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_BTN);
823 snd_soc_component_write(component, RT5668_IL_CMD_1, 0x0040);
824 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
825 RT5668_4BTN_IL_MASK | RT5668_4BTN_IL_RST_MASK,
826 RT5668_4BTN_IL_EN | RT5668_4BTN_IL_NOR);
827 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
828 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_EN);
829 } else {
830 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
831 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_DIS);
832 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
833 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_DIS);
834 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
835 RT5668_4BTN_IL_MASK, RT5668_4BTN_IL_DIS);
836 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
837 RT5668_4BTN_IL_RST_MASK, RT5668_4BTN_IL_RST);
838 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
839 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_TYPE);
840 }
841 }
842
843 /**
844 * rt5668_headset_detect - Detect headset.
845 * @component: SoC audio component device.
846 * @jack_insert: Jack insert or not.
847 *
848 * Detect whether is headset or not when jack inserted.
849 *
850 * Returns detect status.
851 */
rt5668_headset_detect(struct snd_soc_component * component,int jack_insert)852 static int rt5668_headset_detect(struct snd_soc_component *component,
853 int jack_insert)
854 {
855 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
856 struct snd_soc_dapm_context *dapm =
857 snd_soc_component_get_dapm(component);
858 unsigned int val, count;
859
860 if (jack_insert) {
861 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
862 snd_soc_dapm_sync(dapm);
863 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
864 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_HIGH);
865
866 count = 0;
867 val = snd_soc_component_read(component, RT5668_CBJ_CTRL_2)
868 & RT5668_JACK_TYPE_MASK;
869 while (val == 0 && count < 50) {
870 usleep_range(10000, 15000);
871 val = snd_soc_component_read(component,
872 RT5668_CBJ_CTRL_2) & RT5668_JACK_TYPE_MASK;
873 count++;
874 }
875
876 switch (val) {
877 case 0x1:
878 case 0x2:
879 rt5668->jack_type = SND_JACK_HEADSET;
880 rt5668_enable_push_button_irq(component, true);
881 break;
882 default:
883 rt5668->jack_type = SND_JACK_HEADPHONE;
884 }
885
886 } else {
887 rt5668_enable_push_button_irq(component, false);
888 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
889 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_LOW);
890 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
891 snd_soc_dapm_sync(dapm);
892
893 rt5668->jack_type = 0;
894 }
895
896 dev_dbg(component->dev, "jack_type = %d\n", rt5668->jack_type);
897 return rt5668->jack_type;
898 }
899
rt5668_irq(int irq,void * data)900 static irqreturn_t rt5668_irq(int irq, void *data)
901 {
902 struct rt5668_priv *rt5668 = data;
903
904 mod_delayed_work(system_power_efficient_wq,
905 &rt5668->jack_detect_work, msecs_to_jiffies(250));
906
907 return IRQ_HANDLED;
908 }
909
rt5668_jd_check_handler(struct work_struct * work)910 static void rt5668_jd_check_handler(struct work_struct *work)
911 {
912 struct rt5668_priv *rt5668 = container_of(work, struct rt5668_priv,
913 jd_check_work.work);
914
915 if (snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL)
916 & RT5668_JDH_RS_MASK) {
917 /* jack out */
918 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
919
920 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
921 SND_JACK_HEADSET |
922 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
923 SND_JACK_BTN_2 | SND_JACK_BTN_3);
924 } else {
925 schedule_delayed_work(&rt5668->jd_check_work, 500);
926 }
927 }
928
rt5668_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)929 static int rt5668_set_jack_detect(struct snd_soc_component *component,
930 struct snd_soc_jack *hs_jack, void *data)
931 {
932 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
933
934 switch (rt5668->pdata.jd_src) {
935 case RT5668_JD1:
936 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_2,
937 RT5668_EXT_JD_SRC, RT5668_EXT_JD_SRC_MANUAL);
938 snd_soc_component_write(component, RT5668_CBJ_CTRL_1, 0xd002);
939 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_3,
940 RT5668_CBJ_IN_BUF_EN, RT5668_CBJ_IN_BUF_EN);
941 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
942 RT5668_SAR_POW_MASK, RT5668_SAR_POW_EN);
943 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
944 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_IRQ);
945 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
946 RT5668_POW_IRQ | RT5668_POW_JDH |
947 RT5668_POW_ANA, RT5668_POW_IRQ |
948 RT5668_POW_JDH | RT5668_POW_ANA);
949 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_2,
950 RT5668_PWR_JDH | RT5668_PWR_JDL,
951 RT5668_PWR_JDH | RT5668_PWR_JDL);
952 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
953 RT5668_JD1_EN_MASK | RT5668_JD1_POL_MASK,
954 RT5668_JD1_EN | RT5668_JD1_POL_NOR);
955 mod_delayed_work(system_power_efficient_wq,
956 &rt5668->jack_detect_work, msecs_to_jiffies(250));
957 break;
958
959 case RT5668_JD_NULL:
960 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
961 RT5668_JD1_EN_MASK, RT5668_JD1_DIS);
962 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
963 RT5668_POW_JDH | RT5668_POW_JDL, 0);
964 break;
965
966 default:
967 dev_warn(component->dev, "Wrong JD source\n");
968 break;
969 }
970
971 rt5668->hs_jack = hs_jack;
972
973 return 0;
974 }
975
rt5668_jack_detect_handler(struct work_struct * work)976 static void rt5668_jack_detect_handler(struct work_struct *work)
977 {
978 struct rt5668_priv *rt5668 =
979 container_of(work, struct rt5668_priv, jack_detect_work.work);
980 int val, btn_type;
981
982 if (!rt5668->component ||
983 !snd_soc_card_is_instantiated(rt5668->component->card)) {
984 /* card not yet ready, try later */
985 mod_delayed_work(system_power_efficient_wq,
986 &rt5668->jack_detect_work, msecs_to_jiffies(15));
987 return;
988 }
989
990 mutex_lock(&rt5668->calibrate_mutex);
991
992 val = snd_soc_component_read(rt5668->component, RT5668_AJD1_CTRL)
993 & RT5668_JDH_RS_MASK;
994 if (!val) {
995 /* jack in */
996 if (rt5668->jack_type == 0) {
997 /* jack was out, report jack type */
998 rt5668->jack_type =
999 rt5668_headset_detect(rt5668->component, 1);
1000 } else {
1001 /* jack is already in, report button event */
1002 rt5668->jack_type = SND_JACK_HEADSET;
1003 btn_type = rt5668_button_detect(rt5668->component);
1004 /**
1005 * rt5668 can report three kinds of button behavior,
1006 * one click, double click and hold. However,
1007 * currently we will report button pressed/released
1008 * event. So all the three button behaviors are
1009 * treated as button pressed.
1010 */
1011 switch (btn_type) {
1012 case 0x8000:
1013 case 0x4000:
1014 case 0x2000:
1015 rt5668->jack_type |= SND_JACK_BTN_0;
1016 break;
1017 case 0x1000:
1018 case 0x0800:
1019 case 0x0400:
1020 rt5668->jack_type |= SND_JACK_BTN_1;
1021 break;
1022 case 0x0200:
1023 case 0x0100:
1024 case 0x0080:
1025 rt5668->jack_type |= SND_JACK_BTN_2;
1026 break;
1027 case 0x0040:
1028 case 0x0020:
1029 case 0x0010:
1030 rt5668->jack_type |= SND_JACK_BTN_3;
1031 break;
1032 case 0x0000: /* unpressed */
1033 break;
1034 default:
1035 btn_type = 0;
1036 dev_err(rt5668->component->dev,
1037 "Unexpected button code 0x%04x\n",
1038 btn_type);
1039 break;
1040 }
1041 }
1042 } else {
1043 /* jack out */
1044 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
1045 }
1046
1047 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
1048 SND_JACK_HEADSET |
1049 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1050 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1051
1052 if (rt5668->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1053 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1054 schedule_delayed_work(&rt5668->jd_check_work, 0);
1055 else
1056 cancel_delayed_work_sync(&rt5668->jd_check_work);
1057
1058 mutex_unlock(&rt5668->calibrate_mutex);
1059 }
1060
1061 static const struct snd_kcontrol_new rt5668_snd_controls[] = {
1062 /* Headphone Output Volume */
1063 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5668_HPL_GAIN,
1064 RT5668_HPR_GAIN, RT5668_G_HP_SFT, 15, 1, hp_vol_tlv),
1065
1066 /* DAC Digital Volume */
1067 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5668_DAC1_DIG_VOL,
1068 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 175, 0, dac_vol_tlv),
1069
1070 /* IN Boost Volume */
1071 SOC_SINGLE_TLV("CBJ Boost Volume", RT5668_CBJ_BST_CTRL,
1072 RT5668_BST_CBJ_SFT, 8, 0, bst_tlv),
1073
1074 /* ADC Digital Volume Control */
1075 SOC_DOUBLE("STO1 ADC Capture Switch", RT5668_STO1_ADC_DIG_VOL,
1076 RT5668_L_MUTE_SFT, RT5668_R_MUTE_SFT, 1, 1),
1077 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5668_STO1_ADC_DIG_VOL,
1078 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 127, 0, adc_vol_tlv),
1079
1080 /* ADC Boost Volume Control */
1081 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5668_STO1_ADC_BOOST,
1082 RT5668_STO1_ADC_L_BST_SFT, RT5668_STO1_ADC_R_BST_SFT,
1083 3, 0, adc_bst_tlv),
1084 };
1085
1086
rt5668_div_sel(struct rt5668_priv * rt5668,int target,const int div[],int size)1087 static int rt5668_div_sel(struct rt5668_priv *rt5668,
1088 int target, const int div[], int size)
1089 {
1090 int i;
1091
1092 if (rt5668->sysclk < target) {
1093 pr_err("sysclk rate %d is too low\n",
1094 rt5668->sysclk);
1095 return 0;
1096 }
1097
1098 for (i = 0; i < size - 1; i++) {
1099 pr_info("div[%d]=%d\n", i, div[i]);
1100 if (target * div[i] == rt5668->sysclk)
1101 return i;
1102 if (target * div[i + 1] > rt5668->sysclk) {
1103 pr_err("can't find div for sysclk %d\n",
1104 rt5668->sysclk);
1105 return i;
1106 }
1107 }
1108
1109 if (target * div[i] < rt5668->sysclk)
1110 pr_err("sysclk rate %d is too high\n",
1111 rt5668->sysclk);
1112
1113 return size - 1;
1114
1115 }
1116
1117 /**
1118 * set_dmic_clk - Set parameter of dmic.
1119 *
1120 * @w: DAPM widget.
1121 * @kcontrol: The kcontrol of this widget.
1122 * @event: Event id.
1123 *
1124 * Choose dmic clock between 1MHz and 3MHz.
1125 * It is better for clock to approximate 3MHz.
1126 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1127 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1128 struct snd_kcontrol *kcontrol, int event)
1129 {
1130 struct snd_soc_component *component =
1131 snd_soc_dapm_to_component(w->dapm);
1132 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1133 int idx;
1134 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1135
1136 idx = rt5668_div_sel(rt5668, 1500000, div, ARRAY_SIZE(div));
1137
1138 snd_soc_component_update_bits(component, RT5668_DMIC_CTRL_1,
1139 RT5668_DMIC_CLK_MASK, idx << RT5668_DMIC_CLK_SFT);
1140
1141 return 0;
1142 }
1143
set_filter_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1144 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1145 struct snd_kcontrol *kcontrol, int event)
1146 {
1147 struct snd_soc_component *component =
1148 snd_soc_dapm_to_component(w->dapm);
1149 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1150 int ref, val, reg, idx;
1151 static const int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1152
1153 val = snd_soc_component_read(component, RT5668_GPIO_CTRL_1) &
1154 RT5668_GP4_PIN_MASK;
1155 if (w->shift == RT5668_PWR_ADC_S1F_BIT &&
1156 val == RT5668_GP4_PIN_ADCDAT2)
1157 ref = 256 * rt5668->lrck[RT5668_AIF2];
1158 else
1159 ref = 256 * rt5668->lrck[RT5668_AIF1];
1160
1161 idx = rt5668_div_sel(rt5668, ref, div, ARRAY_SIZE(div));
1162
1163 if (w->shift == RT5668_PWR_ADC_S1F_BIT)
1164 reg = RT5668_PLL_TRACK_3;
1165 else
1166 reg = RT5668_PLL_TRACK_2;
1167
1168 snd_soc_component_update_bits(component, reg,
1169 RT5668_FILTER_CLK_SEL_MASK, idx << RT5668_FILTER_CLK_SEL_SFT);
1170
1171 return 0;
1172 }
1173
is_sys_clk_from_pll1(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1174 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1175 struct snd_soc_dapm_widget *sink)
1176 {
1177 unsigned int val;
1178 struct snd_soc_component *component =
1179 snd_soc_dapm_to_component(w->dapm);
1180
1181 val = snd_soc_component_read(component, RT5668_GLB_CLK);
1182 val &= RT5668_SCLK_SRC_MASK;
1183 if (val == RT5668_SCLK_SRC_PLL1)
1184 return 1;
1185 else
1186 return 0;
1187 }
1188
is_using_asrc(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1189 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1190 struct snd_soc_dapm_widget *sink)
1191 {
1192 unsigned int reg, shift, val;
1193 struct snd_soc_component *component =
1194 snd_soc_dapm_to_component(w->dapm);
1195
1196 switch (w->shift) {
1197 case RT5668_ADC_STO1_ASRC_SFT:
1198 reg = RT5668_PLL_TRACK_3;
1199 shift = RT5668_FILTER_CLK_SEL_SFT;
1200 break;
1201 case RT5668_DAC_STO1_ASRC_SFT:
1202 reg = RT5668_PLL_TRACK_2;
1203 shift = RT5668_FILTER_CLK_SEL_SFT;
1204 break;
1205 default:
1206 return 0;
1207 }
1208
1209 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1210 switch (val) {
1211 case RT5668_CLK_SEL_I2S1_ASRC:
1212 case RT5668_CLK_SEL_I2S2_ASRC:
1213 return 1;
1214 default:
1215 return 0;
1216 }
1217
1218 }
1219
1220 /* Digital Mixer */
1221 static const struct snd_kcontrol_new rt5668_sto1_adc_l_mix[] = {
1222 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
1223 RT5668_M_STO1_ADC_L1_SFT, 1, 1),
1224 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
1225 RT5668_M_STO1_ADC_L2_SFT, 1, 1),
1226 };
1227
1228 static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
1229 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
1230 RT5668_M_STO1_ADC_R1_SFT, 1, 1),
1231 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
1232 RT5668_M_STO1_ADC_R2_SFT, 1, 1),
1233 };
1234
1235 static const struct snd_kcontrol_new rt5668_dac_l_mix[] = {
1236 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
1237 RT5668_M_ADCMIX_L_SFT, 1, 1),
1238 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
1239 RT5668_M_DAC1_L_SFT, 1, 1),
1240 };
1241
1242 static const struct snd_kcontrol_new rt5668_dac_r_mix[] = {
1243 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
1244 RT5668_M_ADCMIX_R_SFT, 1, 1),
1245 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
1246 RT5668_M_DAC1_R_SFT, 1, 1),
1247 };
1248
1249 static const struct snd_kcontrol_new rt5668_sto1_dac_l_mix[] = {
1250 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
1251 RT5668_M_DAC_L1_STO_L_SFT, 1, 1),
1252 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
1253 RT5668_M_DAC_R1_STO_L_SFT, 1, 1),
1254 };
1255
1256 static const struct snd_kcontrol_new rt5668_sto1_dac_r_mix[] = {
1257 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
1258 RT5668_M_DAC_L1_STO_R_SFT, 1, 1),
1259 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
1260 RT5668_M_DAC_R1_STO_R_SFT, 1, 1),
1261 };
1262
1263 /* Analog Input Mixer */
1264 static const struct snd_kcontrol_new rt5668_rec1_l_mix[] = {
1265 SOC_DAPM_SINGLE("CBJ Switch", RT5668_REC_MIXER,
1266 RT5668_M_CBJ_RM1_L_SFT, 1, 1),
1267 };
1268
1269 /* STO1 ADC1 Source */
1270 /* MX-26 [13] [5] */
1271 static const char * const rt5668_sto1_adc1_src[] = {
1272 "DAC MIX", "ADC"
1273 };
1274
1275 static SOC_ENUM_SINGLE_DECL(
1276 rt5668_sto1_adc1l_enum, RT5668_STO1_ADC_MIXER,
1277 RT5668_STO1_ADC1L_SRC_SFT, rt5668_sto1_adc1_src);
1278
1279 static const struct snd_kcontrol_new rt5668_sto1_adc1l_mux =
1280 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1l_enum);
1281
1282 static SOC_ENUM_SINGLE_DECL(
1283 rt5668_sto1_adc1r_enum, RT5668_STO1_ADC_MIXER,
1284 RT5668_STO1_ADC1R_SRC_SFT, rt5668_sto1_adc1_src);
1285
1286 static const struct snd_kcontrol_new rt5668_sto1_adc1r_mux =
1287 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1r_enum);
1288
1289 /* STO1 ADC Source */
1290 /* MX-26 [11:10] [3:2] */
1291 static const char * const rt5668_sto1_adc_src[] = {
1292 "ADC1 L", "ADC1 R"
1293 };
1294
1295 static SOC_ENUM_SINGLE_DECL(
1296 rt5668_sto1_adcl_enum, RT5668_STO1_ADC_MIXER,
1297 RT5668_STO1_ADCL_SRC_SFT, rt5668_sto1_adc_src);
1298
1299 static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
1300 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5668_sto1_adcl_enum);
1301
1302 static SOC_ENUM_SINGLE_DECL(
1303 rt5668_sto1_adcr_enum, RT5668_STO1_ADC_MIXER,
1304 RT5668_STO1_ADCR_SRC_SFT, rt5668_sto1_adc_src);
1305
1306 static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
1307 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5668_sto1_adcr_enum);
1308
1309 /* STO1 ADC2 Source */
1310 /* MX-26 [12] [4] */
1311 static const char * const rt5668_sto1_adc2_src[] = {
1312 "DAC MIX", "DMIC"
1313 };
1314
1315 static SOC_ENUM_SINGLE_DECL(
1316 rt5668_sto1_adc2l_enum, RT5668_STO1_ADC_MIXER,
1317 RT5668_STO1_ADC2L_SRC_SFT, rt5668_sto1_adc2_src);
1318
1319 static const struct snd_kcontrol_new rt5668_sto1_adc2l_mux =
1320 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5668_sto1_adc2l_enum);
1321
1322 static SOC_ENUM_SINGLE_DECL(
1323 rt5668_sto1_adc2r_enum, RT5668_STO1_ADC_MIXER,
1324 RT5668_STO1_ADC2R_SRC_SFT, rt5668_sto1_adc2_src);
1325
1326 static const struct snd_kcontrol_new rt5668_sto1_adc2r_mux =
1327 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5668_sto1_adc2r_enum);
1328
1329 /* MX-79 [6:4] I2S1 ADC data location */
1330 static const unsigned int rt5668_if1_adc_slot_values[] = {
1331 0,
1332 2,
1333 4,
1334 6,
1335 };
1336
1337 static const char * const rt5668_if1_adc_slot_src[] = {
1338 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1339 };
1340
1341 static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_if1_adc_slot_enum,
1342 RT5668_TDM_CTRL, RT5668_TDM_ADC_LCA_SFT, RT5668_TDM_ADC_LCA_MASK,
1343 rt5668_if1_adc_slot_src, rt5668_if1_adc_slot_values);
1344
1345 static const struct snd_kcontrol_new rt5668_if1_adc_slot_mux =
1346 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5668_if1_adc_slot_enum);
1347
1348 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1349 /* MX-2B [4], MX-2B [0]*/
1350 static const char * const rt5668_alg_dac1_src[] = {
1351 "Stereo1 DAC Mixer", "DAC1"
1352 };
1353
1354 static SOC_ENUM_SINGLE_DECL(
1355 rt5668_alg_dac_l1_enum, RT5668_A_DAC1_MUX,
1356 RT5668_A_DACL1_SFT, rt5668_alg_dac1_src);
1357
1358 static const struct snd_kcontrol_new rt5668_alg_dac_l1_mux =
1359 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5668_alg_dac_l1_enum);
1360
1361 static SOC_ENUM_SINGLE_DECL(
1362 rt5668_alg_dac_r1_enum, RT5668_A_DAC1_MUX,
1363 RT5668_A_DACR1_SFT, rt5668_alg_dac1_src);
1364
1365 static const struct snd_kcontrol_new rt5668_alg_dac_r1_mux =
1366 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5668_alg_dac_r1_enum);
1367
1368 /* Out Switch */
1369 static const struct snd_kcontrol_new hpol_switch =
1370 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
1371 RT5668_L_MUTE_SFT, 1, 1);
1372 static const struct snd_kcontrol_new hpor_switch =
1373 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
1374 RT5668_R_MUTE_SFT, 1, 1);
1375
rt5668_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1376 static int rt5668_hp_event(struct snd_soc_dapm_widget *w,
1377 struct snd_kcontrol *kcontrol, int event)
1378 {
1379 struct snd_soc_component *component =
1380 snd_soc_dapm_to_component(w->dapm);
1381
1382 switch (event) {
1383 case SND_SOC_DAPM_PRE_PMU:
1384 snd_soc_component_write(component,
1385 RT5668_HP_LOGIC_CTRL_2, 0x0012);
1386 snd_soc_component_write(component,
1387 RT5668_HP_CTRL_2, 0x6000);
1388 snd_soc_component_update_bits(component, RT5668_STO_NG2_CTRL_1,
1389 RT5668_NG2_EN_MASK, RT5668_NG2_EN);
1390 snd_soc_component_update_bits(component,
1391 RT5668_DEPOP_1, 0x60, 0x60);
1392 break;
1393
1394 case SND_SOC_DAPM_POST_PMD:
1395 snd_soc_component_update_bits(component,
1396 RT5668_DEPOP_1, 0x60, 0x0);
1397 snd_soc_component_write(component,
1398 RT5668_HP_CTRL_2, 0x0000);
1399 break;
1400
1401 default:
1402 return 0;
1403 }
1404
1405 return 0;
1406
1407 }
1408
set_dmic_power(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1409 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1410 struct snd_kcontrol *kcontrol, int event)
1411 {
1412 switch (event) {
1413 case SND_SOC_DAPM_POST_PMU:
1414 /*Add delay to avoid pop noise*/
1415 msleep(150);
1416 break;
1417
1418 default:
1419 return 0;
1420 }
1421
1422 return 0;
1423 }
1424
rt5655_set_verf(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1425 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1426 struct snd_kcontrol *kcontrol, int event)
1427 {
1428 struct snd_soc_component *component =
1429 snd_soc_dapm_to_component(w->dapm);
1430
1431 switch (event) {
1432 case SND_SOC_DAPM_PRE_PMU:
1433 switch (w->shift) {
1434 case RT5668_PWR_VREF1_BIT:
1435 snd_soc_component_update_bits(component,
1436 RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 0);
1437 break;
1438
1439 case RT5668_PWR_VREF2_BIT:
1440 snd_soc_component_update_bits(component,
1441 RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 0);
1442 break;
1443
1444 default:
1445 break;
1446 }
1447 break;
1448
1449 case SND_SOC_DAPM_POST_PMU:
1450 usleep_range(15000, 20000);
1451 switch (w->shift) {
1452 case RT5668_PWR_VREF1_BIT:
1453 snd_soc_component_update_bits(component,
1454 RT5668_PWR_ANLG_1, RT5668_PWR_FV1,
1455 RT5668_PWR_FV1);
1456 break;
1457
1458 case RT5668_PWR_VREF2_BIT:
1459 snd_soc_component_update_bits(component,
1460 RT5668_PWR_ANLG_1, RT5668_PWR_FV2,
1461 RT5668_PWR_FV2);
1462 break;
1463
1464 default:
1465 break;
1466 }
1467 break;
1468
1469 default:
1470 return 0;
1471 }
1472
1473 return 0;
1474 }
1475
1476 static const unsigned int rt5668_adcdat_pin_values[] = {
1477 1,
1478 3,
1479 };
1480
1481 static const char * const rt5668_adcdat_pin_select[] = {
1482 "ADCDAT1",
1483 "ADCDAT2",
1484 };
1485
1486 static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_adcdat_pin_enum,
1487 RT5668_GPIO_CTRL_1, RT5668_GP4_PIN_SFT, RT5668_GP4_PIN_MASK,
1488 rt5668_adcdat_pin_select, rt5668_adcdat_pin_values);
1489
1490 static const struct snd_kcontrol_new rt5668_adcdat_pin_ctrl =
1491 SOC_DAPM_ENUM("ADCDAT", rt5668_adcdat_pin_enum);
1492
1493 static const struct snd_soc_dapm_widget rt5668_dapm_widgets[] = {
1494 SND_SOC_DAPM_SUPPLY("LDO2", RT5668_PWR_ANLG_3, RT5668_PWR_LDO2_BIT,
1495 0, NULL, 0),
1496 SND_SOC_DAPM_SUPPLY("PLL1", RT5668_PWR_ANLG_3, RT5668_PWR_PLL_BIT,
1497 0, NULL, 0),
1498 SND_SOC_DAPM_SUPPLY("PLL2B", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2B_BIT,
1499 0, NULL, 0),
1500 SND_SOC_DAPM_SUPPLY("PLL2F", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2F_BIT,
1501 0, NULL, 0),
1502 SND_SOC_DAPM_SUPPLY("Vref1", RT5668_PWR_ANLG_1, RT5668_PWR_VREF1_BIT, 0,
1503 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1504 SND_SOC_DAPM_SUPPLY("Vref2", RT5668_PWR_ANLG_1, RT5668_PWR_VREF2_BIT, 0,
1505 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1506
1507 /* ASRC */
1508 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
1509 RT5668_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1510 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
1511 RT5668_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1512 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5668_PLL_TRACK_1,
1513 RT5668_AD_ASRC_SFT, 0, NULL, 0),
1514 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5668_PLL_TRACK_1,
1515 RT5668_DA_ASRC_SFT, 0, NULL, 0),
1516 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5668_PLL_TRACK_1,
1517 RT5668_DMIC_ASRC_SFT, 0, NULL, 0),
1518
1519 /* Input Side */
1520 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5668_PWR_ANLG_2, RT5668_PWR_MB1_BIT,
1521 0, NULL, 0),
1522 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5668_PWR_ANLG_2, RT5668_PWR_MB2_BIT,
1523 0, NULL, 0),
1524
1525 /* Input Lines */
1526 SND_SOC_DAPM_INPUT("DMIC L1"),
1527 SND_SOC_DAPM_INPUT("DMIC R1"),
1528
1529 SND_SOC_DAPM_INPUT("IN1P"),
1530
1531 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1532 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1533 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5668_DMIC_CTRL_1,
1534 RT5668_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1535
1536 /* Boost */
1537 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1538 0, 0, NULL, 0),
1539
1540 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5668_PWR_ANLG_3,
1541 RT5668_PWR_CBJ_BIT, 0, NULL, 0),
1542
1543 /* REC Mixer */
1544 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_rec1_l_mix,
1545 ARRAY_SIZE(rt5668_rec1_l_mix)),
1546 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5668_PWR_ANLG_2,
1547 RT5668_PWR_RM1_L_BIT, 0, NULL, 0),
1548
1549 /* ADCs */
1550 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1551 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1552
1553 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5668_PWR_DIG_1,
1554 RT5668_PWR_ADC_L1_BIT, 0, NULL, 0),
1555 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5668_PWR_DIG_1,
1556 RT5668_PWR_ADC_R1_BIT, 0, NULL, 0),
1557 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5668_CHOP_ADC,
1558 RT5668_CKGEN_ADC1_SFT, 0, NULL, 0),
1559
1560 /* ADC Mux */
1561 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1562 &rt5668_sto1_adc1l_mux),
1563 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1564 &rt5668_sto1_adc1r_mux),
1565 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1566 &rt5668_sto1_adc2l_mux),
1567 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1568 &rt5668_sto1_adc2r_mux),
1569 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1570 &rt5668_sto1_adcl_mux),
1571 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1572 &rt5668_sto1_adcr_mux),
1573 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1574 &rt5668_if1_adc_slot_mux),
1575
1576 /* ADC Mixer */
1577 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5668_PWR_DIG_2,
1578 RT5668_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1579 SND_SOC_DAPM_PRE_PMU),
1580 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5668_STO1_ADC_DIG_VOL,
1581 RT5668_L_MUTE_SFT, 1, rt5668_sto1_adc_l_mix,
1582 ARRAY_SIZE(rt5668_sto1_adc_l_mix)),
1583 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5668_STO1_ADC_DIG_VOL,
1584 RT5668_R_MUTE_SFT, 1, rt5668_sto1_adc_r_mix,
1585 ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
1586
1587 /* ADC PGA */
1588 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1589
1590 /* Digital Interface */
1591 SND_SOC_DAPM_SUPPLY("I2S1", RT5668_PWR_DIG_1, RT5668_PWR_I2S1_BIT,
1592 0, NULL, 0),
1593 SND_SOC_DAPM_SUPPLY("I2S2", RT5668_PWR_DIG_1, RT5668_PWR_I2S2_BIT,
1594 0, NULL, 0),
1595 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1596 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1597 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1598
1599 /* Digital Interface Select */
1600 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1601 &rt5668_if1_01_adc_swap_mux),
1602 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1603 &rt5668_if1_23_adc_swap_mux),
1604 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1605 &rt5668_if1_45_adc_swap_mux),
1606 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1607 &rt5668_if1_67_adc_swap_mux),
1608 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1609 &rt5668_if2_adc_swap_mux),
1610
1611 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1612 &rt5668_adcdat_pin_ctrl),
1613
1614 /* Audio Interface */
1615 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1616 RT5668_I2S1_SDP, RT5668_SEL_ADCDAT_SFT, 1),
1617 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1618 RT5668_I2S2_SDP, RT5668_I2S2_PIN_CFG_SFT, 1),
1619 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1620
1621 /* Output Side */
1622 /* DAC mixer before sound effect */
1623 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1624 rt5668_dac_l_mix, ARRAY_SIZE(rt5668_dac_l_mix)),
1625 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1626 rt5668_dac_r_mix, ARRAY_SIZE(rt5668_dac_r_mix)),
1627
1628 /* DAC channel Mux */
1629 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1630 &rt5668_alg_dac_l1_mux),
1631 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1632 &rt5668_alg_dac_r1_mux),
1633
1634 /* DAC Mixer */
1635 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5668_PWR_DIG_2,
1636 RT5668_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1637 SND_SOC_DAPM_PRE_PMU),
1638 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1639 rt5668_sto1_dac_l_mix, ARRAY_SIZE(rt5668_sto1_dac_l_mix)),
1640 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1641 rt5668_sto1_dac_r_mix, ARRAY_SIZE(rt5668_sto1_dac_r_mix)),
1642
1643 /* DACs */
1644 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5668_PWR_DIG_1,
1645 RT5668_PWR_DAC_L1_BIT, 0),
1646 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5668_PWR_DIG_1,
1647 RT5668_PWR_DAC_R1_BIT, 0),
1648 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5668_CHOP_DAC,
1649 RT5668_CKGEN_DAC1_SFT, 0, NULL, 0),
1650
1651 /* HPO */
1652 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5668_hp_event,
1653 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1654
1655 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5668_PWR_ANLG_1,
1656 RT5668_PWR_HA_L_BIT, 0, NULL, 0),
1657 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5668_PWR_ANLG_1,
1658 RT5668_PWR_HA_R_BIT, 0, NULL, 0),
1659 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5668_DEPOP_1,
1660 RT5668_PUMP_EN_SFT, 0, NULL, 0),
1661 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5668_DEPOP_1,
1662 RT5668_CAPLESS_EN_SFT, 0, NULL, 0),
1663
1664 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1665 &hpol_switch),
1666 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1667 &hpor_switch),
1668
1669 /* CLK DET */
1670 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5668_CLK_DET,
1671 RT5668_SYS_CLK_DET_SFT, 0, NULL, 0),
1672 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5668_CLK_DET,
1673 RT5668_PLL1_CLK_DET_SFT, 0, NULL, 0),
1674 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5668_CLK_DET,
1675 RT5668_PLL2_CLK_DET_SFT, 0, NULL, 0),
1676 SND_SOC_DAPM_SUPPLY("CLKDET", RT5668_CLK_DET,
1677 RT5668_POW_CLK_DET_SFT, 0, NULL, 0),
1678
1679 /* Output Lines */
1680 SND_SOC_DAPM_OUTPUT("HPOL"),
1681 SND_SOC_DAPM_OUTPUT("HPOR"),
1682
1683 };
1684
1685 static const struct snd_soc_dapm_route rt5668_dapm_routes[] = {
1686 /*PLL*/
1687 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1688 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1689
1690 /*ASRC*/
1691 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1692 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1693 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1694 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1695
1696 /*Vref*/
1697 {"MICBIAS1", NULL, "Vref1"},
1698 {"MICBIAS1", NULL, "Vref2"},
1699 {"MICBIAS2", NULL, "Vref1"},
1700 {"MICBIAS2", NULL, "Vref2"},
1701
1702 {"CLKDET SYS", NULL, "CLKDET"},
1703
1704 {"IN1P", NULL, "LDO2"},
1705
1706 {"BST1 CBJ", NULL, "IN1P"},
1707 {"BST1 CBJ", NULL, "CBJ Power"},
1708 {"CBJ Power", NULL, "Vref2"},
1709
1710 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1711 {"RECMIX1L", NULL, "RECMIX1L Power"},
1712
1713 {"ADC1 L", NULL, "RECMIX1L"},
1714 {"ADC1 L", NULL, "ADC1 L Power"},
1715 {"ADC1 L", NULL, "ADC1 clock"},
1716
1717 {"DMIC L1", NULL, "DMIC CLK"},
1718 {"DMIC L1", NULL, "DMIC1 Power"},
1719 {"DMIC R1", NULL, "DMIC CLK"},
1720 {"DMIC R1", NULL, "DMIC1 Power"},
1721 {"DMIC CLK", NULL, "DMIC ASRC"},
1722
1723 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1724 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1725 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1726 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1727
1728 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1729 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1730 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1731 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1732
1733 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1734 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1735 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1736 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1737
1738 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1739 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1740 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1741
1742 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1743 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1744 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1745
1746 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1747 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1748
1749 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1750 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1751 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1752 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1753 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1754 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1755 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1756 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1757 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1758 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1759 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1760 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1761 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1762 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1763 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1764 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1765
1766 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1767 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1768 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1769 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1770 {"IF1_ADC Mux", NULL, "I2S1"},
1771 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1772 {"AIF1TX", NULL, "ADCDAT Mux"},
1773 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1774 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1775 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1776 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1777 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1778 {"AIF2TX", NULL, "ADCDAT Mux"},
1779
1780 {"IF1 DAC1 L", NULL, "AIF1RX"},
1781 {"IF1 DAC1 L", NULL, "I2S1"},
1782 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1783 {"IF1 DAC1 R", NULL, "AIF1RX"},
1784 {"IF1 DAC1 R", NULL, "I2S1"},
1785 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1786
1787 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1788 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1789 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1790 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1791
1792 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1793 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1794
1795 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1796 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1797
1798 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1799 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1800 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1801 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1802
1803 {"DAC L1", NULL, "DAC L1 Source"},
1804 {"DAC R1", NULL, "DAC R1 Source"},
1805
1806 {"DAC L1", NULL, "DAC 1 Clock"},
1807 {"DAC R1", NULL, "DAC 1 Clock"},
1808
1809 {"HP Amp", NULL, "DAC L1"},
1810 {"HP Amp", NULL, "DAC R1"},
1811 {"HP Amp", NULL, "HP Amp L"},
1812 {"HP Amp", NULL, "HP Amp R"},
1813 {"HP Amp", NULL, "Capless"},
1814 {"HP Amp", NULL, "Charge Pump"},
1815 {"HP Amp", NULL, "CLKDET SYS"},
1816 {"HP Amp", NULL, "CBJ Power"},
1817 {"HP Amp", NULL, "Vref2"},
1818 {"HPOL Playback", "Switch", "HP Amp"},
1819 {"HPOR Playback", "Switch", "HP Amp"},
1820 {"HPOL", NULL, "HPOL Playback"},
1821 {"HPOR", NULL, "HPOR Playback"},
1822 };
1823
rt5668_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1824 static int rt5668_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1825 unsigned int rx_mask, int slots, int slot_width)
1826 {
1827 struct snd_soc_component *component = dai->component;
1828 unsigned int val = 0;
1829
1830 switch (slots) {
1831 case 4:
1832 val |= RT5668_TDM_TX_CH_4;
1833 val |= RT5668_TDM_RX_CH_4;
1834 break;
1835 case 6:
1836 val |= RT5668_TDM_TX_CH_6;
1837 val |= RT5668_TDM_RX_CH_6;
1838 break;
1839 case 8:
1840 val |= RT5668_TDM_TX_CH_8;
1841 val |= RT5668_TDM_RX_CH_8;
1842 break;
1843 case 2:
1844 break;
1845 default:
1846 return -EINVAL;
1847 }
1848
1849 snd_soc_component_update_bits(component, RT5668_TDM_CTRL,
1850 RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val);
1851
1852 switch (slot_width) {
1853 case 16:
1854 val = RT5668_TDM_CL_16;
1855 break;
1856 case 20:
1857 val = RT5668_TDM_CL_20;
1858 break;
1859 case 24:
1860 val = RT5668_TDM_CL_24;
1861 break;
1862 case 32:
1863 val = RT5668_TDM_CL_32;
1864 break;
1865 default:
1866 return -EINVAL;
1867 }
1868
1869 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
1870 RT5668_TDM_CL_MASK, val);
1871
1872 return 0;
1873 }
1874
1875
rt5668_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1876 static int rt5668_hw_params(struct snd_pcm_substream *substream,
1877 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1878 {
1879 struct snd_soc_component *component = dai->component;
1880 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1881 unsigned int len_1 = 0, len_2 = 0;
1882 int pre_div, frame_size;
1883
1884 rt5668->lrck[dai->id] = params_rate(params);
1885 pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]);
1886
1887 frame_size = snd_soc_params_to_frame_size(params);
1888 if (frame_size < 0) {
1889 dev_err(component->dev, "Unsupported frame size: %d\n",
1890 frame_size);
1891 return -EINVAL;
1892 }
1893
1894 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1895 rt5668->lrck[dai->id], pre_div, dai->id);
1896
1897 switch (params_width(params)) {
1898 case 16:
1899 break;
1900 case 20:
1901 len_1 |= RT5668_I2S1_DL_20;
1902 len_2 |= RT5668_I2S2_DL_20;
1903 break;
1904 case 24:
1905 len_1 |= RT5668_I2S1_DL_24;
1906 len_2 |= RT5668_I2S2_DL_24;
1907 break;
1908 case 32:
1909 len_1 |= RT5668_I2S1_DL_32;
1910 len_2 |= RT5668_I2S2_DL_24;
1911 break;
1912 case 8:
1913 len_1 |= RT5668_I2S2_DL_8;
1914 len_2 |= RT5668_I2S2_DL_8;
1915 break;
1916 default:
1917 return -EINVAL;
1918 }
1919
1920 switch (dai->id) {
1921 case RT5668_AIF1:
1922 snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
1923 RT5668_I2S1_DL_MASK, len_1);
1924 if (rt5668->master[RT5668_AIF1]) {
1925 snd_soc_component_update_bits(component,
1926 RT5668_ADDA_CLK_1, RT5668_I2S_M_DIV_MASK,
1927 pre_div << RT5668_I2S_M_DIV_SFT);
1928 }
1929 if (params_channels(params) == 1) /* mono mode */
1930 snd_soc_component_update_bits(component,
1931 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
1932 RT5668_I2S1_MONO_EN);
1933 else
1934 snd_soc_component_update_bits(component,
1935 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
1936 RT5668_I2S1_MONO_DIS);
1937 break;
1938 case RT5668_AIF2:
1939 snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
1940 RT5668_I2S2_DL_MASK, len_2);
1941 if (rt5668->master[RT5668_AIF2]) {
1942 snd_soc_component_update_bits(component,
1943 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_M_PD_MASK,
1944 pre_div << RT5668_I2S2_M_PD_SFT);
1945 }
1946 if (params_channels(params) == 1) /* mono mode */
1947 snd_soc_component_update_bits(component,
1948 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
1949 RT5668_I2S2_MONO_EN);
1950 else
1951 snd_soc_component_update_bits(component,
1952 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
1953 RT5668_I2S2_MONO_DIS);
1954 break;
1955 default:
1956 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1957 return -EINVAL;
1958 }
1959
1960 return 0;
1961 }
1962
rt5668_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1963 static int rt5668_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1964 {
1965 struct snd_soc_component *component = dai->component;
1966 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1967 unsigned int reg_val = 0, tdm_ctrl = 0;
1968
1969 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1970 case SND_SOC_DAIFMT_CBP_CFP:
1971 rt5668->master[dai->id] = 1;
1972 break;
1973 case SND_SOC_DAIFMT_CBC_CFC:
1974 rt5668->master[dai->id] = 0;
1975 break;
1976 default:
1977 return -EINVAL;
1978 }
1979
1980 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1981 case SND_SOC_DAIFMT_NB_NF:
1982 break;
1983 case SND_SOC_DAIFMT_IB_NF:
1984 reg_val |= RT5668_I2S_BP_INV;
1985 tdm_ctrl |= RT5668_TDM_S_BP_INV;
1986 break;
1987 case SND_SOC_DAIFMT_NB_IF:
1988 if (dai->id == RT5668_AIF1)
1989 tdm_ctrl |= RT5668_TDM_S_LP_INV | RT5668_TDM_M_BP_INV;
1990 else
1991 return -EINVAL;
1992 break;
1993 case SND_SOC_DAIFMT_IB_IF:
1994 if (dai->id == RT5668_AIF1)
1995 tdm_ctrl |= RT5668_TDM_S_BP_INV | RT5668_TDM_S_LP_INV |
1996 RT5668_TDM_M_BP_INV | RT5668_TDM_M_LP_INV;
1997 else
1998 return -EINVAL;
1999 break;
2000 default:
2001 return -EINVAL;
2002 }
2003
2004 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2005 case SND_SOC_DAIFMT_I2S:
2006 break;
2007 case SND_SOC_DAIFMT_LEFT_J:
2008 reg_val |= RT5668_I2S_DF_LEFT;
2009 tdm_ctrl |= RT5668_TDM_DF_LEFT;
2010 break;
2011 case SND_SOC_DAIFMT_DSP_A:
2012 reg_val |= RT5668_I2S_DF_PCM_A;
2013 tdm_ctrl |= RT5668_TDM_DF_PCM_A;
2014 break;
2015 case SND_SOC_DAIFMT_DSP_B:
2016 reg_val |= RT5668_I2S_DF_PCM_B;
2017 tdm_ctrl |= RT5668_TDM_DF_PCM_B;
2018 break;
2019 default:
2020 return -EINVAL;
2021 }
2022
2023 switch (dai->id) {
2024 case RT5668_AIF1:
2025 snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
2026 RT5668_I2S_DF_MASK, reg_val);
2027 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
2028 RT5668_TDM_MS_MASK | RT5668_TDM_S_BP_MASK |
2029 RT5668_TDM_DF_MASK | RT5668_TDM_M_BP_MASK |
2030 RT5668_TDM_M_LP_MASK | RT5668_TDM_S_LP_MASK,
2031 tdm_ctrl | rt5668->master[dai->id]);
2032 break;
2033 case RT5668_AIF2:
2034 if (rt5668->master[dai->id] == 0)
2035 reg_val |= RT5668_I2S2_MS_S;
2036 snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
2037 RT5668_I2S2_MS_MASK | RT5668_I2S_BP_MASK |
2038 RT5668_I2S_DF_MASK, reg_val);
2039 break;
2040 default:
2041 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2042 return -EINVAL;
2043 }
2044 return 0;
2045 }
2046
rt5668_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)2047 static int rt5668_set_component_sysclk(struct snd_soc_component *component,
2048 int clk_id, int source, unsigned int freq, int dir)
2049 {
2050 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2051 unsigned int reg_val = 0, src = 0;
2052
2053 if (freq == rt5668->sysclk && clk_id == rt5668->sysclk_src)
2054 return 0;
2055
2056 switch (clk_id) {
2057 case RT5668_SCLK_S_MCLK:
2058 reg_val |= RT5668_SCLK_SRC_MCLK;
2059 src = RT5668_CLK_SRC_MCLK;
2060 break;
2061 case RT5668_SCLK_S_PLL1:
2062 reg_val |= RT5668_SCLK_SRC_PLL1;
2063 src = RT5668_CLK_SRC_PLL1;
2064 break;
2065 case RT5668_SCLK_S_PLL2:
2066 reg_val |= RT5668_SCLK_SRC_PLL2;
2067 src = RT5668_CLK_SRC_PLL2;
2068 break;
2069 case RT5668_SCLK_S_RCCLK:
2070 reg_val |= RT5668_SCLK_SRC_RCCLK;
2071 src = RT5668_CLK_SRC_RCCLK;
2072 break;
2073 default:
2074 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2075 return -EINVAL;
2076 }
2077 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2078 RT5668_SCLK_SRC_MASK, reg_val);
2079
2080 if (rt5668->master[RT5668_AIF2]) {
2081 snd_soc_component_update_bits(component,
2082 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_SRC_MASK,
2083 src << RT5668_I2S2_SRC_SFT);
2084 }
2085
2086 rt5668->sysclk = freq;
2087 rt5668->sysclk_src = clk_id;
2088
2089 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2090 freq, clk_id);
2091
2092 return 0;
2093 }
2094
rt5668_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2095 static int rt5668_set_component_pll(struct snd_soc_component *component,
2096 int pll_id, int source, unsigned int freq_in,
2097 unsigned int freq_out)
2098 {
2099 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2100 struct rl6231_pll_code pll_code;
2101 int ret;
2102
2103 if (source == rt5668->pll_src && freq_in == rt5668->pll_in &&
2104 freq_out == rt5668->pll_out)
2105 return 0;
2106
2107 if (!freq_in || !freq_out) {
2108 dev_dbg(component->dev, "PLL disabled\n");
2109
2110 rt5668->pll_in = 0;
2111 rt5668->pll_out = 0;
2112 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2113 RT5668_SCLK_SRC_MASK, RT5668_SCLK_SRC_MCLK);
2114 return 0;
2115 }
2116
2117 switch (source) {
2118 case RT5668_PLL1_S_MCLK:
2119 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2120 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_MCLK);
2121 break;
2122 case RT5668_PLL1_S_BCLK1:
2123 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2124 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_BCLK1);
2125 break;
2126 default:
2127 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2128 return -EINVAL;
2129 }
2130
2131 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2132 if (ret < 0) {
2133 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2134 return ret;
2135 }
2136
2137 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2138 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2139 pll_code.n_code, pll_code.k_code);
2140
2141 snd_soc_component_write(component, RT5668_PLL_CTRL_1,
2142 pll_code.n_code << RT5668_PLL_N_SFT | pll_code.k_code);
2143 snd_soc_component_write(component, RT5668_PLL_CTRL_2,
2144 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SFT) |
2145 (pll_code.m_bp << RT5668_PLL_M_BP_SFT));
2146
2147 rt5668->pll_in = freq_in;
2148 rt5668->pll_out = freq_out;
2149 rt5668->pll_src = source;
2150
2151 return 0;
2152 }
2153
rt5668_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)2154 static int rt5668_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2155 {
2156 struct snd_soc_component *component = dai->component;
2157 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2158
2159 rt5668->bclk[dai->id] = ratio;
2160
2161 switch (ratio) {
2162 case 64:
2163 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
2164 RT5668_I2S2_BCLK_MS2_MASK,
2165 RT5668_I2S2_BCLK_MS2_64);
2166 break;
2167 case 32:
2168 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
2169 RT5668_I2S2_BCLK_MS2_MASK,
2170 RT5668_I2S2_BCLK_MS2_32);
2171 break;
2172 default:
2173 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2174 return -EINVAL;
2175 }
2176
2177 return 0;
2178 }
2179
rt5668_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2180 static int rt5668_set_bias_level(struct snd_soc_component *component,
2181 enum snd_soc_bias_level level)
2182 {
2183 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2184
2185 switch (level) {
2186 case SND_SOC_BIAS_PREPARE:
2187 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2188 RT5668_PWR_MB | RT5668_PWR_BG,
2189 RT5668_PWR_MB | RT5668_PWR_BG);
2190 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
2191 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO,
2192 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO);
2193 break;
2194
2195 case SND_SOC_BIAS_STANDBY:
2196 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2197 RT5668_PWR_MB, RT5668_PWR_MB);
2198 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
2199 RT5668_DIG_GATE_CTRL, RT5668_DIG_GATE_CTRL);
2200 break;
2201 case SND_SOC_BIAS_OFF:
2202 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
2203 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 0);
2204 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2205 RT5668_PWR_MB | RT5668_PWR_BG, 0);
2206 break;
2207
2208 default:
2209 break;
2210 }
2211
2212 return 0;
2213 }
2214
rt5668_probe(struct snd_soc_component * component)2215 static int rt5668_probe(struct snd_soc_component *component)
2216 {
2217 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2218
2219 rt5668->component = component;
2220
2221 return 0;
2222 }
2223
rt5668_remove(struct snd_soc_component * component)2224 static void rt5668_remove(struct snd_soc_component *component)
2225 {
2226 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2227
2228 rt5668_reset(rt5668->regmap);
2229 }
2230
2231 #ifdef CONFIG_PM
rt5668_suspend(struct snd_soc_component * component)2232 static int rt5668_suspend(struct snd_soc_component *component)
2233 {
2234 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2235
2236 regcache_cache_only(rt5668->regmap, true);
2237 regcache_mark_dirty(rt5668->regmap);
2238 return 0;
2239 }
2240
rt5668_resume(struct snd_soc_component * component)2241 static int rt5668_resume(struct snd_soc_component *component)
2242 {
2243 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2244
2245 regcache_cache_only(rt5668->regmap, false);
2246 regcache_sync(rt5668->regmap);
2247
2248 return 0;
2249 }
2250 #else
2251 #define rt5668_suspend NULL
2252 #define rt5668_resume NULL
2253 #endif
2254
2255 #define RT5668_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2256 #define RT5668_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2257 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2258
2259 static const struct snd_soc_dai_ops rt5668_aif1_dai_ops = {
2260 .hw_params = rt5668_hw_params,
2261 .set_fmt = rt5668_set_dai_fmt,
2262 .set_tdm_slot = rt5668_set_tdm_slot,
2263 };
2264
2265 static const struct snd_soc_dai_ops rt5668_aif2_dai_ops = {
2266 .hw_params = rt5668_hw_params,
2267 .set_fmt = rt5668_set_dai_fmt,
2268 .set_bclk_ratio = rt5668_set_bclk_ratio,
2269 };
2270
2271 static struct snd_soc_dai_driver rt5668_dai[] = {
2272 {
2273 .name = "rt5668-aif1",
2274 .id = RT5668_AIF1,
2275 .playback = {
2276 .stream_name = "AIF1 Playback",
2277 .channels_min = 1,
2278 .channels_max = 2,
2279 .rates = RT5668_STEREO_RATES,
2280 .formats = RT5668_FORMATS,
2281 },
2282 .capture = {
2283 .stream_name = "AIF1 Capture",
2284 .channels_min = 1,
2285 .channels_max = 2,
2286 .rates = RT5668_STEREO_RATES,
2287 .formats = RT5668_FORMATS,
2288 },
2289 .ops = &rt5668_aif1_dai_ops,
2290 },
2291 {
2292 .name = "rt5668-aif2",
2293 .id = RT5668_AIF2,
2294 .capture = {
2295 .stream_name = "AIF2 Capture",
2296 .channels_min = 1,
2297 .channels_max = 2,
2298 .rates = RT5668_STEREO_RATES,
2299 .formats = RT5668_FORMATS,
2300 },
2301 .ops = &rt5668_aif2_dai_ops,
2302 },
2303 };
2304
2305 static const struct snd_soc_component_driver soc_component_dev_rt5668 = {
2306 .probe = rt5668_probe,
2307 .remove = rt5668_remove,
2308 .suspend = rt5668_suspend,
2309 .resume = rt5668_resume,
2310 .set_bias_level = rt5668_set_bias_level,
2311 .controls = rt5668_snd_controls,
2312 .num_controls = ARRAY_SIZE(rt5668_snd_controls),
2313 .dapm_widgets = rt5668_dapm_widgets,
2314 .num_dapm_widgets = ARRAY_SIZE(rt5668_dapm_widgets),
2315 .dapm_routes = rt5668_dapm_routes,
2316 .num_dapm_routes = ARRAY_SIZE(rt5668_dapm_routes),
2317 .set_sysclk = rt5668_set_component_sysclk,
2318 .set_pll = rt5668_set_component_pll,
2319 .set_jack = rt5668_set_jack_detect,
2320 .use_pmdown_time = 1,
2321 .endianness = 1,
2322 };
2323
2324 static const struct regmap_config rt5668_regmap = {
2325 .reg_bits = 16,
2326 .val_bits = 16,
2327 .max_register = RT5668_I2C_MODE,
2328 .volatile_reg = rt5668_volatile_register,
2329 .readable_reg = rt5668_readable_register,
2330 .cache_type = REGCACHE_MAPLE,
2331 .reg_defaults = rt5668_reg,
2332 .num_reg_defaults = ARRAY_SIZE(rt5668_reg),
2333 .use_single_read = true,
2334 .use_single_write = true,
2335 };
2336
2337 static const struct i2c_device_id rt5668_i2c_id[] = {
2338 {"rt5668b"},
2339 {}
2340 };
2341 MODULE_DEVICE_TABLE(i2c, rt5668_i2c_id);
2342
rt5668_parse_dt(struct rt5668_priv * rt5668,struct device * dev)2343 static int rt5668_parse_dt(struct rt5668_priv *rt5668, struct device *dev)
2344 {
2345
2346 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
2347 &rt5668->pdata.dmic1_data_pin);
2348 of_property_read_u32(dev->of_node, "realtek,dmic1-clk-pin",
2349 &rt5668->pdata.dmic1_clk_pin);
2350 of_property_read_u32(dev->of_node, "realtek,jd-src",
2351 &rt5668->pdata.jd_src);
2352
2353 return 0;
2354 }
2355
rt5668_calibrate(struct rt5668_priv * rt5668)2356 static void rt5668_calibrate(struct rt5668_priv *rt5668)
2357 {
2358 int value, count;
2359
2360 mutex_lock(&rt5668->calibrate_mutex);
2361
2362 rt5668_reset(rt5668->regmap);
2363 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xa2bf);
2364 usleep_range(15000, 20000);
2365 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xf2bf);
2366 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
2367 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8001);
2368 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
2369 regmap_write(rt5668->regmap, RT5668_STO1_DAC_MIXER, 0x2080);
2370 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x4040);
2371 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0069);
2372 regmap_write(rt5668->regmap, RT5668_CHOP_DAC, 0x3000);
2373 regmap_write(rt5668->regmap, RT5668_HP_CTRL_2, 0x6000);
2374 regmap_write(rt5668->regmap, RT5668_HP_CHARGE_PUMP_1, 0x0f26);
2375 regmap_write(rt5668->regmap, RT5668_CALIB_ADC_CTRL, 0x7f05);
2376 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x686c);
2377 regmap_write(rt5668->regmap, RT5668_CAL_REC, 0x0d0d);
2378 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_9, 0x000f);
2379 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8d01);
2380 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_2, 0x0321);
2381 regmap_write(rt5668->regmap, RT5668_HP_LOGIC_CTRL_2, 0x0004);
2382 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0x7c00);
2383 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_3, 0x06a1);
2384 regmap_write(rt5668->regmap, RT5668_A_DAC1_MUX, 0x0311);
2385 regmap_write(rt5668->regmap, RT5668_RESET_HPF_CTRL, 0x0000);
2386 regmap_write(rt5668->regmap, RT5668_ADC_STO1_HP_CTRL_1, 0x3320);
2387
2388 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0xfc00);
2389
2390 for (count = 0; count < 60; count++) {
2391 regmap_read(rt5668->regmap, RT5668_HP_CALIB_STA_1, &value);
2392 if (!(value & 0x8000))
2393 break;
2394
2395 usleep_range(10000, 10005);
2396 }
2397
2398 if (count >= 60)
2399 pr_err("HP Calibration Failure\n");
2400
2401 /* restore settings */
2402 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0xc0c4);
2403 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x0000);
2404
2405 mutex_unlock(&rt5668->calibrate_mutex);
2406
2407 }
2408
rt5668_i2c_probe(struct i2c_client * i2c)2409 static int rt5668_i2c_probe(struct i2c_client *i2c)
2410 {
2411 struct rt5668_platform_data *pdata = dev_get_platdata(&i2c->dev);
2412 struct rt5668_priv *rt5668;
2413 int i, ret;
2414 unsigned int val;
2415
2416 rt5668 = devm_kzalloc(&i2c->dev, sizeof(struct rt5668_priv),
2417 GFP_KERNEL);
2418
2419 if (rt5668 == NULL)
2420 return -ENOMEM;
2421
2422 i2c_set_clientdata(i2c, rt5668);
2423
2424 if (pdata)
2425 rt5668->pdata = *pdata;
2426 else
2427 rt5668_parse_dt(rt5668, &i2c->dev);
2428
2429 rt5668->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
2430 if (IS_ERR(rt5668->regmap)) {
2431 ret = PTR_ERR(rt5668->regmap);
2432 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2433 ret);
2434 return ret;
2435 }
2436
2437 for (i = 0; i < ARRAY_SIZE(rt5668->supplies); i++)
2438 rt5668->supplies[i].supply = rt5668_supply_names[i];
2439
2440 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5668->supplies),
2441 rt5668->supplies);
2442 if (ret != 0) {
2443 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2444 return ret;
2445 }
2446
2447 ret = regulator_bulk_enable(ARRAY_SIZE(rt5668->supplies),
2448 rt5668->supplies);
2449 if (ret != 0) {
2450 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2451 return ret;
2452 }
2453
2454 rt5668->ldo1_en = devm_gpiod_get_optional(&i2c->dev,
2455 "realtek,ldo1-en",
2456 GPIOD_OUT_HIGH);
2457 if (IS_ERR(rt5668->ldo1_en)) {
2458 dev_err(&i2c->dev, "Fail gpio request ldo1_en\n");
2459 return PTR_ERR(rt5668->ldo1_en);
2460 }
2461
2462 /* Sleep for 300 ms miniumum */
2463 usleep_range(300000, 350000);
2464
2465 regmap_write(rt5668->regmap, RT5668_I2C_MODE, 0x1);
2466 usleep_range(10000, 15000);
2467
2468 regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val);
2469 if (val != DEVICE_ID) {
2470 pr_err("Device with ID register %x is not rt5668\n", val);
2471 return -ENODEV;
2472 }
2473
2474 rt5668_reset(rt5668->regmap);
2475
2476 rt5668_calibrate(rt5668);
2477
2478 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0000);
2479
2480 /* DMIC pin*/
2481 if (rt5668->pdata.dmic1_data_pin != RT5668_DMIC1_NULL) {
2482 switch (rt5668->pdata.dmic1_data_pin) {
2483 case RT5668_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2484 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
2485 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO2);
2486 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2487 RT5668_GP2_PIN_MASK, RT5668_GP2_PIN_DMIC_SDA);
2488 break;
2489
2490 case RT5668_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2491 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
2492 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO5);
2493 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2494 RT5668_GP5_PIN_MASK, RT5668_GP5_PIN_DMIC_SDA);
2495 break;
2496
2497 default:
2498 dev_dbg(&i2c->dev, "invalid DMIC_DAT pin\n");
2499 break;
2500 }
2501
2502 switch (rt5668->pdata.dmic1_clk_pin) {
2503 case RT5668_DMIC1_CLK_GPIO1: /* share with IRQ */
2504 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2505 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_DMIC_CLK);
2506 break;
2507
2508 case RT5668_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2509 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2510 RT5668_GP3_PIN_MASK, RT5668_GP3_PIN_DMIC_CLK);
2511 break;
2512
2513 default:
2514 dev_dbg(&i2c->dev, "invalid DMIC_CLK pin\n");
2515 break;
2516 }
2517 }
2518
2519 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2520 RT5668_LDO1_DVO_MASK | RT5668_HP_DRIVER_MASK,
2521 RT5668_LDO1_DVO_14 | RT5668_HP_DRIVER_5X);
2522 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
2523 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2524 RT5668_GP4_PIN_MASK | RT5668_GP5_PIN_MASK,
2525 RT5668_GP4_PIN_ADCDAT1 | RT5668_GP5_PIN_DACDAT1);
2526 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
2527
2528 INIT_DELAYED_WORK(&rt5668->jack_detect_work,
2529 rt5668_jack_detect_handler);
2530 INIT_DELAYED_WORK(&rt5668->jd_check_work,
2531 rt5668_jd_check_handler);
2532
2533 mutex_init(&rt5668->calibrate_mutex);
2534
2535 if (i2c->irq) {
2536 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2537 rt5668_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2538 | IRQF_ONESHOT, "rt5668", rt5668);
2539 if (ret)
2540 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
2541
2542 }
2543
2544 return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5668,
2545 rt5668_dai, ARRAY_SIZE(rt5668_dai));
2546 }
2547
rt5668_i2c_shutdown(struct i2c_client * client)2548 static void rt5668_i2c_shutdown(struct i2c_client *client)
2549 {
2550 struct rt5668_priv *rt5668 = i2c_get_clientdata(client);
2551
2552 rt5668_reset(rt5668->regmap);
2553 }
2554
2555 #ifdef CONFIG_OF
2556 static const struct of_device_id rt5668_of_match[] = {
2557 {.compatible = "realtek,rt5668b"},
2558 { }
2559 };
2560 MODULE_DEVICE_TABLE(of, rt5668_of_match);
2561 #endif
2562
2563 #ifdef CONFIG_ACPI
2564 static const struct acpi_device_id rt5668_acpi_match[] = {
2565 { "10EC5668" },
2566 { }
2567 };
2568 MODULE_DEVICE_TABLE(acpi, rt5668_acpi_match);
2569 #endif
2570
2571 static struct i2c_driver rt5668_i2c_driver = {
2572 .driver = {
2573 .name = "rt5668b",
2574 .of_match_table = of_match_ptr(rt5668_of_match),
2575 .acpi_match_table = ACPI_PTR(rt5668_acpi_match),
2576 },
2577 .probe = rt5668_i2c_probe,
2578 .shutdown = rt5668_i2c_shutdown,
2579 .id_table = rt5668_i2c_id,
2580 };
2581 module_i2c_driver(rt5668_i2c_driver);
2582
2583 MODULE_DESCRIPTION("ASoC RT5668B driver");
2584 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2585 MODULE_LICENSE("GPL v2");
2586