xref: /linux/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c (revision 3ef7acec975bde28ab9cef92af76be8fc2ce684d)
1 /*
2  * SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2018, The Linux Foundation
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/iopoll.h>
9 
10 #include "dsi_phy.h"
11 #include "dsi.xml.h"
12 #include "dsi_phy_7nm.xml.h"
13 
14 /*
15  * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
16  *
17  *           dsi0_pll_out_div_clk  dsi0_pll_bit_clk
18  *                              |                |
19  *                              |                |
20  *                 +---------+  |  +----------+  |  +----+
21  *  dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22  *                 +---------+  |  +----------+  |  +----+
23  *                              |                |
24  *                              |                |         dsi0_pll_by_2_bit_clk
25  *                              |                |          |
26  *                              |                |  +----+  |  |\  dsi0_pclk_mux
27  *                              |                |--| /2 |--o--| \   |
28  *                              |                |  +----+     |  \  |  +---------+
29  *                              |                --------------|  |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
30  *                              |------------------------------|  /     +---------+
31  *                              |          +-----+             | /
32  *                              -----------| /4? |--o----------|/
33  *                                         +-----+  |           |
34  *                                                  |           |dsiclk_sel
35  *                                                  |
36  *                                                  dsi0_pll_post_out_div_clk
37  */
38 
39 #define VCO_REF_CLK_RATE		19200000
40 #define FRAC_BITS 18
41 
42 /* Hardware is pre V4.1 */
43 #define DSI_PHY_7NM_QUIRK_PRE_V4_1	BIT(0)
44 /* Hardware is V4.1 */
45 #define DSI_PHY_7NM_QUIRK_V4_1		BIT(1)
46 /* Hardware is V4.2 */
47 #define DSI_PHY_7NM_QUIRK_V4_2		BIT(2)
48 /* Hardware is V4.3 */
49 #define DSI_PHY_7NM_QUIRK_V4_3		BIT(3)
50 /* Hardware is V5.2 */
51 #define DSI_PHY_7NM_QUIRK_V5_2		BIT(4)
52 
53 struct dsi_pll_config {
54 	bool enable_ssc;
55 	bool ssc_center;
56 	u32 ssc_freq;
57 	u32 ssc_offset;
58 	u32 ssc_adj_per;
59 
60 	/* out */
61 	u32 decimal_div_start;
62 	u32 frac_div_start;
63 	u32 pll_clock_inverters;
64 	u32 ssc_stepsize;
65 	u32 ssc_div_per;
66 };
67 
68 struct pll_7nm_cached_state {
69 	unsigned long vco_rate;
70 	u8 bit_clk_div;
71 	u8 pix_clk_div;
72 	u8 pll_out_div;
73 	u8 pll_mux;
74 };
75 
76 struct dsi_pll_7nm {
77 	struct clk_hw clk_hw;
78 
79 	struct msm_dsi_phy *phy;
80 
81 	u64 vco_current_rate;
82 
83 	/* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
84 	spinlock_t postdiv_lock;
85 
86 	/* protects REG_DSI_7nm_PHY_CMN_CLK_CFG1 register */
87 	spinlock_t pclk_mux_lock;
88 
89 	struct pll_7nm_cached_state cached_state;
90 
91 	struct dsi_pll_7nm *slave;
92 };
93 
94 #define to_pll_7nm(x)	container_of(x, struct dsi_pll_7nm, clk_hw)
95 
96 /*
97  * Global list of private DSI PLL struct pointers. We need this for bonded DSI
98  * mode, where the master PLL's clk_ops needs access the slave's private data
99  */
100 static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
101 
dsi_pll_setup_config(struct dsi_pll_config * config)102 static void dsi_pll_setup_config(struct dsi_pll_config *config)
103 {
104 	config->ssc_freq = 31500;
105 	config->ssc_offset = 4800;
106 	config->ssc_adj_per = 2;
107 
108 	/* TODO: ssc enable */
109 	config->enable_ssc = false;
110 	config->ssc_center = 0;
111 }
112 
dsi_pll_calc_dec_frac(struct dsi_pll_7nm * pll,struct dsi_pll_config * config)113 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
114 {
115 	u64 fref = VCO_REF_CLK_RATE;
116 	u64 pll_freq;
117 	u64 divider;
118 	u64 dec, dec_multiple;
119 	u32 frac;
120 	u64 multiplier;
121 
122 	pll_freq = pll->vco_current_rate;
123 
124 	divider = fref * 2;
125 
126 	multiplier = 1 << FRAC_BITS;
127 	dec_multiple = div_u64(pll_freq * multiplier, divider);
128 	dec = div_u64_rem(dec_multiple, multiplier, &frac);
129 
130 	if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
131 		config->pll_clock_inverters = 0x28;
132 	else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
133 		if (pll_freq <= 1300000000ULL)
134 			config->pll_clock_inverters = 0xa0;
135 		else if (pll_freq <= 2500000000ULL)
136 			config->pll_clock_inverters = 0x20;
137 		else if (pll_freq <= 4000000000ULL)
138 			config->pll_clock_inverters = 0x00;
139 		else
140 			config->pll_clock_inverters = 0x40;
141 	} else if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
142 		if (pll_freq <= 1000000000ULL)
143 			config->pll_clock_inverters = 0xa0;
144 		else if (pll_freq <= 2500000000ULL)
145 			config->pll_clock_inverters = 0x20;
146 		else if (pll_freq <= 3020000000ULL)
147 			config->pll_clock_inverters = 0x00;
148 		else
149 			config->pll_clock_inverters = 0x40;
150 	} else {
151 		/* 4.2, 4.3 */
152 		if (pll_freq <= 1000000000ULL)
153 			config->pll_clock_inverters = 0xa0;
154 		else if (pll_freq <= 2500000000ULL)
155 			config->pll_clock_inverters = 0x20;
156 		else if (pll_freq <= 3500000000ULL)
157 			config->pll_clock_inverters = 0x00;
158 		else
159 			config->pll_clock_inverters = 0x40;
160 	}
161 
162 	config->decimal_div_start = dec;
163 	config->frac_div_start = frac;
164 }
165 
166 #define SSC_CENTER		BIT(0)
167 #define SSC_EN			BIT(1)
168 
dsi_pll_calc_ssc(struct dsi_pll_7nm * pll,struct dsi_pll_config * config)169 static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
170 {
171 	u32 ssc_per;
172 	u32 ssc_mod;
173 	u64 ssc_step_size;
174 	u64 frac;
175 
176 	if (!config->enable_ssc) {
177 		DBG("SSC not enabled\n");
178 		return;
179 	}
180 
181 	ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
182 	ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
183 	ssc_per -= ssc_mod;
184 
185 	frac = config->frac_div_start;
186 	ssc_step_size = config->decimal_div_start;
187 	ssc_step_size *= (1 << FRAC_BITS);
188 	ssc_step_size += frac;
189 	ssc_step_size *= config->ssc_offset;
190 	ssc_step_size *= (config->ssc_adj_per + 1);
191 	ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
192 	ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
193 
194 	config->ssc_div_per = ssc_per;
195 	config->ssc_stepsize = ssc_step_size;
196 
197 	pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
198 		 config->decimal_div_start, frac, FRAC_BITS);
199 	pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
200 		 ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
201 }
202 
dsi_pll_ssc_commit(struct dsi_pll_7nm * pll,struct dsi_pll_config * config)203 static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
204 {
205 	void __iomem *base = pll->phy->pll_base;
206 
207 	if (config->enable_ssc) {
208 		pr_debug("SSC is enabled\n");
209 
210 		writel(config->ssc_stepsize & 0xff,
211 		       base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1);
212 		writel(config->ssc_stepsize >> 8,
213 		       base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1);
214 		writel(config->ssc_div_per & 0xff,
215 		       base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1);
216 		writel(config->ssc_div_per >> 8,
217 		       base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1);
218 		writel(config->ssc_adj_per & 0xff,
219 		       base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1);
220 		writel(config->ssc_adj_per >> 8,
221 		       base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1);
222 		writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0),
223 		       base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL);
224 	}
225 }
226 
dsi_pll_config_hzindep_reg(struct dsi_pll_7nm * pll)227 static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
228 {
229 	void __iomem *base = pll->phy->pll_base;
230 	u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
231 
232 	if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
233 		if (pll->vco_current_rate >= 3100000000ULL)
234 			analog_controls_five_1 = 0x03;
235 
236 	if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
237 		if (pll->vco_current_rate < 1520000000ULL)
238 			vco_config_1 = 0x08;
239 		else if (pll->vco_current_rate < 2990000000ULL)
240 			vco_config_1 = 0x01;
241 	}
242 
243 	if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
244 	    (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
245 		if (pll->vco_current_rate < 1520000000ULL)
246 			vco_config_1 = 0x08;
247 		else if (pll->vco_current_rate >= 2990000000ULL)
248 			vco_config_1 = 0x01;
249 	}
250 
251 	if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
252 		if (pll->vco_current_rate < 1557000000ULL)
253 			vco_config_1 = 0x08;
254 		else
255 			vco_config_1 = 0x01;
256 	}
257 
258 	writel(analog_controls_five_1, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1);
259 	writel(vco_config_1, base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1);
260 	writel(0x01, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE);
261 	writel(0x03, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO);
262 	writel(0x00, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE);
263 	writel(0x00, base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER);
264 	writel(0x4e, base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER);
265 	writel(0x40, base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS);
266 	writel(0xba, base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE);
267 	writel(0x0c, base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE);
268 	writel(0x00, base + REG_DSI_7nm_PHY_PLL_OUTDIV);
269 	writel(0x00, base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE);
270 	writel(0x08, base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO);
271 	writel(0x0a, base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1);
272 	writel(0xc0, base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1);
273 	writel(0x84, base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1);
274 	writel(0x82, base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1);
275 	writel(0x4c, base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1);
276 	writel(0x80, base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE);
277 	writel(0x29, base + REG_DSI_7nm_PHY_PLL_PFILT);
278 	writel(0x2f, base + REG_DSI_7nm_PHY_PLL_PFILT);
279 	writel(0x2a, base + REG_DSI_7nm_PHY_PLL_IFILT);
280 	writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22,
281 	       base + REG_DSI_7nm_PHY_PLL_IFILT);
282 
283 	if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) {
284 		writel(0x22, base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE);
285 		if (pll->slave)
286 			writel(0x22, pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE);
287 	}
288 }
289 
dsi_pll_commit(struct dsi_pll_7nm * pll,struct dsi_pll_config * config)290 static void dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config)
291 {
292 	void __iomem *base = pll->phy->pll_base;
293 
294 	writel(0x12, base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE);
295 	writel(config->decimal_div_start,
296 	       base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
297 	writel(config->frac_div_start & 0xff,
298 	       base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
299 	writel((config->frac_div_start & 0xff00) >> 8,
300 	       base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1);
301 	writel((config->frac_div_start & 0x30000) >> 16,
302 	       base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1);
303 	writel(0x40, base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1);
304 	writel(0x06, base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY);
305 	writel(pll->phy->cphy_mode ? 0x00 : 0x10,
306 	       base + REG_DSI_7nm_PHY_PLL_CMODE_1);
307 	writel(config->pll_clock_inverters,
308 	       base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS);
309 }
310 
dsi_pll_7nm_vco_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)311 static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
312 				     unsigned long parent_rate)
313 {
314 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
315 	struct dsi_pll_config config;
316 
317 	DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
318 	    parent_rate);
319 
320 	pll_7nm->vco_current_rate = rate;
321 
322 	dsi_pll_setup_config(&config);
323 
324 	dsi_pll_calc_dec_frac(pll_7nm, &config);
325 
326 	dsi_pll_calc_ssc(pll_7nm, &config);
327 
328 	dsi_pll_commit(pll_7nm, &config);
329 
330 	dsi_pll_config_hzindep_reg(pll_7nm);
331 
332 	dsi_pll_ssc_commit(pll_7nm, &config);
333 
334 	/* flush, ensure all register writes are done*/
335 	wmb();
336 
337 	return 0;
338 }
339 
dsi_pll_7nm_lock_status(struct dsi_pll_7nm * pll)340 static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
341 {
342 	int rc;
343 	u32 status = 0;
344 	u32 const delay_us = 100;
345 	u32 const timeout_us = 5000;
346 
347 	rc = readl_poll_timeout_atomic(pll->phy->pll_base +
348 				       REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE,
349 				       status,
350 				       ((status & BIT(0)) > 0),
351 				       delay_us,
352 				       timeout_us);
353 	if (rc)
354 		pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
355 		       pll->phy->id, status);
356 
357 	return rc;
358 }
359 
dsi_pll_disable_pll_bias(struct dsi_pll_7nm * pll)360 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
361 {
362 	u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
363 
364 	writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
365 	writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
366 	ndelay(250);
367 }
368 
dsi_pll_enable_pll_bias(struct dsi_pll_7nm * pll)369 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
370 {
371 	u32 data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
372 
373 	writel(data | BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
374 	writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
375 	ndelay(250);
376 }
377 
dsi_pll_cmn_clk_cfg0_write(struct dsi_pll_7nm * pll,u32 val)378 static void dsi_pll_cmn_clk_cfg0_write(struct dsi_pll_7nm *pll, u32 val)
379 {
380 	unsigned long flags;
381 
382 	spin_lock_irqsave(&pll->postdiv_lock, flags);
383 	writel(val, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
384 	spin_unlock_irqrestore(&pll->postdiv_lock, flags);
385 }
386 
dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm * pll,u32 mask,u32 val)387 static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask,
388 					u32 val)
389 {
390 	unsigned long flags;
391 	u32 data;
392 
393 	spin_lock_irqsave(&pll->pclk_mux_lock, flags);
394 	data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
395 	data &= ~mask;
396 	data |= val & mask;
397 
398 	writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
399 	spin_unlock_irqrestore(&pll->pclk_mux_lock, flags);
400 }
401 
dsi_pll_disable_global_clk(struct dsi_pll_7nm * pll)402 static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
403 {
404 	dsi_pll_cmn_clk_cfg1_update(pll, DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN, 0);
405 }
406 
dsi_pll_enable_global_clk(struct dsi_pll_7nm * pll)407 static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
408 {
409 	u32 cfg_1 = DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN | DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN_SEL;
410 
411 	writel(0x04, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3);
412 	dsi_pll_cmn_clk_cfg1_update(pll, cfg_1, cfg_1);
413 }
414 
dsi_pll_phy_dig_reset(struct dsi_pll_7nm * pll)415 static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
416 {
417 	/*
418 	 * Reset the PHY digital domain. This would be needed when
419 	 * coming out of a CX or analog rail power collapse while
420 	 * ensuring that the pads maintain LP00 or LP11 state
421 	 */
422 	writel(BIT(0), pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4);
423 	wmb(); /* Ensure that the reset is deasserted */
424 	writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4);
425 	wmb(); /* Ensure that the reset is deasserted */
426 }
427 
dsi_pll_7nm_vco_prepare(struct clk_hw * hw)428 static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
429 {
430 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
431 	int rc;
432 
433 	dsi_pll_enable_pll_bias(pll_7nm);
434 	if (pll_7nm->slave)
435 		dsi_pll_enable_pll_bias(pll_7nm->slave);
436 
437 	/* Start PLL */
438 	writel(BIT(0), pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
439 
440 	/*
441 	 * ensure all PLL configurations are written prior to checking
442 	 * for PLL lock.
443 	 */
444 	wmb();
445 
446 	/* Check for PLL lock */
447 	rc = dsi_pll_7nm_lock_status(pll_7nm);
448 	if (rc) {
449 		pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id);
450 		goto error;
451 	}
452 
453 	pll_7nm->phy->pll_on = true;
454 
455 	/*
456 	 * assert power on reset for PHY digital in case the PLL is
457 	 * enabled after CX of analog domain power collapse. This needs
458 	 * to be done before enabling the global clk.
459 	 */
460 	dsi_pll_phy_dig_reset(pll_7nm);
461 	if (pll_7nm->slave)
462 		dsi_pll_phy_dig_reset(pll_7nm->slave);
463 
464 	dsi_pll_enable_global_clk(pll_7nm);
465 	if (pll_7nm->slave)
466 		dsi_pll_enable_global_clk(pll_7nm->slave);
467 
468 error:
469 	return rc;
470 }
471 
dsi_pll_disable_sub(struct dsi_pll_7nm * pll)472 static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
473 {
474 	writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL);
475 	dsi_pll_disable_pll_bias(pll);
476 }
477 
dsi_pll_7nm_vco_unprepare(struct clk_hw * hw)478 static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
479 {
480 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
481 
482 	/*
483 	 * To avoid any stray glitches while abruptly powering down the PLL
484 	 * make sure to gate the clock using the clock enable bit before
485 	 * powering down the PLL
486 	 */
487 	dsi_pll_disable_global_clk(pll_7nm);
488 	writel(0, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
489 	dsi_pll_disable_sub(pll_7nm);
490 	if (pll_7nm->slave) {
491 		dsi_pll_disable_global_clk(pll_7nm->slave);
492 		dsi_pll_disable_sub(pll_7nm->slave);
493 	}
494 	/* flush, ensure all register writes are done */
495 	wmb();
496 	pll_7nm->phy->pll_on = false;
497 }
498 
dsi_pll_7nm_vco_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)499 static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
500 						  unsigned long parent_rate)
501 {
502 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
503 	void __iomem *base = pll_7nm->phy->pll_base;
504 	u64 ref_clk = VCO_REF_CLK_RATE;
505 	u64 vco_rate = 0x0;
506 	u64 multiplier;
507 	u32 frac;
508 	u32 dec;
509 	u64 pll_freq, tmp64;
510 
511 	dec = readl(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
512 	dec &= 0xff;
513 
514 	frac = readl(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
515 	frac |= ((readl(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
516 		  0xff) << 8);
517 	frac |= ((readl(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
518 		  0x3) << 16);
519 
520 	/*
521 	 * TODO:
522 	 *	1. Assumes prescaler is disabled
523 	 */
524 	multiplier = 1 << FRAC_BITS;
525 	pll_freq = dec * (ref_clk * 2);
526 	tmp64 = (ref_clk * 2 * frac);
527 	pll_freq += div_u64(tmp64, multiplier);
528 
529 	vco_rate = pll_freq;
530 	pll_7nm->vco_current_rate = vco_rate;
531 
532 	DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
533 	    pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
534 
535 	return (unsigned long)vco_rate;
536 }
537 
dsi_pll_7nm_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)538 static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw,
539 		unsigned long rate, unsigned long *parent_rate)
540 {
541 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
542 
543 	if      (rate < pll_7nm->phy->cfg->min_pll_rate)
544 		return  pll_7nm->phy->cfg->min_pll_rate;
545 	else if (rate > pll_7nm->phy->cfg->max_pll_rate)
546 		return  pll_7nm->phy->cfg->max_pll_rate;
547 	else
548 		return rate;
549 }
550 
551 static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
552 	.round_rate = dsi_pll_7nm_clk_round_rate,
553 	.set_rate = dsi_pll_7nm_vco_set_rate,
554 	.recalc_rate = dsi_pll_7nm_vco_recalc_rate,
555 	.prepare = dsi_pll_7nm_vco_prepare,
556 	.unprepare = dsi_pll_7nm_vco_unprepare,
557 };
558 
559 /*
560  * PLL Callbacks
561  */
562 
dsi_7nm_pll_save_state(struct msm_dsi_phy * phy)563 static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy)
564 {
565 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
566 	struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
567 	void __iomem *phy_base = pll_7nm->phy->base;
568 	u32 cmn_clk_cfg0, cmn_clk_cfg1;
569 
570 	cached->pll_out_div = readl(pll_7nm->phy->pll_base +
571 			REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
572 	cached->pll_out_div &= 0x3;
573 
574 	cmn_clk_cfg0 = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
575 	cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
576 	cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
577 
578 	cmn_clk_cfg1 = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
579 	cached->pll_mux = cmn_clk_cfg1 & 0x3;
580 
581 	DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
582 	    pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
583 	    cached->pix_clk_div, cached->pll_mux);
584 }
585 
dsi_7nm_pll_restore_state(struct msm_dsi_phy * phy)586 static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
587 {
588 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
589 	struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
590 	u32 val;
591 	int ret;
592 
593 	val = readl(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
594 	val &= ~0x3;
595 	val |= cached->pll_out_div;
596 	writel(val, pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
597 
598 	dsi_pll_cmn_clk_cfg0_write(pll_7nm,
599 				   DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(cached->bit_clk_div) |
600 				   DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(cached->pix_clk_div));
601 	dsi_pll_cmn_clk_cfg1_update(pll_7nm, 0x3, cached->pll_mux);
602 
603 	ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
604 			pll_7nm->vco_current_rate,
605 			VCO_REF_CLK_RATE);
606 	if (ret) {
607 		DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
608 			"restore vco rate failed. ret=%d\n", ret);
609 		return ret;
610 	}
611 
612 	DBG("DSI PLL%d", pll_7nm->phy->id);
613 
614 	return 0;
615 }
616 
dsi_7nm_set_usecase(struct msm_dsi_phy * phy)617 static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
618 {
619 	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
620 	u32 data = 0x0;	/* internal PLL */
621 
622 	DBG("DSI PLL%d", pll_7nm->phy->id);
623 
624 	switch (phy->usecase) {
625 	case MSM_DSI_PHY_STANDALONE:
626 		break;
627 	case MSM_DSI_PHY_MASTER:
628 		pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
629 		break;
630 	case MSM_DSI_PHY_SLAVE:
631 		data = 0x1; /* external PLL */
632 		break;
633 	default:
634 		return -EINVAL;
635 	}
636 
637 	/* set PLL src */
638 	dsi_pll_cmn_clk_cfg1_update(pll_7nm, DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL__MASK,
639 				    DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL(data));
640 
641 	return 0;
642 }
643 
644 /*
645  * The post dividers and mux clocks are created using the standard divider and
646  * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
647  * state to follow the master PLL's divider/mux state. Therefore, we don't
648  * require special clock ops that also configure the slave PLL registers
649  */
pll_7nm_register(struct dsi_pll_7nm * pll_7nm,struct clk_hw ** provided_clocks)650 static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks)
651 {
652 	char clk_name[32];
653 	struct clk_init_data vco_init = {
654 		.parent_data = &(const struct clk_parent_data) {
655 			.fw_name = "ref",
656 		},
657 		.num_parents = 1,
658 		.name = clk_name,
659 		.flags = CLK_IGNORE_UNUSED,
660 		.ops = &clk_ops_dsi_pll_7nm_vco,
661 	};
662 	struct device *dev = &pll_7nm->phy->pdev->dev;
663 	struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit;
664 	struct clk_hw *pll_post_out_div, *phy_pll_out_dsi_parent;
665 	int ret;
666 
667 	DBG("DSI%d", pll_7nm->phy->id);
668 
669 	snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_7nm->phy->id);
670 	pll_7nm->clk_hw.init = &vco_init;
671 
672 	ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
673 	if (ret)
674 		return ret;
675 
676 	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
677 
678 	pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
679 			&pll_7nm->clk_hw, CLK_SET_RATE_PARENT,
680 			pll_7nm->phy->pll_base +
681 				REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
682 			0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
683 	if (IS_ERR(pll_out_div)) {
684 		ret = PTR_ERR(pll_out_div);
685 		goto fail;
686 	}
687 
688 	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_7nm->phy->id);
689 
690 	/* BIT CLK: DIV_CTRL_3_0 */
691 	pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
692 			pll_out_div, CLK_SET_RATE_PARENT,
693 			pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
694 			0, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);
695 	if (IS_ERR(pll_bit)) {
696 		ret = PTR_ERR(pll_bit);
697 		goto fail;
698 	}
699 
700 	snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id);
701 
702 	/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
703 	hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
704 			pll_bit, CLK_SET_RATE_PARENT, 1,
705 			pll_7nm->phy->cphy_mode ? 7 : 8);
706 	if (IS_ERR(hw)) {
707 		ret = PTR_ERR(hw);
708 		goto fail;
709 	}
710 
711 	provided_clocks[DSI_BYTE_PLL_CLK] = hw;
712 
713 	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
714 
715 	pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev,
716 			clk_name, pll_bit, 0, 1, 2);
717 	if (IS_ERR(pll_by_2_bit)) {
718 		ret = PTR_ERR(pll_by_2_bit);
719 		goto fail;
720 	}
721 
722 	snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
723 
724 	if (pll_7nm->phy->cphy_mode)
725 		pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw(
726 				dev, clk_name, pll_out_div, 0, 2, 7);
727 	else
728 		pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw(
729 				dev, clk_name, pll_out_div, 0, 1, 4);
730 	if (IS_ERR(pll_post_out_div)) {
731 		ret = PTR_ERR(pll_post_out_div);
732 		goto fail;
733 	}
734 
735 	/* in CPHY mode, pclk_mux will always have post_out_div as parent
736 	 * don't register a pclk_mux clock and just use post_out_div instead
737 	 */
738 	if (pll_7nm->phy->cphy_mode) {
739 		u32 data;
740 
741 		data = readl(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
742 		writel(data | 3, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
743 
744 		phy_pll_out_dsi_parent = pll_post_out_div;
745 	} else {
746 		snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_7nm->phy->id);
747 
748 		hw = devm_clk_hw_register_mux_parent_hws(dev, clk_name,
749 				((const struct clk_hw *[]){
750 					pll_bit,
751 					pll_by_2_bit,
752 				}), 2, 0, pll_7nm->phy->base +
753 					REG_DSI_7nm_PHY_CMN_CLK_CFG1,
754 				0, 1, 0, &pll_7nm->pclk_mux_lock);
755 		if (IS_ERR(hw)) {
756 			ret = PTR_ERR(hw);
757 			goto fail;
758 		}
759 
760 		phy_pll_out_dsi_parent = hw;
761 	}
762 
763 	snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);
764 
765 	/* PIX CLK DIV : DIV_CTRL_7_4*/
766 	hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
767 			phy_pll_out_dsi_parent, 0,
768 			pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
769 			4, 4, CLK_DIVIDER_ONE_BASED, &pll_7nm->postdiv_lock);
770 	if (IS_ERR(hw)) {
771 		ret = PTR_ERR(hw);
772 		goto fail;
773 	}
774 
775 	provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
776 
777 	return 0;
778 
779 fail:
780 
781 	return ret;
782 }
783 
dsi_pll_7nm_init(struct msm_dsi_phy * phy)784 static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
785 {
786 	struct platform_device *pdev = phy->pdev;
787 	struct dsi_pll_7nm *pll_7nm;
788 	int ret;
789 
790 	pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
791 	if (!pll_7nm)
792 		return -ENOMEM;
793 
794 	DBG("DSI PLL%d", phy->id);
795 
796 	pll_7nm_list[phy->id] = pll_7nm;
797 
798 	spin_lock_init(&pll_7nm->postdiv_lock);
799 	spin_lock_init(&pll_7nm->pclk_mux_lock);
800 
801 	pll_7nm->phy = phy;
802 
803 	ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
804 	if (ret) {
805 		DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
806 		return ret;
807 	}
808 
809 	phy->vco_hw = &pll_7nm->clk_hw;
810 
811 	/* TODO: Remove this when we have proper display handover support */
812 	msm_dsi_phy_pll_save_state(phy);
813 
814 	return 0;
815 }
816 
dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy * phy)817 static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy)
818 {
819 	void __iomem *base = phy->base;
820 	u32 data = 0;
821 
822 	data = readl(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
823 	mb(); /* make sure read happened */
824 
825 	return (data & BIT(0));
826 }
827 
dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy * phy,bool enable)828 static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
829 {
830 	void __iomem *lane_base = phy->lane_base;
831 	int phy_lane_0 = 0;	/* TODO: Support all lane swap configs */
832 
833 	/*
834 	 * LPRX and CDRX need to enabled only for physical data lane
835 	 * corresponding to the logical data lane 0
836 	 */
837 	if (enable)
838 		writel(0x3, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0));
839 	else
840 		writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0));
841 }
842 
dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy * phy)843 static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
844 {
845 	int i;
846 	const u8 tx_dctrl_0[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
847 	const u8 tx_dctrl_1[] = { 0x40, 0x40, 0x40, 0x46, 0x41 };
848 	const u8 *tx_dctrl = tx_dctrl_0;
849 	void __iomem *lane_base = phy->lane_base;
850 
851 	if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
852 		tx_dctrl = tx_dctrl_1;
853 
854 	/* Strength ctrl settings */
855 	for (i = 0; i < 5; i++) {
856 		/*
857 		 * Disable LPRX and CDRX for all lanes. And later on, it will
858 		 * be only enabled for the physical data lane corresponding
859 		 * to the logical data lane 0
860 		 */
861 		writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i));
862 		writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i));
863 	}
864 
865 	dsi_phy_hw_v4_0_config_lpcdrx(phy, true);
866 
867 	/* other settings */
868 	for (i = 0; i < 5; i++) {
869 		writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG0(i));
870 		writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG1(i));
871 		writel(i == 4 ? 0x8a : 0xa, lane_base + REG_DSI_7nm_PHY_LN_CFG2(i));
872 		writel(tx_dctrl[i], lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i));
873 	}
874 }
875 
dsi_7nm_phy_enable(struct msm_dsi_phy * phy,struct msm_dsi_phy_clk_request * clk_req)876 static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
877 			      struct msm_dsi_phy_clk_request *clk_req)
878 {
879 	int ret;
880 	u32 status;
881 	u32 const delay_us = 5;
882 	u32 const timeout_us = 1000;
883 	struct msm_dsi_dphy_timing *timing = &phy->timing;
884 	void __iomem *base = phy->base;
885 	bool less_than_1500_mhz;
886 	u32 vreg_ctrl_0, vreg_ctrl_1, lane_ctrl0;
887 	u32 glbl_pemph_ctrl_0;
888 	u32 glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0;
889 	u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl;
890 	u32 data;
891 
892 	DBG("");
893 
894 	if (phy->cphy_mode)
895 		ret = msm_dsi_cphy_timing_calc_v4(timing, clk_req);
896 	else
897 		ret = msm_dsi_dphy_timing_calc_v4(timing, clk_req);
898 	if (ret) {
899 		DRM_DEV_ERROR(&phy->pdev->dev,
900 			      "%s: PHY timing calculation failed\n", __func__);
901 		return -EINVAL;
902 	}
903 
904 	if (dsi_phy_hw_v4_0_is_pll_on(phy))
905 		pr_warn("PLL turned on before configuring PHY\n");
906 
907 	/* Request for REFGEN READY */
908 	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
909 	    (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
910 		writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
911 		udelay(500);
912 	}
913 
914 	/* wait for REFGEN READY */
915 	ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS,
916 					status, (status & BIT(0)),
917 					delay_us, timeout_us);
918 	if (ret) {
919 		pr_err("Ref gen not ready. Aborting\n");
920 		return -EINVAL;
921 	}
922 
923 	/* TODO: CPHY enable path (this is for DPHY only) */
924 
925 	/* Alter PHY configurations if data rate less than 1.5GHZ*/
926 	less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
927 
928 	glbl_str_swi_cal_sel_ctrl = 0x00;
929 	if (phy->cphy_mode) {
930 		vreg_ctrl_0 = 0x51;
931 		vreg_ctrl_1 = 0x55;
932 		glbl_hstx_str_ctrl_0 = 0x00;
933 		glbl_pemph_ctrl_0 = 0x11;
934 		lane_ctrl0 = 0x17;
935 	} else {
936 		vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
937 		vreg_ctrl_1 = 0x5c;
938 		glbl_hstx_str_ctrl_0 = 0x88;
939 		glbl_pemph_ctrl_0 = 0x00;
940 		lane_ctrl0 = 0x1f;
941 	}
942 
943 	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
944 		if (phy->cphy_mode) {
945 			vreg_ctrl_0 = 0x45;
946 			vreg_ctrl_1 = 0x41;
947 			glbl_rescode_top_ctrl = 0x00;
948 			glbl_rescode_bot_ctrl = 0x00;
949 		} else {
950 			vreg_ctrl_0 = 0x44;
951 			vreg_ctrl_1 = 0x19;
952 			glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c :  0x03;
953 			glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 :  0x3c;
954 		}
955 	} else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
956 		if (phy->cphy_mode) {
957 			glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x01;
958 			glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 :  0x3b;
959 		} else {
960 			glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x01;
961 			glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 :  0x39;
962 		}
963 	} else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) {
964 		if (phy->cphy_mode) {
965 			glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x01;
966 			glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 :  0x3b;
967 		} else {
968 			glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c :  0x00;
969 			glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 :  0x39;
970 		}
971 	} else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
972 		if (phy->cphy_mode) {
973 			glbl_hstx_str_ctrl_0 = 0x88;
974 			glbl_rescode_top_ctrl = 0x00;
975 			glbl_rescode_bot_ctrl = 0x3c;
976 		} else {
977 			glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x00;
978 			glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 :  0x3c;
979 		}
980 	} else {
981 		if (phy->cphy_mode) {
982 			glbl_str_swi_cal_sel_ctrl = 0x03;
983 			glbl_hstx_str_ctrl_0 = 0x66;
984 		} else {
985 			vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
986 			glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
987 			glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
988 		}
989 		glbl_rescode_top_ctrl = 0x03;
990 		glbl_rescode_bot_ctrl = 0x3c;
991 	}
992 
993 	/* de-assert digital and pll power down */
994 	data = BIT(6) | BIT(5);
995 	writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
996 
997 	/* Assert PLL core reset */
998 	writel(0x00, base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
999 
1000 	/* turn off resync FIFO */
1001 	writel(0x00, base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL);
1002 
1003 	/* program CMN_CTRL_4 for minor_ver 2 chipsets*/
1004 	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
1005 	    (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
1006 		writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4);
1007 
1008 	/* Configure PHY lane swap (TODO: we need to calculate this) */
1009 	writel(0x21, base + REG_DSI_7nm_PHY_CMN_LANE_CFG0);
1010 	writel(0x84, base + REG_DSI_7nm_PHY_CMN_LANE_CFG1);
1011 
1012 	if (phy->cphy_mode)
1013 		writel(BIT(6), base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL);
1014 
1015 	/* Enable LDO */
1016 	writel(vreg_ctrl_0, base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0);
1017 	writel(vreg_ctrl_1, base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1);
1018 
1019 	writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_3);
1020 	writel(glbl_str_swi_cal_sel_ctrl,
1021 	       base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL);
1022 	writel(glbl_hstx_str_ctrl_0,
1023 	       base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0);
1024 	writel(glbl_pemph_ctrl_0,
1025 	       base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0);
1026 	if (phy->cphy_mode)
1027 		writel(0x01, base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1);
1028 	writel(glbl_rescode_top_ctrl,
1029 	       base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL);
1030 	writel(glbl_rescode_bot_ctrl,
1031 	       base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL);
1032 	writel(0x55, base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL);
1033 
1034 	/* Remove power down from all blocks */
1035 	writel(0x7f, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
1036 
1037 	writel(lane_ctrl0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0);
1038 
1039 	/* Select full-rate mode */
1040 	if (!phy->cphy_mode)
1041 		writel(0x40, base + REG_DSI_7nm_PHY_CMN_CTRL_2);
1042 
1043 	ret = dsi_7nm_set_usecase(phy);
1044 	if (ret) {
1045 		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
1046 			__func__, ret);
1047 		return ret;
1048 	}
1049 
1050 	/* DSI PHY timings */
1051 	if (phy->cphy_mode) {
1052 		writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0);
1053 		writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4);
1054 		writel(timing->shared_timings.clk_pre,
1055 		       base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5);
1056 		writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6);
1057 		writel(timing->shared_timings.clk_post,
1058 		       base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7);
1059 		writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8);
1060 		writel(0x02, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9);
1061 		writel(0x04, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10);
1062 		writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11);
1063 	} else {
1064 		writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0);
1065 		writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1);
1066 		writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2);
1067 		writel(timing->clk_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3);
1068 		writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4);
1069 		writel(timing->hs_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5);
1070 		writel(timing->hs_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6);
1071 		writel(timing->hs_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7);
1072 		writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8);
1073 		writel(0x02, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9);
1074 		writel(0x04, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10);
1075 		writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11);
1076 		writel(timing->shared_timings.clk_pre,
1077 		       base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12);
1078 		writel(timing->shared_timings.clk_post,
1079 		       base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13);
1080 	}
1081 
1082 	/* DSI lane settings */
1083 	dsi_phy_hw_v4_0_lane_settings(phy);
1084 
1085 	DBG("DSI%d PHY enabled", phy->id);
1086 
1087 	return 0;
1088 }
1089 
dsi_7nm_set_continuous_clock(struct msm_dsi_phy * phy,bool enable)1090 static bool dsi_7nm_set_continuous_clock(struct msm_dsi_phy *phy, bool enable)
1091 {
1092 	void __iomem *base = phy->base;
1093 	u32 data;
1094 
1095 	data = readl(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1);
1096 	if (enable)
1097 		data |= BIT(5) | BIT(6);
1098 	else
1099 		data &= ~(BIT(5) | BIT(6));
1100 	writel(data, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1);
1101 
1102 	return enable;
1103 }
1104 
dsi_7nm_phy_disable(struct msm_dsi_phy * phy)1105 static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
1106 {
1107 	void __iomem *base = phy->base;
1108 	u32 data;
1109 
1110 	DBG("");
1111 
1112 	if (dsi_phy_hw_v4_0_is_pll_on(phy))
1113 		pr_warn("Turning OFF PHY while PLL is on\n");
1114 
1115 	dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
1116 
1117 	/* Turn off REFGEN Vote */
1118 	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
1119 	    (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
1120 		writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
1121 		wmb();
1122 		/* Delay to ensure HW removes vote before PHY shut down */
1123 		udelay(2);
1124 	}
1125 
1126 	data = readl(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
1127 
1128 	/* disable all lanes */
1129 	data &= ~0x1F;
1130 	writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
1131 	writel(0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0);
1132 
1133 	/* Turn off all PHY blocks */
1134 	writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
1135 	/* make sure phy is turned off */
1136 	wmb();
1137 
1138 	DBG("DSI%d PHY disabled", phy->id);
1139 }
1140 
1141 static const struct regulator_bulk_data dsi_phy_7nm_36mA_regulators[] = {
1142 	{ .supply = "vdds", .init_load_uA = 36000 },
1143 };
1144 
1145 static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = {
1146 	{ .supply = "vdds", .init_load_uA = 37550 },
1147 };
1148 
1149 static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = {
1150 	{ .supply = "vdds", .init_load_uA = 98000 },
1151 };
1152 
1153 static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
1154 	{ .supply = "vdds", .init_load_uA = 97800 },
1155 };
1156 
1157 static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = {
1158 	{ .supply = "vdds", .init_load_uA = 98400 },
1159 };
1160 
1161 const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
1162 	.has_phy_lane = true,
1163 	.regulator_data = dsi_phy_7nm_36mA_regulators,
1164 	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators),
1165 	.ops = {
1166 		.enable = dsi_7nm_phy_enable,
1167 		.disable = dsi_7nm_phy_disable,
1168 		.pll_init = dsi_pll_7nm_init,
1169 		.save_pll_state = dsi_7nm_pll_save_state,
1170 		.restore_pll_state = dsi_7nm_pll_restore_state,
1171 		.set_continuous_clock = dsi_7nm_set_continuous_clock,
1172 	},
1173 	.min_pll_rate = 600000000UL,
1174 #ifdef CONFIG_64BIT
1175 	.max_pll_rate = 5000000000UL,
1176 #else
1177 	.max_pll_rate = ULONG_MAX,
1178 #endif
1179 	.io_start = { 0xae94400, 0xae96400 },
1180 	.num_dsi_phy = 2,
1181 	.quirks = DSI_PHY_7NM_QUIRK_V4_1,
1182 };
1183 
1184 const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs = {
1185 	.has_phy_lane = true,
1186 	.ops = {
1187 		.enable = dsi_7nm_phy_enable,
1188 		.disable = dsi_7nm_phy_disable,
1189 		.pll_init = dsi_pll_7nm_init,
1190 		.save_pll_state = dsi_7nm_pll_save_state,
1191 		.restore_pll_state = dsi_7nm_pll_restore_state,
1192 	},
1193 	.min_pll_rate = 600000000UL,
1194 #ifdef CONFIG_64BIT
1195 	.max_pll_rate = 5000000000ULL,
1196 #else
1197 	.max_pll_rate = ULONG_MAX,
1198 #endif
1199 	.io_start = { 0x5e94400 },
1200 	.num_dsi_phy = 1,
1201 	.quirks = DSI_PHY_7NM_QUIRK_V4_1,
1202 };
1203 
1204 const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
1205 	.has_phy_lane = true,
1206 	.regulator_data = dsi_phy_7nm_36mA_regulators,
1207 	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_36mA_regulators),
1208 	.ops = {
1209 		.enable = dsi_7nm_phy_enable,
1210 		.disable = dsi_7nm_phy_disable,
1211 		.pll_init = dsi_pll_7nm_init,
1212 		.save_pll_state = dsi_7nm_pll_save_state,
1213 		.restore_pll_state = dsi_7nm_pll_restore_state,
1214 		.set_continuous_clock = dsi_7nm_set_continuous_clock,
1215 	},
1216 	.min_pll_rate = 1000000000UL,
1217 	.max_pll_rate = 3500000000UL,
1218 	.io_start = { 0xae94400, 0xae96400 },
1219 	.num_dsi_phy = 2,
1220 	.quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1,
1221 };
1222 
1223 const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
1224 	.has_phy_lane = true,
1225 	.regulator_data = dsi_phy_7nm_37750uA_regulators,
1226 	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators),
1227 	.ops = {
1228 		.enable = dsi_7nm_phy_enable,
1229 		.disable = dsi_7nm_phy_disable,
1230 		.pll_init = dsi_pll_7nm_init,
1231 		.save_pll_state = dsi_7nm_pll_save_state,
1232 		.restore_pll_state = dsi_7nm_pll_restore_state,
1233 	},
1234 	.min_pll_rate = 600000000UL,
1235 #ifdef CONFIG_64BIT
1236 	.max_pll_rate = 5000000000ULL,
1237 #else
1238 	.max_pll_rate = ULONG_MAX,
1239 #endif
1240 	.io_start = { 0xae94400 },
1241 	.num_dsi_phy = 1,
1242 	.quirks = DSI_PHY_7NM_QUIRK_V4_1,
1243 };
1244 
1245 const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = {
1246 	.has_phy_lane = true,
1247 	.regulator_data = dsi_phy_7nm_37750uA_regulators,
1248 	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators),
1249 	.ops = {
1250 		.enable = dsi_7nm_phy_enable,
1251 		.disable = dsi_7nm_phy_disable,
1252 		.pll_init = dsi_pll_7nm_init,
1253 		.save_pll_state = dsi_7nm_pll_save_state,
1254 		.restore_pll_state = dsi_7nm_pll_restore_state,
1255 		.set_continuous_clock = dsi_7nm_set_continuous_clock,
1256 	},
1257 	.min_pll_rate = 600000000UL,
1258 #ifdef CONFIG_64BIT
1259 	.max_pll_rate = 5000000000UL,
1260 #else
1261 	.max_pll_rate = ULONG_MAX,
1262 #endif
1263 	.io_start = { 0xae94400, 0xae96400 },
1264 	.num_dsi_phy = 2,
1265 	.quirks = DSI_PHY_7NM_QUIRK_V4_2,
1266 };
1267 
1268 const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
1269 	.has_phy_lane = true,
1270 	.regulator_data = dsi_phy_7nm_97800uA_regulators,
1271 	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators),
1272 	.ops = {
1273 		.enable = dsi_7nm_phy_enable,
1274 		.disable = dsi_7nm_phy_disable,
1275 		.pll_init = dsi_pll_7nm_init,
1276 		.save_pll_state = dsi_7nm_pll_save_state,
1277 		.restore_pll_state = dsi_7nm_pll_restore_state,
1278 		.set_continuous_clock = dsi_7nm_set_continuous_clock,
1279 	},
1280 	.min_pll_rate = 600000000UL,
1281 #ifdef CONFIG_64BIT
1282 	.max_pll_rate = 5000000000UL,
1283 #else
1284 	.max_pll_rate = ULONG_MAX,
1285 #endif
1286 	.io_start = { 0xae94400, 0xae96400 },
1287 	.num_dsi_phy = 2,
1288 	.quirks = DSI_PHY_7NM_QUIRK_V4_3,
1289 };
1290 
1291 const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
1292 	.has_phy_lane = true,
1293 	.regulator_data = dsi_phy_7nm_98400uA_regulators,
1294 	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators),
1295 	.ops = {
1296 		.enable = dsi_7nm_phy_enable,
1297 		.disable = dsi_7nm_phy_disable,
1298 		.pll_init = dsi_pll_7nm_init,
1299 		.save_pll_state = dsi_7nm_pll_save_state,
1300 		.restore_pll_state = dsi_7nm_pll_restore_state,
1301 		.set_continuous_clock = dsi_7nm_set_continuous_clock,
1302 	},
1303 	.min_pll_rate = 600000000UL,
1304 #ifdef CONFIG_64BIT
1305 	.max_pll_rate = 5000000000UL,
1306 #else
1307 	.max_pll_rate = ULONG_MAX,
1308 #endif
1309 	.io_start = { 0xae95000, 0xae97000 },
1310 	.num_dsi_phy = 2,
1311 	.quirks = DSI_PHY_7NM_QUIRK_V5_2,
1312 };
1313 
1314 const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {
1315 	.has_phy_lane = true,
1316 	.regulator_data = dsi_phy_7nm_98000uA_regulators,
1317 	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
1318 	.ops = {
1319 		.enable = dsi_7nm_phy_enable,
1320 		.disable = dsi_7nm_phy_disable,
1321 		.pll_init = dsi_pll_7nm_init,
1322 		.save_pll_state = dsi_7nm_pll_save_state,
1323 		.restore_pll_state = dsi_7nm_pll_restore_state,
1324 		.set_continuous_clock = dsi_7nm_set_continuous_clock,
1325 	},
1326 	.min_pll_rate = 600000000UL,
1327 #ifdef CONFIG_64BIT
1328 	.max_pll_rate = 5000000000UL,
1329 #else
1330 	.max_pll_rate = ULONG_MAX,
1331 #endif
1332 	.io_start = { 0xae95000, 0xae97000 },
1333 	.num_dsi_phy = 2,
1334 	.quirks = DSI_PHY_7NM_QUIRK_V5_2,
1335 };
1336