1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com> 4 */ 5 6/ { 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 cpus { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 timebase-frequency = <50000000>; 14 15 cpu0: cpu@0 { 16 compatible = "thead,c920", "riscv"; 17 reg = <0>; 18 i-cache-block-size = <64>; 19 i-cache-size = <65536>; 20 i-cache-sets = <512>; 21 d-cache-block-size = <64>; 22 d-cache-size = <65536>; 23 d-cache-sets = <512>; 24 device_type = "cpu"; 25 mmu-type = "riscv,sv48"; 26 next-level-cache = <&l2_cache0>; 27 riscv,isa = "rv64imafdcv"; 28 riscv,isa-base = "rv64i"; 29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 30 "v", "sscofpmf", "sstc", 31 "svinval", "svnapot", "svpbmt", 32 "zawrs", "zba", "zbb", "zbc", 33 "zbs", "zca", "zcb", "zcd", 34 "zfa", "zfbfmin", "zfh", "zfhmin", 35 "zicbom", "zicbop", "zicboz", "ziccrse", 36 "zicntr", "zicond","zicsr", "zifencei", 37 "zihintntl", "zihintpause", "zihpm", 38 "zvfbfmin", "zvfbfwma", "zvfh", 39 "zvfhmin"; 40 riscv,cbom-block-size = <64>; 41 riscv,cbop-block-size = <64>; 42 riscv,cboz-block-size = <64>; 43 44 cpu0_intc: interrupt-controller { 45 compatible = "riscv,cpu-intc"; 46 interrupt-controller; 47 #interrupt-cells = <1>; 48 }; 49 }; 50 51 cpu1: cpu@1 { 52 compatible = "thead,c920", "riscv"; 53 reg = <1>; 54 i-cache-block-size = <64>; 55 i-cache-size = <65536>; 56 i-cache-sets = <512>; 57 d-cache-block-size = <64>; 58 d-cache-size = <65536>; 59 d-cache-sets = <512>; 60 device_type = "cpu"; 61 mmu-type = "riscv,sv48"; 62 next-level-cache = <&l2_cache0>; 63 riscv,isa = "rv64imafdcv"; 64 riscv,isa-base = "rv64i"; 65 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 66 "v", "sscofpmf", "sstc", 67 "svinval", "svnapot", "svpbmt", 68 "zawrs", "zba", "zbb", "zbc", 69 "zbs", "zca", "zcb", "zcd", 70 "zfa", "zfbfmin", "zfh", "zfhmin", 71 "zicbom", "zicbop", "zicboz", "ziccrse", 72 "zicntr", "zicond","zicsr", "zifencei", 73 "zihintntl", "zihintpause", "zihpm", 74 "zvfbfmin", "zvfbfwma", "zvfh", 75 "zvfhmin"; 76 riscv,cbom-block-size = <64>; 77 riscv,cbop-block-size = <64>; 78 riscv,cboz-block-size = <64>; 79 80 cpu1_intc: interrupt-controller { 81 compatible = "riscv,cpu-intc"; 82 interrupt-controller; 83 #interrupt-cells = <1>; 84 }; 85 }; 86 87 cpu2: cpu@2 { 88 compatible = "thead,c920", "riscv"; 89 reg = <2>; 90 i-cache-block-size = <64>; 91 i-cache-size = <65536>; 92 i-cache-sets = <512>; 93 d-cache-block-size = <64>; 94 d-cache-size = <65536>; 95 d-cache-sets = <512>; 96 device_type = "cpu"; 97 mmu-type = "riscv,sv48"; 98 next-level-cache = <&l2_cache0>; 99 riscv,isa = "rv64imafdcv"; 100 riscv,isa-base = "rv64i"; 101 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 102 "v", "sscofpmf", "sstc", 103 "svinval", "svnapot", "svpbmt", 104 "zawrs", "zba", "zbb", "zbc", 105 "zbs", "zca", "zcb", "zcd", 106 "zfa", "zfbfmin", "zfh", "zfhmin", 107 "zicbom", "zicbop", "zicboz", "ziccrse", 108 "zicntr", "zicond","zicsr", "zifencei", 109 "zihintntl", "zihintpause", "zihpm", 110 "zvfbfmin", "zvfbfwma", "zvfh", 111 "zvfhmin"; 112 riscv,cbom-block-size = <64>; 113 riscv,cbop-block-size = <64>; 114 riscv,cboz-block-size = <64>; 115 116 cpu2_intc: interrupt-controller { 117 compatible = "riscv,cpu-intc"; 118 interrupt-controller; 119 #interrupt-cells = <1>; 120 }; 121 }; 122 123 cpu3: cpu@3 { 124 compatible = "thead,c920", "riscv"; 125 reg = <3>; 126 i-cache-block-size = <64>; 127 i-cache-size = <65536>; 128 i-cache-sets = <512>; 129 d-cache-block-size = <64>; 130 d-cache-size = <65536>; 131 d-cache-sets = <512>; 132 device_type = "cpu"; 133 mmu-type = "riscv,sv48"; 134 next-level-cache = <&l2_cache0>; 135 riscv,isa = "rv64imafdcv"; 136 riscv,isa-base = "rv64i"; 137 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 138 "v", "sscofpmf", "sstc", 139 "svinval", "svnapot", "svpbmt", 140 "zawrs", "zba", "zbb", "zbc", 141 "zbs", "zca", "zcb", "zcd", 142 "zfa", "zfbfmin", "zfh", "zfhmin", 143 "zicbom", "zicbop", "zicboz", "ziccrse", 144 "zicntr", "zicond","zicsr", "zifencei", 145 "zihintntl", "zihintpause", "zihpm", 146 "zvfbfmin", "zvfbfwma", "zvfh", 147 "zvfhmin"; 148 riscv,cbom-block-size = <64>; 149 riscv,cbop-block-size = <64>; 150 riscv,cboz-block-size = <64>; 151 152 cpu3_intc: interrupt-controller { 153 compatible = "riscv,cpu-intc"; 154 interrupt-controller; 155 #interrupt-cells = <1>; 156 }; 157 }; 158 159 cpu4: cpu@4 { 160 compatible = "thead,c920", "riscv"; 161 reg = <4>; 162 i-cache-block-size = <64>; 163 i-cache-size = <65536>; 164 i-cache-sets = <512>; 165 d-cache-block-size = <64>; 166 d-cache-size = <65536>; 167 d-cache-sets = <512>; 168 device_type = "cpu"; 169 mmu-type = "riscv,sv48"; 170 next-level-cache = <&l2_cache1>; 171 riscv,isa = "rv64imafdcv"; 172 riscv,isa-base = "rv64i"; 173 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 174 "v", "sscofpmf", "sstc", 175 "svinval", "svnapot", "svpbmt", 176 "zawrs", "zba", "zbb", "zbc", 177 "zbs", "zca", "zcb", "zcd", 178 "zfa", "zfbfmin", "zfh", "zfhmin", 179 "zicbom", "zicbop", "zicboz", "ziccrse", 180 "zicntr", "zicond","zicsr", "zifencei", 181 "zihintntl", "zihintpause", "zihpm", 182 "zvfbfmin", "zvfbfwma", "zvfh", 183 "zvfhmin"; 184 riscv,cbom-block-size = <64>; 185 riscv,cbop-block-size = <64>; 186 riscv,cboz-block-size = <64>; 187 188 cpu4_intc: interrupt-controller { 189 compatible = "riscv,cpu-intc"; 190 interrupt-controller; 191 #interrupt-cells = <1>; 192 }; 193 }; 194 195 cpu5: cpu@5 { 196 compatible = "thead,c920", "riscv"; 197 reg = <5>; 198 i-cache-block-size = <64>; 199 i-cache-size = <65536>; 200 i-cache-sets = <512>; 201 d-cache-block-size = <64>; 202 d-cache-size = <65536>; 203 d-cache-sets = <512>; 204 device_type = "cpu"; 205 mmu-type = "riscv,sv48"; 206 next-level-cache = <&l2_cache1>; 207 riscv,isa = "rv64imafdcv"; 208 riscv,isa-base = "rv64i"; 209 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 210 "v", "sscofpmf", "sstc", 211 "svinval", "svnapot", "svpbmt", 212 "zawrs", "zba", "zbb", "zbc", 213 "zbs", "zca", "zcb", "zcd", 214 "zfa", "zfbfmin", "zfh", "zfhmin", 215 "zicbom", "zicbop", "zicboz", "ziccrse", 216 "zicntr", "zicond","zicsr", "zifencei", 217 "zihintntl", "zihintpause", "zihpm", 218 "zvfbfmin", "zvfbfwma", "zvfh", 219 "zvfhmin"; 220 riscv,cbom-block-size = <64>; 221 riscv,cbop-block-size = <64>; 222 riscv,cboz-block-size = <64>; 223 224 cpu5_intc: interrupt-controller { 225 compatible = "riscv,cpu-intc"; 226 interrupt-controller; 227 #interrupt-cells = <1>; 228 }; 229 }; 230 231 cpu6: cpu@6 { 232 compatible = "thead,c920", "riscv"; 233 reg = <6>; 234 i-cache-block-size = <64>; 235 i-cache-size = <65536>; 236 i-cache-sets = <512>; 237 d-cache-block-size = <64>; 238 d-cache-size = <65536>; 239 d-cache-sets = <512>; 240 device_type = "cpu"; 241 mmu-type = "riscv,sv48"; 242 next-level-cache = <&l2_cache1>; 243 riscv,isa = "rv64imafdcv"; 244 riscv,isa-base = "rv64i"; 245 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 246 "v", "sscofpmf", "sstc", 247 "svinval", "svnapot", "svpbmt", 248 "zawrs", "zba", "zbb", "zbc", 249 "zbs", "zca", "zcb", "zcd", 250 "zfa", "zfbfmin", "zfh", "zfhmin", 251 "zicbom", "zicbop", "zicboz", "ziccrse", 252 "zicntr", "zicond","zicsr", "zifencei", 253 "zihintntl", "zihintpause", "zihpm", 254 "zvfbfmin", "zvfbfwma", "zvfh", 255 "zvfhmin"; 256 riscv,cbom-block-size = <64>; 257 riscv,cbop-block-size = <64>; 258 riscv,cboz-block-size = <64>; 259 260 cpu6_intc: interrupt-controller { 261 compatible = "riscv,cpu-intc"; 262 interrupt-controller; 263 #interrupt-cells = <1>; 264 }; 265 }; 266 267 cpu7: cpu@7 { 268 compatible = "thead,c920", "riscv"; 269 reg = <7>; 270 i-cache-block-size = <64>; 271 i-cache-size = <65536>; 272 i-cache-sets = <512>; 273 d-cache-block-size = <64>; 274 d-cache-size = <65536>; 275 d-cache-sets = <512>; 276 device_type = "cpu"; 277 mmu-type = "riscv,sv48"; 278 next-level-cache = <&l2_cache1>; 279 riscv,isa = "rv64imafdcv"; 280 riscv,isa-base = "rv64i"; 281 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 282 "v", "sscofpmf", "sstc", 283 "svinval", "svnapot", "svpbmt", 284 "zawrs", "zba", "zbb", "zbc", 285 "zbs", "zca", "zcb", "zcd", 286 "zfa", "zfbfmin", "zfh", "zfhmin", 287 "zicbom", "zicbop", "zicboz", "ziccrse", 288 "zicntr", "zicond","zicsr", "zifencei", 289 "zihintntl", "zihintpause", "zihpm", 290 "zvfbfmin", "zvfbfwma", "zvfh", 291 "zvfhmin"; 292 riscv,cbom-block-size = <64>; 293 riscv,cbop-block-size = <64>; 294 riscv,cboz-block-size = <64>; 295 296 cpu7_intc: interrupt-controller { 297 compatible = "riscv,cpu-intc"; 298 interrupt-controller; 299 #interrupt-cells = <1>; 300 }; 301 }; 302 303 cpu8: cpu@8 { 304 compatible = "thead,c920", "riscv"; 305 reg = <8>; 306 i-cache-block-size = <64>; 307 i-cache-size = <65536>; 308 i-cache-sets = <512>; 309 d-cache-block-size = <64>; 310 d-cache-size = <65536>; 311 d-cache-sets = <512>; 312 device_type = "cpu"; 313 mmu-type = "riscv,sv48"; 314 next-level-cache = <&l2_cache2>; 315 riscv,isa = "rv64imafdcv"; 316 riscv,isa-base = "rv64i"; 317 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 318 "v", "sscofpmf", "sstc", 319 "svinval", "svnapot", "svpbmt", 320 "zawrs", "zba", "zbb", "zbc", 321 "zbs", "zca", "zcb", "zcd", 322 "zfa", "zfbfmin", "zfh", "zfhmin", 323 "zicbom", "zicbop", "zicboz", "ziccrse", 324 "zicntr", "zicond","zicsr", "zifencei", 325 "zihintntl", "zihintpause", "zihpm", 326 "zvfbfmin", "zvfbfwma", "zvfh", 327 "zvfhmin"; 328 riscv,cbom-block-size = <64>; 329 riscv,cbop-block-size = <64>; 330 riscv,cboz-block-size = <64>; 331 332 cpu8_intc: interrupt-controller { 333 compatible = "riscv,cpu-intc"; 334 interrupt-controller; 335 #interrupt-cells = <1>; 336 }; 337 }; 338 339 cpu9: cpu@9 { 340 compatible = "thead,c920", "riscv"; 341 reg = <9>; 342 i-cache-block-size = <64>; 343 i-cache-size = <65536>; 344 i-cache-sets = <512>; 345 d-cache-block-size = <64>; 346 d-cache-size = <65536>; 347 d-cache-sets = <512>; 348 device_type = "cpu"; 349 mmu-type = "riscv,sv48"; 350 next-level-cache = <&l2_cache2>; 351 riscv,isa = "rv64imafdcv"; 352 riscv,isa-base = "rv64i"; 353 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 354 "v", "sscofpmf", "sstc", 355 "svinval", "svnapot", "svpbmt", 356 "zawrs", "zba", "zbb", "zbc", 357 "zbs", "zca", "zcb", "zcd", 358 "zfa", "zfbfmin", "zfh", "zfhmin", 359 "zicbom", "zicbop", "zicboz", "ziccrse", 360 "zicntr", "zicond","zicsr", "zifencei", 361 "zihintntl", "zihintpause", "zihpm", 362 "zvfbfmin", "zvfbfwma", "zvfh", 363 "zvfhmin"; 364 riscv,cbom-block-size = <64>; 365 riscv,cbop-block-size = <64>; 366 riscv,cboz-block-size = <64>; 367 368 cpu9_intc: interrupt-controller { 369 compatible = "riscv,cpu-intc"; 370 interrupt-controller; 371 #interrupt-cells = <1>; 372 }; 373 }; 374 375 cpu10: cpu@10 { 376 compatible = "thead,c920", "riscv"; 377 reg = <10>; 378 i-cache-block-size = <64>; 379 i-cache-size = <65536>; 380 i-cache-sets = <512>; 381 d-cache-block-size = <64>; 382 d-cache-size = <65536>; 383 d-cache-sets = <512>; 384 device_type = "cpu"; 385 mmu-type = "riscv,sv48"; 386 next-level-cache = <&l2_cache2>; 387 riscv,isa = "rv64imafdcv"; 388 riscv,isa-base = "rv64i"; 389 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 390 "v", "sscofpmf", "sstc", 391 "svinval", "svnapot", "svpbmt", 392 "zawrs", "zba", "zbb", "zbc", 393 "zbs", "zca", "zcb", "zcd", 394 "zfa", "zfbfmin", "zfh", "zfhmin", 395 "zicbom", "zicbop", "zicboz", "ziccrse", 396 "zicntr", "zicond","zicsr", "zifencei", 397 "zihintntl", "zihintpause", "zihpm", 398 "zvfbfmin", "zvfbfwma", "zvfh", 399 "zvfhmin"; 400 riscv,cbom-block-size = <64>; 401 riscv,cbop-block-size = <64>; 402 riscv,cboz-block-size = <64>; 403 404 cpu10_intc: interrupt-controller { 405 compatible = "riscv,cpu-intc"; 406 interrupt-controller; 407 #interrupt-cells = <1>; 408 }; 409 }; 410 411 cpu11: cpu@11 { 412 compatible = "thead,c920", "riscv"; 413 reg = <11>; 414 i-cache-block-size = <64>; 415 i-cache-size = <65536>; 416 i-cache-sets = <512>; 417 d-cache-block-size = <64>; 418 d-cache-size = <65536>; 419 d-cache-sets = <512>; 420 device_type = "cpu"; 421 mmu-type = "riscv,sv48"; 422 next-level-cache = <&l2_cache2>; 423 riscv,isa = "rv64imafdcv"; 424 riscv,isa-base = "rv64i"; 425 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 426 "v", "sscofpmf", "sstc", 427 "svinval", "svnapot", "svpbmt", 428 "zawrs", "zba", "zbb", "zbc", 429 "zbs", "zca", "zcb", "zcd", 430 "zfa", "zfbfmin", "zfh", "zfhmin", 431 "zicbom", "zicbop", "zicboz", "ziccrse", 432 "zicntr", "zicond","zicsr", "zifencei", 433 "zihintntl", "zihintpause", "zihpm", 434 "zvfbfmin", "zvfbfwma", "zvfh", 435 "zvfhmin"; 436 riscv,cbom-block-size = <64>; 437 riscv,cbop-block-size = <64>; 438 riscv,cboz-block-size = <64>; 439 440 cpu11_intc: interrupt-controller { 441 compatible = "riscv,cpu-intc"; 442 interrupt-controller; 443 #interrupt-cells = <1>; 444 }; 445 }; 446 447 cpu12: cpu@12 { 448 compatible = "thead,c920", "riscv"; 449 reg = <12>; 450 i-cache-block-size = <64>; 451 i-cache-size = <65536>; 452 i-cache-sets = <512>; 453 d-cache-block-size = <64>; 454 d-cache-size = <65536>; 455 d-cache-sets = <512>; 456 device_type = "cpu"; 457 mmu-type = "riscv,sv48"; 458 next-level-cache = <&l2_cache3>; 459 riscv,isa = "rv64imafdcv"; 460 riscv,isa-base = "rv64i"; 461 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 462 "v", "sscofpmf", "sstc", 463 "svinval", "svnapot", "svpbmt", 464 "zawrs", "zba", "zbb", "zbc", 465 "zbs", "zca", "zcb", "zcd", 466 "zfa", "zfbfmin", "zfh", "zfhmin", 467 "zicbom", "zicbop", "zicboz", "ziccrse", 468 "zicntr", "zicond","zicsr", "zifencei", 469 "zihintntl", "zihintpause", "zihpm", 470 "zvfbfmin", "zvfbfwma", "zvfh", 471 "zvfhmin"; 472 riscv,cbom-block-size = <64>; 473 riscv,cbop-block-size = <64>; 474 riscv,cboz-block-size = <64>; 475 476 cpu12_intc: interrupt-controller { 477 compatible = "riscv,cpu-intc"; 478 interrupt-controller; 479 #interrupt-cells = <1>; 480 }; 481 }; 482 483 cpu13: cpu@13 { 484 compatible = "thead,c920", "riscv"; 485 reg = <13>; 486 i-cache-block-size = <64>; 487 i-cache-size = <65536>; 488 i-cache-sets = <512>; 489 d-cache-block-size = <64>; 490 d-cache-size = <65536>; 491 d-cache-sets = <512>; 492 device_type = "cpu"; 493 mmu-type = "riscv,sv48"; 494 next-level-cache = <&l2_cache3>; 495 riscv,isa = "rv64imafdcv"; 496 riscv,isa-base = "rv64i"; 497 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 498 "v", "sscofpmf", "sstc", 499 "svinval", "svnapot", "svpbmt", 500 "zawrs", "zba", "zbb", "zbc", 501 "zbs", "zca", "zcb", "zcd", 502 "zfa", "zfbfmin", "zfh", "zfhmin", 503 "zicbom", "zicbop", "zicboz", "ziccrse", 504 "zicntr", "zicond","zicsr", "zifencei", 505 "zihintntl", "zihintpause", "zihpm", 506 "zvfbfmin", "zvfbfwma", "zvfh", 507 "zvfhmin"; 508 riscv,cbom-block-size = <64>; 509 riscv,cbop-block-size = <64>; 510 riscv,cboz-block-size = <64>; 511 512 cpu13_intc: interrupt-controller { 513 compatible = "riscv,cpu-intc"; 514 interrupt-controller; 515 #interrupt-cells = <1>; 516 }; 517 }; 518 519 cpu14: cpu@14 { 520 compatible = "thead,c920", "riscv"; 521 reg = <14>; 522 i-cache-block-size = <64>; 523 i-cache-size = <65536>; 524 i-cache-sets = <512>; 525 d-cache-block-size = <64>; 526 d-cache-size = <65536>; 527 d-cache-sets = <512>; 528 device_type = "cpu"; 529 mmu-type = "riscv,sv48"; 530 next-level-cache = <&l2_cache3>; 531 riscv,isa = "rv64imafdcv"; 532 riscv,isa-base = "rv64i"; 533 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 534 "v", "sscofpmf", "sstc", 535 "svinval", "svnapot", "svpbmt", 536 "zawrs", "zba", "zbb", "zbc", 537 "zbs", "zca", "zcb", "zcd", 538 "zfa", "zfbfmin", "zfh", "zfhmin", 539 "zicbom", "zicbop", "zicboz", "ziccrse", 540 "zicntr", "zicond","zicsr", "zifencei", 541 "zihintntl", "zihintpause", "zihpm", 542 "zvfbfmin", "zvfbfwma", "zvfh", 543 "zvfhmin"; 544 riscv,cbom-block-size = <64>; 545 riscv,cbop-block-size = <64>; 546 riscv,cboz-block-size = <64>; 547 548 cpu14_intc: interrupt-controller { 549 compatible = "riscv,cpu-intc"; 550 interrupt-controller; 551 #interrupt-cells = <1>; 552 }; 553 }; 554 555 cpu15: cpu@15 { 556 compatible = "thead,c920", "riscv"; 557 reg = <15>; 558 i-cache-block-size = <64>; 559 i-cache-size = <65536>; 560 i-cache-sets = <512>; 561 d-cache-block-size = <64>; 562 d-cache-size = <65536>; 563 d-cache-sets = <512>; 564 device_type = "cpu"; 565 mmu-type = "riscv,sv48"; 566 next-level-cache = <&l2_cache3>; 567 riscv,isa = "rv64imafdcv"; 568 riscv,isa-base = "rv64i"; 569 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 570 "v", "sscofpmf", "sstc", 571 "svinval", "svnapot", "svpbmt", 572 "zawrs", "zba", "zbb", "zbc", 573 "zbs", "zca", "zcb", "zcd", 574 "zfa", "zfbfmin", "zfh", "zfhmin", 575 "zicbom", "zicbop", "zicboz", "ziccrse", 576 "zicntr", "zicond","zicsr", "zifencei", 577 "zihintntl", "zihintpause", "zihpm", 578 "zvfbfmin", "zvfbfwma", "zvfh", 579 "zvfhmin"; 580 riscv,cbom-block-size = <64>; 581 riscv,cbop-block-size = <64>; 582 riscv,cboz-block-size = <64>; 583 584 cpu15_intc: interrupt-controller { 585 compatible = "riscv,cpu-intc"; 586 interrupt-controller; 587 #interrupt-cells = <1>; 588 }; 589 }; 590 591 cpu16: cpu@16 { 592 compatible = "thead,c920", "riscv"; 593 reg = <16>; 594 i-cache-block-size = <64>; 595 i-cache-size = <65536>; 596 i-cache-sets = <512>; 597 d-cache-block-size = <64>; 598 d-cache-size = <65536>; 599 d-cache-sets = <512>; 600 device_type = "cpu"; 601 mmu-type = "riscv,sv48"; 602 next-level-cache = <&l2_cache4>; 603 riscv,isa = "rv64imafdcv"; 604 riscv,isa-base = "rv64i"; 605 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 606 "v", "sscofpmf", "sstc", 607 "svinval", "svnapot", "svpbmt", 608 "zawrs", "zba", "zbb", "zbc", 609 "zbs", "zca", "zcb", "zcd", 610 "zfa", "zfbfmin", "zfh", "zfhmin", 611 "zicbom", "zicbop", "zicboz", "ziccrse", 612 "zicntr", "zicond","zicsr", "zifencei", 613 "zihintntl", "zihintpause", "zihpm", 614 "zvfbfmin", "zvfbfwma", "zvfh", 615 "zvfhmin"; 616 riscv,cbom-block-size = <64>; 617 riscv,cbop-block-size = <64>; 618 riscv,cboz-block-size = <64>; 619 620 cpu16_intc: interrupt-controller { 621 compatible = "riscv,cpu-intc"; 622 interrupt-controller; 623 #interrupt-cells = <1>; 624 }; 625 }; 626 627 cpu17: cpu@17 { 628 compatible = "thead,c920", "riscv"; 629 reg = <17>; 630 i-cache-block-size = <64>; 631 i-cache-size = <65536>; 632 i-cache-sets = <512>; 633 d-cache-block-size = <64>; 634 d-cache-size = <65536>; 635 d-cache-sets = <512>; 636 device_type = "cpu"; 637 mmu-type = "riscv,sv48"; 638 next-level-cache = <&l2_cache4>; 639 riscv,isa = "rv64imafdcv"; 640 riscv,isa-base = "rv64i"; 641 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 642 "v", "sscofpmf", "sstc", 643 "svinval", "svnapot", "svpbmt", 644 "zawrs", "zba", "zbb", "zbc", 645 "zbs", "zca", "zcb", "zcd", 646 "zfa", "zfbfmin", "zfh", "zfhmin", 647 "zicbom", "zicbop", "zicboz", "ziccrse", 648 "zicntr", "zicond","zicsr", "zifencei", 649 "zihintntl", "zihintpause", "zihpm", 650 "zvfbfmin", "zvfbfwma", "zvfh", 651 "zvfhmin"; 652 riscv,cbom-block-size = <64>; 653 riscv,cbop-block-size = <64>; 654 riscv,cboz-block-size = <64>; 655 656 cpu17_intc: interrupt-controller { 657 compatible = "riscv,cpu-intc"; 658 interrupt-controller; 659 #interrupt-cells = <1>; 660 }; 661 }; 662 663 cpu18: cpu@18 { 664 compatible = "thead,c920", "riscv"; 665 reg = <18>; 666 i-cache-block-size = <64>; 667 i-cache-size = <65536>; 668 i-cache-sets = <512>; 669 d-cache-block-size = <64>; 670 d-cache-size = <65536>; 671 d-cache-sets = <512>; 672 device_type = "cpu"; 673 mmu-type = "riscv,sv48"; 674 next-level-cache = <&l2_cache4>; 675 riscv,isa = "rv64imafdcv"; 676 riscv,isa-base = "rv64i"; 677 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 678 "v", "sscofpmf", "sstc", 679 "svinval", "svnapot", "svpbmt", 680 "zawrs", "zba", "zbb", "zbc", 681 "zbs", "zca", "zcb", "zcd", 682 "zfa", "zfbfmin", "zfh", "zfhmin", 683 "zicbom", "zicbop", "zicboz", "ziccrse", 684 "zicntr", "zicond","zicsr", "zifencei", 685 "zihintntl", "zihintpause", "zihpm", 686 "zvfbfmin", "zvfbfwma", "zvfh", 687 "zvfhmin"; 688 riscv,cbom-block-size = <64>; 689 riscv,cbop-block-size = <64>; 690 riscv,cboz-block-size = <64>; 691 692 cpu18_intc: interrupt-controller { 693 compatible = "riscv,cpu-intc"; 694 interrupt-controller; 695 #interrupt-cells = <1>; 696 }; 697 }; 698 699 cpu19: cpu@19 { 700 compatible = "thead,c920", "riscv"; 701 reg = <19>; 702 i-cache-block-size = <64>; 703 i-cache-size = <65536>; 704 i-cache-sets = <512>; 705 d-cache-block-size = <64>; 706 d-cache-size = <65536>; 707 d-cache-sets = <512>; 708 device_type = "cpu"; 709 mmu-type = "riscv,sv48"; 710 next-level-cache = <&l2_cache4>; 711 riscv,isa = "rv64imafdcv"; 712 riscv,isa-base = "rv64i"; 713 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 714 "v", "sscofpmf", "sstc", 715 "svinval", "svnapot", "svpbmt", 716 "zawrs", "zba", "zbb", "zbc", 717 "zbs", "zca", "zcb", "zcd", 718 "zfa", "zfbfmin", "zfh", "zfhmin", 719 "zicbom", "zicbop", "zicboz", "ziccrse", 720 "zicntr", "zicond","zicsr", "zifencei", 721 "zihintntl", "zihintpause", "zihpm", 722 "zvfbfmin", "zvfbfwma", "zvfh", 723 "zvfhmin"; 724 riscv,cbom-block-size = <64>; 725 riscv,cbop-block-size = <64>; 726 riscv,cboz-block-size = <64>; 727 728 cpu19_intc: interrupt-controller { 729 compatible = "riscv,cpu-intc"; 730 interrupt-controller; 731 #interrupt-cells = <1>; 732 }; 733 }; 734 735 cpu20: cpu@20 { 736 compatible = "thead,c920", "riscv"; 737 reg = <20>; 738 i-cache-block-size = <64>; 739 i-cache-size = <65536>; 740 i-cache-sets = <512>; 741 d-cache-block-size = <64>; 742 d-cache-size = <65536>; 743 d-cache-sets = <512>; 744 device_type = "cpu"; 745 mmu-type = "riscv,sv48"; 746 next-level-cache = <&l2_cache5>; 747 riscv,isa = "rv64imafdcv"; 748 riscv,isa-base = "rv64i"; 749 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 750 "v", "sscofpmf", "sstc", 751 "svinval", "svnapot", "svpbmt", 752 "zawrs", "zba", "zbb", "zbc", 753 "zbs", "zca", "zcb", "zcd", 754 "zfa", "zfbfmin", "zfh", "zfhmin", 755 "zicbom", "zicbop", "zicboz", "ziccrse", 756 "zicntr", "zicond","zicsr", "zifencei", 757 "zihintntl", "zihintpause", "zihpm", 758 "zvfbfmin", "zvfbfwma", "zvfh", 759 "zvfhmin"; 760 riscv,cbom-block-size = <64>; 761 riscv,cbop-block-size = <64>; 762 riscv,cboz-block-size = <64>; 763 764 cpu20_intc: interrupt-controller { 765 compatible = "riscv,cpu-intc"; 766 interrupt-controller; 767 #interrupt-cells = <1>; 768 }; 769 }; 770 771 cpu21: cpu@21 { 772 compatible = "thead,c920", "riscv"; 773 reg = <21>; 774 i-cache-block-size = <64>; 775 i-cache-size = <65536>; 776 i-cache-sets = <512>; 777 d-cache-block-size = <64>; 778 d-cache-size = <65536>; 779 d-cache-sets = <512>; 780 device_type = "cpu"; 781 mmu-type = "riscv,sv48"; 782 next-level-cache = <&l2_cache5>; 783 riscv,isa = "rv64imafdcv"; 784 riscv,isa-base = "rv64i"; 785 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 786 "v", "sscofpmf", "sstc", 787 "svinval", "svnapot", "svpbmt", 788 "zawrs", "zba", "zbb", "zbc", 789 "zbs", "zca", "zcb", "zcd", 790 "zfa", "zfbfmin", "zfh", "zfhmin", 791 "zicbom", "zicbop", "zicboz", "ziccrse", 792 "zicntr", "zicond","zicsr", "zifencei", 793 "zihintntl", "zihintpause", "zihpm", 794 "zvfbfmin", "zvfbfwma", "zvfh", 795 "zvfhmin"; 796 riscv,cbom-block-size = <64>; 797 riscv,cbop-block-size = <64>; 798 riscv,cboz-block-size = <64>; 799 800 cpu21_intc: interrupt-controller { 801 compatible = "riscv,cpu-intc"; 802 interrupt-controller; 803 #interrupt-cells = <1>; 804 }; 805 }; 806 807 cpu22: cpu@22 { 808 compatible = "thead,c920", "riscv"; 809 reg = <22>; 810 i-cache-block-size = <64>; 811 i-cache-size = <65536>; 812 i-cache-sets = <512>; 813 d-cache-block-size = <64>; 814 d-cache-size = <65536>; 815 d-cache-sets = <512>; 816 device_type = "cpu"; 817 mmu-type = "riscv,sv48"; 818 next-level-cache = <&l2_cache5>; 819 riscv,isa = "rv64imafdcv"; 820 riscv,isa-base = "rv64i"; 821 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 822 "v", "sscofpmf", "sstc", 823 "svinval", "svnapot", "svpbmt", 824 "zawrs", "zba", "zbb", "zbc", 825 "zbs", "zca", "zcb", "zcd", 826 "zfa", "zfbfmin", "zfh", "zfhmin", 827 "zicbom", "zicbop", "zicboz", "ziccrse", 828 "zicntr", "zicond","zicsr", "zifencei", 829 "zihintntl", "zihintpause", "zihpm", 830 "zvfbfmin", "zvfbfwma", "zvfh", 831 "zvfhmin"; 832 riscv,cbom-block-size = <64>; 833 riscv,cbop-block-size = <64>; 834 riscv,cboz-block-size = <64>; 835 836 cpu22_intc: interrupt-controller { 837 compatible = "riscv,cpu-intc"; 838 interrupt-controller; 839 #interrupt-cells = <1>; 840 }; 841 }; 842 843 cpu23: cpu@23 { 844 compatible = "thead,c920", "riscv"; 845 reg = <23>; 846 i-cache-block-size = <64>; 847 i-cache-size = <65536>; 848 i-cache-sets = <512>; 849 d-cache-block-size = <64>; 850 d-cache-size = <65536>; 851 d-cache-sets = <512>; 852 device_type = "cpu"; 853 mmu-type = "riscv,sv48"; 854 next-level-cache = <&l2_cache5>; 855 riscv,isa = "rv64imafdcv"; 856 riscv,isa-base = "rv64i"; 857 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 858 "v", "sscofpmf", "sstc", 859 "svinval", "svnapot", "svpbmt", 860 "zawrs", "zba", "zbb", "zbc", 861 "zbs", "zca", "zcb", "zcd", 862 "zfa", "zfbfmin", "zfh", "zfhmin", 863 "zicbom", "zicbop", "zicboz", "ziccrse", 864 "zicntr", "zicond","zicsr", "zifencei", 865 "zihintntl", "zihintpause", "zihpm", 866 "zvfbfmin", "zvfbfwma", "zvfh", 867 "zvfhmin"; 868 riscv,cbom-block-size = <64>; 869 riscv,cbop-block-size = <64>; 870 riscv,cboz-block-size = <64>; 871 872 cpu23_intc: interrupt-controller { 873 compatible = "riscv,cpu-intc"; 874 interrupt-controller; 875 #interrupt-cells = <1>; 876 }; 877 }; 878 879 cpu24: cpu@24 { 880 compatible = "thead,c920", "riscv"; 881 reg = <24>; 882 i-cache-block-size = <64>; 883 i-cache-size = <65536>; 884 i-cache-sets = <512>; 885 d-cache-block-size = <64>; 886 d-cache-size = <65536>; 887 d-cache-sets = <512>; 888 device_type = "cpu"; 889 mmu-type = "riscv,sv48"; 890 next-level-cache = <&l2_cache6>; 891 riscv,isa = "rv64imafdcv"; 892 riscv,isa-base = "rv64i"; 893 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 894 "v", "sscofpmf", "sstc", 895 "svinval", "svnapot", "svpbmt", 896 "zawrs", "zba", "zbb", "zbc", 897 "zbs", "zca", "zcb", "zcd", 898 "zfa", "zfbfmin", "zfh", "zfhmin", 899 "zicbom", "zicbop", "zicboz", "ziccrse", 900 "zicntr", "zicond","zicsr", "zifencei", 901 "zihintntl", "zihintpause", "zihpm", 902 "zvfbfmin", "zvfbfwma", "zvfh", 903 "zvfhmin"; 904 riscv,cbom-block-size = <64>; 905 riscv,cbop-block-size = <64>; 906 riscv,cboz-block-size = <64>; 907 908 cpu24_intc: interrupt-controller { 909 compatible = "riscv,cpu-intc"; 910 interrupt-controller; 911 #interrupt-cells = <1>; 912 }; 913 }; 914 915 cpu25: cpu@25 { 916 compatible = "thead,c920", "riscv"; 917 reg = <25>; 918 i-cache-block-size = <64>; 919 i-cache-size = <65536>; 920 i-cache-sets = <512>; 921 d-cache-block-size = <64>; 922 d-cache-size = <65536>; 923 d-cache-sets = <512>; 924 device_type = "cpu"; 925 mmu-type = "riscv,sv48"; 926 next-level-cache = <&l2_cache6>; 927 riscv,isa = "rv64imafdcv"; 928 riscv,isa-base = "rv64i"; 929 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 930 "v", "sscofpmf", "sstc", 931 "svinval", "svnapot", "svpbmt", 932 "zawrs", "zba", "zbb", "zbc", 933 "zbs", "zca", "zcb", "zcd", 934 "zfa", "zfbfmin", "zfh", "zfhmin", 935 "zicbom", "zicbop", "zicboz", "ziccrse", 936 "zicntr", "zicond","zicsr", "zifencei", 937 "zihintntl", "zihintpause", "zihpm", 938 "zvfbfmin", "zvfbfwma", "zvfh", 939 "zvfhmin"; 940 riscv,cbom-block-size = <64>; 941 riscv,cbop-block-size = <64>; 942 riscv,cboz-block-size = <64>; 943 944 cpu25_intc: interrupt-controller { 945 compatible = "riscv,cpu-intc"; 946 interrupt-controller; 947 #interrupt-cells = <1>; 948 }; 949 }; 950 951 cpu26: cpu@26 { 952 compatible = "thead,c920", "riscv"; 953 reg = <26>; 954 i-cache-block-size = <64>; 955 i-cache-size = <65536>; 956 i-cache-sets = <512>; 957 d-cache-block-size = <64>; 958 d-cache-size = <65536>; 959 d-cache-sets = <512>; 960 device_type = "cpu"; 961 mmu-type = "riscv,sv48"; 962 next-level-cache = <&l2_cache6>; 963 riscv,isa = "rv64imafdcv"; 964 riscv,isa-base = "rv64i"; 965 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 966 "v", "sscofpmf", "sstc", 967 "svinval", "svnapot", "svpbmt", 968 "zawrs", "zba", "zbb", "zbc", 969 "zbs", "zca", "zcb", "zcd", 970 "zfa", "zfbfmin", "zfh", "zfhmin", 971 "zicbom", "zicbop", "zicboz", "ziccrse", 972 "zicntr", "zicond","zicsr", "zifencei", 973 "zihintntl", "zihintpause", "zihpm", 974 "zvfbfmin", "zvfbfwma", "zvfh", 975 "zvfhmin"; 976 riscv,cbom-block-size = <64>; 977 riscv,cbop-block-size = <64>; 978 riscv,cboz-block-size = <64>; 979 980 cpu26_intc: interrupt-controller { 981 compatible = "riscv,cpu-intc"; 982 interrupt-controller; 983 #interrupt-cells = <1>; 984 }; 985 }; 986 987 cpu27: cpu@27 { 988 compatible = "thead,c920", "riscv"; 989 reg = <27>; 990 i-cache-block-size = <64>; 991 i-cache-size = <65536>; 992 i-cache-sets = <512>; 993 d-cache-block-size = <64>; 994 d-cache-size = <65536>; 995 d-cache-sets = <512>; 996 device_type = "cpu"; 997 mmu-type = "riscv,sv48"; 998 next-level-cache = <&l2_cache6>; 999 riscv,isa = "rv64imafdcv"; 1000 riscv,isa-base = "rv64i"; 1001 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1002 "v", "sscofpmf", "sstc", 1003 "svinval", "svnapot", "svpbmt", 1004 "zawrs", "zba", "zbb", "zbc", 1005 "zbs", "zca", "zcb", "zcd", 1006 "zfa", "zfbfmin", "zfh", "zfhmin", 1007 "zicbom", "zicbop", "zicboz", "ziccrse", 1008 "zicntr", "zicond","zicsr", "zifencei", 1009 "zihintntl", "zihintpause", "zihpm", 1010 "zvfbfmin", "zvfbfwma", "zvfh", 1011 "zvfhmin"; 1012 riscv,cbom-block-size = <64>; 1013 riscv,cbop-block-size = <64>; 1014 riscv,cboz-block-size = <64>; 1015 1016 cpu27_intc: interrupt-controller { 1017 compatible = "riscv,cpu-intc"; 1018 interrupt-controller; 1019 #interrupt-cells = <1>; 1020 }; 1021 }; 1022 1023 cpu28: cpu@28 { 1024 compatible = "thead,c920", "riscv"; 1025 reg = <28>; 1026 i-cache-block-size = <64>; 1027 i-cache-size = <65536>; 1028 i-cache-sets = <512>; 1029 d-cache-block-size = <64>; 1030 d-cache-size = <65536>; 1031 d-cache-sets = <512>; 1032 device_type = "cpu"; 1033 mmu-type = "riscv,sv48"; 1034 next-level-cache = <&l2_cache7>; 1035 riscv,isa = "rv64imafdcv"; 1036 riscv,isa-base = "rv64i"; 1037 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1038 "v", "sscofpmf", "sstc", 1039 "svinval", "svnapot", "svpbmt", 1040 "zawrs", "zba", "zbb", "zbc", 1041 "zbs", "zca", "zcb", "zcd", 1042 "zfa", "zfbfmin", "zfh", "zfhmin", 1043 "zicbom", "zicbop", "zicboz", "ziccrse", 1044 "zicntr", "zicond","zicsr", "zifencei", 1045 "zihintntl", "zihintpause", "zihpm", 1046 "zvfbfmin", "zvfbfwma", "zvfh", 1047 "zvfhmin"; 1048 riscv,cbom-block-size = <64>; 1049 riscv,cbop-block-size = <64>; 1050 riscv,cboz-block-size = <64>; 1051 1052 cpu28_intc: interrupt-controller { 1053 compatible = "riscv,cpu-intc"; 1054 interrupt-controller; 1055 #interrupt-cells = <1>; 1056 }; 1057 }; 1058 1059 cpu29: cpu@29 { 1060 compatible = "thead,c920", "riscv"; 1061 reg = <29>; 1062 i-cache-block-size = <64>; 1063 i-cache-size = <65536>; 1064 i-cache-sets = <512>; 1065 d-cache-block-size = <64>; 1066 d-cache-size = <65536>; 1067 d-cache-sets = <512>; 1068 device_type = "cpu"; 1069 mmu-type = "riscv,sv48"; 1070 next-level-cache = <&l2_cache7>; 1071 riscv,isa = "rv64imafdcv"; 1072 riscv,isa-base = "rv64i"; 1073 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1074 "v", "sscofpmf", "sstc", 1075 "svinval", "svnapot", "svpbmt", 1076 "zawrs", "zba", "zbb", "zbc", 1077 "zbs", "zca", "zcb", "zcd", 1078 "zfa", "zfbfmin", "zfh", "zfhmin", 1079 "zicbom", "zicbop", "zicboz", "ziccrse", 1080 "zicntr", "zicond","zicsr", "zifencei", 1081 "zihintntl", "zihintpause", "zihpm", 1082 "zvfbfmin", "zvfbfwma", "zvfh", 1083 "zvfhmin"; 1084 riscv,cbom-block-size = <64>; 1085 riscv,cbop-block-size = <64>; 1086 riscv,cboz-block-size = <64>; 1087 1088 cpu29_intc: interrupt-controller { 1089 compatible = "riscv,cpu-intc"; 1090 interrupt-controller; 1091 #interrupt-cells = <1>; 1092 }; 1093 }; 1094 1095 cpu30: cpu@30 { 1096 compatible = "thead,c920", "riscv"; 1097 reg = <30>; 1098 i-cache-block-size = <64>; 1099 i-cache-size = <65536>; 1100 i-cache-sets = <512>; 1101 d-cache-block-size = <64>; 1102 d-cache-size = <65536>; 1103 d-cache-sets = <512>; 1104 device_type = "cpu"; 1105 mmu-type = "riscv,sv48"; 1106 next-level-cache = <&l2_cache7>; 1107 riscv,isa = "rv64imafdcv"; 1108 riscv,isa-base = "rv64i"; 1109 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1110 "v", "sscofpmf", "sstc", 1111 "svinval", "svnapot", "svpbmt", 1112 "zawrs", "zba", "zbb", "zbc", 1113 "zbs", "zca", "zcb", "zcd", 1114 "zfa", "zfbfmin", "zfh", "zfhmin", 1115 "zicbom", "zicbop", "zicboz", "ziccrse", 1116 "zicntr", "zicond","zicsr", "zifencei", 1117 "zihintntl", "zihintpause", "zihpm", 1118 "zvfbfmin", "zvfbfwma", "zvfh", 1119 "zvfhmin"; 1120 riscv,cbom-block-size = <64>; 1121 riscv,cbop-block-size = <64>; 1122 riscv,cboz-block-size = <64>; 1123 1124 cpu30_intc: interrupt-controller { 1125 compatible = "riscv,cpu-intc"; 1126 interrupt-controller; 1127 #interrupt-cells = <1>; 1128 }; 1129 }; 1130 1131 cpu31: cpu@31 { 1132 compatible = "thead,c920", "riscv"; 1133 reg = <31>; 1134 i-cache-block-size = <64>; 1135 i-cache-size = <65536>; 1136 i-cache-sets = <512>; 1137 d-cache-block-size = <64>; 1138 d-cache-size = <65536>; 1139 d-cache-sets = <512>; 1140 device_type = "cpu"; 1141 mmu-type = "riscv,sv48"; 1142 next-level-cache = <&l2_cache7>; 1143 riscv,isa = "rv64imafdcv"; 1144 riscv,isa-base = "rv64i"; 1145 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1146 "v", "sscofpmf", "sstc", 1147 "svinval", "svnapot", "svpbmt", 1148 "zawrs", "zba", "zbb", "zbc", 1149 "zbs", "zca", "zcb", "zcd", 1150 "zfa", "zfbfmin", "zfh", "zfhmin", 1151 "zicbom", "zicbop", "zicboz", "ziccrse", 1152 "zicntr", "zicond","zicsr", "zifencei", 1153 "zihintntl", "zihintpause", "zihpm", 1154 "zvfbfmin", "zvfbfwma", "zvfh", 1155 "zvfhmin"; 1156 riscv,cbom-block-size = <64>; 1157 riscv,cbop-block-size = <64>; 1158 riscv,cboz-block-size = <64>; 1159 1160 cpu31_intc: interrupt-controller { 1161 compatible = "riscv,cpu-intc"; 1162 interrupt-controller; 1163 #interrupt-cells = <1>; 1164 }; 1165 }; 1166 1167 cpu32: cpu@32 { 1168 compatible = "thead,c920", "riscv"; 1169 reg = <32>; 1170 i-cache-block-size = <64>; 1171 i-cache-size = <65536>; 1172 i-cache-sets = <512>; 1173 d-cache-block-size = <64>; 1174 d-cache-size = <65536>; 1175 d-cache-sets = <512>; 1176 device_type = "cpu"; 1177 mmu-type = "riscv,sv48"; 1178 next-level-cache = <&l2_cache8>; 1179 riscv,isa = "rv64imafdcv"; 1180 riscv,isa-base = "rv64i"; 1181 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1182 "v", "sscofpmf", "sstc", 1183 "svinval", "svnapot", "svpbmt", 1184 "zawrs", "zba", "zbb", "zbc", 1185 "zbs", "zca", "zcb", "zcd", 1186 "zfa", "zfbfmin", "zfh", "zfhmin", 1187 "zicbom", "zicbop", "zicboz", "ziccrse", 1188 "zicntr", "zicond","zicsr", "zifencei", 1189 "zihintntl", "zihintpause", "zihpm", 1190 "zvfbfmin", "zvfbfwma", "zvfh", 1191 "zvfhmin"; 1192 riscv,cbom-block-size = <64>; 1193 riscv,cbop-block-size = <64>; 1194 riscv,cboz-block-size = <64>; 1195 1196 cpu32_intc: interrupt-controller { 1197 compatible = "riscv,cpu-intc"; 1198 interrupt-controller; 1199 #interrupt-cells = <1>; 1200 }; 1201 }; 1202 1203 cpu33: cpu@33 { 1204 compatible = "thead,c920", "riscv"; 1205 reg = <33>; 1206 i-cache-block-size = <64>; 1207 i-cache-size = <65536>; 1208 i-cache-sets = <512>; 1209 d-cache-block-size = <64>; 1210 d-cache-size = <65536>; 1211 d-cache-sets = <512>; 1212 device_type = "cpu"; 1213 mmu-type = "riscv,sv48"; 1214 next-level-cache = <&l2_cache8>; 1215 riscv,isa = "rv64imafdcv"; 1216 riscv,isa-base = "rv64i"; 1217 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1218 "v", "sscofpmf", "sstc", 1219 "svinval", "svnapot", "svpbmt", 1220 "zawrs", "zba", "zbb", "zbc", 1221 "zbs", "zca", "zcb", "zcd", 1222 "zfa", "zfbfmin", "zfh", "zfhmin", 1223 "zicbom", "zicbop", "zicboz", "ziccrse", 1224 "zicntr", "zicond","zicsr", "zifencei", 1225 "zihintntl", "zihintpause", "zihpm", 1226 "zvfbfmin", "zvfbfwma", "zvfh", 1227 "zvfhmin"; 1228 riscv,cbom-block-size = <64>; 1229 riscv,cbop-block-size = <64>; 1230 riscv,cboz-block-size = <64>; 1231 1232 cpu33_intc: interrupt-controller { 1233 compatible = "riscv,cpu-intc"; 1234 interrupt-controller; 1235 #interrupt-cells = <1>; 1236 }; 1237 }; 1238 1239 cpu34: cpu@34 { 1240 compatible = "thead,c920", "riscv"; 1241 reg = <34>; 1242 i-cache-block-size = <64>; 1243 i-cache-size = <65536>; 1244 i-cache-sets = <512>; 1245 d-cache-block-size = <64>; 1246 d-cache-size = <65536>; 1247 d-cache-sets = <512>; 1248 device_type = "cpu"; 1249 mmu-type = "riscv,sv48"; 1250 next-level-cache = <&l2_cache8>; 1251 riscv,isa = "rv64imafdcv"; 1252 riscv,isa-base = "rv64i"; 1253 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1254 "v", "sscofpmf", "sstc", 1255 "svinval", "svnapot", "svpbmt", 1256 "zawrs", "zba", "zbb", "zbc", 1257 "zbs", "zca", "zcb", "zcd", 1258 "zfa", "zfbfmin", "zfh", "zfhmin", 1259 "zicbom", "zicbop", "zicboz", "ziccrse", 1260 "zicntr", "zicond","zicsr", "zifencei", 1261 "zihintntl", "zihintpause", "zihpm", 1262 "zvfbfmin", "zvfbfwma", "zvfh", 1263 "zvfhmin"; 1264 riscv,cbom-block-size = <64>; 1265 riscv,cbop-block-size = <64>; 1266 riscv,cboz-block-size = <64>; 1267 1268 cpu34_intc: interrupt-controller { 1269 compatible = "riscv,cpu-intc"; 1270 interrupt-controller; 1271 #interrupt-cells = <1>; 1272 }; 1273 }; 1274 1275 cpu35: cpu@35 { 1276 compatible = "thead,c920", "riscv"; 1277 reg = <35>; 1278 i-cache-block-size = <64>; 1279 i-cache-size = <65536>; 1280 i-cache-sets = <512>; 1281 d-cache-block-size = <64>; 1282 d-cache-size = <65536>; 1283 d-cache-sets = <512>; 1284 device_type = "cpu"; 1285 mmu-type = "riscv,sv48"; 1286 next-level-cache = <&l2_cache8>; 1287 riscv,isa = "rv64imafdcv"; 1288 riscv,isa-base = "rv64i"; 1289 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1290 "v", "sscofpmf", "sstc", 1291 "svinval", "svnapot", "svpbmt", 1292 "zawrs", "zba", "zbb", "zbc", 1293 "zbs", "zca", "zcb", "zcd", 1294 "zfa", "zfbfmin", "zfh", "zfhmin", 1295 "zicbom", "zicbop", "zicboz", "ziccrse", 1296 "zicntr", "zicond","zicsr", "zifencei", 1297 "zihintntl", "zihintpause", "zihpm", 1298 "zvfbfmin", "zvfbfwma", "zvfh", 1299 "zvfhmin"; 1300 riscv,cbom-block-size = <64>; 1301 riscv,cbop-block-size = <64>; 1302 riscv,cboz-block-size = <64>; 1303 1304 cpu35_intc: interrupt-controller { 1305 compatible = "riscv,cpu-intc"; 1306 interrupt-controller; 1307 #interrupt-cells = <1>; 1308 }; 1309 }; 1310 1311 cpu36: cpu@36 { 1312 compatible = "thead,c920", "riscv"; 1313 reg = <36>; 1314 i-cache-block-size = <64>; 1315 i-cache-size = <65536>; 1316 i-cache-sets = <512>; 1317 d-cache-block-size = <64>; 1318 d-cache-size = <65536>; 1319 d-cache-sets = <512>; 1320 device_type = "cpu"; 1321 mmu-type = "riscv,sv48"; 1322 next-level-cache = <&l2_cache9>; 1323 riscv,isa = "rv64imafdcv"; 1324 riscv,isa-base = "rv64i"; 1325 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1326 "v", "sscofpmf", "sstc", 1327 "svinval", "svnapot", "svpbmt", 1328 "zawrs", "zba", "zbb", "zbc", 1329 "zbs", "zca", "zcb", "zcd", 1330 "zfa", "zfbfmin", "zfh", "zfhmin", 1331 "zicbom", "zicbop", "zicboz", "ziccrse", 1332 "zicntr", "zicond","zicsr", "zifencei", 1333 "zihintntl", "zihintpause", "zihpm", 1334 "zvfbfmin", "zvfbfwma", "zvfh", 1335 "zvfhmin"; 1336 riscv,cbom-block-size = <64>; 1337 riscv,cbop-block-size = <64>; 1338 riscv,cboz-block-size = <64>; 1339 1340 cpu36_intc: interrupt-controller { 1341 compatible = "riscv,cpu-intc"; 1342 interrupt-controller; 1343 #interrupt-cells = <1>; 1344 }; 1345 }; 1346 1347 cpu37: cpu@37 { 1348 compatible = "thead,c920", "riscv"; 1349 reg = <37>; 1350 i-cache-block-size = <64>; 1351 i-cache-size = <65536>; 1352 i-cache-sets = <512>; 1353 d-cache-block-size = <64>; 1354 d-cache-size = <65536>; 1355 d-cache-sets = <512>; 1356 device_type = "cpu"; 1357 mmu-type = "riscv,sv48"; 1358 next-level-cache = <&l2_cache9>; 1359 riscv,isa = "rv64imafdcv"; 1360 riscv,isa-base = "rv64i"; 1361 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1362 "v", "sscofpmf", "sstc", 1363 "svinval", "svnapot", "svpbmt", 1364 "zawrs", "zba", "zbb", "zbc", 1365 "zbs", "zca", "zcb", "zcd", 1366 "zfa", "zfbfmin", "zfh", "zfhmin", 1367 "zicbom", "zicbop", "zicboz", "ziccrse", 1368 "zicntr", "zicond","zicsr", "zifencei", 1369 "zihintntl", "zihintpause", "zihpm", 1370 "zvfbfmin", "zvfbfwma", "zvfh", 1371 "zvfhmin"; 1372 riscv,cbom-block-size = <64>; 1373 riscv,cbop-block-size = <64>; 1374 riscv,cboz-block-size = <64>; 1375 1376 cpu37_intc: interrupt-controller { 1377 compatible = "riscv,cpu-intc"; 1378 interrupt-controller; 1379 #interrupt-cells = <1>; 1380 }; 1381 }; 1382 1383 cpu38: cpu@38 { 1384 compatible = "thead,c920", "riscv"; 1385 reg = <38>; 1386 i-cache-block-size = <64>; 1387 i-cache-size = <65536>; 1388 i-cache-sets = <512>; 1389 d-cache-block-size = <64>; 1390 d-cache-size = <65536>; 1391 d-cache-sets = <512>; 1392 device_type = "cpu"; 1393 mmu-type = "riscv,sv48"; 1394 next-level-cache = <&l2_cache9>; 1395 riscv,isa = "rv64imafdcv"; 1396 riscv,isa-base = "rv64i"; 1397 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1398 "v", "sscofpmf", "sstc", 1399 "svinval", "svnapot", "svpbmt", 1400 "zawrs", "zba", "zbb", "zbc", 1401 "zbs", "zca", "zcb", "zcd", 1402 "zfa", "zfbfmin", "zfh", "zfhmin", 1403 "zicbom", "zicbop", "zicboz", "ziccrse", 1404 "zicntr", "zicond","zicsr", "zifencei", 1405 "zihintntl", "zihintpause", "zihpm", 1406 "zvfbfmin", "zvfbfwma", "zvfh", 1407 "zvfhmin"; 1408 riscv,cbom-block-size = <64>; 1409 riscv,cbop-block-size = <64>; 1410 riscv,cboz-block-size = <64>; 1411 1412 cpu38_intc: interrupt-controller { 1413 compatible = "riscv,cpu-intc"; 1414 interrupt-controller; 1415 #interrupt-cells = <1>; 1416 }; 1417 }; 1418 1419 cpu39: cpu@39 { 1420 compatible = "thead,c920", "riscv"; 1421 reg = <39>; 1422 i-cache-block-size = <64>; 1423 i-cache-size = <65536>; 1424 i-cache-sets = <512>; 1425 d-cache-block-size = <64>; 1426 d-cache-size = <65536>; 1427 d-cache-sets = <512>; 1428 device_type = "cpu"; 1429 mmu-type = "riscv,sv48"; 1430 next-level-cache = <&l2_cache9>; 1431 riscv,isa = "rv64imafdcv"; 1432 riscv,isa-base = "rv64i"; 1433 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1434 "v", "sscofpmf", "sstc", 1435 "svinval", "svnapot", "svpbmt", 1436 "zawrs", "zba", "zbb", "zbc", 1437 "zbs", "zca", "zcb", "zcd", 1438 "zfa", "zfbfmin", "zfh", "zfhmin", 1439 "zicbom", "zicbop", "zicboz", "ziccrse", 1440 "zicntr", "zicond","zicsr", "zifencei", 1441 "zihintntl", "zihintpause", "zihpm", 1442 "zvfbfmin", "zvfbfwma", "zvfh", 1443 "zvfhmin"; 1444 riscv,cbom-block-size = <64>; 1445 riscv,cbop-block-size = <64>; 1446 riscv,cboz-block-size = <64>; 1447 1448 cpu39_intc: interrupt-controller { 1449 compatible = "riscv,cpu-intc"; 1450 interrupt-controller; 1451 #interrupt-cells = <1>; 1452 }; 1453 }; 1454 1455 cpu40: cpu@40 { 1456 compatible = "thead,c920", "riscv"; 1457 reg = <40>; 1458 i-cache-block-size = <64>; 1459 i-cache-size = <65536>; 1460 i-cache-sets = <512>; 1461 d-cache-block-size = <64>; 1462 d-cache-size = <65536>; 1463 d-cache-sets = <512>; 1464 device_type = "cpu"; 1465 mmu-type = "riscv,sv48"; 1466 next-level-cache = <&l2_cache10>; 1467 riscv,isa = "rv64imafdcv"; 1468 riscv,isa-base = "rv64i"; 1469 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1470 "v", "sscofpmf", "sstc", 1471 "svinval", "svnapot", "svpbmt", 1472 "zawrs", "zba", "zbb", "zbc", 1473 "zbs", "zca", "zcb", "zcd", 1474 "zfa", "zfbfmin", "zfh", "zfhmin", 1475 "zicbom", "zicbop", "zicboz", "ziccrse", 1476 "zicntr", "zicond","zicsr", "zifencei", 1477 "zihintntl", "zihintpause", "zihpm", 1478 "zvfbfmin", "zvfbfwma", "zvfh", 1479 "zvfhmin"; 1480 riscv,cbom-block-size = <64>; 1481 riscv,cbop-block-size = <64>; 1482 riscv,cboz-block-size = <64>; 1483 1484 cpu40_intc: interrupt-controller { 1485 compatible = "riscv,cpu-intc"; 1486 interrupt-controller; 1487 #interrupt-cells = <1>; 1488 }; 1489 }; 1490 1491 cpu41: cpu@41 { 1492 compatible = "thead,c920", "riscv"; 1493 reg = <41>; 1494 i-cache-block-size = <64>; 1495 i-cache-size = <65536>; 1496 i-cache-sets = <512>; 1497 d-cache-block-size = <64>; 1498 d-cache-size = <65536>; 1499 d-cache-sets = <512>; 1500 device_type = "cpu"; 1501 mmu-type = "riscv,sv48"; 1502 next-level-cache = <&l2_cache10>; 1503 riscv,isa = "rv64imafdcv"; 1504 riscv,isa-base = "rv64i"; 1505 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1506 "v", "sscofpmf", "sstc", 1507 "svinval", "svnapot", "svpbmt", 1508 "zawrs", "zba", "zbb", "zbc", 1509 "zbs", "zca", "zcb", "zcd", 1510 "zfa", "zfbfmin", "zfh", "zfhmin", 1511 "zicbom", "zicbop", "zicboz", "ziccrse", 1512 "zicntr", "zicond","zicsr", "zifencei", 1513 "zihintntl", "zihintpause", "zihpm", 1514 "zvfbfmin", "zvfbfwma", "zvfh", 1515 "zvfhmin"; 1516 riscv,cbom-block-size = <64>; 1517 riscv,cbop-block-size = <64>; 1518 riscv,cboz-block-size = <64>; 1519 1520 cpu41_intc: interrupt-controller { 1521 compatible = "riscv,cpu-intc"; 1522 interrupt-controller; 1523 #interrupt-cells = <1>; 1524 }; 1525 }; 1526 1527 cpu42: cpu@42 { 1528 compatible = "thead,c920", "riscv"; 1529 reg = <42>; 1530 i-cache-block-size = <64>; 1531 i-cache-size = <65536>; 1532 i-cache-sets = <512>; 1533 d-cache-block-size = <64>; 1534 d-cache-size = <65536>; 1535 d-cache-sets = <512>; 1536 device_type = "cpu"; 1537 mmu-type = "riscv,sv48"; 1538 next-level-cache = <&l2_cache10>; 1539 riscv,isa = "rv64imafdcv"; 1540 riscv,isa-base = "rv64i"; 1541 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1542 "v", "sscofpmf", "sstc", 1543 "svinval", "svnapot", "svpbmt", 1544 "zawrs", "zba", "zbb", "zbc", 1545 "zbs", "zca", "zcb", "zcd", 1546 "zfa", "zfbfmin", "zfh", "zfhmin", 1547 "zicbom", "zicbop", "zicboz", "ziccrse", 1548 "zicntr", "zicond","zicsr", "zifencei", 1549 "zihintntl", "zihintpause", "zihpm", 1550 "zvfbfmin", "zvfbfwma", "zvfh", 1551 "zvfhmin"; 1552 riscv,cbom-block-size = <64>; 1553 riscv,cbop-block-size = <64>; 1554 riscv,cboz-block-size = <64>; 1555 1556 cpu42_intc: interrupt-controller { 1557 compatible = "riscv,cpu-intc"; 1558 interrupt-controller; 1559 #interrupt-cells = <1>; 1560 }; 1561 }; 1562 1563 cpu43: cpu@43 { 1564 compatible = "thead,c920", "riscv"; 1565 reg = <43>; 1566 i-cache-block-size = <64>; 1567 i-cache-size = <65536>; 1568 i-cache-sets = <512>; 1569 d-cache-block-size = <64>; 1570 d-cache-size = <65536>; 1571 d-cache-sets = <512>; 1572 device_type = "cpu"; 1573 mmu-type = "riscv,sv48"; 1574 next-level-cache = <&l2_cache10>; 1575 riscv,isa = "rv64imafdcv"; 1576 riscv,isa-base = "rv64i"; 1577 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1578 "v", "sscofpmf", "sstc", 1579 "svinval", "svnapot", "svpbmt", 1580 "zawrs", "zba", "zbb", "zbc", 1581 "zbs", "zca", "zcb", "zcd", 1582 "zfa", "zfbfmin", "zfh", "zfhmin", 1583 "zicbom", "zicbop", "zicboz", "ziccrse", 1584 "zicntr", "zicond","zicsr", "zifencei", 1585 "zihintntl", "zihintpause", "zihpm", 1586 "zvfbfmin", "zvfbfwma", "zvfh", 1587 "zvfhmin"; 1588 riscv,cbom-block-size = <64>; 1589 riscv,cbop-block-size = <64>; 1590 riscv,cboz-block-size = <64>; 1591 1592 cpu43_intc: interrupt-controller { 1593 compatible = "riscv,cpu-intc"; 1594 interrupt-controller; 1595 #interrupt-cells = <1>; 1596 }; 1597 }; 1598 1599 cpu44: cpu@44 { 1600 compatible = "thead,c920", "riscv"; 1601 reg = <44>; 1602 i-cache-block-size = <64>; 1603 i-cache-size = <65536>; 1604 i-cache-sets = <512>; 1605 d-cache-block-size = <64>; 1606 d-cache-size = <65536>; 1607 d-cache-sets = <512>; 1608 device_type = "cpu"; 1609 mmu-type = "riscv,sv48"; 1610 next-level-cache = <&l2_cache11>; 1611 riscv,isa = "rv64imafdcv"; 1612 riscv,isa-base = "rv64i"; 1613 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1614 "v", "sscofpmf", "sstc", 1615 "svinval", "svnapot", "svpbmt", 1616 "zawrs", "zba", "zbb", "zbc", 1617 "zbs", "zca", "zcb", "zcd", 1618 "zfa", "zfbfmin", "zfh", "zfhmin", 1619 "zicbom", "zicbop", "zicboz", "ziccrse", 1620 "zicntr", "zicond","zicsr", "zifencei", 1621 "zihintntl", "zihintpause", "zihpm", 1622 "zvfbfmin", "zvfbfwma", "zvfh", 1623 "zvfhmin"; 1624 riscv,cbom-block-size = <64>; 1625 riscv,cbop-block-size = <64>; 1626 riscv,cboz-block-size = <64>; 1627 1628 cpu44_intc: interrupt-controller { 1629 compatible = "riscv,cpu-intc"; 1630 interrupt-controller; 1631 #interrupt-cells = <1>; 1632 }; 1633 }; 1634 1635 cpu45: cpu@45 { 1636 compatible = "thead,c920", "riscv"; 1637 reg = <45>; 1638 i-cache-block-size = <64>; 1639 i-cache-size = <65536>; 1640 i-cache-sets = <512>; 1641 d-cache-block-size = <64>; 1642 d-cache-size = <65536>; 1643 d-cache-sets = <512>; 1644 device_type = "cpu"; 1645 mmu-type = "riscv,sv48"; 1646 next-level-cache = <&l2_cache11>; 1647 riscv,isa = "rv64imafdcv"; 1648 riscv,isa-base = "rv64i"; 1649 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1650 "v", "sscofpmf", "sstc", 1651 "svinval", "svnapot", "svpbmt", 1652 "zawrs", "zba", "zbb", "zbc", 1653 "zbs", "zca", "zcb", "zcd", 1654 "zfa", "zfbfmin", "zfh", "zfhmin", 1655 "zicbom", "zicbop", "zicboz", "ziccrse", 1656 "zicntr", "zicond","zicsr", "zifencei", 1657 "zihintntl", "zihintpause", "zihpm", 1658 "zvfbfmin", "zvfbfwma", "zvfh", 1659 "zvfhmin"; 1660 riscv,cbom-block-size = <64>; 1661 riscv,cbop-block-size = <64>; 1662 riscv,cboz-block-size = <64>; 1663 1664 cpu45_intc: interrupt-controller { 1665 compatible = "riscv,cpu-intc"; 1666 interrupt-controller; 1667 #interrupt-cells = <1>; 1668 }; 1669 }; 1670 1671 cpu46: cpu@46 { 1672 compatible = "thead,c920", "riscv"; 1673 reg = <46>; 1674 i-cache-block-size = <64>; 1675 i-cache-size = <65536>; 1676 i-cache-sets = <512>; 1677 d-cache-block-size = <64>; 1678 d-cache-size = <65536>; 1679 d-cache-sets = <512>; 1680 device_type = "cpu"; 1681 mmu-type = "riscv,sv48"; 1682 next-level-cache = <&l2_cache11>; 1683 riscv,isa = "rv64imafdcv"; 1684 riscv,isa-base = "rv64i"; 1685 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1686 "v", "sscofpmf", "sstc", 1687 "svinval", "svnapot", "svpbmt", 1688 "zawrs", "zba", "zbb", "zbc", 1689 "zbs", "zca", "zcb", "zcd", 1690 "zfa", "zfbfmin", "zfh", "zfhmin", 1691 "zicbom", "zicbop", "zicboz", "ziccrse", 1692 "zicntr", "zicond","zicsr", "zifencei", 1693 "zihintntl", "zihintpause", "zihpm", 1694 "zvfbfmin", "zvfbfwma", "zvfh", 1695 "zvfhmin"; 1696 riscv,cbom-block-size = <64>; 1697 riscv,cbop-block-size = <64>; 1698 riscv,cboz-block-size = <64>; 1699 1700 cpu46_intc: interrupt-controller { 1701 compatible = "riscv,cpu-intc"; 1702 interrupt-controller; 1703 #interrupt-cells = <1>; 1704 }; 1705 }; 1706 1707 cpu47: cpu@47 { 1708 compatible = "thead,c920", "riscv"; 1709 reg = <47>; 1710 i-cache-block-size = <64>; 1711 i-cache-size = <65536>; 1712 i-cache-sets = <512>; 1713 d-cache-block-size = <64>; 1714 d-cache-size = <65536>; 1715 d-cache-sets = <512>; 1716 device_type = "cpu"; 1717 mmu-type = "riscv,sv48"; 1718 next-level-cache = <&l2_cache11>; 1719 riscv,isa = "rv64imafdcv"; 1720 riscv,isa-base = "rv64i"; 1721 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1722 "v", "sscofpmf", "sstc", 1723 "svinval", "svnapot", "svpbmt", 1724 "zawrs", "zba", "zbb", "zbc", 1725 "zbs", "zca", "zcb", "zcd", 1726 "zfa", "zfbfmin", "zfh", "zfhmin", 1727 "zicbom", "zicbop", "zicboz", "ziccrse", 1728 "zicntr", "zicond","zicsr", "zifencei", 1729 "zihintntl", "zihintpause", "zihpm", 1730 "zvfbfmin", "zvfbfwma", "zvfh", 1731 "zvfhmin"; 1732 riscv,cbom-block-size = <64>; 1733 riscv,cbop-block-size = <64>; 1734 riscv,cboz-block-size = <64>; 1735 1736 cpu47_intc: interrupt-controller { 1737 compatible = "riscv,cpu-intc"; 1738 interrupt-controller; 1739 #interrupt-cells = <1>; 1740 }; 1741 }; 1742 1743 cpu48: cpu@48 { 1744 compatible = "thead,c920", "riscv"; 1745 reg = <48>; 1746 i-cache-block-size = <64>; 1747 i-cache-size = <65536>; 1748 i-cache-sets = <512>; 1749 d-cache-block-size = <64>; 1750 d-cache-size = <65536>; 1751 d-cache-sets = <512>; 1752 device_type = "cpu"; 1753 mmu-type = "riscv,sv48"; 1754 next-level-cache = <&l2_cache12>; 1755 riscv,isa = "rv64imafdcv"; 1756 riscv,isa-base = "rv64i"; 1757 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1758 "v", "sscofpmf", "sstc", 1759 "svinval", "svnapot", "svpbmt", 1760 "zawrs", "zba", "zbb", "zbc", 1761 "zbs", "zca", "zcb", "zcd", 1762 "zfa", "zfbfmin", "zfh", "zfhmin", 1763 "zicbom", "zicbop", "zicboz", "ziccrse", 1764 "zicntr", "zicond","zicsr", "zifencei", 1765 "zihintntl", "zihintpause", "zihpm", 1766 "zvfbfmin", "zvfbfwma", "zvfh", 1767 "zvfhmin"; 1768 riscv,cbom-block-size = <64>; 1769 riscv,cbop-block-size = <64>; 1770 riscv,cboz-block-size = <64>; 1771 1772 cpu48_intc: interrupt-controller { 1773 compatible = "riscv,cpu-intc"; 1774 interrupt-controller; 1775 #interrupt-cells = <1>; 1776 }; 1777 }; 1778 1779 cpu49: cpu@49 { 1780 compatible = "thead,c920", "riscv"; 1781 reg = <49>; 1782 i-cache-block-size = <64>; 1783 i-cache-size = <65536>; 1784 i-cache-sets = <512>; 1785 d-cache-block-size = <64>; 1786 d-cache-size = <65536>; 1787 d-cache-sets = <512>; 1788 device_type = "cpu"; 1789 mmu-type = "riscv,sv48"; 1790 next-level-cache = <&l2_cache12>; 1791 riscv,isa = "rv64imafdcv"; 1792 riscv,isa-base = "rv64i"; 1793 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1794 "v", "sscofpmf", "sstc", 1795 "svinval", "svnapot", "svpbmt", 1796 "zawrs", "zba", "zbb", "zbc", 1797 "zbs", "zca", "zcb", "zcd", 1798 "zfa", "zfbfmin", "zfh", "zfhmin", 1799 "zicbom", "zicbop", "zicboz", "ziccrse", 1800 "zicntr", "zicond","zicsr", "zifencei", 1801 "zihintntl", "zihintpause", "zihpm", 1802 "zvfbfmin", "zvfbfwma", "zvfh", 1803 "zvfhmin"; 1804 riscv,cbom-block-size = <64>; 1805 riscv,cbop-block-size = <64>; 1806 riscv,cboz-block-size = <64>; 1807 1808 cpu49_intc: interrupt-controller { 1809 compatible = "riscv,cpu-intc"; 1810 interrupt-controller; 1811 #interrupt-cells = <1>; 1812 }; 1813 }; 1814 1815 cpu50: cpu@50 { 1816 compatible = "thead,c920", "riscv"; 1817 reg = <50>; 1818 i-cache-block-size = <64>; 1819 i-cache-size = <65536>; 1820 i-cache-sets = <512>; 1821 d-cache-block-size = <64>; 1822 d-cache-size = <65536>; 1823 d-cache-sets = <512>; 1824 device_type = "cpu"; 1825 mmu-type = "riscv,sv48"; 1826 next-level-cache = <&l2_cache12>; 1827 riscv,isa = "rv64imafdcv"; 1828 riscv,isa-base = "rv64i"; 1829 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1830 "v", "sscofpmf", "sstc", 1831 "svinval", "svnapot", "svpbmt", 1832 "zawrs", "zba", "zbb", "zbc", 1833 "zbs", "zca", "zcb", "zcd", 1834 "zfa", "zfbfmin", "zfh", "zfhmin", 1835 "zicbom", "zicbop", "zicboz", "ziccrse", 1836 "zicntr", "zicond","zicsr", "zifencei", 1837 "zihintntl", "zihintpause", "zihpm", 1838 "zvfbfmin", "zvfbfwma", "zvfh", 1839 "zvfhmin"; 1840 riscv,cbom-block-size = <64>; 1841 riscv,cbop-block-size = <64>; 1842 riscv,cboz-block-size = <64>; 1843 1844 cpu50_intc: interrupt-controller { 1845 compatible = "riscv,cpu-intc"; 1846 interrupt-controller; 1847 #interrupt-cells = <1>; 1848 }; 1849 }; 1850 1851 cpu51: cpu@51 { 1852 compatible = "thead,c920", "riscv"; 1853 reg = <51>; 1854 i-cache-block-size = <64>; 1855 i-cache-size = <65536>; 1856 i-cache-sets = <512>; 1857 d-cache-block-size = <64>; 1858 d-cache-size = <65536>; 1859 d-cache-sets = <512>; 1860 device_type = "cpu"; 1861 mmu-type = "riscv,sv48"; 1862 next-level-cache = <&l2_cache12>; 1863 riscv,isa = "rv64imafdcv"; 1864 riscv,isa-base = "rv64i"; 1865 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1866 "v", "sscofpmf", "sstc", 1867 "svinval", "svnapot", "svpbmt", 1868 "zawrs", "zba", "zbb", "zbc", 1869 "zbs", "zca", "zcb", "zcd", 1870 "zfa", "zfbfmin", "zfh", "zfhmin", 1871 "zicbom", "zicbop", "zicboz", "ziccrse", 1872 "zicntr", "zicond","zicsr", "zifencei", 1873 "zihintntl", "zihintpause", "zihpm", 1874 "zvfbfmin", "zvfbfwma", "zvfh", 1875 "zvfhmin"; 1876 riscv,cbom-block-size = <64>; 1877 riscv,cbop-block-size = <64>; 1878 riscv,cboz-block-size = <64>; 1879 1880 cpu51_intc: interrupt-controller { 1881 compatible = "riscv,cpu-intc"; 1882 interrupt-controller; 1883 #interrupt-cells = <1>; 1884 }; 1885 }; 1886 1887 cpu52: cpu@52 { 1888 compatible = "thead,c920", "riscv"; 1889 reg = <52>; 1890 i-cache-block-size = <64>; 1891 i-cache-size = <65536>; 1892 i-cache-sets = <512>; 1893 d-cache-block-size = <64>; 1894 d-cache-size = <65536>; 1895 d-cache-sets = <512>; 1896 device_type = "cpu"; 1897 mmu-type = "riscv,sv48"; 1898 next-level-cache = <&l2_cache13>; 1899 riscv,isa = "rv64imafdcv"; 1900 riscv,isa-base = "rv64i"; 1901 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1902 "v", "sscofpmf", "sstc", 1903 "svinval", "svnapot", "svpbmt", 1904 "zawrs", "zba", "zbb", "zbc", 1905 "zbs", "zca", "zcb", "zcd", 1906 "zfa", "zfbfmin", "zfh", "zfhmin", 1907 "zicbom", "zicbop", "zicboz", "ziccrse", 1908 "zicntr", "zicond","zicsr", "zifencei", 1909 "zihintntl", "zihintpause", "zihpm", 1910 "zvfbfmin", "zvfbfwma", "zvfh", 1911 "zvfhmin"; 1912 riscv,cbom-block-size = <64>; 1913 riscv,cbop-block-size = <64>; 1914 riscv,cboz-block-size = <64>; 1915 1916 cpu52_intc: interrupt-controller { 1917 compatible = "riscv,cpu-intc"; 1918 interrupt-controller; 1919 #interrupt-cells = <1>; 1920 }; 1921 }; 1922 1923 cpu53: cpu@53 { 1924 compatible = "thead,c920", "riscv"; 1925 reg = <53>; 1926 i-cache-block-size = <64>; 1927 i-cache-size = <65536>; 1928 i-cache-sets = <512>; 1929 d-cache-block-size = <64>; 1930 d-cache-size = <65536>; 1931 d-cache-sets = <512>; 1932 device_type = "cpu"; 1933 mmu-type = "riscv,sv48"; 1934 next-level-cache = <&l2_cache13>; 1935 riscv,isa = "rv64imafdcv"; 1936 riscv,isa-base = "rv64i"; 1937 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1938 "v", "sscofpmf", "sstc", 1939 "svinval", "svnapot", "svpbmt", 1940 "zawrs", "zba", "zbb", "zbc", 1941 "zbs", "zca", "zcb", "zcd", 1942 "zfa", "zfbfmin", "zfh", "zfhmin", 1943 "zicbom", "zicbop", "zicboz", "ziccrse", 1944 "zicntr", "zicond","zicsr", "zifencei", 1945 "zihintntl", "zihintpause", "zihpm", 1946 "zvfbfmin", "zvfbfwma", "zvfh", 1947 "zvfhmin"; 1948 riscv,cbom-block-size = <64>; 1949 riscv,cbop-block-size = <64>; 1950 riscv,cboz-block-size = <64>; 1951 1952 cpu53_intc: interrupt-controller { 1953 compatible = "riscv,cpu-intc"; 1954 interrupt-controller; 1955 #interrupt-cells = <1>; 1956 }; 1957 }; 1958 1959 cpu54: cpu@54 { 1960 compatible = "thead,c920", "riscv"; 1961 reg = <54>; 1962 i-cache-block-size = <64>; 1963 i-cache-size = <65536>; 1964 i-cache-sets = <512>; 1965 d-cache-block-size = <64>; 1966 d-cache-size = <65536>; 1967 d-cache-sets = <512>; 1968 device_type = "cpu"; 1969 mmu-type = "riscv,sv48"; 1970 next-level-cache = <&l2_cache13>; 1971 riscv,isa = "rv64imafdcv"; 1972 riscv,isa-base = "rv64i"; 1973 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 1974 "v", "sscofpmf", "sstc", 1975 "svinval", "svnapot", "svpbmt", 1976 "zawrs", "zba", "zbb", "zbc", 1977 "zbs", "zca", "zcb", "zcd", 1978 "zfa", "zfbfmin", "zfh", "zfhmin", 1979 "zicbom", "zicbop", "zicboz", "ziccrse", 1980 "zicntr", "zicond","zicsr", "zifencei", 1981 "zihintntl", "zihintpause", "zihpm", 1982 "zvfbfmin", "zvfbfwma", "zvfh", 1983 "zvfhmin"; 1984 riscv,cbom-block-size = <64>; 1985 riscv,cbop-block-size = <64>; 1986 riscv,cboz-block-size = <64>; 1987 1988 cpu54_intc: interrupt-controller { 1989 compatible = "riscv,cpu-intc"; 1990 interrupt-controller; 1991 #interrupt-cells = <1>; 1992 }; 1993 }; 1994 1995 cpu55: cpu@55 { 1996 compatible = "thead,c920", "riscv"; 1997 reg = <55>; 1998 i-cache-block-size = <64>; 1999 i-cache-size = <65536>; 2000 i-cache-sets = <512>; 2001 d-cache-block-size = <64>; 2002 d-cache-size = <65536>; 2003 d-cache-sets = <512>; 2004 device_type = "cpu"; 2005 mmu-type = "riscv,sv48"; 2006 next-level-cache = <&l2_cache13>; 2007 riscv,isa = "rv64imafdcv"; 2008 riscv,isa-base = "rv64i"; 2009 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2010 "v", "sscofpmf", "sstc", 2011 "svinval", "svnapot", "svpbmt", 2012 "zawrs", "zba", "zbb", "zbc", 2013 "zbs", "zca", "zcb", "zcd", 2014 "zfa", "zfbfmin", "zfh", "zfhmin", 2015 "zicbom", "zicbop", "zicboz", "ziccrse", 2016 "zicntr", "zicond","zicsr", "zifencei", 2017 "zihintntl", "zihintpause", "zihpm", 2018 "zvfbfmin", "zvfbfwma", "zvfh", 2019 "zvfhmin"; 2020 riscv,cbom-block-size = <64>; 2021 riscv,cbop-block-size = <64>; 2022 riscv,cboz-block-size = <64>; 2023 2024 cpu55_intc: interrupt-controller { 2025 compatible = "riscv,cpu-intc"; 2026 interrupt-controller; 2027 #interrupt-cells = <1>; 2028 }; 2029 }; 2030 2031 cpu56: cpu@56 { 2032 compatible = "thead,c920", "riscv"; 2033 reg = <56>; 2034 i-cache-block-size = <64>; 2035 i-cache-size = <65536>; 2036 i-cache-sets = <512>; 2037 d-cache-block-size = <64>; 2038 d-cache-size = <65536>; 2039 d-cache-sets = <512>; 2040 device_type = "cpu"; 2041 mmu-type = "riscv,sv48"; 2042 next-level-cache = <&l2_cache14>; 2043 riscv,isa = "rv64imafdcv"; 2044 riscv,isa-base = "rv64i"; 2045 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2046 "v", "sscofpmf", "sstc", 2047 "svinval", "svnapot", "svpbmt", 2048 "zawrs", "zba", "zbb", "zbc", 2049 "zbs", "zca", "zcb", "zcd", 2050 "zfa", "zfbfmin", "zfh", "zfhmin", 2051 "zicbom", "zicbop", "zicboz", "ziccrse", 2052 "zicntr", "zicond","zicsr", "zifencei", 2053 "zihintntl", "zihintpause", "zihpm", 2054 "zvfbfmin", "zvfbfwma", "zvfh", 2055 "zvfhmin"; 2056 riscv,cbom-block-size = <64>; 2057 riscv,cbop-block-size = <64>; 2058 riscv,cboz-block-size = <64>; 2059 2060 cpu56_intc: interrupt-controller { 2061 compatible = "riscv,cpu-intc"; 2062 interrupt-controller; 2063 #interrupt-cells = <1>; 2064 }; 2065 }; 2066 2067 cpu57: cpu@57 { 2068 compatible = "thead,c920", "riscv"; 2069 reg = <57>; 2070 i-cache-block-size = <64>; 2071 i-cache-size = <65536>; 2072 i-cache-sets = <512>; 2073 d-cache-block-size = <64>; 2074 d-cache-size = <65536>; 2075 d-cache-sets = <512>; 2076 device_type = "cpu"; 2077 mmu-type = "riscv,sv48"; 2078 next-level-cache = <&l2_cache14>; 2079 riscv,isa = "rv64imafdcv"; 2080 riscv,isa-base = "rv64i"; 2081 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2082 "v", "sscofpmf", "sstc", 2083 "svinval", "svnapot", "svpbmt", 2084 "zawrs", "zba", "zbb", "zbc", 2085 "zbs", "zca", "zcb", "zcd", 2086 "zfa", "zfbfmin", "zfh", "zfhmin", 2087 "zicbom", "zicbop", "zicboz", "ziccrse", 2088 "zicntr", "zicond","zicsr", "zifencei", 2089 "zihintntl", "zihintpause", "zihpm", 2090 "zvfbfmin", "zvfbfwma", "zvfh", 2091 "zvfhmin"; 2092 riscv,cbom-block-size = <64>; 2093 riscv,cbop-block-size = <64>; 2094 riscv,cboz-block-size = <64>; 2095 2096 cpu57_intc: interrupt-controller { 2097 compatible = "riscv,cpu-intc"; 2098 interrupt-controller; 2099 #interrupt-cells = <1>; 2100 }; 2101 }; 2102 2103 cpu58: cpu@58 { 2104 compatible = "thead,c920", "riscv"; 2105 reg = <58>; 2106 i-cache-block-size = <64>; 2107 i-cache-size = <65536>; 2108 i-cache-sets = <512>; 2109 d-cache-block-size = <64>; 2110 d-cache-size = <65536>; 2111 d-cache-sets = <512>; 2112 device_type = "cpu"; 2113 mmu-type = "riscv,sv48"; 2114 next-level-cache = <&l2_cache14>; 2115 riscv,isa = "rv64imafdcv"; 2116 riscv,isa-base = "rv64i"; 2117 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2118 "v", "sscofpmf", "sstc", 2119 "svinval", "svnapot", "svpbmt", 2120 "zawrs", "zba", "zbb", "zbc", 2121 "zbs", "zca", "zcb", "zcd", 2122 "zfa", "zfbfmin", "zfh", "zfhmin", 2123 "zicbom", "zicbop", "zicboz", "ziccrse", 2124 "zicntr", "zicond","zicsr", "zifencei", 2125 "zihintntl", "zihintpause", "zihpm", 2126 "zvfbfmin", "zvfbfwma", "zvfh", 2127 "zvfhmin"; 2128 riscv,cbom-block-size = <64>; 2129 riscv,cbop-block-size = <64>; 2130 riscv,cboz-block-size = <64>; 2131 2132 cpu58_intc: interrupt-controller { 2133 compatible = "riscv,cpu-intc"; 2134 interrupt-controller; 2135 #interrupt-cells = <1>; 2136 }; 2137 }; 2138 2139 cpu59: cpu@59 { 2140 compatible = "thead,c920", "riscv"; 2141 reg = <59>; 2142 i-cache-block-size = <64>; 2143 i-cache-size = <65536>; 2144 i-cache-sets = <512>; 2145 d-cache-block-size = <64>; 2146 d-cache-size = <65536>; 2147 d-cache-sets = <512>; 2148 device_type = "cpu"; 2149 mmu-type = "riscv,sv48"; 2150 next-level-cache = <&l2_cache14>; 2151 riscv,isa = "rv64imafdcv"; 2152 riscv,isa-base = "rv64i"; 2153 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2154 "v", "sscofpmf", "sstc", 2155 "svinval", "svnapot", "svpbmt", 2156 "zawrs", "zba", "zbb", "zbc", 2157 "zbs", "zca", "zcb", "zcd", 2158 "zfa", "zfbfmin", "zfh", "zfhmin", 2159 "zicbom", "zicbop", "zicboz", "ziccrse", 2160 "zicntr", "zicond","zicsr", "zifencei", 2161 "zihintntl", "zihintpause", "zihpm", 2162 "zvfbfmin", "zvfbfwma", "zvfh", 2163 "zvfhmin"; 2164 riscv,cbom-block-size = <64>; 2165 riscv,cbop-block-size = <64>; 2166 riscv,cboz-block-size = <64>; 2167 2168 cpu59_intc: interrupt-controller { 2169 compatible = "riscv,cpu-intc"; 2170 interrupt-controller; 2171 #interrupt-cells = <1>; 2172 }; 2173 }; 2174 2175 cpu60: cpu@60 { 2176 compatible = "thead,c920", "riscv"; 2177 reg = <60>; 2178 i-cache-block-size = <64>; 2179 i-cache-size = <65536>; 2180 i-cache-sets = <512>; 2181 d-cache-block-size = <64>; 2182 d-cache-size = <65536>; 2183 d-cache-sets = <512>; 2184 device_type = "cpu"; 2185 mmu-type = "riscv,sv48"; 2186 next-level-cache = <&l2_cache15>; 2187 riscv,isa = "rv64imafdcv"; 2188 riscv,isa-base = "rv64i"; 2189 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2190 "v", "sscofpmf", "sstc", 2191 "svinval", "svnapot", "svpbmt", 2192 "zawrs", "zba", "zbb", "zbc", 2193 "zbs", "zca", "zcb", "zcd", 2194 "zfa", "zfbfmin", "zfh", "zfhmin", 2195 "zicbom", "zicbop", "zicboz", "ziccrse", 2196 "zicntr", "zicond","zicsr", "zifencei", 2197 "zihintntl", "zihintpause", "zihpm", 2198 "zvfbfmin", "zvfbfwma", "zvfh", 2199 "zvfhmin"; 2200 riscv,cbom-block-size = <64>; 2201 riscv,cbop-block-size = <64>; 2202 riscv,cboz-block-size = <64>; 2203 2204 cpu60_intc: interrupt-controller { 2205 compatible = "riscv,cpu-intc"; 2206 interrupt-controller; 2207 #interrupt-cells = <1>; 2208 }; 2209 }; 2210 2211 cpu61: cpu@61 { 2212 compatible = "thead,c920", "riscv"; 2213 reg = <61>; 2214 i-cache-block-size = <64>; 2215 i-cache-size = <65536>; 2216 i-cache-sets = <512>; 2217 d-cache-block-size = <64>; 2218 d-cache-size = <65536>; 2219 d-cache-sets = <512>; 2220 device_type = "cpu"; 2221 mmu-type = "riscv,sv48"; 2222 next-level-cache = <&l2_cache15>; 2223 riscv,isa = "rv64imafdcv"; 2224 riscv,isa-base = "rv64i"; 2225 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2226 "v", "sscofpmf", "sstc", 2227 "svinval", "svnapot", "svpbmt", 2228 "zawrs", "zba", "zbb", "zbc", 2229 "zbs", "zca", "zcb", "zcd", 2230 "zfa", "zfbfmin", "zfh", "zfhmin", 2231 "zicbom", "zicbop", "zicboz", "ziccrse", 2232 "zicntr", "zicond","zicsr", "zifencei", 2233 "zihintntl", "zihintpause", "zihpm", 2234 "zvfbfmin", "zvfbfwma", "zvfh", 2235 "zvfhmin"; 2236 riscv,cbom-block-size = <64>; 2237 riscv,cbop-block-size = <64>; 2238 riscv,cboz-block-size = <64>; 2239 2240 cpu61_intc: interrupt-controller { 2241 compatible = "riscv,cpu-intc"; 2242 interrupt-controller; 2243 #interrupt-cells = <1>; 2244 }; 2245 }; 2246 2247 cpu62: cpu@62 { 2248 compatible = "thead,c920", "riscv"; 2249 reg = <62>; 2250 i-cache-block-size = <64>; 2251 i-cache-size = <65536>; 2252 i-cache-sets = <512>; 2253 d-cache-block-size = <64>; 2254 d-cache-size = <65536>; 2255 d-cache-sets = <512>; 2256 device_type = "cpu"; 2257 mmu-type = "riscv,sv48"; 2258 next-level-cache = <&l2_cache15>; 2259 riscv,isa = "rv64imafdcv"; 2260 riscv,isa-base = "rv64i"; 2261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2262 "v", "sscofpmf", "sstc", 2263 "svinval", "svnapot", "svpbmt", 2264 "zawrs", "zba", "zbb", "zbc", 2265 "zbs", "zca", "zcb", "zcd", 2266 "zfa", "zfbfmin", "zfh", "zfhmin", 2267 "zicbom", "zicbop", "zicboz", "ziccrse", 2268 "zicntr", "zicond","zicsr", "zifencei", 2269 "zihintntl", "zihintpause", "zihpm", 2270 "zvfbfmin", "zvfbfwma", "zvfh", 2271 "zvfhmin"; 2272 riscv,cbom-block-size = <64>; 2273 riscv,cbop-block-size = <64>; 2274 riscv,cboz-block-size = <64>; 2275 2276 cpu62_intc: interrupt-controller { 2277 compatible = "riscv,cpu-intc"; 2278 interrupt-controller; 2279 #interrupt-cells = <1>; 2280 }; 2281 }; 2282 2283 cpu63: cpu@63 { 2284 compatible = "thead,c920", "riscv"; 2285 reg = <63>; 2286 i-cache-block-size = <64>; 2287 i-cache-size = <65536>; 2288 i-cache-sets = <512>; 2289 d-cache-block-size = <64>; 2290 d-cache-size = <65536>; 2291 d-cache-sets = <512>; 2292 device_type = "cpu"; 2293 mmu-type = "riscv,sv48"; 2294 next-level-cache = <&l2_cache15>; 2295 riscv,isa = "rv64imafdcv"; 2296 riscv,isa-base = "rv64i"; 2297 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 2298 "v", "sscofpmf", "sstc", 2299 "svinval", "svnapot", "svpbmt", 2300 "zawrs", "zba", "zbb", "zbc", 2301 "zbs", "zca", "zcb", "zcd", 2302 "zfa", "zfbfmin", "zfh", "zfhmin", 2303 "zicbom", "zicbop", "zicboz", "ziccrse", 2304 "zicntr", "zicond","zicsr", "zifencei", 2305 "zihintntl", "zihintpause", "zihpm", 2306 "zvfbfmin", "zvfbfwma", "zvfh", 2307 "zvfhmin"; 2308 riscv,cbom-block-size = <64>; 2309 riscv,cbop-block-size = <64>; 2310 riscv,cboz-block-size = <64>; 2311 2312 cpu63_intc: interrupt-controller { 2313 compatible = "riscv,cpu-intc"; 2314 interrupt-controller; 2315 #interrupt-cells = <1>; 2316 }; 2317 }; 2318 2319 cpu-map { 2320 socket0 { 2321 cluster0 { 2322 core0 { 2323 cpu = <&cpu0>; 2324 }; 2325 2326 core1 { 2327 cpu = <&cpu1>; 2328 }; 2329 2330 core2 { 2331 cpu = <&cpu2>; 2332 }; 2333 2334 core3 { 2335 cpu = <&cpu3>; 2336 }; 2337 }; 2338 2339 cluster1 { 2340 core0 { 2341 cpu = <&cpu4>; 2342 }; 2343 2344 core1 { 2345 cpu = <&cpu5>; 2346 }; 2347 2348 core2 { 2349 cpu = <&cpu6>; 2350 }; 2351 2352 core3 { 2353 cpu = <&cpu7>; 2354 }; 2355 }; 2356 2357 cluster2 { 2358 core0 { 2359 cpu = <&cpu8>; 2360 }; 2361 2362 core1 { 2363 cpu = <&cpu9>; 2364 }; 2365 2366 core2 { 2367 cpu = <&cpu10>; 2368 }; 2369 2370 core3 { 2371 cpu = <&cpu11>; 2372 }; 2373 }; 2374 2375 cluster3 { 2376 core0 { 2377 cpu = <&cpu12>; 2378 }; 2379 2380 core1 { 2381 cpu = <&cpu13>; 2382 }; 2383 2384 core2 { 2385 cpu = <&cpu14>; 2386 }; 2387 2388 core3 { 2389 cpu = <&cpu15>; 2390 }; 2391 }; 2392 2393 cluster4 { 2394 core0 { 2395 cpu = <&cpu16>; 2396 }; 2397 2398 core1 { 2399 cpu = <&cpu17>; 2400 }; 2401 2402 core2 { 2403 cpu = <&cpu18>; 2404 }; 2405 2406 core3 { 2407 cpu = <&cpu19>; 2408 }; 2409 }; 2410 2411 cluster5 { 2412 core0 { 2413 cpu = <&cpu20>; 2414 }; 2415 2416 core1 { 2417 cpu = <&cpu21>; 2418 }; 2419 2420 core2 { 2421 cpu = <&cpu22>; 2422 }; 2423 2424 core3 { 2425 cpu = <&cpu23>; 2426 }; 2427 }; 2428 2429 cluster6 { 2430 core0 { 2431 cpu = <&cpu24>; 2432 }; 2433 2434 core1 { 2435 cpu = <&cpu25>; 2436 }; 2437 2438 core2 { 2439 cpu = <&cpu26>; 2440 }; 2441 2442 core3 { 2443 cpu = <&cpu27>; 2444 }; 2445 }; 2446 2447 cluster7 { 2448 core0 { 2449 cpu = <&cpu28>; 2450 }; 2451 2452 core1 { 2453 cpu = <&cpu29>; 2454 }; 2455 2456 core2 { 2457 cpu = <&cpu30>; 2458 }; 2459 2460 core3 { 2461 cpu = <&cpu31>; 2462 }; 2463 }; 2464 2465 cluster8 { 2466 core0 { 2467 cpu = <&cpu32>; 2468 }; 2469 2470 core1 { 2471 cpu = <&cpu33>; 2472 }; 2473 2474 core2 { 2475 cpu = <&cpu34>; 2476 }; 2477 2478 core3 { 2479 cpu = <&cpu35>; 2480 }; 2481 }; 2482 2483 cluster9 { 2484 core0 { 2485 cpu = <&cpu36>; 2486 }; 2487 2488 core1 { 2489 cpu = <&cpu37>; 2490 }; 2491 2492 core2 { 2493 cpu = <&cpu38>; 2494 }; 2495 2496 core3 { 2497 cpu = <&cpu39>; 2498 }; 2499 }; 2500 2501 cluster10 { 2502 core0 { 2503 cpu = <&cpu40>; 2504 }; 2505 2506 core1 { 2507 cpu = <&cpu41>; 2508 }; 2509 2510 core2 { 2511 cpu = <&cpu42>; 2512 }; 2513 2514 core3 { 2515 cpu = <&cpu43>; 2516 }; 2517 }; 2518 2519 cluster11 { 2520 core0 { 2521 cpu = <&cpu44>; 2522 }; 2523 2524 core1 { 2525 cpu = <&cpu45>; 2526 }; 2527 2528 core2 { 2529 cpu = <&cpu46>; 2530 }; 2531 2532 core3 { 2533 cpu = <&cpu47>; 2534 }; 2535 }; 2536 2537 cluster12 { 2538 core0 { 2539 cpu = <&cpu48>; 2540 }; 2541 2542 core1 { 2543 cpu = <&cpu49>; 2544 }; 2545 2546 core2 { 2547 cpu = <&cpu50>; 2548 }; 2549 2550 core3 { 2551 cpu = <&cpu51>; 2552 }; 2553 }; 2554 2555 cluster13 { 2556 core0 { 2557 cpu = <&cpu52>; 2558 }; 2559 2560 core1 { 2561 cpu = <&cpu53>; 2562 }; 2563 2564 core2 { 2565 cpu = <&cpu54>; 2566 }; 2567 2568 core3 { 2569 cpu = <&cpu55>; 2570 }; 2571 }; 2572 2573 cluster14 { 2574 core0 { 2575 cpu = <&cpu56>; 2576 }; 2577 2578 core1 { 2579 cpu = <&cpu57>; 2580 }; 2581 2582 core2 { 2583 cpu = <&cpu58>; 2584 }; 2585 2586 core3 { 2587 cpu = <&cpu59>; 2588 }; 2589 }; 2590 2591 cluster15 { 2592 core0 { 2593 cpu = <&cpu60>; 2594 }; 2595 2596 core1 { 2597 cpu = <&cpu61>; 2598 }; 2599 2600 core2 { 2601 cpu = <&cpu62>; 2602 }; 2603 2604 core3 { 2605 cpu = <&cpu63>; 2606 }; 2607 }; 2608 }; 2609 }; 2610 2611 l2_cache0: cache-controller-0 { 2612 compatible = "cache"; 2613 cache-block-size = <64>; 2614 cache-level = <2>; 2615 cache-size = <2097152>; 2616 cache-sets = <2048>; 2617 cache-unified; 2618 next-level-cache = <&l3_cache>; 2619 }; 2620 2621 l2_cache1: cache-controller-1 { 2622 compatible = "cache"; 2623 cache-block-size = <64>; 2624 cache-level = <2>; 2625 cache-size = <2097152>; 2626 cache-sets = <2048>; 2627 cache-unified; 2628 next-level-cache = <&l3_cache>; 2629 }; 2630 2631 l2_cache2: cache-controller-2 { 2632 compatible = "cache"; 2633 cache-block-size = <64>; 2634 cache-level = <2>; 2635 cache-size = <2097152>; 2636 cache-sets = <2048>; 2637 cache-unified; 2638 next-level-cache = <&l3_cache>; 2639 }; 2640 2641 l2_cache3: cache-controller-3 { 2642 compatible = "cache"; 2643 cache-block-size = <64>; 2644 cache-level = <2>; 2645 cache-size = <2097152>; 2646 cache-sets = <2048>; 2647 cache-unified; 2648 next-level-cache = <&l3_cache>; 2649 }; 2650 2651 l2_cache4: cache-controller-4 { 2652 compatible = "cache"; 2653 cache-block-size = <64>; 2654 cache-level = <2>; 2655 cache-size = <2097152>; 2656 cache-sets = <2048>; 2657 cache-unified; 2658 next-level-cache = <&l3_cache>; 2659 }; 2660 2661 l2_cache5: cache-controller-5 { 2662 compatible = "cache"; 2663 cache-block-size = <64>; 2664 cache-level = <2>; 2665 cache-size = <2097152>; 2666 cache-sets = <2048>; 2667 cache-unified; 2668 next-level-cache = <&l3_cache>; 2669 }; 2670 2671 l2_cache6: cache-controller-6 { 2672 compatible = "cache"; 2673 cache-block-size = <64>; 2674 cache-level = <2>; 2675 cache-size = <2097152>; 2676 cache-sets = <2048>; 2677 cache-unified; 2678 next-level-cache = <&l3_cache>; 2679 }; 2680 2681 l2_cache7: cache-controller-7 { 2682 compatible = "cache"; 2683 cache-block-size = <64>; 2684 cache-level = <2>; 2685 cache-size = <2097152>; 2686 cache-sets = <2048>; 2687 cache-unified; 2688 next-level-cache = <&l3_cache>; 2689 }; 2690 2691 l2_cache8: cache-controller-8 { 2692 compatible = "cache"; 2693 cache-block-size = <64>; 2694 cache-level = <2>; 2695 cache-size = <2097152>; 2696 cache-sets = <2048>; 2697 cache-unified; 2698 next-level-cache = <&l3_cache>; 2699 }; 2700 2701 l2_cache9: cache-controller-9 { 2702 compatible = "cache"; 2703 cache-block-size = <64>; 2704 cache-level = <2>; 2705 cache-size = <2097152>; 2706 cache-sets = <2048>; 2707 cache-unified; 2708 next-level-cache = <&l3_cache>; 2709 }; 2710 2711 l2_cache10: cache-controller-10 { 2712 compatible = "cache"; 2713 cache-block-size = <64>; 2714 cache-level = <2>; 2715 cache-size = <2097152>; 2716 cache-sets = <2048>; 2717 cache-unified; 2718 next-level-cache = <&l3_cache>; 2719 }; 2720 2721 l2_cache11: cache-controller-11 { 2722 compatible = "cache"; 2723 cache-block-size = <64>; 2724 cache-level = <2>; 2725 cache-size = <2097152>; 2726 cache-sets = <2048>; 2727 cache-unified; 2728 next-level-cache = <&l3_cache>; 2729 }; 2730 2731 l2_cache12: cache-controller-12 { 2732 compatible = "cache"; 2733 cache-block-size = <64>; 2734 cache-level = <2>; 2735 cache-size = <2097152>; 2736 cache-sets = <2048>; 2737 cache-unified; 2738 next-level-cache = <&l3_cache>; 2739 }; 2740 2741 l2_cache13: cache-controller-13 { 2742 compatible = "cache"; 2743 cache-block-size = <64>; 2744 cache-level = <2>; 2745 cache-size = <2097152>; 2746 cache-sets = <2048>; 2747 cache-unified; 2748 next-level-cache = <&l3_cache>; 2749 }; 2750 2751 l2_cache14: cache-controller-14 { 2752 compatible = "cache"; 2753 cache-block-size = <64>; 2754 cache-level = <2>; 2755 cache-size = <2097152>; 2756 cache-sets = <2048>; 2757 cache-unified; 2758 next-level-cache = <&l3_cache>; 2759 }; 2760 2761 l2_cache15: cache-controller-15 { 2762 compatible = "cache"; 2763 cache-block-size = <64>; 2764 cache-level = <2>; 2765 cache-size = <2097152>; 2766 cache-sets = <2048>; 2767 cache-unified; 2768 next-level-cache = <&l3_cache>; 2769 }; 2770 2771 l3_cache: cache-controller-16 { 2772 compatible = "cache"; 2773 cache-block-size = <64>; 2774 cache-level = <3>; 2775 cache-size = <67108864>; 2776 cache-sets = <4096>; 2777 cache-unified; 2778 }; 2779 }; 2780 2781 pmu { 2782 compatible = "riscv,pmu"; 2783 riscv,event-to-mhpmevent = 2784 <0x00003 0x00000000 0x00000010>, 2785 <0x00004 0x00000000 0x00000011>, 2786 <0x00005 0x00000000 0x00000007>, 2787 <0x00006 0x00000000 0x00000006>, 2788 <0x00008 0x00000000 0x00000027>, 2789 <0x00009 0x00000000 0x00000028>, 2790 <0x10000 0x00000000 0x0000000c>, 2791 <0x10001 0x00000000 0x0000000d>, 2792 <0x10002 0x00000000 0x0000000e>, 2793 <0x10003 0x00000000 0x0000000f>, 2794 <0x10008 0x00000000 0x00000001>, 2795 <0x10009 0x00000000 0x00000002>, 2796 <0x10010 0x00000000 0x00000010>, 2797 <0x10011 0x00000000 0x00000011>, 2798 <0x10012 0x00000000 0x00000012>, 2799 <0x10013 0x00000000 0x00000013>, 2800 <0x10019 0x00000000 0x00000004>, 2801 <0x10021 0x00000000 0x00000003>, 2802 <0x10030 0x00000000 0x0000001c>, 2803 <0x10031 0x00000000 0x0000001b>; 2804 riscv,event-to-mhpmcounters = 2805 <0x00003 0x00003 0xfffffff8>, 2806 <0x00004 0x00004 0xfffffff8>, 2807 <0x00005 0x00005 0xfffffff8>, 2808 <0x00006 0x00006 0xfffffff8>, 2809 <0x00007 0x00007 0xfffffff8>, 2810 <0x00008 0x00008 0xfffffff8>, 2811 <0x00009 0x00009 0xfffffff8>, 2812 <0x0000a 0x0000a 0xfffffff8>, 2813 <0x10000 0x10000 0xfffffff8>, 2814 <0x10001 0x10001 0xfffffff8>, 2815 <0x10002 0x10002 0xfffffff8>, 2816 <0x10003 0x10003 0xfffffff8>, 2817 <0x10008 0x10008 0xfffffff8>, 2818 <0x10009 0x10009 0xfffffff8>, 2819 <0x10010 0x10010 0xfffffff8>, 2820 <0x10011 0x10011 0xfffffff8>, 2821 <0x10012 0x10012 0xfffffff8>, 2822 <0x10013 0x10013 0xfffffff8>, 2823 <0x10019 0x10019 0xfffffff8>, 2824 <0x10021 0x10021 0xfffffff8>, 2825 <0x10030 0x10030 0xfffffff8>, 2826 <0x10031 0x10031 0xfffffff8>; 2827 riscv,raw-event-to-mhpmcounters = 2828 <0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>, 2829 <0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>, 2830 <0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>, 2831 <0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>, 2832 <0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>, 2833 <0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>, 2834 <0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>, 2835 <0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>, 2836 <0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>, 2837 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>, 2838 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>, 2839 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>, 2840 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>, 2841 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>, 2842 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>, 2843 <0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>, 2844 <0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>, 2845 <0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>, 2846 <0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>, 2847 <0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>, 2848 <0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>, 2849 <0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>, 2850 <0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>, 2851 <0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>, 2852 <0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>, 2853 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>, 2854 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>, 2855 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>, 2856 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>, 2857 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>, 2858 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>, 2859 <0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>, 2860 <0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>, 2861 <0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>, 2862 <0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>, 2863 <0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>, 2864 <0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>, 2865 <0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>, 2866 <0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>, 2867 <0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>, 2868 <0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>, 2869 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>; 2870 }; 2871 2872 soc { 2873 intc: interrupt-controller@6d40000000 { 2874 compatible = "sophgo,sg2044-plic", "thead,c900-plic"; 2875 #address-cells = <0>; 2876 #interrupt-cells = <2>; 2877 reg = <0x6d 0x40000000 0x0 0x4000000>; 2878 interrupt-controller; 2879 interrupts-extended = 2880 <&cpu0_intc 11>, <&cpu0_intc 9>, 2881 <&cpu1_intc 11>, <&cpu1_intc 9>, 2882 <&cpu2_intc 11>, <&cpu2_intc 9>, 2883 <&cpu3_intc 11>, <&cpu3_intc 9>, 2884 <&cpu4_intc 11>, <&cpu4_intc 9>, 2885 <&cpu5_intc 11>, <&cpu5_intc 9>, 2886 <&cpu6_intc 11>, <&cpu6_intc 9>, 2887 <&cpu7_intc 11>, <&cpu7_intc 9>, 2888 <&cpu8_intc 11>, <&cpu8_intc 9>, 2889 <&cpu9_intc 11>, <&cpu9_intc 9>, 2890 <&cpu10_intc 11>, <&cpu10_intc 9>, 2891 <&cpu11_intc 11>, <&cpu11_intc 9>, 2892 <&cpu12_intc 11>, <&cpu12_intc 9>, 2893 <&cpu13_intc 11>, <&cpu13_intc 9>, 2894 <&cpu14_intc 11>, <&cpu14_intc 9>, 2895 <&cpu15_intc 11>, <&cpu15_intc 9>, 2896 <&cpu16_intc 11>, <&cpu16_intc 9>, 2897 <&cpu17_intc 11>, <&cpu17_intc 9>, 2898 <&cpu18_intc 11>, <&cpu18_intc 9>, 2899 <&cpu19_intc 11>, <&cpu19_intc 9>, 2900 <&cpu20_intc 11>, <&cpu20_intc 9>, 2901 <&cpu21_intc 11>, <&cpu21_intc 9>, 2902 <&cpu22_intc 11>, <&cpu22_intc 9>, 2903 <&cpu23_intc 11>, <&cpu23_intc 9>, 2904 <&cpu24_intc 11>, <&cpu24_intc 9>, 2905 <&cpu25_intc 11>, <&cpu25_intc 9>, 2906 <&cpu26_intc 11>, <&cpu26_intc 9>, 2907 <&cpu27_intc 11>, <&cpu27_intc 9>, 2908 <&cpu28_intc 11>, <&cpu28_intc 9>, 2909 <&cpu29_intc 11>, <&cpu29_intc 9>, 2910 <&cpu30_intc 11>, <&cpu30_intc 9>, 2911 <&cpu31_intc 11>, <&cpu31_intc 9>, 2912 <&cpu32_intc 11>, <&cpu32_intc 9>, 2913 <&cpu33_intc 11>, <&cpu33_intc 9>, 2914 <&cpu34_intc 11>, <&cpu34_intc 9>, 2915 <&cpu35_intc 11>, <&cpu35_intc 9>, 2916 <&cpu36_intc 11>, <&cpu36_intc 9>, 2917 <&cpu37_intc 11>, <&cpu37_intc 9>, 2918 <&cpu38_intc 11>, <&cpu38_intc 9>, 2919 <&cpu39_intc 11>, <&cpu39_intc 9>, 2920 <&cpu40_intc 11>, <&cpu40_intc 9>, 2921 <&cpu41_intc 11>, <&cpu41_intc 9>, 2922 <&cpu42_intc 11>, <&cpu42_intc 9>, 2923 <&cpu43_intc 11>, <&cpu43_intc 9>, 2924 <&cpu44_intc 11>, <&cpu44_intc 9>, 2925 <&cpu45_intc 11>, <&cpu45_intc 9>, 2926 <&cpu46_intc 11>, <&cpu46_intc 9>, 2927 <&cpu47_intc 11>, <&cpu47_intc 9>, 2928 <&cpu48_intc 11>, <&cpu48_intc 9>, 2929 <&cpu49_intc 11>, <&cpu49_intc 9>, 2930 <&cpu50_intc 11>, <&cpu50_intc 9>, 2931 <&cpu51_intc 11>, <&cpu51_intc 9>, 2932 <&cpu52_intc 11>, <&cpu52_intc 9>, 2933 <&cpu53_intc 11>, <&cpu53_intc 9>, 2934 <&cpu54_intc 11>, <&cpu54_intc 9>, 2935 <&cpu55_intc 11>, <&cpu55_intc 9>, 2936 <&cpu56_intc 11>, <&cpu56_intc 9>, 2937 <&cpu57_intc 11>, <&cpu57_intc 9>, 2938 <&cpu58_intc 11>, <&cpu58_intc 9>, 2939 <&cpu59_intc 11>, <&cpu59_intc 9>, 2940 <&cpu60_intc 11>, <&cpu60_intc 9>, 2941 <&cpu61_intc 11>, <&cpu61_intc 9>, 2942 <&cpu62_intc 11>, <&cpu62_intc 9>, 2943 <&cpu63_intc 11>, <&cpu63_intc 9>; 2944 riscv,ndev = <863>; 2945 }; 2946 2947 aclint_mswi: interrupt-controller@6d44000000 { 2948 compatible = "sophgo,sg2044-aclint-mswi", "thead,c900-aclint-mswi"; 2949 reg = <0x6d 0x44000000 0x0 0x4000>; 2950 interrupts-extended = <&cpu0_intc 3>, 2951 <&cpu1_intc 3>, 2952 <&cpu2_intc 3>, 2953 <&cpu3_intc 3>, 2954 <&cpu4_intc 3>, 2955 <&cpu5_intc 3>, 2956 <&cpu6_intc 3>, 2957 <&cpu7_intc 3>, 2958 <&cpu8_intc 3>, 2959 <&cpu9_intc 3>, 2960 <&cpu10_intc 3>, 2961 <&cpu11_intc 3>, 2962 <&cpu12_intc 3>, 2963 <&cpu13_intc 3>, 2964 <&cpu14_intc 3>, 2965 <&cpu15_intc 3>, 2966 <&cpu16_intc 3>, 2967 <&cpu17_intc 3>, 2968 <&cpu18_intc 3>, 2969 <&cpu19_intc 3>, 2970 <&cpu20_intc 3>, 2971 <&cpu21_intc 3>, 2972 <&cpu22_intc 3>, 2973 <&cpu23_intc 3>, 2974 <&cpu24_intc 3>, 2975 <&cpu25_intc 3>, 2976 <&cpu26_intc 3>, 2977 <&cpu27_intc 3>, 2978 <&cpu28_intc 3>, 2979 <&cpu29_intc 3>, 2980 <&cpu30_intc 3>, 2981 <&cpu31_intc 3>, 2982 <&cpu32_intc 3>, 2983 <&cpu33_intc 3>, 2984 <&cpu34_intc 3>, 2985 <&cpu35_intc 3>, 2986 <&cpu36_intc 3>, 2987 <&cpu37_intc 3>, 2988 <&cpu38_intc 3>, 2989 <&cpu39_intc 3>, 2990 <&cpu40_intc 3>, 2991 <&cpu41_intc 3>, 2992 <&cpu42_intc 3>, 2993 <&cpu43_intc 3>, 2994 <&cpu44_intc 3>, 2995 <&cpu45_intc 3>, 2996 <&cpu46_intc 3>, 2997 <&cpu47_intc 3>, 2998 <&cpu48_intc 3>, 2999 <&cpu49_intc 3>, 3000 <&cpu50_intc 3>, 3001 <&cpu51_intc 3>, 3002 <&cpu52_intc 3>, 3003 <&cpu53_intc 3>, 3004 <&cpu54_intc 3>, 3005 <&cpu55_intc 3>, 3006 <&cpu56_intc 3>, 3007 <&cpu57_intc 3>, 3008 <&cpu58_intc 3>, 3009 <&cpu59_intc 3>, 3010 <&cpu60_intc 3>, 3011 <&cpu61_intc 3>, 3012 <&cpu62_intc 3>, 3013 <&cpu63_intc 3>; 3014 }; 3015 3016 aclint_mtimer: timer@6d44004000 { 3017 compatible = "sophgo,sg2044-aclint-mtimer", "thead,c900-aclint-mtimer"; 3018 reg = <0x6d 0x44004000 0x0 0x8000>; 3019 reg-names = "mtimecmp"; 3020 interrupts-extended = <&cpu0_intc 7>, 3021 <&cpu1_intc 7>, 3022 <&cpu2_intc 7>, 3023 <&cpu3_intc 7>, 3024 <&cpu4_intc 7>, 3025 <&cpu5_intc 7>, 3026 <&cpu6_intc 7>, 3027 <&cpu7_intc 7>, 3028 <&cpu8_intc 7>, 3029 <&cpu9_intc 7>, 3030 <&cpu10_intc 7>, 3031 <&cpu11_intc 7>, 3032 <&cpu12_intc 7>, 3033 <&cpu13_intc 7>, 3034 <&cpu14_intc 7>, 3035 <&cpu15_intc 7>, 3036 <&cpu16_intc 7>, 3037 <&cpu17_intc 7>, 3038 <&cpu18_intc 7>, 3039 <&cpu19_intc 7>, 3040 <&cpu20_intc 7>, 3041 <&cpu21_intc 7>, 3042 <&cpu22_intc 7>, 3043 <&cpu23_intc 7>, 3044 <&cpu24_intc 7>, 3045 <&cpu25_intc 7>, 3046 <&cpu26_intc 7>, 3047 <&cpu27_intc 7>, 3048 <&cpu28_intc 7>, 3049 <&cpu29_intc 7>, 3050 <&cpu30_intc 7>, 3051 <&cpu31_intc 7>, 3052 <&cpu32_intc 7>, 3053 <&cpu33_intc 7>, 3054 <&cpu34_intc 7>, 3055 <&cpu35_intc 7>, 3056 <&cpu36_intc 7>, 3057 <&cpu37_intc 7>, 3058 <&cpu38_intc 7>, 3059 <&cpu39_intc 7>, 3060 <&cpu40_intc 7>, 3061 <&cpu41_intc 7>, 3062 <&cpu42_intc 7>, 3063 <&cpu43_intc 7>, 3064 <&cpu44_intc 7>, 3065 <&cpu45_intc 7>, 3066 <&cpu46_intc 7>, 3067 <&cpu47_intc 7>, 3068 <&cpu48_intc 7>, 3069 <&cpu49_intc 7>, 3070 <&cpu50_intc 7>, 3071 <&cpu51_intc 7>, 3072 <&cpu52_intc 7>, 3073 <&cpu53_intc 7>, 3074 <&cpu54_intc 7>, 3075 <&cpu55_intc 7>, 3076 <&cpu56_intc 7>, 3077 <&cpu57_intc 7>, 3078 <&cpu58_intc 7>, 3079 <&cpu59_intc 7>, 3080 <&cpu60_intc 7>, 3081 <&cpu61_intc 7>, 3082 <&cpu62_intc 7>, 3083 <&cpu63_intc 7>; 3084 }; 3085 3086 aclint_sswi: interrupt-controller@6d4400c000 { 3087 compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi"; 3088 reg = <0x6d 0x4400c000 0x0 0x1000>; 3089 #interrupt-cells = <0>; 3090 interrupt-controller; 3091 interrupts-extended = <&cpu0_intc 1>, 3092 <&cpu1_intc 1>, 3093 <&cpu2_intc 1>, 3094 <&cpu3_intc 1>, 3095 <&cpu4_intc 1>, 3096 <&cpu5_intc 1>, 3097 <&cpu6_intc 1>, 3098 <&cpu7_intc 1>, 3099 <&cpu8_intc 1>, 3100 <&cpu9_intc 1>, 3101 <&cpu10_intc 1>, 3102 <&cpu11_intc 1>, 3103 <&cpu12_intc 1>, 3104 <&cpu13_intc 1>, 3105 <&cpu14_intc 1>, 3106 <&cpu15_intc 1>, 3107 <&cpu16_intc 1>, 3108 <&cpu17_intc 1>, 3109 <&cpu18_intc 1>, 3110 <&cpu19_intc 1>, 3111 <&cpu20_intc 1>, 3112 <&cpu21_intc 1>, 3113 <&cpu22_intc 1>, 3114 <&cpu23_intc 1>, 3115 <&cpu24_intc 1>, 3116 <&cpu25_intc 1>, 3117 <&cpu26_intc 1>, 3118 <&cpu27_intc 1>, 3119 <&cpu28_intc 1>, 3120 <&cpu29_intc 1>, 3121 <&cpu30_intc 1>, 3122 <&cpu31_intc 1>, 3123 <&cpu32_intc 1>, 3124 <&cpu33_intc 1>, 3125 <&cpu34_intc 1>, 3126 <&cpu35_intc 1>, 3127 <&cpu36_intc 1>, 3128 <&cpu37_intc 1>, 3129 <&cpu38_intc 1>, 3130 <&cpu39_intc 1>, 3131 <&cpu40_intc 1>, 3132 <&cpu41_intc 1>, 3133 <&cpu42_intc 1>, 3134 <&cpu43_intc 1>, 3135 <&cpu44_intc 1>, 3136 <&cpu45_intc 1>, 3137 <&cpu46_intc 1>, 3138 <&cpu47_intc 1>, 3139 <&cpu48_intc 1>, 3140 <&cpu49_intc 1>, 3141 <&cpu50_intc 1>, 3142 <&cpu51_intc 1>, 3143 <&cpu52_intc 1>, 3144 <&cpu53_intc 1>, 3145 <&cpu54_intc 1>, 3146 <&cpu55_intc 1>, 3147 <&cpu56_intc 1>, 3148 <&cpu57_intc 1>, 3149 <&cpu58_intc 1>, 3150 <&cpu59_intc 1>, 3151 <&cpu60_intc 1>, 3152 <&cpu61_intc 1>, 3153 <&cpu62_intc 1>, 3154 <&cpu63_intc 1>; 3155 }; 3156 }; 3157}; 3158