1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
8 #define __ARM64_KVM_HYP_SWITCH_H__
9
10 #include <hyp/adjust_pc.h>
11 #include <hyp/fault.h>
12
13 #include <linux/arm-smccc.h>
14 #include <linux/kvm_host.h>
15 #include <linux/types.h>
16 #include <linux/jump_label.h>
17 #include <uapi/linux/psci.h>
18
19 #include <kvm/arm_psci.h>
20
21 #include <asm/barrier.h>
22 #include <asm/cpufeature.h>
23 #include <asm/extable.h>
24 #include <asm/kprobes.h>
25 #include <asm/kvm_asm.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_hyp.h>
28 #include <asm/kvm_mmu.h>
29 #include <asm/kvm_nested.h>
30 #include <asm/fpsimd.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/processor.h>
33 #include <asm/traps.h>
34
35 struct kvm_exception_table_entry {
36 int insn, fixup;
37 };
38
39 extern struct kvm_exception_table_entry __start___kvm_ex_table;
40 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
41
42 /* Save the 32-bit only FPSIMD system register state */
__fpsimd_save_fpexc32(struct kvm_vcpu * vcpu)43 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
44 {
45 if (!vcpu_el1_is_32bit(vcpu))
46 return;
47
48 __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2);
49 }
50
__activate_traps_fpsimd32(struct kvm_vcpu * vcpu)51 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
52 {
53 /*
54 * We are about to set CPTR_EL2.TFP to trap all floating point
55 * register accesses to EL2, however, the ARM ARM clearly states that
56 * traps are only taken to EL2 if the operation would not otherwise
57 * trap to EL1. Therefore, always make sure that for 32-bit guests,
58 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
59 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
60 * it will cause an exception.
61 */
62 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
63 write_sysreg(1 << 30, fpexc32_el2);
64 isb();
65 }
66 }
67
68 #define compute_clr_set(vcpu, reg, clr, set) \
69 do { \
70 u64 hfg; \
71 hfg = __vcpu_sys_reg(vcpu, reg) & ~__ ## reg ## _RES0; \
72 set |= hfg & __ ## reg ## _MASK; \
73 clr |= ~hfg & __ ## reg ## _nMASK; \
74 } while(0)
75
76 #define reg_to_fgt_group_id(reg) \
77 ({ \
78 enum fgt_group_id id; \
79 switch(reg) { \
80 case HFGRTR_EL2: \
81 case HFGWTR_EL2: \
82 id = HFGxTR_GROUP; \
83 break; \
84 case HFGITR_EL2: \
85 id = HFGITR_GROUP; \
86 break; \
87 case HDFGRTR_EL2: \
88 case HDFGWTR_EL2: \
89 id = HDFGRTR_GROUP; \
90 break; \
91 case HAFGRTR_EL2: \
92 id = HAFGRTR_GROUP; \
93 break; \
94 default: \
95 BUILD_BUG_ON(1); \
96 } \
97 \
98 id; \
99 })
100
101 #define compute_undef_clr_set(vcpu, kvm, reg, clr, set) \
102 do { \
103 u64 hfg = kvm->arch.fgu[reg_to_fgt_group_id(reg)]; \
104 set |= hfg & __ ## reg ## _MASK; \
105 clr |= hfg & __ ## reg ## _nMASK; \
106 } while(0)
107
108 #define update_fgt_traps_cs(hctxt, vcpu, kvm, reg, clr, set) \
109 do { \
110 u64 c = 0, s = 0; \
111 \
112 ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg); \
113 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) \
114 compute_clr_set(vcpu, reg, c, s); \
115 \
116 compute_undef_clr_set(vcpu, kvm, reg, c, s); \
117 \
118 s |= set; \
119 c |= clr; \
120 if (c || s) { \
121 u64 val = __ ## reg ## _nMASK; \
122 val |= s; \
123 val &= ~c; \
124 write_sysreg_s(val, SYS_ ## reg); \
125 } \
126 } while(0)
127
128 #define update_fgt_traps(hctxt, vcpu, kvm, reg) \
129 update_fgt_traps_cs(hctxt, vcpu, kvm, reg, 0, 0)
130
131 /*
132 * Validate the fine grain trap masks.
133 * Check that the masks do not overlap and that all bits are accounted for.
134 */
135 #define CHECK_FGT_MASKS(reg) \
136 do { \
137 BUILD_BUG_ON((__ ## reg ## _MASK) & (__ ## reg ## _nMASK)); \
138 BUILD_BUG_ON(~((__ ## reg ## _RES0) ^ (__ ## reg ## _MASK) ^ \
139 (__ ## reg ## _nMASK))); \
140 } while(0)
141
cpu_has_amu(void)142 static inline bool cpu_has_amu(void)
143 {
144 u64 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
145
146 return cpuid_feature_extract_unsigned_field(pfr0,
147 ID_AA64PFR0_EL1_AMU_SHIFT);
148 }
149
__activate_traps_hfgxtr(struct kvm_vcpu * vcpu)150 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
151 {
152 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
153 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
154
155 CHECK_FGT_MASKS(HFGRTR_EL2);
156 CHECK_FGT_MASKS(HFGWTR_EL2);
157 CHECK_FGT_MASKS(HFGITR_EL2);
158 CHECK_FGT_MASKS(HDFGRTR_EL2);
159 CHECK_FGT_MASKS(HDFGWTR_EL2);
160 CHECK_FGT_MASKS(HAFGRTR_EL2);
161 CHECK_FGT_MASKS(HCRX_EL2);
162
163 if (!cpus_have_final_cap(ARM64_HAS_FGT))
164 return;
165
166 update_fgt_traps(hctxt, vcpu, kvm, HFGRTR_EL2);
167 update_fgt_traps_cs(hctxt, vcpu, kvm, HFGWTR_EL2, 0,
168 cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) ?
169 HFGxTR_EL2_TCR_EL1_MASK : 0);
170 update_fgt_traps(hctxt, vcpu, kvm, HFGITR_EL2);
171 update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR_EL2);
172 update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR_EL2);
173
174 if (cpu_has_amu())
175 update_fgt_traps(hctxt, vcpu, kvm, HAFGRTR_EL2);
176 }
177
178 #define __deactivate_fgt(htcxt, vcpu, kvm, reg) \
179 do { \
180 if ((vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) || \
181 kvm->arch.fgu[reg_to_fgt_group_id(reg)]) \
182 write_sysreg_s(ctxt_sys_reg(hctxt, reg), \
183 SYS_ ## reg); \
184 } while(0)
185
__deactivate_traps_hfgxtr(struct kvm_vcpu * vcpu)186 static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
187 {
188 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
189 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
190
191 if (!cpus_have_final_cap(ARM64_HAS_FGT))
192 return;
193
194 __deactivate_fgt(hctxt, vcpu, kvm, HFGRTR_EL2);
195 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
196 write_sysreg_s(ctxt_sys_reg(hctxt, HFGWTR_EL2), SYS_HFGWTR_EL2);
197 else
198 __deactivate_fgt(hctxt, vcpu, kvm, HFGWTR_EL2);
199 __deactivate_fgt(hctxt, vcpu, kvm, HFGITR_EL2);
200 __deactivate_fgt(hctxt, vcpu, kvm, HDFGRTR_EL2);
201 __deactivate_fgt(hctxt, vcpu, kvm, HDFGWTR_EL2);
202
203 if (cpu_has_amu())
204 __deactivate_fgt(hctxt, vcpu, kvm, HAFGRTR_EL2);
205 }
206
__activate_traps_common(struct kvm_vcpu * vcpu)207 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
208 {
209 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
210 write_sysreg(1 << 15, hstr_el2);
211
212 /*
213 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
214 * PMSELR_EL0 to make sure it never contains the cycle
215 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
216 * EL1 instead of being trapped to EL2.
217 */
218 if (kvm_arm_support_pmu_v3()) {
219 struct kvm_cpu_context *hctxt;
220
221 write_sysreg(0, pmselr_el0);
222
223 hctxt = host_data_ptr(host_ctxt);
224 ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
225 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
226 vcpu_set_flag(vcpu, PMUSERENR_ON_CPU);
227 }
228
229 *host_data_ptr(host_debug_state.mdcr_el2) = read_sysreg(mdcr_el2);
230 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
231
232 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
233 u64 hcrx = vcpu->arch.hcrx_el2;
234 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
235 u64 clr = 0, set = 0;
236
237 compute_clr_set(vcpu, HCRX_EL2, clr, set);
238
239 hcrx |= set;
240 hcrx &= ~clr;
241 }
242
243 write_sysreg_s(hcrx, SYS_HCRX_EL2);
244 }
245
246 __activate_traps_hfgxtr(vcpu);
247 }
248
__deactivate_traps_common(struct kvm_vcpu * vcpu)249 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
250 {
251 write_sysreg(*host_data_ptr(host_debug_state.mdcr_el2), mdcr_el2);
252
253 write_sysreg(0, hstr_el2);
254 if (kvm_arm_support_pmu_v3()) {
255 struct kvm_cpu_context *hctxt;
256
257 hctxt = host_data_ptr(host_ctxt);
258 write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
259 vcpu_clear_flag(vcpu, PMUSERENR_ON_CPU);
260 }
261
262 if (cpus_have_final_cap(ARM64_HAS_HCX))
263 write_sysreg_s(HCRX_HOST_FLAGS, SYS_HCRX_EL2);
264
265 __deactivate_traps_hfgxtr(vcpu);
266 }
267
___activate_traps(struct kvm_vcpu * vcpu,u64 hcr)268 static inline void ___activate_traps(struct kvm_vcpu *vcpu, u64 hcr)
269 {
270 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
271 hcr |= HCR_TVM;
272
273 write_sysreg(hcr, hcr_el2);
274
275 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
276 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
277 }
278
___deactivate_traps(struct kvm_vcpu * vcpu)279 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
280 {
281 /*
282 * If we pended a virtual abort, preserve it until it gets
283 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
284 * the crucial bit is "On taking a vSError interrupt,
285 * HCR_EL2.VSE is cleared to 0."
286 */
287 if (vcpu->arch.hcr_el2 & HCR_VSE) {
288 vcpu->arch.hcr_el2 &= ~HCR_VSE;
289 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
290 }
291 }
292
__populate_fault_info(struct kvm_vcpu * vcpu)293 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
294 {
295 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
296 }
297
kvm_hyp_handle_mops(struct kvm_vcpu * vcpu,u64 * exit_code)298 static bool kvm_hyp_handle_mops(struct kvm_vcpu *vcpu, u64 *exit_code)
299 {
300 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
301 arm64_mops_reset_regs(vcpu_gp_regs(vcpu), vcpu->arch.fault.esr_el2);
302 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
303
304 /*
305 * Finish potential single step before executing the prologue
306 * instruction.
307 */
308 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
309 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
310
311 return true;
312 }
313
__hyp_sve_restore_guest(struct kvm_vcpu * vcpu)314 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
315 {
316 /*
317 * The vCPU's saved SVE state layout always matches the max VL of the
318 * vCPU. Start off with the max VL so we can load the SVE state.
319 */
320 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
321 __sve_restore_state(vcpu_sve_pffr(vcpu),
322 &vcpu->arch.ctxt.fp_regs.fpsr,
323 true);
324
325 /*
326 * The effective VL for a VM could differ from the max VL when running a
327 * nested guest, as the guest hypervisor could select a smaller VL. Slap
328 * that into hardware before wrapping up.
329 */
330 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu))
331 sve_cond_update_zcr_vq(__vcpu_sys_reg(vcpu, ZCR_EL2), SYS_ZCR_EL2);
332
333 write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)), SYS_ZCR);
334 }
335
__hyp_sve_save_host(void)336 static inline void __hyp_sve_save_host(void)
337 {
338 struct cpu_sve_state *sve_state = *host_data_ptr(sve_state);
339
340 sve_state->zcr_el1 = read_sysreg_el1(SYS_ZCR);
341 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL2);
342 __sve_save_state(sve_state->sve_regs + sve_ffr_offset(kvm_host_sve_max_vl),
343 &sve_state->fpsr,
344 true);
345 }
346
347 static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu);
348
349 /*
350 * We trap the first access to the FP/SIMD to save the host context and
351 * restore the guest context lazily.
352 * If FP/SIMD is not implemented, handle the trap and inject an undefined
353 * instruction exception to the guest. Similarly for trapped SVE accesses.
354 */
kvm_hyp_handle_fpsimd(struct kvm_vcpu * vcpu,u64 * exit_code)355 static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
356 {
357 bool sve_guest;
358 u8 esr_ec;
359
360 if (!system_supports_fpsimd())
361 return false;
362
363 sve_guest = vcpu_has_sve(vcpu);
364 esr_ec = kvm_vcpu_trap_get_class(vcpu);
365
366 /* Only handle traps the vCPU can support here: */
367 switch (esr_ec) {
368 case ESR_ELx_EC_FP_ASIMD:
369 /* Forward traps to the guest hypervisor as required */
370 if (guest_hyp_fpsimd_traps_enabled(vcpu))
371 return false;
372 break;
373 case ESR_ELx_EC_SYS64:
374 if (WARN_ON_ONCE(!is_hyp_ctxt(vcpu)))
375 return false;
376 fallthrough;
377 case ESR_ELx_EC_SVE:
378 if (!sve_guest)
379 return false;
380 if (guest_hyp_sve_traps_enabled(vcpu))
381 return false;
382 break;
383 default:
384 return false;
385 }
386
387 /* Valid trap. Switch the context: */
388
389 /* First disable enough traps to allow us to update the registers */
390 if (sve_guest || (is_protected_kvm_enabled() && system_supports_sve()))
391 cpacr_clear_set(0, CPACR_ELx_FPEN | CPACR_ELx_ZEN);
392 else
393 cpacr_clear_set(0, CPACR_ELx_FPEN);
394 isb();
395
396 /* Write out the host state if it's in the registers */
397 if (host_owns_fp_regs())
398 kvm_hyp_save_fpsimd_host(vcpu);
399
400 /* Restore the guest state */
401 if (sve_guest)
402 __hyp_sve_restore_guest(vcpu);
403 else
404 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
405
406 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
407 write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR);
408
409 /* Skip restoring fpexc32 for AArch64 guests */
410 if (!(read_sysreg(hcr_el2) & HCR_RW))
411 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
412
413 *host_data_ptr(fp_owner) = FP_STATE_GUEST_OWNED;
414
415 return true;
416 }
417
handle_tx2_tvm(struct kvm_vcpu * vcpu)418 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
419 {
420 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
421 int rt = kvm_vcpu_sys_get_rt(vcpu);
422 u64 val = vcpu_get_reg(vcpu, rt);
423
424 /*
425 * The normal sysreg handling code expects to see the traps,
426 * let's not do anything here.
427 */
428 if (vcpu->arch.hcr_el2 & HCR_TVM)
429 return false;
430
431 switch (sysreg) {
432 case SYS_SCTLR_EL1:
433 write_sysreg_el1(val, SYS_SCTLR);
434 break;
435 case SYS_TTBR0_EL1:
436 write_sysreg_el1(val, SYS_TTBR0);
437 break;
438 case SYS_TTBR1_EL1:
439 write_sysreg_el1(val, SYS_TTBR1);
440 break;
441 case SYS_TCR_EL1:
442 write_sysreg_el1(val, SYS_TCR);
443 break;
444 case SYS_ESR_EL1:
445 write_sysreg_el1(val, SYS_ESR);
446 break;
447 case SYS_FAR_EL1:
448 write_sysreg_el1(val, SYS_FAR);
449 break;
450 case SYS_AFSR0_EL1:
451 write_sysreg_el1(val, SYS_AFSR0);
452 break;
453 case SYS_AFSR1_EL1:
454 write_sysreg_el1(val, SYS_AFSR1);
455 break;
456 case SYS_MAIR_EL1:
457 write_sysreg_el1(val, SYS_MAIR);
458 break;
459 case SYS_AMAIR_EL1:
460 write_sysreg_el1(val, SYS_AMAIR);
461 break;
462 case SYS_CONTEXTIDR_EL1:
463 write_sysreg_el1(val, SYS_CONTEXTIDR);
464 break;
465 default:
466 return false;
467 }
468
469 __kvm_skip_instr(vcpu);
470 return true;
471 }
472
kvm_hyp_handle_cntpct(struct kvm_vcpu * vcpu)473 static bool kvm_hyp_handle_cntpct(struct kvm_vcpu *vcpu)
474 {
475 struct arch_timer_context *ctxt;
476 u32 sysreg;
477 u64 val;
478
479 /*
480 * We only get here for 64bit guests, 32bit guests will hit
481 * the long and winding road all the way to the standard
482 * handling. Yes, it sucks to be irrelevant.
483 */
484 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
485
486 switch (sysreg) {
487 case SYS_CNTPCT_EL0:
488 case SYS_CNTPCTSS_EL0:
489 if (vcpu_has_nv(vcpu)) {
490 if (is_hyp_ctxt(vcpu)) {
491 ctxt = vcpu_hptimer(vcpu);
492 break;
493 }
494
495 /* Check for guest hypervisor trapping */
496 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
497 if (!vcpu_el2_e2h_is_set(vcpu))
498 val = (val & CNTHCTL_EL1PCTEN) << 10;
499
500 if (!(val & (CNTHCTL_EL1PCTEN << 10)))
501 return false;
502 }
503
504 ctxt = vcpu_ptimer(vcpu);
505 break;
506 default:
507 return false;
508 }
509
510 val = arch_timer_read_cntpct_el0();
511
512 if (ctxt->offset.vm_offset)
513 val -= *kern_hyp_va(ctxt->offset.vm_offset);
514 if (ctxt->offset.vcpu_offset)
515 val -= *kern_hyp_va(ctxt->offset.vcpu_offset);
516
517 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
518 __kvm_skip_instr(vcpu);
519 return true;
520 }
521
handle_ampere1_tcr(struct kvm_vcpu * vcpu)522 static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
523 {
524 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
525 int rt = kvm_vcpu_sys_get_rt(vcpu);
526 u64 val = vcpu_get_reg(vcpu, rt);
527
528 if (sysreg != SYS_TCR_EL1)
529 return false;
530
531 /*
532 * Affected parts do not advertise support for hardware Access Flag /
533 * Dirty state management in ID_AA64MMFR1_EL1.HAFDBS, but the underlying
534 * control bits are still functional. The architecture requires these be
535 * RES0 on systems that do not implement FEAT_HAFDBS.
536 *
537 * Uphold the requirements of the architecture by masking guest writes
538 * to TCR_EL1.{HA,HD} here.
539 */
540 val &= ~(TCR_HD | TCR_HA);
541 write_sysreg_el1(val, SYS_TCR);
542 __kvm_skip_instr(vcpu);
543 return true;
544 }
545
kvm_hyp_handle_sysreg(struct kvm_vcpu * vcpu,u64 * exit_code)546 static bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
547 {
548 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
549 handle_tx2_tvm(vcpu))
550 return true;
551
552 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) &&
553 handle_ampere1_tcr(vcpu))
554 return true;
555
556 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
557 __vgic_v3_perform_cpuif_access(vcpu) == 1)
558 return true;
559
560 if (kvm_hyp_handle_cntpct(vcpu))
561 return true;
562
563 return false;
564 }
565
kvm_hyp_handle_cp15_32(struct kvm_vcpu * vcpu,u64 * exit_code)566 static bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
567 {
568 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
569 __vgic_v3_perform_cpuif_access(vcpu) == 1)
570 return true;
571
572 return false;
573 }
574
kvm_hyp_handle_memory_fault(struct kvm_vcpu * vcpu,u64 * exit_code)575 static bool kvm_hyp_handle_memory_fault(struct kvm_vcpu *vcpu, u64 *exit_code)
576 {
577 if (!__populate_fault_info(vcpu))
578 return true;
579
580 return false;
581 }
582 static bool kvm_hyp_handle_iabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
583 __alias(kvm_hyp_handle_memory_fault);
584 static bool kvm_hyp_handle_watchpt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
585 __alias(kvm_hyp_handle_memory_fault);
586
kvm_hyp_handle_dabt_low(struct kvm_vcpu * vcpu,u64 * exit_code)587 static bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
588 {
589 if (kvm_hyp_handle_memory_fault(vcpu, exit_code))
590 return true;
591
592 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
593 bool valid;
594
595 valid = kvm_vcpu_trap_is_translation_fault(vcpu) &&
596 kvm_vcpu_dabt_isvalid(vcpu) &&
597 !kvm_vcpu_abt_issea(vcpu) &&
598 !kvm_vcpu_abt_iss1tw(vcpu);
599
600 if (valid) {
601 int ret = __vgic_v2_perform_cpuif_access(vcpu);
602
603 if (ret == 1)
604 return true;
605
606 /* Promote an illegal access to an SError.*/
607 if (ret == -1)
608 *exit_code = ARM_EXCEPTION_EL1_SERROR;
609 }
610 }
611
612 return false;
613 }
614
615 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
616
617 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu);
618
619 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code);
620
621 /*
622 * Allow the hypervisor to handle the exit with an exit handler if it has one.
623 *
624 * Returns true if the hypervisor handled the exit, and control should go back
625 * to the guest, or false if it hasn't.
626 */
kvm_hyp_handle_exit(struct kvm_vcpu * vcpu,u64 * exit_code)627 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
628 {
629 const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu);
630 exit_handler_fn fn;
631
632 fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
633
634 if (fn)
635 return fn(vcpu, exit_code);
636
637 return false;
638 }
639
synchronize_vcpu_pstate(struct kvm_vcpu * vcpu,u64 * exit_code)640 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
641 {
642 /*
643 * Check for the conditions of Cortex-A510's #2077057. When these occur
644 * SPSR_EL2 can't be trusted, but isn't needed either as it is
645 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
646 * Are we single-stepping the guest, and took a PAC exception from the
647 * active-not-pending state?
648 */
649 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) &&
650 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
651 *vcpu_cpsr(vcpu) & DBG_SPSR_SS &&
652 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
653 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
654
655 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
656 }
657
658 /*
659 * Return true when we were able to fixup the guest exit and should return to
660 * the guest, false when we should restore the host state and return to the
661 * main run loop.
662 */
fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code)663 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
664 {
665 /*
666 * Save PSTATE early so that we can evaluate the vcpu mode
667 * early on.
668 */
669 synchronize_vcpu_pstate(vcpu, exit_code);
670
671 /*
672 * Check whether we want to repaint the state one way or
673 * another.
674 */
675 early_exit_filter(vcpu, exit_code);
676
677 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
678 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
679
680 if (ARM_SERROR_PENDING(*exit_code) &&
681 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
682 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
683
684 /*
685 * HVC already have an adjusted PC, which we need to
686 * correct in order to return to after having injected
687 * the SError.
688 *
689 * SMC, on the other hand, is *trapped*, meaning its
690 * preferred return address is the SMC itself.
691 */
692 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
693 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
694 }
695
696 /*
697 * We're using the raw exception code in order to only process
698 * the trap if no SError is pending. We will come back to the
699 * same PC once the SError has been injected, and replay the
700 * trapping instruction.
701 */
702 if (*exit_code != ARM_EXCEPTION_TRAP)
703 goto exit;
704
705 /* Check if there's an exit handler and allow it to handle the exit. */
706 if (kvm_hyp_handle_exit(vcpu, exit_code))
707 goto guest;
708 exit:
709 /* Return to the host kernel and handle the exit */
710 return false;
711
712 guest:
713 /* Re-enter the guest */
714 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
715 return true;
716 }
717
__kvm_unexpected_el2_exception(void)718 static inline void __kvm_unexpected_el2_exception(void)
719 {
720 extern char __guest_exit_restore_elr_and_panic[];
721 unsigned long addr, fixup;
722 struct kvm_exception_table_entry *entry, *end;
723 unsigned long elr_el2 = read_sysreg(elr_el2);
724
725 entry = &__start___kvm_ex_table;
726 end = &__stop___kvm_ex_table;
727
728 while (entry < end) {
729 addr = (unsigned long)&entry->insn + entry->insn;
730 fixup = (unsigned long)&entry->fixup + entry->fixup;
731
732 if (addr != elr_el2) {
733 entry++;
734 continue;
735 }
736
737 write_sysreg(fixup, elr_el2);
738 return;
739 }
740
741 /* Trigger a panic after restoring the hyp context. */
742 this_cpu_ptr(&kvm_hyp_ctxt)->sys_regs[ELR_EL2] = elr_el2;
743 write_sysreg(__guest_exit_restore_elr_and_panic, elr_el2);
744 }
745
746 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */
747