1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #pragma ident "%Z%%M% %I% %E% SMI"
27
28 /*
29 * This plugin supports debugging functionality unique to Intel processors based
30 * on the P6 core (Pentium Pro, Pentium II, and Pentium III). It does not
31 * support the Pentium M processor, which uses a P4-style branch trace stack.
32 * The Pentium M is supported by the P4 plugin.
33 */
34
35 #include <kmdb/kvm_cpu_impl.h>
36 #include <kmdb/kmdb_dpi.h>
37 #include <kmdb/kmdb_kdi.h>
38 #include <kmdb/kvm.h>
39 #include <mdb/mdb_err.h>
40 #include <mdb/mdb.h>
41
42 #include <sys/x86_archext.h>
43
44 typedef struct kmt_cpu_p6 {
45 uint64_t p6_debugctl;
46 } kmt_cpu_p6_t;
47
48 /*
49 * The debugctl value in this struct needs to outlive the destruction of the
50 * kmt_cpu_t. It needs to be around for the final exit from the debugger so
51 * we can do the final write of the debugctl MSR.
52 */
53 static kmt_cpu_p6_t kmt_cpu_p6;
54
55 static void
kmt_p6_branch(uint_t cpuid,const char * label,uint_t msr)56 kmt_p6_branch(uint_t cpuid, const char *label, uint_t msr)
57 {
58 char buf[BUFSIZ];
59 uintptr_t addr;
60
61 addr = (uintptr_t)kmdb_dpi_msr_get_by_cpu(cpuid, msr);
62
63 mdb_printf("%s: %p %A\n", label, addr, addr);
64
65 if (mdb_dis_ins2str(mdb.m_disasm, mdb.m_target,
66 MDB_TGT_AS_VIRT, buf, sizeof (buf), addr) != addr)
67 mdb_printf("%*s %s\n", strlen(label), "", buf);
68 }
69
70 /*ARGSUSED*/
71 static int
kmt_p6_branches(uintptr_t addr,uint_t flags,int argc,const mdb_arg_t * argv)72 kmt_p6_branches(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv)
73 {
74 intptr_t cpuid = DPI_MASTER_CPUID;
75
76 if (mdb_getopts(argc, argv,
77 'c', MDB_OPT_UINTPTR, &cpuid,
78 NULL) != argc)
79 return (DCMD_USAGE);
80
81 kmt_p6_branch(cpuid, "LastBranchToIP ", MSR_LBR_TO);
82 kmt_p6_branch(cpuid, "LastBranchFromIP ", MSR_LBR_FROM);
83 kmt_p6_branch(cpuid, "LastExceptionToIP ", MSR_LEX_TO);
84 kmt_p6_branch(cpuid, "LastExceptionFromIP", MSR_LEX_FROM);
85
86 return (0);
87 }
88
89 /*
90 * MSRs that we want to track. These will be read each time the debugger is
91 * entered.
92 */
93 static const kdi_msr_t kmt_p6_msr[] = {
94 { MSR_DEBUGCTL, KDI_MSR_CLEARENTRY },
95 { MSR_DEBUGCTL, KDI_MSR_WRITEDELAY, &kmt_cpu_p6.p6_debugctl },
96 { MSR_LBR_TO, KDI_MSR_READ },
97 { MSR_LBR_FROM, KDI_MSR_READ },
98 { MSR_LEX_TO, KDI_MSR_READ },
99 { MSR_LEX_FROM, KDI_MSR_READ },
100 { NULL }
101 };
102
103 /*ARGSUSED*/
104 static void
kmt_p6_destroy(kmt_cpu_t * cpu)105 kmt_p6_destroy(kmt_cpu_t *cpu)
106 {
107 /* Leave LBR on */
108
109 mdb_free(cpu, sizeof (kmt_cpu_t));
110 }
111
112 /*ARGSUSED*/
113 static const char *
kmt_p6_name(kmt_cpu_t * cpu)114 kmt_p6_name(kmt_cpu_t *cpu)
115 {
116 return ("Intel P6 family (Pentium Pro, Pentium II, Pentium III)");
117 }
118
119 /*ARGSUSED*/
120 static void
kmt_p6_btf_clear(mdb_tgt_t * t,int id,void * arg)121 kmt_p6_btf_clear(mdb_tgt_t *t, int id, void *arg)
122 {
123 kmt_cpu_p6_t *p6 = arg;
124 kreg_t efl;
125
126 p6->p6_debugctl &= ~DEBUGCTL_BTF;
127
128 (void) kmdb_dpi_get_register("eflags", &efl);
129 efl &= ~(1 << KREG_EFLAGS_TF_SHIFT);
130 (void) kmdb_dpi_set_register("eflags", efl);
131 }
132
133 /* Enable branch stepping, to be disabled on the next debugger entry */
134 static int
kmt_p6_step_branch(kmt_cpu_t * cpu,mdb_tgt_t * t)135 kmt_p6_step_branch(kmt_cpu_t *cpu, mdb_tgt_t *t)
136 {
137 kmt_cpu_p6_t *p6 = cpu->kmt_cpu_data;
138 kreg_t efl;
139
140 (void) kmdb_dpi_get_register("eflags", &efl);
141 (void) kmdb_dpi_set_register("eflags",
142 (efl | (1 << KREG_EFLAGS_TF_SHIFT)));
143
144 p6->p6_debugctl |= DEBUGCTL_BTF;
145
146 return (mdb_tgt_add_fault(t, KMT_TRAP_ALL,
147 MDB_TGT_SPEC_HIDDEN | MDB_TGT_SPEC_TEMPORARY,
148 kmt_p6_btf_clear, p6));
149 }
150
151 static kmt_cpu_ops_t kmt_p6_ops = {
152 kmt_p6_destroy,
153 kmt_p6_name,
154 kmt_p6_step_branch
155 };
156
157 static const mdb_dcmd_t kmt_p6_dcmds[] = {
158 { "branches", NULL, "describe the recently-taken branches",
159 kmt_p6_branches },
160 { NULL }
161 };
162
163 /* See 07/04 AP-485 Intel Processor Identification and the CPUID Instruction */
164 #define KMT_CPU_FAMILY_P6 0x6
165 #define KMT_CPU_MODEL_PM_9 0x9 /* Pentium M, model 9 */
166 #define KMT_CPU_MODEL_PM_D 0xd /* Pentium M, model d */
167
168 kmt_cpu_t *
kmt_cpu_p6_create(mdb_tgt_t * t)169 kmt_cpu_p6_create(mdb_tgt_t *t)
170 {
171 uint_t vendor, family, model;
172 kmt_cpu_t *cpu;
173
174 if (kmdb_kdi_get_cpuinfo(&vendor, &family, &model) < 0)
175 return (NULL); /* errno is set for us */
176
177 if (vendor != X86_VENDOR_Intel || family != KMT_CPU_FAMILY_P6 ||
178 model == KMT_CPU_MODEL_PM_9 || model == KMT_CPU_MODEL_PM_D) {
179 (void) set_errno(ENOTSUP);
180 return (NULL);
181 }
182
183 cpu = mdb_zalloc(sizeof (kmt_cpu_t), UM_SLEEP);
184 cpu->kmt_cpu_ops = &kmt_p6_ops;
185 cpu->kmt_cpu_data = &kmt_cpu_p6;
186
187 kmdb_dpi_msr_add(kmt_p6_msr);
188
189 kmt_cpu_p6.p6_debugctl = DEBUGCTL_LBR; /* enable LBR on resume */
190
191 (void) mdb_tgt_register_dcmds(t, kmt_p6_dcmds, MDB_MOD_FORCE);
192
193 return (cpu);
194 }
195