1/* 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2007-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * MMU code derived from arch/ppc/kernel/head_4xx.S: 7 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 8 * Initial PowerPC version. 9 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 10 * Rewritten for PReP 11 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 12 * Low-level exception handers, MMU support, and rewrite. 13 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 14 * PowerPC 8xx modifications. 15 * Copyright (c) 1998-1999 TiVo, Inc. 16 * PowerPC 403GCX modifications. 17 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 18 * PowerPC 403GCX/405GP modifications. 19 * Copyright 2000 MontaVista Software Inc. 20 * PPC405 modifications 21 * PowerPC 403GCX/405GP modifications. 22 * Author: MontaVista Software, Inc. 23 * frank_rowand@mvista.com or source@mvista.com 24 * debbie_chu@mvista.com 25 * 26 * This file is subject to the terms and conditions of the GNU General Public 27 * License. See the file "COPYING" in the main directory of this archive 28 * for more details. 29 */ 30 31#include <linux/init.h> 32#include <linux/linkage.h> 33#include <asm/thread_info.h> 34#include <asm/page.h> 35#include <linux/of_fdt.h> /* for OF_DT_HEADER */ 36 37#include <asm/setup.h> /* COMMAND_LINE_SIZE */ 38#include <asm/mmu.h> 39#include <asm/processor.h> 40 41.section .data 42.global swapper_pg_dir 43swapper_pg_dir: 44 .space PAGE_SIZE 45 46.section .rodata 47.align 4 48endian_check: 49 .word 1 50 51 __HEAD 52ENTRY(_start) 53#if CONFIG_KERNEL_BASE_ADDR == 0 54 brai TOPHYS(real_start) 55 .org 0x100 56real_start: 57#endif 58 59 mts rmsr, r0 60/* Disable stack protection from bootloader */ 61 mts rslr, r0 62 addi r8, r0, 0xFFFFFFFF 63 mts rshr, r8 64/* 65 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' 66 * if the msrclr instruction is not enabled. We use this to detect 67 * if the opcode is available, by issuing msrclr and then testing the result. 68 * r8 == 0 - msr instructions are implemented 69 * r8 != 0 - msr instructions are not implemented 70 */ 71 mfs r1, rmsr 72 msrclr r8, 0 /* clear nothing - just read msr for test */ 73 cmpu r8, r8, r1 /* r1 must contain msr reg content */ 74 75/* r7 may point to an FDT, or there may be one linked in. 76 if it's in r7, we've got to save it away ASAP. 77 We ensure r7 points to a valid FDT, just in case the bootloader 78 is broken or non-existent */ 79 beqi r7, no_fdt_arg /* NULL pointer? don't copy */ 80/* Does r7 point to a valid FDT? Load HEADER magic number */ 81 /* Run time Big/Little endian platform */ 82 /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */ 83 lbui r11, r0, TOPHYS(endian_check) 84 beqid r11, big_endian /* DO NOT break delay stop dependency */ 85 lw r11, r0, r7 /* Big endian load in delay slot */ 86 lwr r11, r0, r7 /* Little endian load */ 87big_endian: 88 rsubi r11, r11, OF_DT_HEADER /* Check FDT header */ 89 beqi r11, _prepare_copy_fdt 90 or r7, r0, r0 /* clear R7 when not valid DTB */ 91 bnei r11, no_fdt_arg /* No - get out of here */ 92_prepare_copy_fdt: 93 or r11, r0, r0 /* incremment */ 94 ori r4, r0, TOPHYS(_fdt_start) 95 ori r3, r0, (0x10000 - 4) 96_copy_fdt: 97 lw r12, r7, r11 /* r12 = r7 + r11 */ 98 sw r12, r4, r11 /* addr[r4 + r11] = r12 */ 99 addik r11, r11, 4 /* increment counting */ 100 bgtid r3, _copy_fdt /* loop for all entries */ 101 addik r3, r3, -4 /* descrement loop */ 102no_fdt_arg: 103 104#ifndef CONFIG_CMDLINE_BOOL 105/* 106 * handling command line 107 * copy command line directly to cmd_line placed in data section. 108 */ 109 beqid r5, skip /* Skip if NULL pointer */ 110 or r11, r0, r0 /* incremment */ 111 ori r4, r0, cmd_line /* load address of command line */ 112 tophys(r4,r4) /* convert to phys address */ 113 ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ 114_copy_command_line: 115 /* r2=r5+r11 - r5 contain pointer to command line */ 116 lbu r2, r5, r11 117 beqid r2, skip /* Skip if no data */ 118 sb r2, r4, r11 /* addr[r4+r11]= r2 */ 119 addik r11, r11, 1 /* increment counting */ 120 bgtid r3, _copy_command_line /* loop for all entries */ 121 addik r3, r3, -1 /* decrement loop */ 122 addik r5, r4, 0 /* add new space for command line */ 123 tovirt(r5,r5) 124skip: 125#endif /* CONFIG_CMDLINE_BOOL */ 126 127#ifdef NOT_COMPILE 128/* save bram context */ 129 or r11, r0, r0 /* incremment */ 130 ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */ 131 ori r3, r0, (LMB_SIZE - 4) 132_copy_bram: 133 lw r7, r0, r11 /* r7 = r0 + r11 */ 134 sw r7, r4, r11 /* addr[r4 + r11] = r7 */ 135 addik r11, r11, 4 /* increment counting */ 136 bgtid r3, _copy_bram /* loop for all entries */ 137 addik r3, r3, -4 /* descrement loop */ 138#endif 139 /* We have to turn on the MMU right away. */ 140 141 /* 142 * Set up the initial MMU state so we can do the first level of 143 * kernel initialization. This maps the first 16 MBytes of memory 1:1 144 * virtual to physical. 145 */ 146 nop 147 addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */ 148_invalidate: 149 mts rtlbx, r3 150 mts rtlbhi, r0 /* flush: ensure V is clear */ 151 mts rtlblo, r0 152 bgtid r3, _invalidate /* loop for all entries */ 153 addik r3, r3, -1 154 /* sync */ 155 156 /* Setup the kernel PID */ 157 mts rpid,r0 /* Load the kernel PID */ 158 nop 159 bri 4 160 161 /* 162 * We should still be executing code at physical address area 163 * RAM_BASEADDR at this point. However, kernel code is at 164 * a virtual address. So, set up a TLB mapping to cover this once 165 * translation is enabled. 166 */ 167 168 addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ 169 tophys(r4,r3) /* Load the kernel physical address */ 170 171 /* start to do TLB calculation */ 172 addik r12, r0, _end 173 rsub r12, r3, r12 174 addik r12, r12, CONFIG_LOWMEM_SIZE >> PTE_SHIFT /* that's the pad */ 175 176 or r9, r0, r0 /* TLB0 = 0 */ 177 or r10, r0, r0 /* TLB1 = 0 */ 178 179 addik r11, r12, -0x1000000 180 bgei r11, GT16 /* size is greater than 16MB */ 181 addik r11, r12, -0x0800000 182 bgei r11, GT8 /* size is greater than 8MB */ 183 addik r11, r12, -0x0400000 184 bgei r11, GT4 /* size is greater than 4MB */ 185 /* size is less than 4MB */ 186 addik r11, r12, -0x0200000 187 bgei r11, GT2 /* size is greater than 2MB */ 188 addik r9, r0, 0x0100000 /* TLB0 must be 1MB */ 189 addik r11, r12, -0x0100000 190 bgei r11, GT1 /* size is greater than 1MB */ 191 /* TLB1 is 0 which is setup above */ 192 bri tlb_end 193GT4: /* r11 contains the rest - will be either 1 or 4 */ 194 ori r9, r0, 0x400000 /* TLB0 is 4MB */ 195 bri TLB1 196GT16: /* TLB0 is 16MB */ 197 addik r9, r0, 0x1000000 /* means TLB0 is 16MB */ 198TLB1: 199 /* must be used r2 because of subtract if failed */ 200 addik r2, r11, -0x0400000 201 bgei r2, GT20 /* size is greater than 16MB */ 202 /* size is >16MB and <20MB */ 203 addik r11, r11, -0x0100000 204 bgei r11, GT17 /* size is greater than 17MB */ 205 /* kernel is >16MB and < 17MB */ 206GT1: 207 addik r10, r0, 0x0100000 /* means TLB1 is 1MB */ 208 bri tlb_end 209GT2: /* TLB0 is 0 and TLB1 will be 4MB */ 210GT17: /* TLB1 is 4MB - kernel size <20MB */ 211 addik r10, r0, 0x0400000 /* means TLB1 is 4MB */ 212 bri tlb_end 213GT8: /* TLB0 is still zero that's why I can use only TLB1 */ 214GT20: /* TLB1 is 16MB - kernel size >20MB */ 215 addik r10, r0, 0x1000000 /* means TLB1 is 16MB */ 216tlb_end: 217 218 /* 219 * Configure and load two entries into TLB slots 0 and 1. 220 * In case we are pinning TLBs, these are reserved in by the 221 * other TLB functions. If not reserving, then it doesn't 222 * matter where they are loaded. 223 */ 224 andi r4,r4,0xfffffc00 /* Mask off the real page number */ 225 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 226 227 /* 228 * TLB0 is always used - check if is not zero (r9 stores TLB0 value) 229 * if is use TLB1 value and clear it (r10 stores TLB1 value) 230 */ 231 bnei r9, tlb0_not_zero 232 add r9, r10, r0 233 add r10, r0, r0 234tlb0_not_zero: 235 236 /* look at the code below */ 237 ori r30, r0, 0x200 238 andi r29, r9, 0x100000 239 bneid r29, 1f 240 addik r30, r30, 0x80 241 andi r29, r9, 0x400000 242 bneid r29, 1f 243 addik r30, r30, 0x80 244 andi r29, r9, 0x1000000 245 bneid r29, 1f 246 addik r30, r30, 0x80 2471: 248 andi r3,r3,0xfffffc00 /* Mask off the effective page number */ 249 ori r3,r3,(TLB_VALID) 250 or r3, r3, r30 251 252 /* Load tlb_skip size value which is index to first unused TLB entry */ 253 lwi r11, r0, TOPHYS(tlb_skip) 254 mts rtlbx,r11 /* TLB slow 0 */ 255 256 mts rtlblo,r4 /* Load the data portion of the entry */ 257 mts rtlbhi,r3 /* Load the tag portion of the entry */ 258 259 /* Increase tlb_skip size */ 260 addik r11, r11, 1 261 swi r11, r0, TOPHYS(tlb_skip) 262 263 /* TLB1 can be zeroes that's why we not setup it */ 264 beqi r10, jump_over2 265 266 /* look at the code below */ 267 ori r30, r0, 0x200 268 andi r29, r10, 0x100000 269 bneid r29, 1f 270 addik r30, r30, 0x80 271 andi r29, r10, 0x400000 272 bneid r29, 1f 273 addik r30, r30, 0x80 274 andi r29, r10, 0x1000000 275 bneid r29, 1f 276 addik r30, r30, 0x80 2771: 278 addk r4, r4, r9 /* previous addr + TLB0 size */ 279 addk r3, r3, r9 280 281 andi r3,r3,0xfffffc00 /* Mask off the effective page number */ 282 ori r3,r3,(TLB_VALID) 283 or r3, r3, r30 284 285 lwi r11, r0, TOPHYS(tlb_skip) 286 mts rtlbx, r11 /* r11 is used from TLB0 */ 287 288 mts rtlblo,r4 /* Load the data portion of the entry */ 289 mts rtlbhi,r3 /* Load the tag portion of the entry */ 290 291 /* Increase tlb_skip size */ 292 addik r11, r11, 1 293 swi r11, r0, TOPHYS(tlb_skip) 294 295jump_over2: 296 /* 297 * Load a TLB entry for LMB, since we need access to 298 * the exception vectors, using a 4k real==virtual mapping. 299 */ 300 /* Use temporary TLB_ID for LMB - clear this temporary mapping later */ 301 ori r11, r0, MICROBLAZE_LMB_TLB_ID 302 mts rtlbx,r11 303 304 ori r4,r0,(TLB_WR | TLB_EX) 305 ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) 306 307 mts rtlblo,r4 /* Load the data portion of the entry */ 308 mts rtlbhi,r3 /* Load the tag portion of the entry */ 309 310 /* 311 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the 312 * caches ready to work. 313 */ 314turn_on_mmu: 315 ori r15,r0,start_here 316 ori r4,r0,MSR_KERNEL_VMS 317 mts rmsr,r4 318 nop 319 rted r15,0 /* enables MMU */ 320 nop 321 322start_here: 323 324 /* Initialize small data anchors */ 325 addik r13, r0, _KERNEL_SDA_BASE_ 326 addik r2, r0, _KERNEL_SDA2_BASE_ 327 328 /* Initialize stack pointer */ 329 addik r1, r0, init_thread_union + THREAD_SIZE - 4 330 331 /* Initialize r31 with current task address */ 332 addik r31, r0, init_task 333 334 addik r11, r0, machine_early_init 335 brald r15, r11 336 nop 337 338 /* 339 * Initialize the MMU. 340 */ 341 bralid r15, mmu_init 342 nop 343 344 /* Go back to running unmapped so we can load up new values 345 * and change to using our exception vectors. 346 * On the MicroBlaze, all we invalidate the used TLB entries to clear 347 * the old 16M byte TLB mappings. 348 */ 349 ori r15,r0,TOPHYS(kernel_load_context) 350 ori r4,r0,MSR_KERNEL 351 mts rmsr,r4 352 nop 353 bri 4 354 rted r15,0 355 nop 356 357 /* Load up the kernel context */ 358kernel_load_context: 359 ori r5, r0, MICROBLAZE_LMB_TLB_ID 360 mts rtlbx,r5 361 nop 362 mts rtlbhi,r0 363 nop 364 addi r15, r0, machine_halt 365 ori r17, r0, start_kernel 366 ori r4, r0, MSR_KERNEL_VMS 367 mts rmsr, r4 368 nop 369 rted r17, 0 /* enable MMU and jump to start_kernel */ 370 nop 371