1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/endian.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/mbuf.h>
37 #include <sys/rman.h>
38 #include <sys/module.h>
39 #include <sys/proc.h>
40 #include <sys/queue.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <sys/sysctl.h>
44 #include <sys/taskqueue.h>
45
46 #include <net/bpf.h>
47 #include <net/if.h>
48 #include <net/if_var.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_vlan_var.h>
55
56 #include <netinet/in.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/ip.h>
59 #include <netinet/tcp.h>
60
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
63
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66
67 #include <machine/bus.h>
68 #include <machine/in_cksum.h>
69
70 #include <dev/jme/if_jmereg.h>
71 #include <dev/jme/if_jmevar.h>
72
73 /* "device miibus" required. See GENERIC if you get errors here. */
74 #include "miibus_if.h"
75
76 /* Define the following to disable printing Rx errors. */
77 #undef JME_SHOW_ERRORS
78
79 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
80
81 MODULE_DEPEND(jme, pci, 1, 1, 1);
82 MODULE_DEPEND(jme, ether, 1, 1, 1);
83 MODULE_DEPEND(jme, miibus, 1, 1, 1);
84
85 /* Tunables. */
86 static int msi_disable = 0;
87 static int msix_disable = 0;
88 TUNABLE_INT("hw.jme.msi_disable", &msi_disable);
89 TUNABLE_INT("hw.jme.msix_disable", &msix_disable);
90
91 /*
92 * Devices supported by this driver.
93 */
94 static struct jme_dev {
95 uint16_t jme_vendorid;
96 uint16_t jme_deviceid;
97 const char *jme_name;
98 } jme_devs[] = {
99 { VENDORID_JMICRON, DEVICEID_JMC250,
100 "JMicron Inc, JMC25x Gigabit Ethernet" },
101 { VENDORID_JMICRON, DEVICEID_JMC260,
102 "JMicron Inc, JMC26x Fast Ethernet" },
103 };
104
105 static int jme_miibus_readreg(device_t, int, int);
106 static int jme_miibus_writereg(device_t, int, int, int);
107 static void jme_miibus_statchg(device_t);
108 static void jme_mediastatus(if_t, struct ifmediareq *);
109 static int jme_mediachange(if_t);
110 static int jme_probe(device_t);
111 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
112 static int jme_eeprom_macaddr(struct jme_softc *);
113 static int jme_efuse_macaddr(struct jme_softc *);
114 static void jme_reg_macaddr(struct jme_softc *);
115 static void jme_set_macaddr(struct jme_softc *, uint8_t *);
116 static void jme_map_intr_vector(struct jme_softc *);
117 static int jme_attach(device_t);
118 static int jme_detach(device_t);
119 static void jme_sysctl_node(struct jme_softc *);
120 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int);
121 static int jme_dma_alloc(struct jme_softc *);
122 static void jme_dma_free(struct jme_softc *);
123 static int jme_shutdown(device_t);
124 static void jme_setlinkspeed(struct jme_softc *);
125 static void jme_setwol(struct jme_softc *);
126 static int jme_suspend(device_t);
127 static int jme_resume(device_t);
128 static int jme_encap(struct jme_softc *, struct mbuf **);
129 static void jme_start(if_t);
130 static void jme_start_locked(if_t);
131 static void jme_watchdog(struct jme_softc *);
132 static int jme_ioctl(if_t, u_long, caddr_t);
133 static void jme_mac_config(struct jme_softc *);
134 static void jme_link_task(void *, int);
135 static int jme_intr(void *);
136 static void jme_int_task(void *, int);
137 static void jme_txeof(struct jme_softc *);
138 static __inline void jme_discard_rxbuf(struct jme_softc *, int);
139 static void jme_rxeof(struct jme_softc *);
140 static int jme_rxintr(struct jme_softc *, int);
141 static void jme_tick(void *);
142 static void jme_reset(struct jme_softc *);
143 static void jme_init(void *);
144 static void jme_init_locked(struct jme_softc *);
145 static void jme_stop(struct jme_softc *);
146 static void jme_stop_tx(struct jme_softc *);
147 static void jme_stop_rx(struct jme_softc *);
148 static int jme_init_rx_ring(struct jme_softc *);
149 static void jme_init_tx_ring(struct jme_softc *);
150 static void jme_init_ssb(struct jme_softc *);
151 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
152 static void jme_set_vlan(struct jme_softc *);
153 static void jme_set_filter(struct jme_softc *);
154 static void jme_stats_clear(struct jme_softc *);
155 static void jme_stats_save(struct jme_softc *);
156 static void jme_stats_update(struct jme_softc *);
157 static void jme_phy_down(struct jme_softc *);
158 static void jme_phy_up(struct jme_softc *);
159 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
160 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
161 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
162 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
163 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
164 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS);
165
166
167 static device_method_t jme_methods[] = {
168 /* Device interface. */
169 DEVMETHOD(device_probe, jme_probe),
170 DEVMETHOD(device_attach, jme_attach),
171 DEVMETHOD(device_detach, jme_detach),
172 DEVMETHOD(device_shutdown, jme_shutdown),
173 DEVMETHOD(device_suspend, jme_suspend),
174 DEVMETHOD(device_resume, jme_resume),
175
176 /* MII interface. */
177 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
178 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
179 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
180
181 { NULL, NULL }
182 };
183
184 static driver_t jme_driver = {
185 "jme",
186 jme_methods,
187 sizeof(struct jme_softc)
188 };
189
190 DRIVER_MODULE(jme, pci, jme_driver, 0, 0);
191 DRIVER_MODULE(miibus, jme, miibus_driver, 0, 0);
192
193 static struct resource_spec jme_res_spec_mem[] = {
194 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
195 { -1, 0, 0 }
196 };
197
198 static struct resource_spec jme_irq_spec_legacy[] = {
199 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
200 { -1, 0, 0 }
201 };
202
203 static struct resource_spec jme_irq_spec_msi[] = {
204 { SYS_RES_IRQ, 1, RF_ACTIVE },
205 { -1, 0, 0 }
206 };
207
208 /*
209 * Read a PHY register on the MII of the JMC250.
210 */
211 static int
jme_miibus_readreg(device_t dev,int phy,int reg)212 jme_miibus_readreg(device_t dev, int phy, int reg)
213 {
214 struct jme_softc *sc;
215 uint32_t val;
216 int i;
217
218 sc = device_get_softc(dev);
219
220 /* For FPGA version, PHY address 0 should be ignored. */
221 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
222 return (0);
223
224 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
225 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
226 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
227 DELAY(1);
228 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg);
234 return (0);
235 }
236
237 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
238 }
239
240 /*
241 * Write a PHY register on the MII of the JMC250.
242 */
243 static int
jme_miibus_writereg(device_t dev,int phy,int reg,int val)244 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
245 {
246 struct jme_softc *sc;
247 int i;
248
249 sc = device_get_softc(dev);
250
251 /* For FPGA version, PHY address 0 should be ignored. */
252 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
253 return (0);
254
255 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
256 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
257 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
258 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
259 DELAY(1);
260 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
261 break;
262 }
263
264 if (i == 0)
265 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg);
266
267 return (0);
268 }
269
270 /*
271 * Callback from MII layer when media changes.
272 */
273 static void
jme_miibus_statchg(device_t dev)274 jme_miibus_statchg(device_t dev)
275 {
276 struct jme_softc *sc;
277
278 sc = device_get_softc(dev);
279 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task);
280 }
281
282 /*
283 * Get the current interface media status.
284 */
285 static void
jme_mediastatus(if_t ifp,struct ifmediareq * ifmr)286 jme_mediastatus(if_t ifp, struct ifmediareq *ifmr)
287 {
288 struct jme_softc *sc;
289 struct mii_data *mii;
290
291 sc = if_getsoftc(ifp);
292 JME_LOCK(sc);
293 if ((if_getflags(ifp) & IFF_UP) == 0) {
294 JME_UNLOCK(sc);
295 return;
296 }
297 mii = device_get_softc(sc->jme_miibus);
298
299 mii_pollstat(mii);
300 ifmr->ifm_status = mii->mii_media_status;
301 ifmr->ifm_active = mii->mii_media_active;
302 JME_UNLOCK(sc);
303 }
304
305 /*
306 * Set hardware to newly-selected media.
307 */
308 static int
jme_mediachange(if_t ifp)309 jme_mediachange(if_t ifp)
310 {
311 struct jme_softc *sc;
312 struct mii_data *mii;
313 struct mii_softc *miisc;
314 int error;
315
316 sc = if_getsoftc(ifp);
317 JME_LOCK(sc);
318 mii = device_get_softc(sc->jme_miibus);
319 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
320 PHY_RESET(miisc);
321 error = mii_mediachg(mii);
322 JME_UNLOCK(sc);
323
324 return (error);
325 }
326
327 static int
jme_probe(device_t dev)328 jme_probe(device_t dev)
329 {
330 struct jme_dev *sp;
331 int i;
332 uint16_t vendor, devid;
333
334 vendor = pci_get_vendor(dev);
335 devid = pci_get_device(dev);
336 sp = jme_devs;
337 for (i = 0; i < nitems(jme_devs); i++, sp++) {
338 if (vendor == sp->jme_vendorid &&
339 devid == sp->jme_deviceid) {
340 device_set_desc(dev, sp->jme_name);
341 return (BUS_PROBE_DEFAULT);
342 }
343 }
344
345 return (ENXIO);
346 }
347
348 static int
jme_eeprom_read_byte(struct jme_softc * sc,uint8_t addr,uint8_t * val)349 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
350 {
351 uint32_t reg;
352 int i;
353
354 *val = 0;
355 for (i = JME_TIMEOUT; i > 0; i--) {
356 reg = CSR_READ_4(sc, JME_SMBCSR);
357 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
358 break;
359 DELAY(1);
360 }
361
362 if (i == 0) {
363 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
364 return (ETIMEDOUT);
365 }
366
367 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
368 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
369 for (i = JME_TIMEOUT; i > 0; i--) {
370 DELAY(1);
371 reg = CSR_READ_4(sc, JME_SMBINTF);
372 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
373 break;
374 }
375
376 if (i == 0) {
377 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
378 return (ETIMEDOUT);
379 }
380
381 reg = CSR_READ_4(sc, JME_SMBINTF);
382 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
383
384 return (0);
385 }
386
387 static int
jme_eeprom_macaddr(struct jme_softc * sc)388 jme_eeprom_macaddr(struct jme_softc *sc)
389 {
390 uint8_t eaddr[ETHER_ADDR_LEN];
391 uint8_t fup, reg, val;
392 uint32_t offset;
393 int match;
394
395 offset = 0;
396 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
397 fup != JME_EEPROM_SIG0)
398 return (ENOENT);
399 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
400 fup != JME_EEPROM_SIG1)
401 return (ENOENT);
402 match = 0;
403 do {
404 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
405 break;
406 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
407 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
408 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
409 break;
410 if (reg >= JME_PAR0 &&
411 reg < JME_PAR0 + ETHER_ADDR_LEN) {
412 if (jme_eeprom_read_byte(sc, offset + 2,
413 &val) != 0)
414 break;
415 eaddr[reg - JME_PAR0] = val;
416 match++;
417 }
418 }
419 /* Check for the end of EEPROM descriptor. */
420 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
421 break;
422 /* Try next eeprom descriptor. */
423 offset += JME_EEPROM_DESC_BYTES;
424 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
425
426 if (match == ETHER_ADDR_LEN) {
427 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN);
428 return (0);
429 }
430
431 return (ENOENT);
432 }
433
434 static int
jme_efuse_macaddr(struct jme_softc * sc)435 jme_efuse_macaddr(struct jme_softc *sc)
436 {
437 uint32_t reg;
438 int i;
439
440 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
441 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) !=
442 EFUSE_CTL1_AUTOLAOD_DONE)
443 return (ENOENT);
444 /* Reset eFuse controller. */
445 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
446 reg |= EFUSE_CTL2_RESET;
447 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
448 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4);
449 reg &= ~EFUSE_CTL2_RESET;
450 pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4);
451
452 /* Have eFuse reload station address to MAC controller. */
453 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
454 reg &= ~EFUSE_CTL1_CMD_MASK;
455 reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE;
456 pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4);
457
458 /*
459 * Verify completion of eFuse autload command. It should be
460 * completed within 108us.
461 */
462 DELAY(110);
463 for (i = 10; i > 0; i--) {
464 reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4);
465 if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR |
466 EFUSE_CTL1_AUTOLAOD_DONE)) != EFUSE_CTL1_AUTOLAOD_DONE) {
467 DELAY(20);
468 continue;
469 }
470 if ((reg & EFUSE_CTL1_EXECUTE) == 0)
471 break;
472 /* Station address loading is still in progress. */
473 DELAY(20);
474 }
475 if (i == 0) {
476 device_printf(sc->jme_dev, "eFuse autoload timed out.\n");
477 return (ETIMEDOUT);
478 }
479
480 return (0);
481 }
482
483 static void
jme_reg_macaddr(struct jme_softc * sc)484 jme_reg_macaddr(struct jme_softc *sc)
485 {
486 uint32_t par0, par1;
487
488 /* Read station address. */
489 par0 = CSR_READ_4(sc, JME_PAR0);
490 par1 = CSR_READ_4(sc, JME_PAR1);
491 par1 &= 0xFFFF;
492 if ((par0 == 0 && par1 == 0) ||
493 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) {
494 device_printf(sc->jme_dev,
495 "Failed to retrieve Ethernet address.\n");
496 } else {
497 /*
498 * For controllers that use eFuse, the station address
499 * could also be extracted from JME_PCI_PAR0 and
500 * JME_PCI_PAR1 registers in PCI configuration space.
501 * Each register holds exactly half of station address(24bits)
502 * so use JME_PAR0, JME_PAR1 registers instead.
503 */
504 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
505 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
506 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
507 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF;
508 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF;
509 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF;
510 }
511 }
512
513 static void
jme_set_macaddr(struct jme_softc * sc,uint8_t * eaddr)514 jme_set_macaddr(struct jme_softc *sc, uint8_t *eaddr)
515 {
516 uint32_t val;
517 int i;
518
519 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) {
520 /*
521 * Avoid reprogramming station address if the address
522 * is the same as previous one. Note, reprogrammed
523 * station address is permanent as if it was written
524 * to EEPROM. So if station address was changed by
525 * admistrator it's possible to lose factory configured
526 * address when driver fails to restore its address.
527 * (e.g. reboot or system crash)
528 */
529 if (bcmp(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN) != 0) {
530 for (i = 0; i < ETHER_ADDR_LEN; i++) {
531 val = JME_EFUSE_EEPROM_FUNC0 <<
532 JME_EFUSE_EEPROM_FUNC_SHIFT;
533 val |= JME_EFUSE_EEPROM_PAGE_BAR1 <<
534 JME_EFUSE_EEPROM_PAGE_SHIFT;
535 val |= (JME_PAR0 + i) <<
536 JME_EFUSE_EEPROM_ADDR_SHIFT;
537 val |= eaddr[i] << JME_EFUSE_EEPROM_DATA_SHIFT;
538 pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM,
539 val | JME_EFUSE_EEPROM_WRITE, 4);
540 }
541 }
542 } else {
543 CSR_WRITE_4(sc, JME_PAR0,
544 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
545 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
546 }
547 }
548
549 static void
jme_map_intr_vector(struct jme_softc * sc)550 jme_map_intr_vector(struct jme_softc *sc)
551 {
552 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];
553
554 bzero(map, sizeof(map));
555
556 /* Map Tx interrupts source to MSI/MSIX vector 2. */
557 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =
558 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP);
559 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |=
560 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP);
561 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |=
562 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP);
563 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |=
564 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP);
565 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
566 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP);
567 map[MSINUM_REG_INDEX(N_INTR_TXQ5_COMP)] |=
568 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP);
569 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |=
570 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP);
571 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |=
572 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP);
573 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |=
574 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL);
575 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |=
576 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO);
577
578 /* Map Rx interrupts source to MSI/MSIX vector 1. */
579 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] =
580 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP);
581 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] =
582 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP);
583 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] =
584 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP);
585 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] =
586 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP);
587 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] =
588 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY);
589 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] =
590 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY);
591 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] =
592 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY);
593 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] =
594 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY);
595 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] =
596 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL);
597 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] =
598 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL);
599 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] =
600 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL);
601 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] =
602 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL);
603 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] =
604 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO);
605 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] =
606 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO);
607 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] =
608 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO);
609 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] =
610 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO);
611
612 /* Map all other interrupts source to MSI/MSIX vector 0. */
613 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]);
614 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]);
615 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]);
616 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]);
617 }
618
619 static int
jme_attach(device_t dev)620 jme_attach(device_t dev)
621 {
622 struct jme_softc *sc;
623 if_t ifp;
624 struct mii_softc *miisc;
625 struct mii_data *mii;
626 uint32_t reg;
627 uint16_t burst;
628 int error, i, mii_flags, msic, msixc, pmc;
629
630 error = 0;
631 sc = device_get_softc(dev);
632 sc->jme_dev = dev;
633
634 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
635 MTX_DEF);
636 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0);
637 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc);
638 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc);
639
640 /*
641 * Map the device. JMC250 supports both memory mapped and I/O
642 * register space access. Because I/O register access should
643 * use different BARs to access registers it's waste of time
644 * to use I/O register spce access. JMC250 uses 16K to map
645 * entire memory space.
646 */
647 pci_enable_busmaster(dev);
648 sc->jme_res_spec = jme_res_spec_mem;
649 sc->jme_irq_spec = jme_irq_spec_legacy;
650 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res);
651 if (error != 0) {
652 device_printf(dev, "cannot allocate memory resources.\n");
653 goto fail;
654 }
655
656 /* Allocate IRQ resources. */
657 msixc = pci_msix_count(dev);
658 msic = pci_msi_count(dev);
659 if (bootverbose) {
660 device_printf(dev, "MSIX count : %d\n", msixc);
661 device_printf(dev, "MSI count : %d\n", msic);
662 }
663
664 /* Use 1 MSI/MSI-X. */
665 if (msixc > 1)
666 msixc = 1;
667 if (msic > 1)
668 msic = 1;
669 /* Prefer MSIX over MSI. */
670 if (msix_disable == 0 || msi_disable == 0) {
671 if (msix_disable == 0 && msixc > 0 &&
672 pci_alloc_msix(dev, &msixc) == 0) {
673 if (msixc == 1) {
674 device_printf(dev, "Using %d MSIX messages.\n",
675 msixc);
676 sc->jme_flags |= JME_FLAG_MSIX;
677 sc->jme_irq_spec = jme_irq_spec_msi;
678 } else
679 pci_release_msi(dev);
680 }
681 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 &&
682 msic > 0 && pci_alloc_msi(dev, &msic) == 0) {
683 if (msic == 1) {
684 device_printf(dev, "Using %d MSI messages.\n",
685 msic);
686 sc->jme_flags |= JME_FLAG_MSI;
687 sc->jme_irq_spec = jme_irq_spec_msi;
688 } else
689 pci_release_msi(dev);
690 }
691 /* Map interrupt vector 0, 1 and 2. */
692 if ((sc->jme_flags & JME_FLAG_MSI) != 0 ||
693 (sc->jme_flags & JME_FLAG_MSIX) != 0)
694 jme_map_intr_vector(sc);
695 }
696
697 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq);
698 if (error != 0) {
699 device_printf(dev, "cannot allocate IRQ resources.\n");
700 goto fail;
701 }
702
703 sc->jme_rev = pci_get_device(dev);
704 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) {
705 sc->jme_flags |= JME_FLAG_FASTETH;
706 sc->jme_flags |= JME_FLAG_NOJUMBO;
707 }
708 reg = CSR_READ_4(sc, JME_CHIPMODE);
709 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;
710 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
711 CHIPMODE_NOT_FPGA)
712 sc->jme_flags |= JME_FLAG_FPGA;
713 if (bootverbose) {
714 device_printf(dev, "PCI device revision : 0x%04x\n",
715 sc->jme_rev);
716 device_printf(dev, "Chip revision : 0x%02x\n",
717 sc->jme_chip_rev);
718 if ((sc->jme_flags & JME_FLAG_FPGA) != 0)
719 device_printf(dev, "FPGA revision : 0x%04x\n",
720 (reg & CHIPMODE_FPGA_REV_MASK) >>
721 CHIPMODE_FPGA_REV_SHIFT);
722 }
723 if (sc->jme_chip_rev == 0xFF) {
724 device_printf(dev, "Unknown chip revision : 0x%02x\n",
725 sc->jme_rev);
726 error = ENXIO;
727 goto fail;
728 }
729
730 /* Identify controller features and bugs. */
731 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
732 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
733 CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
734 sc->jme_flags |= JME_FLAG_DMA32BIT;
735 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5)
736 sc->jme_flags |= JME_FLAG_EFUSE | JME_FLAG_PCCPCD;
737 sc->jme_flags |= JME_FLAG_TXCLK | JME_FLAG_RXCLK;
738 sc->jme_flags |= JME_FLAG_HWMIB;
739 }
740
741 /* Reset the ethernet controller. */
742 jme_reset(sc);
743
744 /* Get station address. */
745 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) {
746 error = jme_efuse_macaddr(sc);
747 if (error == 0)
748 jme_reg_macaddr(sc);
749 } else {
750 error = ENOENT;
751 reg = CSR_READ_4(sc, JME_SMBCSR);
752 if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
753 error = jme_eeprom_macaddr(sc);
754 if (error != 0 && bootverbose)
755 device_printf(sc->jme_dev,
756 "ethernet hardware address not found in EEPROM.\n");
757 if (error != 0)
758 jme_reg_macaddr(sc);
759 }
760
761 /*
762 * Save PHY address.
763 * Integrated JR0211 has fixed PHY address whereas FPGA version
764 * requires PHY probing to get correct PHY address.
765 */
766 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {
767 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
768 GPREG0_PHY_ADDR_MASK;
769 if (bootverbose)
770 device_printf(dev, "PHY is at address %d.\n",
771 sc->jme_phyaddr);
772 } else
773 sc->jme_phyaddr = 0;
774
775 /* Set max allowable DMA size. */
776 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
777 sc->jme_flags |= JME_FLAG_PCIE;
778 burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
779 if (bootverbose) {
780 device_printf(dev, "Read request size : %d bytes.\n",
781 128 << ((burst >> 12) & 0x07));
782 device_printf(dev, "TLP payload size : %d bytes.\n",
783 128 << ((burst >> 5) & 0x07));
784 }
785 switch ((burst >> 12) & 0x07) {
786 case 0:
787 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
788 break;
789 case 1:
790 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
791 break;
792 default:
793 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
794 break;
795 }
796 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
797 } else {
798 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
799 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
800 }
801 /* Create coalescing sysctl node. */
802 jme_sysctl_node(sc);
803 if ((error = jme_dma_alloc(sc)) != 0)
804 goto fail;
805
806 ifp = sc->jme_ifp = if_alloc(IFT_ETHER);
807 if_setsoftc(ifp, sc);
808 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
809 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
810 if_setioctlfn(ifp, jme_ioctl);
811 if_setstartfn(ifp, jme_start);
812 if_setinitfn(ifp, jme_init);
813 if_setsendqlen(ifp, JME_TX_RING_CNT - 1);
814 if_setsendqready(ifp);
815 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */
816 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4);
817 if_sethwassist(ifp, JME_CSUM_FEATURES | CSUM_TSO);
818 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
819 sc->jme_flags |= JME_FLAG_PMCAP;
820 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
821 }
822 if_setcapenable(ifp, if_getcapabilities(ifp));
823
824 /* Wakeup PHY. */
825 jme_phy_up(sc);
826 mii_flags = MIIF_DOPAUSE;
827 /* Ask PHY calibration to PHY driver. */
828 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5)
829 mii_flags |= MIIF_MACPRIV0;
830 /* Set up MII bus. */
831 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange,
832 jme_mediastatus, BMSR_DEFCAPMASK,
833 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr,
834 MII_OFFSET_ANY, mii_flags);
835 if (error != 0) {
836 device_printf(dev, "attaching PHYs failed\n");
837 goto fail;
838 }
839
840 /*
841 * Force PHY to FPGA mode.
842 */
843 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
844 mii = device_get_softc(sc->jme_miibus);
845 if (mii->mii_instance != 0) {
846 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
847 if (miisc->mii_phy != 0) {
848 sc->jme_phyaddr = miisc->mii_phy;
849 break;
850 }
851 }
852 if (sc->jme_phyaddr != 0) {
853 device_printf(sc->jme_dev,
854 "FPGA PHY is at %d\n", sc->jme_phyaddr);
855 /* vendor magic. */
856 jme_miibus_writereg(dev, sc->jme_phyaddr, 27,
857 0x0004);
858 }
859 }
860 }
861
862 ether_ifattach(ifp, sc->jme_eaddr);
863
864 /* VLAN capability setup */
865 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
866 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
867 if_setcapenable(ifp, if_getcapabilities(ifp));
868
869 /* Tell the upper layer(s) we support long frames. */
870 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
871
872 /* Create local taskq. */
873 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK,
874 taskqueue_thread_enqueue, &sc->jme_tq);
875 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq",
876 device_get_nameunit(sc->jme_dev));
877
878 for (i = 0; i < 1; i++) {
879 error = bus_setup_intr(dev, sc->jme_irq[i],
880 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc,
881 &sc->jme_intrhand[i]);
882 if (error != 0)
883 break;
884 }
885
886 if (error != 0) {
887 device_printf(dev, "could not set up interrupt handler.\n");
888 taskqueue_free(sc->jme_tq);
889 sc->jme_tq = NULL;
890 ether_ifdetach(ifp);
891 goto fail;
892 }
893
894 fail:
895 if (error != 0)
896 jme_detach(dev);
897
898 return (error);
899 }
900
901 static int
jme_detach(device_t dev)902 jme_detach(device_t dev)
903 {
904 struct jme_softc *sc;
905 if_t ifp;
906 int i;
907
908 sc = device_get_softc(dev);
909
910 ifp = sc->jme_ifp;
911 if (device_is_attached(dev)) {
912 JME_LOCK(sc);
913 sc->jme_flags |= JME_FLAG_DETACH;
914 jme_stop(sc);
915 JME_UNLOCK(sc);
916 callout_drain(&sc->jme_tick_ch);
917 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
918 taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
919 /* Restore possibly modified station address. */
920 if ((sc->jme_flags & JME_FLAG_EFUSE) != 0)
921 jme_set_macaddr(sc, sc->jme_eaddr);
922 ether_ifdetach(ifp);
923 }
924
925 if (sc->jme_tq != NULL) {
926 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
927 taskqueue_free(sc->jme_tq);
928 sc->jme_tq = NULL;
929 }
930
931 bus_generic_detach(dev);
932 jme_dma_free(sc);
933
934 if (ifp != NULL) {
935 if_free(ifp);
936 sc->jme_ifp = NULL;
937 }
938
939 for (i = 0; i < 1; i++) {
940 if (sc->jme_intrhand[i] != NULL) {
941 bus_teardown_intr(dev, sc->jme_irq[i],
942 sc->jme_intrhand[i]);
943 sc->jme_intrhand[i] = NULL;
944 }
945 }
946
947 if (sc->jme_irq[0] != NULL)
948 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq);
949 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0)
950 pci_release_msi(dev);
951 if (sc->jme_res[0] != NULL)
952 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res);
953 mtx_destroy(&sc->jme_mtx);
954
955 return (0);
956 }
957
958 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \
959 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
960
961 static void
jme_sysctl_node(struct jme_softc * sc)962 jme_sysctl_node(struct jme_softc *sc)
963 {
964 struct sysctl_ctx_list *ctx;
965 struct sysctl_oid_list *child, *parent;
966 struct sysctl_oid *tree;
967 struct jme_hw_stats *stats;
968 int error;
969
970 stats = &sc->jme_stats;
971 ctx = device_get_sysctl_ctx(sc->jme_dev);
972 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev));
973
974 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to",
975 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_tx_coal_to,
976 0, sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
977
978 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt",
979 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_tx_coal_pkt,
980 0, sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
981
982 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to",
983 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_rx_coal_to,
984 0, sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
985
986 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt",
987 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->jme_rx_coal_pkt,
988 0, sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
989
990 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
991 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
992 &sc->jme_process_limit, 0, sysctl_hw_jme_proc_limit, "I",
993 "max number of Rx events to process");
994
995 /* Pull in device tunables. */
996 sc->jme_process_limit = JME_PROC_DEFAULT;
997 error = resource_int_value(device_get_name(sc->jme_dev),
998 device_get_unit(sc->jme_dev), "process_limit",
999 &sc->jme_process_limit);
1000 if (error == 0) {
1001 if (sc->jme_process_limit < JME_PROC_MIN ||
1002 sc->jme_process_limit > JME_PROC_MAX) {
1003 device_printf(sc->jme_dev,
1004 "process_limit value out of range; "
1005 "using default: %d\n", JME_PROC_DEFAULT);
1006 sc->jme_process_limit = JME_PROC_DEFAULT;
1007 }
1008 }
1009
1010 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1011 error = resource_int_value(device_get_name(sc->jme_dev),
1012 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to);
1013 if (error == 0) {
1014 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN ||
1015 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) {
1016 device_printf(sc->jme_dev,
1017 "tx_coal_to value out of range; "
1018 "using default: %d\n", PCCTX_COAL_TO_DEFAULT);
1019 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1020 }
1021 }
1022
1023 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1024 error = resource_int_value(device_get_name(sc->jme_dev),
1025 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to);
1026 if (error == 0) {
1027 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN ||
1028 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) {
1029 device_printf(sc->jme_dev,
1030 "tx_coal_pkt value out of range; "
1031 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT);
1032 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1033 }
1034 }
1035
1036 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1037 error = resource_int_value(device_get_name(sc->jme_dev),
1038 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to);
1039 if (error == 0) {
1040 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN ||
1041 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) {
1042 device_printf(sc->jme_dev,
1043 "rx_coal_to value out of range; "
1044 "using default: %d\n", PCCRX_COAL_TO_DEFAULT);
1045 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1046 }
1047 }
1048
1049 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1050 error = resource_int_value(device_get_name(sc->jme_dev),
1051 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to);
1052 if (error == 0) {
1053 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN ||
1054 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) {
1055 device_printf(sc->jme_dev,
1056 "tx_coal_pkt value out of range; "
1057 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT);
1058 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1059 }
1060 }
1061
1062 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
1063 return;
1064
1065 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
1066 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "JME statistics");
1067 parent = SYSCTL_CHILDREN(tree);
1068
1069 /* Rx statistics. */
1070 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
1071 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
1072 child = SYSCTL_CHILDREN(tree);
1073 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1074 &stats->rx_good_frames, "Good frames");
1075 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
1076 &stats->rx_crc_errs, "CRC errors");
1077 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs",
1078 &stats->rx_mii_errs, "MII errors");
1079 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
1080 &stats->rx_fifo_oflows, "FIFO overflows");
1081 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty",
1082 &stats->rx_desc_empty, "Descriptor empty");
1083 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1084 &stats->rx_bad_frames, "Bad frames");
1085
1086 /* Tx statistics. */
1087 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
1088 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
1089 child = SYSCTL_CHILDREN(tree);
1090 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1091 &stats->tx_good_frames, "Good frames");
1092 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1093 &stats->tx_bad_frames, "Bad frames");
1094 }
1095
1096 #undef JME_SYSCTL_STAT_ADD32
1097
1098 struct jme_dmamap_arg {
1099 bus_addr_t jme_busaddr;
1100 };
1101
1102 static void
jme_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)1103 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1104 {
1105 struct jme_dmamap_arg *ctx;
1106
1107 if (error != 0)
1108 return;
1109
1110 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1111
1112 ctx = (struct jme_dmamap_arg *)arg;
1113 ctx->jme_busaddr = segs[0].ds_addr;
1114 }
1115
1116 static int
jme_dma_alloc(struct jme_softc * sc)1117 jme_dma_alloc(struct jme_softc *sc)
1118 {
1119 struct jme_dmamap_arg ctx;
1120 struct jme_txdesc *txd;
1121 struct jme_rxdesc *rxd;
1122 bus_addr_t lowaddr, rx_ring_end, tx_ring_end;
1123 int error, i;
1124
1125 lowaddr = BUS_SPACE_MAXADDR;
1126 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1127 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1128
1129 again:
1130 /* Create parent ring tag. */
1131 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1132 1, 0, /* algnmnt, boundary */
1133 lowaddr, /* lowaddr */
1134 BUS_SPACE_MAXADDR, /* highaddr */
1135 NULL, NULL, /* filter, filterarg */
1136 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1137 0, /* nsegments */
1138 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1139 0, /* flags */
1140 NULL, NULL, /* lockfunc, lockarg */
1141 &sc->jme_cdata.jme_ring_tag);
1142 if (error != 0) {
1143 device_printf(sc->jme_dev,
1144 "could not create parent ring DMA tag.\n");
1145 goto fail;
1146 }
1147 /* Create tag for Tx ring. */
1148 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1149 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */
1150 BUS_SPACE_MAXADDR, /* lowaddr */
1151 BUS_SPACE_MAXADDR, /* highaddr */
1152 NULL, NULL, /* filter, filterarg */
1153 JME_TX_RING_SIZE, /* maxsize */
1154 1, /* nsegments */
1155 JME_TX_RING_SIZE, /* maxsegsize */
1156 0, /* flags */
1157 NULL, NULL, /* lockfunc, lockarg */
1158 &sc->jme_cdata.jme_tx_ring_tag);
1159 if (error != 0) {
1160 device_printf(sc->jme_dev,
1161 "could not allocate Tx ring DMA tag.\n");
1162 goto fail;
1163 }
1164
1165 /* Create tag for Rx ring. */
1166 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1167 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */
1168 lowaddr, /* lowaddr */
1169 BUS_SPACE_MAXADDR, /* highaddr */
1170 NULL, NULL, /* filter, filterarg */
1171 JME_RX_RING_SIZE, /* maxsize */
1172 1, /* nsegments */
1173 JME_RX_RING_SIZE, /* maxsegsize */
1174 0, /* flags */
1175 NULL, NULL, /* lockfunc, lockarg */
1176 &sc->jme_cdata.jme_rx_ring_tag);
1177 if (error != 0) {
1178 device_printf(sc->jme_dev,
1179 "could not allocate Rx ring DMA tag.\n");
1180 goto fail;
1181 }
1182
1183 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1184 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
1185 (void **)&sc->jme_rdata.jme_tx_ring,
1186 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1187 &sc->jme_cdata.jme_tx_ring_map);
1188 if (error != 0) {
1189 device_printf(sc->jme_dev,
1190 "could not allocate DMA'able memory for Tx ring.\n");
1191 goto fail;
1192 }
1193
1194 ctx.jme_busaddr = 0;
1195 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
1196 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
1197 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1198 if (error != 0 || ctx.jme_busaddr == 0) {
1199 device_printf(sc->jme_dev,
1200 "could not load DMA'able memory for Tx ring.\n");
1201 goto fail;
1202 }
1203 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr;
1204
1205 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1206 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1207 (void **)&sc->jme_rdata.jme_rx_ring,
1208 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1209 &sc->jme_cdata.jme_rx_ring_map);
1210 if (error != 0) {
1211 device_printf(sc->jme_dev,
1212 "could not allocate DMA'able memory for Rx ring.\n");
1213 goto fail;
1214 }
1215
1216 ctx.jme_busaddr = 0;
1217 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1218 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1219 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1220 if (error != 0 || ctx.jme_busaddr == 0) {
1221 device_printf(sc->jme_dev,
1222 "could not load DMA'able memory for Rx ring.\n");
1223 goto fail;
1224 }
1225 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr;
1226
1227 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1228 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
1229 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
1230 JME_TX_RING_SIZE;
1231 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
1232 JME_RX_RING_SIZE;
1233 if ((JME_ADDR_HI(tx_ring_end) !=
1234 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1235 (JME_ADDR_HI(rx_ring_end) !=
1236 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1237 device_printf(sc->jme_dev, "4GB boundary crossed, "
1238 "switching to 32bit DMA address mode.\n");
1239 jme_dma_free(sc);
1240 /* Limit DMA address space to 32bit and try again. */
1241 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1242 goto again;
1243 }
1244 }
1245
1246 lowaddr = BUS_SPACE_MAXADDR;
1247 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1248 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1249 /* Create parent buffer tag. */
1250 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1251 1, 0, /* algnmnt, boundary */
1252 lowaddr, /* lowaddr */
1253 BUS_SPACE_MAXADDR, /* highaddr */
1254 NULL, NULL, /* filter, filterarg */
1255 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1256 0, /* nsegments */
1257 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1258 0, /* flags */
1259 NULL, NULL, /* lockfunc, lockarg */
1260 &sc->jme_cdata.jme_buffer_tag);
1261 if (error != 0) {
1262 device_printf(sc->jme_dev,
1263 "could not create parent buffer DMA tag.\n");
1264 goto fail;
1265 }
1266
1267 /* Create shadow status block tag. */
1268 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1269 JME_SSB_ALIGN, 0, /* algnmnt, boundary */
1270 BUS_SPACE_MAXADDR, /* lowaddr */
1271 BUS_SPACE_MAXADDR, /* highaddr */
1272 NULL, NULL, /* filter, filterarg */
1273 JME_SSB_SIZE, /* maxsize */
1274 1, /* nsegments */
1275 JME_SSB_SIZE, /* maxsegsize */
1276 0, /* flags */
1277 NULL, NULL, /* lockfunc, lockarg */
1278 &sc->jme_cdata.jme_ssb_tag);
1279 if (error != 0) {
1280 device_printf(sc->jme_dev,
1281 "could not create shared status block DMA tag.\n");
1282 goto fail;
1283 }
1284
1285 /* Create tag for Tx buffers. */
1286 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1287 1, 0, /* algnmnt, boundary */
1288 BUS_SPACE_MAXADDR, /* lowaddr */
1289 BUS_SPACE_MAXADDR, /* highaddr */
1290 NULL, NULL, /* filter, filterarg */
1291 JME_TSO_MAXSIZE, /* maxsize */
1292 JME_MAXTXSEGS, /* nsegments */
1293 JME_TSO_MAXSEGSIZE, /* maxsegsize */
1294 0, /* flags */
1295 NULL, NULL, /* lockfunc, lockarg */
1296 &sc->jme_cdata.jme_tx_tag);
1297 if (error != 0) {
1298 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1299 goto fail;
1300 }
1301
1302 /* Create tag for Rx buffers. */
1303 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1304 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
1305 BUS_SPACE_MAXADDR, /* lowaddr */
1306 BUS_SPACE_MAXADDR, /* highaddr */
1307 NULL, NULL, /* filter, filterarg */
1308 MCLBYTES, /* maxsize */
1309 1, /* nsegments */
1310 MCLBYTES, /* maxsegsize */
1311 0, /* flags */
1312 NULL, NULL, /* lockfunc, lockarg */
1313 &sc->jme_cdata.jme_rx_tag);
1314 if (error != 0) {
1315 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1316 goto fail;
1317 }
1318
1319 /*
1320 * Allocate DMA'able memory and load the DMA map for shared
1321 * status block.
1322 */
1323 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1324 (void **)&sc->jme_rdata.jme_ssb_block,
1325 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1326 &sc->jme_cdata.jme_ssb_map);
1327 if (error != 0) {
1328 device_printf(sc->jme_dev, "could not allocate DMA'able "
1329 "memory for shared status block.\n");
1330 goto fail;
1331 }
1332
1333 ctx.jme_busaddr = 0;
1334 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1335 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1336 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1337 if (error != 0 || ctx.jme_busaddr == 0) {
1338 device_printf(sc->jme_dev, "could not load DMA'able memory "
1339 "for shared status block.\n");
1340 goto fail;
1341 }
1342 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr;
1343
1344 /* Create DMA maps for Tx buffers. */
1345 for (i = 0; i < JME_TX_RING_CNT; i++) {
1346 txd = &sc->jme_cdata.jme_txdesc[i];
1347 txd->tx_m = NULL;
1348 txd->tx_dmamap = NULL;
1349 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1350 &txd->tx_dmamap);
1351 if (error != 0) {
1352 device_printf(sc->jme_dev,
1353 "could not create Tx dmamap.\n");
1354 goto fail;
1355 }
1356 }
1357 /* Create DMA maps for Rx buffers. */
1358 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1359 &sc->jme_cdata.jme_rx_sparemap)) != 0) {
1360 device_printf(sc->jme_dev,
1361 "could not create spare Rx dmamap.\n");
1362 goto fail;
1363 }
1364 for (i = 0; i < JME_RX_RING_CNT; i++) {
1365 rxd = &sc->jme_cdata.jme_rxdesc[i];
1366 rxd->rx_m = NULL;
1367 rxd->rx_dmamap = NULL;
1368 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1369 &rxd->rx_dmamap);
1370 if (error != 0) {
1371 device_printf(sc->jme_dev,
1372 "could not create Rx dmamap.\n");
1373 goto fail;
1374 }
1375 }
1376
1377 fail:
1378 return (error);
1379 }
1380
1381 static void
jme_dma_free(struct jme_softc * sc)1382 jme_dma_free(struct jme_softc *sc)
1383 {
1384 struct jme_txdesc *txd;
1385 struct jme_rxdesc *rxd;
1386 int i;
1387
1388 /* Tx ring */
1389 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1390 if (sc->jme_rdata.jme_tx_ring_paddr)
1391 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1392 sc->jme_cdata.jme_tx_ring_map);
1393 if (sc->jme_rdata.jme_tx_ring)
1394 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1395 sc->jme_rdata.jme_tx_ring,
1396 sc->jme_cdata.jme_tx_ring_map);
1397 sc->jme_rdata.jme_tx_ring = NULL;
1398 sc->jme_rdata.jme_tx_ring_paddr = 0;
1399 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1400 sc->jme_cdata.jme_tx_ring_tag = NULL;
1401 }
1402 /* Rx ring */
1403 if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1404 if (sc->jme_rdata.jme_rx_ring_paddr)
1405 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1406 sc->jme_cdata.jme_rx_ring_map);
1407 if (sc->jme_rdata.jme_rx_ring)
1408 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1409 sc->jme_rdata.jme_rx_ring,
1410 sc->jme_cdata.jme_rx_ring_map);
1411 sc->jme_rdata.jme_rx_ring = NULL;
1412 sc->jme_rdata.jme_rx_ring_paddr = 0;
1413 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1414 sc->jme_cdata.jme_rx_ring_tag = NULL;
1415 }
1416 /* Tx buffers */
1417 if (sc->jme_cdata.jme_tx_tag != NULL) {
1418 for (i = 0; i < JME_TX_RING_CNT; i++) {
1419 txd = &sc->jme_cdata.jme_txdesc[i];
1420 if (txd->tx_dmamap != NULL) {
1421 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1422 txd->tx_dmamap);
1423 txd->tx_dmamap = NULL;
1424 }
1425 }
1426 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1427 sc->jme_cdata.jme_tx_tag = NULL;
1428 }
1429 /* Rx buffers */
1430 if (sc->jme_cdata.jme_rx_tag != NULL) {
1431 for (i = 0; i < JME_RX_RING_CNT; i++) {
1432 rxd = &sc->jme_cdata.jme_rxdesc[i];
1433 if (rxd->rx_dmamap != NULL) {
1434 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1435 rxd->rx_dmamap);
1436 rxd->rx_dmamap = NULL;
1437 }
1438 }
1439 if (sc->jme_cdata.jme_rx_sparemap != NULL) {
1440 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1441 sc->jme_cdata.jme_rx_sparemap);
1442 sc->jme_cdata.jme_rx_sparemap = NULL;
1443 }
1444 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1445 sc->jme_cdata.jme_rx_tag = NULL;
1446 }
1447
1448 /* Shared status block. */
1449 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1450 if (sc->jme_rdata.jme_ssb_block_paddr)
1451 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1452 sc->jme_cdata.jme_ssb_map);
1453 if (sc->jme_rdata.jme_ssb_block)
1454 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1455 sc->jme_rdata.jme_ssb_block,
1456 sc->jme_cdata.jme_ssb_map);
1457 sc->jme_rdata.jme_ssb_block = NULL;
1458 sc->jme_rdata.jme_ssb_block_paddr = 0;
1459 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1460 sc->jme_cdata.jme_ssb_tag = NULL;
1461 }
1462
1463 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1464 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1465 sc->jme_cdata.jme_buffer_tag = NULL;
1466 }
1467 if (sc->jme_cdata.jme_ring_tag != NULL) {
1468 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1469 sc->jme_cdata.jme_ring_tag = NULL;
1470 }
1471 }
1472
1473 /*
1474 * Make sure the interface is stopped at reboot time.
1475 */
1476 static int
jme_shutdown(device_t dev)1477 jme_shutdown(device_t dev)
1478 {
1479
1480 return (jme_suspend(dev));
1481 }
1482
1483 /*
1484 * Unlike other ethernet controllers, JMC250 requires
1485 * explicit resetting link speed to 10/100Mbps as gigabit
1486 * link will cunsume more power than 375mA.
1487 * Note, we reset the link speed to 10/100Mbps with
1488 * auto-negotiation but we don't know whether that operation
1489 * would succeed or not as we have no control after powering
1490 * off. If the renegotiation fail WOL may not work. Running
1491 * at 1Gbps draws more power than 375mA at 3.3V which is
1492 * specified in PCI specification and that would result in
1493 * complete shutdowning power to ethernet controller.
1494 *
1495 * TODO
1496 * Save current negotiated media speed/duplex/flow-control
1497 * to softc and restore the same link again after resuming.
1498 * PHY handling such as power down/resetting to 100Mbps
1499 * may be better handled in suspend method in phy driver.
1500 */
1501 static void
jme_setlinkspeed(struct jme_softc * sc)1502 jme_setlinkspeed(struct jme_softc *sc)
1503 {
1504 struct mii_data *mii;
1505 int aneg, i;
1506
1507 JME_LOCK_ASSERT(sc);
1508
1509 mii = device_get_softc(sc->jme_miibus);
1510 mii_pollstat(mii);
1511 aneg = 0;
1512 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1513 switch IFM_SUBTYPE(mii->mii_media_active) {
1514 case IFM_10_T:
1515 case IFM_100_TX:
1516 return;
1517 case IFM_1000_T:
1518 aneg++;
1519 default:
1520 break;
1521 }
1522 }
1523 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1524 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1525 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1526 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1527 BMCR_AUTOEN | BMCR_STARTNEG);
1528 DELAY(1000);
1529 if (aneg != 0) {
1530 /* Poll link state until jme(4) get a 10/100 link. */
1531 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1532 mii_pollstat(mii);
1533 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1534 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1535 case IFM_10_T:
1536 case IFM_100_TX:
1537 jme_mac_config(sc);
1538 return;
1539 default:
1540 break;
1541 }
1542 }
1543 JME_UNLOCK(sc);
1544 pause("jmelnk", hz);
1545 JME_LOCK(sc);
1546 }
1547 if (i == MII_ANEGTICKS_GIGE)
1548 device_printf(sc->jme_dev, "establishing link failed, "
1549 "WOL may not work!");
1550 }
1551 /*
1552 * No link, force MAC to have 100Mbps, full-duplex link.
1553 * This is the last resort and may/may not work.
1554 */
1555 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1556 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1557 jme_mac_config(sc);
1558 }
1559
1560 static void
jme_setwol(struct jme_softc * sc)1561 jme_setwol(struct jme_softc *sc)
1562 {
1563 if_t ifp;
1564 uint32_t gpr, pmcs;
1565 uint16_t pmstat;
1566 int pmc;
1567
1568 JME_LOCK_ASSERT(sc);
1569
1570 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1571 /* Remove Tx MAC/offload clock to save more power. */
1572 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1573 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1574 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1575 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1576 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0)
1577 CSR_WRITE_4(sc, JME_GPREG1,
1578 CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS);
1579 /* No PME capability, PHY power down. */
1580 jme_phy_down(sc);
1581 return;
1582 }
1583
1584 ifp = sc->jme_ifp;
1585 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1586 pmcs = CSR_READ_4(sc, JME_PMCS);
1587 pmcs &= ~PMCS_WOL_ENB_MASK;
1588 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) {
1589 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1590 /* Enable PME message. */
1591 gpr |= GPREG0_PME_ENB;
1592 /* For gigabit controllers, reset link speed to 10/100. */
1593 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0)
1594 jme_setlinkspeed(sc);
1595 }
1596
1597 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1598 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1599 /* Remove Tx MAC/offload clock to save more power. */
1600 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1601 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1602 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1603 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1604 /* Request PME. */
1605 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1606 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1607 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1608 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1609 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1610 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
1611 /* No WOL, PHY power down. */
1612 jme_phy_down(sc);
1613 }
1614 }
1615
1616 static int
jme_suspend(device_t dev)1617 jme_suspend(device_t dev)
1618 {
1619 struct jme_softc *sc;
1620
1621 sc = device_get_softc(dev);
1622
1623 JME_LOCK(sc);
1624 jme_stop(sc);
1625 jme_setwol(sc);
1626 JME_UNLOCK(sc);
1627
1628 return (0);
1629 }
1630
1631 static int
jme_resume(device_t dev)1632 jme_resume(device_t dev)
1633 {
1634 struct jme_softc *sc;
1635 if_t ifp;
1636 uint16_t pmstat;
1637 int pmc;
1638
1639 sc = device_get_softc(dev);
1640
1641 JME_LOCK(sc);
1642 if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) == 0) {
1643 pmstat = pci_read_config(sc->jme_dev,
1644 pmc + PCIR_POWER_STATUS, 2);
1645 /* Disable PME clear PME status. */
1646 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1647 pci_write_config(sc->jme_dev,
1648 pmc + PCIR_POWER_STATUS, pmstat, 2);
1649 }
1650 /* Wakeup PHY. */
1651 jme_phy_up(sc);
1652 ifp = sc->jme_ifp;
1653 if ((if_getflags(ifp) & IFF_UP) != 0) {
1654 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1655 jme_init_locked(sc);
1656 }
1657
1658 JME_UNLOCK(sc);
1659
1660 return (0);
1661 }
1662
1663 static int
jme_encap(struct jme_softc * sc,struct mbuf ** m_head)1664 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1665 {
1666 struct jme_txdesc *txd;
1667 struct jme_desc *desc;
1668 struct mbuf *m;
1669 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1670 int error, i, nsegs, prod;
1671 uint32_t cflags, tsosegsz;
1672
1673 JME_LOCK_ASSERT(sc);
1674
1675 M_ASSERTPKTHDR((*m_head));
1676
1677 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1678 /*
1679 * Due to the adherence to NDIS specification JMC250
1680 * assumes upper stack computed TCP pseudo checksum
1681 * without including payload length. This breaks
1682 * checksum offload for TSO case so recompute TCP
1683 * pseudo checksum for JMC250. Hopefully this wouldn't
1684 * be much burden on modern CPUs.
1685 */
1686 struct ether_header *eh;
1687 struct ip *ip;
1688 struct tcphdr *tcp;
1689 uint32_t ip_off, poff;
1690
1691 if (M_WRITABLE(*m_head) == 0) {
1692 /* Get a writable copy. */
1693 m = m_dup(*m_head, M_NOWAIT);
1694 m_freem(*m_head);
1695 if (m == NULL) {
1696 *m_head = NULL;
1697 return (ENOBUFS);
1698 }
1699 *m_head = m;
1700 }
1701 ip_off = sizeof(struct ether_header);
1702 m = m_pullup(*m_head, ip_off);
1703 if (m == NULL) {
1704 *m_head = NULL;
1705 return (ENOBUFS);
1706 }
1707 eh = mtod(m, struct ether_header *);
1708 /* Check the existence of VLAN tag. */
1709 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1710 ip_off = sizeof(struct ether_vlan_header);
1711 m = m_pullup(m, ip_off);
1712 if (m == NULL) {
1713 *m_head = NULL;
1714 return (ENOBUFS);
1715 }
1716 }
1717 m = m_pullup(m, ip_off + sizeof(struct ip));
1718 if (m == NULL) {
1719 *m_head = NULL;
1720 return (ENOBUFS);
1721 }
1722 ip = (struct ip *)(mtod(m, char *) + ip_off);
1723 poff = ip_off + (ip->ip_hl << 2);
1724 m = m_pullup(m, poff + sizeof(struct tcphdr));
1725 if (m == NULL) {
1726 *m_head = NULL;
1727 return (ENOBUFS);
1728 }
1729 /*
1730 * Reset IP checksum and recompute TCP pseudo
1731 * checksum that NDIS specification requires.
1732 */
1733 ip = (struct ip *)(mtod(m, char *) + ip_off);
1734 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1735 ip->ip_sum = 0;
1736 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1737 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1738 ip->ip_dst.s_addr,
1739 htons((tcp->th_off << 2) + IPPROTO_TCP));
1740 /* No need to TSO, force IP checksum offload. */
1741 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO;
1742 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP;
1743 } else
1744 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1745 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1746 *m_head = m;
1747 }
1748
1749 prod = sc->jme_cdata.jme_tx_prod;
1750 txd = &sc->jme_cdata.jme_txdesc[prod];
1751
1752 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1753 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1754 if (error == EFBIG) {
1755 m = m_collapse(*m_head, M_NOWAIT, JME_MAXTXSEGS);
1756 if (m == NULL) {
1757 m_freem(*m_head);
1758 *m_head = NULL;
1759 return (ENOMEM);
1760 }
1761 *m_head = m;
1762 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1763 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1764 if (error != 0) {
1765 m_freem(*m_head);
1766 *m_head = NULL;
1767 return (error);
1768 }
1769 } else if (error != 0)
1770 return (error);
1771 if (nsegs == 0) {
1772 m_freem(*m_head);
1773 *m_head = NULL;
1774 return (EIO);
1775 }
1776
1777 /*
1778 * Check descriptor overrun. Leave one free descriptor.
1779 * Since we always use 64bit address mode for transmitting,
1780 * each Tx request requires one more dummy descriptor.
1781 */
1782 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) {
1783 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1784 return (ENOBUFS);
1785 }
1786
1787 m = *m_head;
1788 cflags = 0;
1789 tsosegsz = 0;
1790 /* Configure checksum offload and TSO. */
1791 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1792 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz <<
1793 JME_TD_MSS_SHIFT;
1794 cflags |= JME_TD_TSO;
1795 } else {
1796 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1797 cflags |= JME_TD_IPCSUM;
1798 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1799 cflags |= JME_TD_TCPCSUM;
1800 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1801 cflags |= JME_TD_UDPCSUM;
1802 }
1803 /* Configure VLAN. */
1804 if ((m->m_flags & M_VLANTAG) != 0) {
1805 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK);
1806 cflags |= JME_TD_VLAN_TAG;
1807 }
1808
1809 desc = &sc->jme_rdata.jme_tx_ring[prod];
1810 desc->flags = htole32(cflags);
1811 desc->buflen = htole32(tsosegsz);
1812 desc->addr_hi = htole32(m->m_pkthdr.len);
1813 desc->addr_lo = 0;
1814 sc->jme_cdata.jme_tx_cnt++;
1815 JME_DESC_INC(prod, JME_TX_RING_CNT);
1816 for (i = 0; i < nsegs; i++) {
1817 desc = &sc->jme_rdata.jme_tx_ring[prod];
1818 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1819 desc->buflen = htole32(txsegs[i].ds_len);
1820 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1821 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1822 sc->jme_cdata.jme_tx_cnt++;
1823 JME_DESC_INC(prod, JME_TX_RING_CNT);
1824 }
1825
1826 /* Update producer index. */
1827 sc->jme_cdata.jme_tx_prod = prod;
1828 /*
1829 * Finally request interrupt and give the first descriptor
1830 * owenership to hardware.
1831 */
1832 desc = txd->tx_desc;
1833 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1834
1835 txd->tx_m = m;
1836 txd->tx_ndesc = nsegs + 1;
1837
1838 /* Sync descriptors. */
1839 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1840 BUS_DMASYNC_PREWRITE);
1841 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1842 sc->jme_cdata.jme_tx_ring_map,
1843 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1844
1845 return (0);
1846 }
1847
1848 static void
jme_start(if_t ifp)1849 jme_start(if_t ifp)
1850 {
1851 struct jme_softc *sc;
1852
1853 sc = if_getsoftc(ifp);
1854 JME_LOCK(sc);
1855 jme_start_locked(ifp);
1856 JME_UNLOCK(sc);
1857 }
1858
1859 static void
jme_start_locked(if_t ifp)1860 jme_start_locked(if_t ifp)
1861 {
1862 struct jme_softc *sc;
1863 struct mbuf *m_head;
1864 int enq;
1865
1866 sc = if_getsoftc(ifp);
1867
1868 JME_LOCK_ASSERT(sc);
1869
1870 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT)
1871 jme_txeof(sc);
1872
1873 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1874 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0)
1875 return;
1876
1877 for (enq = 0; !if_sendq_empty(ifp); ) {
1878 m_head = if_dequeue(ifp);
1879 if (m_head == NULL)
1880 break;
1881 /*
1882 * Pack the data into the transmit ring. If we
1883 * don't have room, set the OACTIVE flag and wait
1884 * for the NIC to drain the ring.
1885 */
1886 if (jme_encap(sc, &m_head)) {
1887 if (m_head == NULL)
1888 break;
1889 if_sendq_prepend(ifp, m_head);
1890 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1891 break;
1892 }
1893
1894 enq++;
1895 /*
1896 * If there's a BPF listener, bounce a copy of this frame
1897 * to him.
1898 */
1899 ETHER_BPF_MTAP(ifp, m_head);
1900 }
1901
1902 if (enq > 0) {
1903 /*
1904 * Reading TXCSR takes very long time under heavy load
1905 * so cache TXCSR value and writes the ORed value with
1906 * the kick command to the TXCSR. This saves one register
1907 * access cycle.
1908 */
1909 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1910 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1911 /* Set a timeout in case the chip goes out to lunch. */
1912 sc->jme_watchdog_timer = JME_TX_TIMEOUT;
1913 }
1914 }
1915
1916 static void
jme_watchdog(struct jme_softc * sc)1917 jme_watchdog(struct jme_softc *sc)
1918 {
1919 if_t ifp;
1920
1921 JME_LOCK_ASSERT(sc);
1922
1923 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer)
1924 return;
1925
1926 ifp = sc->jme_ifp;
1927 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1928 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n");
1929 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1930 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1931 jme_init_locked(sc);
1932 return;
1933 }
1934 jme_txeof(sc);
1935 if (sc->jme_cdata.jme_tx_cnt == 0) {
1936 if_printf(sc->jme_ifp,
1937 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1938 if (!if_sendq_empty(ifp))
1939 jme_start_locked(ifp);
1940 return;
1941 }
1942
1943 if_printf(sc->jme_ifp, "watchdog timeout\n");
1944 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1945 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1946 jme_init_locked(sc);
1947 if (!if_sendq_empty(ifp))
1948 jme_start_locked(ifp);
1949 }
1950
1951 static int
jme_ioctl(if_t ifp,u_long cmd,caddr_t data)1952 jme_ioctl(if_t ifp, u_long cmd, caddr_t data)
1953 {
1954 struct jme_softc *sc;
1955 struct ifreq *ifr;
1956 struct mii_data *mii;
1957 uint32_t reg;
1958 int error, mask;
1959
1960 sc = if_getsoftc(ifp);
1961 ifr = (struct ifreq *)data;
1962 error = 0;
1963 switch (cmd) {
1964 case SIOCSIFMTU:
1965 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1966 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 &&
1967 ifr->ifr_mtu > JME_MAX_MTU)) {
1968 error = EINVAL;
1969 break;
1970 }
1971
1972 if (if_getmtu(ifp) != ifr->ifr_mtu) {
1973 /*
1974 * No special configuration is required when interface
1975 * MTU is changed but availability of TSO/Tx checksum
1976 * offload should be chcked against new MTU size as
1977 * FIFO size is just 2K.
1978 */
1979 JME_LOCK(sc);
1980 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1981 if_setcapenablebit(ifp, 0,
1982 IFCAP_TXCSUM | IFCAP_TSO4);
1983 if_sethwassistbits(ifp, 0,
1984 JME_CSUM_FEATURES | CSUM_TSO);
1985 VLAN_CAPABILITIES(ifp);
1986 }
1987 if_setmtu(ifp, ifr->ifr_mtu);
1988 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1989 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1990 jme_init_locked(sc);
1991 }
1992 JME_UNLOCK(sc);
1993 }
1994 break;
1995 case SIOCSIFFLAGS:
1996 JME_LOCK(sc);
1997 if ((if_getflags(ifp) & IFF_UP) != 0) {
1998 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1999 if (((if_getflags(ifp) ^ sc->jme_if_flags)
2000 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2001 jme_set_filter(sc);
2002 } else {
2003 if ((sc->jme_flags & JME_FLAG_DETACH) == 0)
2004 jme_init_locked(sc);
2005 }
2006 } else {
2007 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2008 jme_stop(sc);
2009 }
2010 sc->jme_if_flags = if_getflags(ifp);
2011 JME_UNLOCK(sc);
2012 break;
2013 case SIOCADDMULTI:
2014 case SIOCDELMULTI:
2015 JME_LOCK(sc);
2016 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2017 jme_set_filter(sc);
2018 JME_UNLOCK(sc);
2019 break;
2020 case SIOCSIFMEDIA:
2021 case SIOCGIFMEDIA:
2022 mii = device_get_softc(sc->jme_miibus);
2023 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2024 break;
2025 case SIOCSIFCAP:
2026 JME_LOCK(sc);
2027 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
2028 if ((mask & IFCAP_TXCSUM) != 0 &&
2029 if_getmtu(ifp) < JME_TX_FIFO_SIZE) {
2030 if ((IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) {
2031 if_togglecapenable(ifp, IFCAP_TXCSUM);
2032 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0)
2033 if_sethwassistbits(ifp, JME_CSUM_FEATURES, 0);
2034 else
2035 if_sethwassistbits(ifp, 0, JME_CSUM_FEATURES);
2036 }
2037 }
2038 if ((mask & IFCAP_RXCSUM) != 0 &&
2039 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) {
2040 if_togglecapenable(ifp, IFCAP_RXCSUM);
2041 reg = CSR_READ_4(sc, JME_RXMAC);
2042 reg &= ~RXMAC_CSUM_ENB;
2043 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2044 reg |= RXMAC_CSUM_ENB;
2045 CSR_WRITE_4(sc, JME_RXMAC, reg);
2046 }
2047 if ((mask & IFCAP_TSO4) != 0 &&
2048 if_getmtu(ifp) < JME_TX_FIFO_SIZE) {
2049 if ((IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) {
2050 if_togglecapenable(ifp, IFCAP_TSO4);
2051 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0)
2052 if_sethwassistbits(ifp, CSUM_TSO, 0);
2053 else
2054 if_sethwassistbits(ifp, 0, CSUM_TSO);
2055 }
2056 }
2057 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2058 (IFCAP_WOL_MAGIC & if_getcapabilities(ifp)) != 0)
2059 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2060 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2061 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2062 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2063 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2064 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2065 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2066 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2067 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) {
2068 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2069 jme_set_vlan(sc);
2070 }
2071 JME_UNLOCK(sc);
2072 VLAN_CAPABILITIES(ifp);
2073 break;
2074 default:
2075 error = ether_ioctl(ifp, cmd, data);
2076 break;
2077 }
2078
2079 return (error);
2080 }
2081
2082 static void
jme_mac_config(struct jme_softc * sc)2083 jme_mac_config(struct jme_softc *sc)
2084 {
2085 struct mii_data *mii;
2086 uint32_t ghc, gpreg, rxmac, txmac, txpause;
2087 uint32_t txclk;
2088
2089 JME_LOCK_ASSERT(sc);
2090
2091 mii = device_get_softc(sc->jme_miibus);
2092
2093 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2094 DELAY(10);
2095 CSR_WRITE_4(sc, JME_GHC, 0);
2096 ghc = 0;
2097 txclk = 0;
2098 rxmac = CSR_READ_4(sc, JME_RXMAC);
2099 rxmac &= ~RXMAC_FC_ENB;
2100 txmac = CSR_READ_4(sc, JME_TXMAC);
2101 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2102 txpause = CSR_READ_4(sc, JME_TXPFC);
2103 txpause &= ~TXPFC_PAUSE_ENB;
2104 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2105 ghc |= GHC_FULL_DUPLEX;
2106 rxmac &= ~RXMAC_COLL_DET_ENB;
2107 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2108 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2109 TXMAC_FRAME_BURST);
2110 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2111 txpause |= TXPFC_PAUSE_ENB;
2112 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2113 rxmac |= RXMAC_FC_ENB;
2114 /* Disable retry transmit timer/retry limit. */
2115 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2116 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2117 } else {
2118 rxmac |= RXMAC_COLL_DET_ENB;
2119 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2120 /* Enable retry transmit timer/retry limit. */
2121 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2122 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2123 }
2124 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */
2125 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2126 case IFM_10_T:
2127 ghc |= GHC_SPEED_10;
2128 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2129 break;
2130 case IFM_100_TX:
2131 ghc |= GHC_SPEED_100;
2132 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2133 break;
2134 case IFM_1000_T:
2135 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2136 break;
2137 ghc |= GHC_SPEED_1000;
2138 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000;
2139 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2140 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2141 break;
2142 default:
2143 break;
2144 }
2145 if (sc->jme_rev == DEVICEID_JMC250 &&
2146 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) {
2147 /*
2148 * Workaround occasional packet loss issue of JMC250 A2
2149 * when it runs on half-duplex media.
2150 */
2151 gpreg = CSR_READ_4(sc, JME_GPREG1);
2152 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
2153 gpreg &= ~GPREG1_HDPX_FIX;
2154 else
2155 gpreg |= GPREG1_HDPX_FIX;
2156 CSR_WRITE_4(sc, JME_GPREG1, gpreg);
2157 /* Workaround CRC errors at 100Mbps on JMC250 A2. */
2158 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2159 /* Extend interface FIFO depth. */
2160 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2161 0x1B, 0x0000);
2162 } else {
2163 /* Select default interface FIFO depth. */
2164 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2165 0x1B, 0x0004);
2166 }
2167 }
2168 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2169 ghc |= txclk;
2170 CSR_WRITE_4(sc, JME_GHC, ghc);
2171 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2172 CSR_WRITE_4(sc, JME_TXMAC, txmac);
2173 CSR_WRITE_4(sc, JME_TXPFC, txpause);
2174 }
2175
2176 static void
jme_link_task(void * arg,int pending)2177 jme_link_task(void *arg, int pending)
2178 {
2179 struct jme_softc *sc;
2180 struct mii_data *mii;
2181 if_t ifp;
2182 struct jme_txdesc *txd;
2183 bus_addr_t paddr;
2184 int i;
2185
2186 sc = (struct jme_softc *)arg;
2187
2188 JME_LOCK(sc);
2189 mii = device_get_softc(sc->jme_miibus);
2190 ifp = sc->jme_ifp;
2191 if (mii == NULL || ifp == NULL ||
2192 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
2193 JME_UNLOCK(sc);
2194 return;
2195 }
2196
2197 sc->jme_flags &= ~JME_FLAG_LINK;
2198 if ((mii->mii_media_status & IFM_AVALID) != 0) {
2199 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2200 case IFM_10_T:
2201 case IFM_100_TX:
2202 sc->jme_flags |= JME_FLAG_LINK;
2203 break;
2204 case IFM_1000_T:
2205 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2206 break;
2207 sc->jme_flags |= JME_FLAG_LINK;
2208 break;
2209 default:
2210 break;
2211 }
2212 }
2213
2214 /*
2215 * Disabling Rx/Tx MACs have a side-effect of resetting
2216 * JME_TXNDA/JME_RXNDA register to the first address of
2217 * Tx/Rx descriptor address. So driver should reset its
2218 * internal procucer/consumer pointer and reclaim any
2219 * allocated resources. Note, just saving the value of
2220 * JME_TXNDA and JME_RXNDA registers before stopping MAC
2221 * and restoring JME_TXNDA/JME_RXNDA register is not
2222 * sufficient to make sure correct MAC state because
2223 * stopping MAC operation can take a while and hardware
2224 * might have updated JME_TXNDA/JME_RXNDA registers
2225 * during the stop operation.
2226 */
2227 /* Block execution of task. */
2228 taskqueue_block(sc->jme_tq);
2229 /* Disable interrupts and stop driver. */
2230 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2231 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2232 callout_stop(&sc->jme_tick_ch);
2233 sc->jme_watchdog_timer = 0;
2234
2235 /* Stop receiver/transmitter. */
2236 jme_stop_rx(sc);
2237 jme_stop_tx(sc);
2238
2239 /* XXX Drain all queued tasks. */
2240 JME_UNLOCK(sc);
2241 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
2242 JME_LOCK(sc);
2243
2244 if (sc->jme_cdata.jme_rxhead != NULL)
2245 m_freem(sc->jme_cdata.jme_rxhead);
2246 JME_RXCHAIN_RESET(sc);
2247 jme_txeof(sc);
2248 if (sc->jme_cdata.jme_tx_cnt != 0) {
2249 /* Remove queued packets for transmit. */
2250 for (i = 0; i < JME_TX_RING_CNT; i++) {
2251 txd = &sc->jme_cdata.jme_txdesc[i];
2252 if (txd->tx_m != NULL) {
2253 bus_dmamap_sync(
2254 sc->jme_cdata.jme_tx_tag,
2255 txd->tx_dmamap,
2256 BUS_DMASYNC_POSTWRITE);
2257 bus_dmamap_unload(
2258 sc->jme_cdata.jme_tx_tag,
2259 txd->tx_dmamap);
2260 m_freem(txd->tx_m);
2261 txd->tx_m = NULL;
2262 txd->tx_ndesc = 0;
2263 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2264 }
2265 }
2266 }
2267
2268 /*
2269 * Reuse configured Rx descriptors and reset
2270 * producer/consumer index.
2271 */
2272 sc->jme_cdata.jme_rx_cons = 0;
2273 sc->jme_morework = 0;
2274 jme_init_tx_ring(sc);
2275 /* Initialize shadow status block. */
2276 jme_init_ssb(sc);
2277
2278 /* Program MAC with resolved speed/duplex/flow-control. */
2279 if ((sc->jme_flags & JME_FLAG_LINK) != 0) {
2280 jme_mac_config(sc);
2281 jme_stats_clear(sc);
2282
2283 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2284 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2285
2286 /* Set Tx ring address to the hardware. */
2287 paddr = JME_TX_RING_ADDR(sc, 0);
2288 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2289 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2290
2291 /* Set Rx ring address to the hardware. */
2292 paddr = JME_RX_RING_ADDR(sc, 0);
2293 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2294 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2295
2296 /* Restart receiver/transmitter. */
2297 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
2298 RXCSR_RXQ_START);
2299 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
2300 /* Lastly enable TX/RX clock. */
2301 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2302 CSR_WRITE_4(sc, JME_GHC,
2303 CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS);
2304 if ((sc->jme_flags & JME_FLAG_RXCLK) != 0)
2305 CSR_WRITE_4(sc, JME_GPREG1,
2306 CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS);
2307 }
2308
2309 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2310 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2311 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2312 /* Unblock execution of task. */
2313 taskqueue_unblock(sc->jme_tq);
2314 /* Reenable interrupts. */
2315 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2316
2317 JME_UNLOCK(sc);
2318 }
2319
2320 static int
jme_intr(void * arg)2321 jme_intr(void *arg)
2322 {
2323 struct jme_softc *sc;
2324 uint32_t status;
2325
2326 sc = (struct jme_softc *)arg;
2327
2328 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2329 if (status == 0 || status == 0xFFFFFFFF)
2330 return (FILTER_STRAY);
2331 /* Disable interrupts. */
2332 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2333 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2334
2335 return (FILTER_HANDLED);
2336 }
2337
2338 static void
jme_int_task(void * arg,int pending)2339 jme_int_task(void *arg, int pending)
2340 {
2341 struct jme_softc *sc;
2342 if_t ifp;
2343 uint32_t status;
2344 int more;
2345
2346 sc = (struct jme_softc *)arg;
2347 ifp = sc->jme_ifp;
2348
2349 JME_LOCK(sc);
2350 status = CSR_READ_4(sc, JME_INTR_STATUS);
2351 if (sc->jme_morework != 0) {
2352 sc->jme_morework = 0;
2353 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO;
2354 }
2355 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2356 goto done;
2357 /* Reset PCC counter/timer and Ack interrupts. */
2358 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2359 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
2360 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2361 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
2362 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
2363 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2364 more = 0;
2365 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2366 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) {
2367 more = jme_rxintr(sc, sc->jme_process_limit);
2368 if (more != 0)
2369 sc->jme_morework = 1;
2370 }
2371 if ((status & INTR_RXQ_DESC_EMPTY) != 0) {
2372 /*
2373 * Notify hardware availability of new Rx
2374 * buffers.
2375 * Reading RXCSR takes very long time under
2376 * heavy load so cache RXCSR value and writes
2377 * the ORed value with the kick command to
2378 * the RXCSR. This saves one register access
2379 * cycle.
2380 */
2381 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2382 RXCSR_RX_ENB | RXCSR_RXQ_START);
2383 }
2384 if (!if_sendq_empty(ifp))
2385 jme_start_locked(ifp);
2386 }
2387
2388 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) {
2389 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2390 JME_UNLOCK(sc);
2391 return;
2392 }
2393 done:
2394 JME_UNLOCK(sc);
2395
2396 /* Reenable interrupts. */
2397 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2398 }
2399
2400 static void
jme_txeof(struct jme_softc * sc)2401 jme_txeof(struct jme_softc *sc)
2402 {
2403 if_t ifp;
2404 struct jme_txdesc *txd;
2405 uint32_t status;
2406 int cons, nsegs;
2407
2408 JME_LOCK_ASSERT(sc);
2409
2410 ifp = sc->jme_ifp;
2411
2412 cons = sc->jme_cdata.jme_tx_cons;
2413 if (cons == sc->jme_cdata.jme_tx_prod)
2414 return;
2415
2416 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2417 sc->jme_cdata.jme_tx_ring_map,
2418 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2419
2420 /*
2421 * Go through our Tx list and free mbufs for those
2422 * frames which have been transmitted.
2423 */
2424 for (; cons != sc->jme_cdata.jme_tx_prod;) {
2425 txd = &sc->jme_cdata.jme_txdesc[cons];
2426 status = le32toh(txd->tx_desc->flags);
2427 if ((status & JME_TD_OWN) == JME_TD_OWN)
2428 break;
2429
2430 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0)
2431 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2432 else {
2433 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2434 if ((status & JME_TD_COLLISION) != 0)
2435 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2436 le32toh(txd->tx_desc->buflen) &
2437 JME_TD_BUF_LEN_MASK);
2438 }
2439 /*
2440 * Only the first descriptor of multi-descriptor
2441 * transmission is updated so driver have to skip entire
2442 * chained buffers for the transmiited frame. In other
2443 * words, JME_TD_OWN bit is valid only at the first
2444 * descriptor of a multi-descriptor transmission.
2445 */
2446 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2447 sc->jme_rdata.jme_tx_ring[cons].flags = 0;
2448 JME_DESC_INC(cons, JME_TX_RING_CNT);
2449 }
2450
2451 /* Reclaim transferred mbufs. */
2452 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
2453 BUS_DMASYNC_POSTWRITE);
2454 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2455
2456 KASSERT(txd->tx_m != NULL,
2457 ("%s: freeing NULL mbuf!\n", __func__));
2458 m_freem(txd->tx_m);
2459 txd->tx_m = NULL;
2460 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2461 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2462 ("%s: Active Tx desc counter was garbled\n", __func__));
2463 txd->tx_ndesc = 0;
2464 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2465 }
2466 sc->jme_cdata.jme_tx_cons = cons;
2467 /* Unarm watchdog timer when there is no pending descriptors in queue. */
2468 if (sc->jme_cdata.jme_tx_cnt == 0)
2469 sc->jme_watchdog_timer = 0;
2470
2471 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2472 sc->jme_cdata.jme_tx_ring_map,
2473 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2474 }
2475
2476 static __inline void
jme_discard_rxbuf(struct jme_softc * sc,int cons)2477 jme_discard_rxbuf(struct jme_softc *sc, int cons)
2478 {
2479 struct jme_desc *desc;
2480
2481 desc = &sc->jme_rdata.jme_rx_ring[cons];
2482 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2483 desc->buflen = htole32(MCLBYTES);
2484 }
2485
2486 /* Receive a frame. */
2487 static void
jme_rxeof(struct jme_softc * sc)2488 jme_rxeof(struct jme_softc *sc)
2489 {
2490 if_t ifp;
2491 struct jme_desc *desc;
2492 struct jme_rxdesc *rxd;
2493 struct mbuf *mp, *m;
2494 uint32_t flags, status;
2495 int cons, count, nsegs;
2496
2497 JME_LOCK_ASSERT(sc);
2498
2499 ifp = sc->jme_ifp;
2500
2501 cons = sc->jme_cdata.jme_rx_cons;
2502 desc = &sc->jme_rdata.jme_rx_ring[cons];
2503 flags = le32toh(desc->flags);
2504 status = le32toh(desc->buflen);
2505 nsegs = JME_RX_NSEGS(status);
2506 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2507 if ((status & JME_RX_ERR_STAT) != 0) {
2508 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2509 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons);
2510 #ifdef JME_SHOW_ERRORS
2511 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2512 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2513 #endif
2514 sc->jme_cdata.jme_rx_cons += nsegs;
2515 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2516 return;
2517 }
2518
2519 for (count = 0; count < nsegs; count++,
2520 JME_DESC_INC(cons, JME_RX_RING_CNT)) {
2521 rxd = &sc->jme_cdata.jme_rxdesc[cons];
2522 mp = rxd->rx_m;
2523 /* Add a new receive buffer to the ring. */
2524 if (jme_newbuf(sc, rxd) != 0) {
2525 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2526 /* Reuse buffer. */
2527 for (; count < nsegs; count++) {
2528 jme_discard_rxbuf(sc, cons);
2529 JME_DESC_INC(cons, JME_RX_RING_CNT);
2530 }
2531 if (sc->jme_cdata.jme_rxhead != NULL) {
2532 m_freem(sc->jme_cdata.jme_rxhead);
2533 JME_RXCHAIN_RESET(sc);
2534 }
2535 break;
2536 }
2537
2538 /*
2539 * Assume we've received a full sized frame.
2540 * Actual size is fixed when we encounter the end of
2541 * multi-segmented frame.
2542 */
2543 mp->m_len = MCLBYTES;
2544
2545 /* Chain received mbufs. */
2546 if (sc->jme_cdata.jme_rxhead == NULL) {
2547 sc->jme_cdata.jme_rxhead = mp;
2548 sc->jme_cdata.jme_rxtail = mp;
2549 } else {
2550 /*
2551 * Receive processor can receive a maximum frame
2552 * size of 65535 bytes.
2553 */
2554 mp->m_flags &= ~M_PKTHDR;
2555 sc->jme_cdata.jme_rxtail->m_next = mp;
2556 sc->jme_cdata.jme_rxtail = mp;
2557 }
2558
2559 if (count == nsegs - 1) {
2560 /* Last desc. for this frame. */
2561 m = sc->jme_cdata.jme_rxhead;
2562 m->m_flags |= M_PKTHDR;
2563 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2564 if (nsegs > 1) {
2565 /* Set first mbuf size. */
2566 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2567 /* Set last mbuf size. */
2568 mp->m_len = sc->jme_cdata.jme_rxlen -
2569 ((MCLBYTES - JME_RX_PAD_BYTES) +
2570 (MCLBYTES * (nsegs - 2)));
2571 } else
2572 m->m_len = sc->jme_cdata.jme_rxlen;
2573 m->m_pkthdr.rcvif = ifp;
2574
2575 /*
2576 * Account for 10bytes auto padding which is used
2577 * to align IP header on 32bit boundary. Also note,
2578 * CRC bytes is automatically removed by the
2579 * hardware.
2580 */
2581 m->m_data += JME_RX_PAD_BYTES;
2582
2583 /* Set checksum information. */
2584 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
2585 (flags & JME_RD_IPV4) != 0) {
2586 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2587 if ((flags & JME_RD_IPCSUM) != 0)
2588 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2589 if (((flags & JME_RD_MORE_FRAG) == 0) &&
2590 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2591 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2592 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2593 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2594 m->m_pkthdr.csum_flags |=
2595 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2596 m->m_pkthdr.csum_data = 0xffff;
2597 }
2598 }
2599
2600 /* Check for VLAN tagged packets. */
2601 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
2602 (flags & JME_RD_VLAN_TAG) != 0) {
2603 m->m_pkthdr.ether_vtag =
2604 flags & JME_RD_VLAN_MASK;
2605 m->m_flags |= M_VLANTAG;
2606 }
2607
2608 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2609 /* Pass it on. */
2610 JME_UNLOCK(sc);
2611 if_input(ifp, m);
2612 JME_LOCK(sc);
2613
2614 /* Reset mbuf chains. */
2615 JME_RXCHAIN_RESET(sc);
2616 }
2617 }
2618
2619 sc->jme_cdata.jme_rx_cons += nsegs;
2620 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2621 }
2622
2623 static int
jme_rxintr(struct jme_softc * sc,int count)2624 jme_rxintr(struct jme_softc *sc, int count)
2625 {
2626 struct jme_desc *desc;
2627 int nsegs, prog, pktlen;
2628
2629 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2630 sc->jme_cdata.jme_rx_ring_map,
2631 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2632
2633 for (prog = 0; count > 0; prog++) {
2634 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2635 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2636 break;
2637 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2638 break;
2639 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2640 /*
2641 * Check number of segments against received bytes.
2642 * Non-matching value would indicate that hardware
2643 * is still trying to update Rx descriptors. I'm not
2644 * sure whether this check is needed.
2645 */
2646 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2647 if (nsegs != howmany(pktlen, MCLBYTES))
2648 break;
2649 prog++;
2650 /* Received a frame. */
2651 jme_rxeof(sc);
2652 count -= nsegs;
2653 }
2654
2655 if (prog > 0)
2656 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2657 sc->jme_cdata.jme_rx_ring_map,
2658 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2659
2660 return (count > 0 ? 0 : EAGAIN);
2661 }
2662
2663 static void
jme_tick(void * arg)2664 jme_tick(void *arg)
2665 {
2666 struct jme_softc *sc;
2667 struct mii_data *mii;
2668
2669 sc = (struct jme_softc *)arg;
2670
2671 JME_LOCK_ASSERT(sc);
2672
2673 mii = device_get_softc(sc->jme_miibus);
2674 mii_tick(mii);
2675 /*
2676 * Reclaim Tx buffers that have been completed. It's not
2677 * needed here but it would release allocated mbuf chains
2678 * faster and limit the maximum delay to a hz.
2679 */
2680 jme_txeof(sc);
2681 jme_stats_update(sc);
2682 jme_watchdog(sc);
2683 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2684 }
2685
2686 static void
jme_reset(struct jme_softc * sc)2687 jme_reset(struct jme_softc *sc)
2688 {
2689 uint32_t ghc, gpreg;
2690
2691 /* Stop receiver, transmitter. */
2692 jme_stop_rx(sc);
2693 jme_stop_tx(sc);
2694
2695 /* Reset controller. */
2696 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2697 CSR_READ_4(sc, JME_GHC);
2698 DELAY(10);
2699 /*
2700 * Workaround Rx FIFO overruns seen under certain conditions.
2701 * Explicitly synchorize TX/RX clock. TX/RX clock should be
2702 * enabled only after enabling TX/RX MACs.
2703 */
2704 if ((sc->jme_flags & (JME_FLAG_TXCLK | JME_FLAG_RXCLK)) != 0) {
2705 /* Disable TX clock. */
2706 CSR_WRITE_4(sc, JME_GHC, GHC_RESET | GHC_TX_MAC_CLK_DIS);
2707 /* Disable RX clock. */
2708 gpreg = CSR_READ_4(sc, JME_GPREG1);
2709 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS);
2710 gpreg = CSR_READ_4(sc, JME_GPREG1);
2711 /* De-assert RESET but still disable TX clock. */
2712 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS);
2713 ghc = CSR_READ_4(sc, JME_GHC);
2714
2715 /* Enable TX clock. */
2716 CSR_WRITE_4(sc, JME_GHC, ghc & ~GHC_TX_MAC_CLK_DIS);
2717 /* Enable RX clock. */
2718 CSR_WRITE_4(sc, JME_GPREG1, gpreg & ~GPREG1_RX_MAC_CLK_DIS);
2719 CSR_READ_4(sc, JME_GPREG1);
2720
2721 /* Disable TX/RX clock again. */
2722 CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS);
2723 CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS);
2724 } else
2725 CSR_WRITE_4(sc, JME_GHC, 0);
2726 CSR_READ_4(sc, JME_GHC);
2727 DELAY(10);
2728 }
2729
2730 static void
jme_init(void * xsc)2731 jme_init(void *xsc)
2732 {
2733 struct jme_softc *sc;
2734
2735 sc = (struct jme_softc *)xsc;
2736 JME_LOCK(sc);
2737 jme_init_locked(sc);
2738 JME_UNLOCK(sc);
2739 }
2740
2741 static void
jme_init_locked(struct jme_softc * sc)2742 jme_init_locked(struct jme_softc *sc)
2743 {
2744 if_t ifp;
2745 struct mii_data *mii;
2746 bus_addr_t paddr;
2747 uint32_t reg;
2748 int error;
2749
2750 JME_LOCK_ASSERT(sc);
2751
2752 ifp = sc->jme_ifp;
2753 mii = device_get_softc(sc->jme_miibus);
2754
2755 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2756 return;
2757 /*
2758 * Cancel any pending I/O.
2759 */
2760 jme_stop(sc);
2761
2762 /*
2763 * Reset the chip to a known state.
2764 */
2765 jme_reset(sc);
2766
2767 /* Init descriptors. */
2768 error = jme_init_rx_ring(sc);
2769 if (error != 0) {
2770 device_printf(sc->jme_dev,
2771 "%s: initialization failed: no memory for Rx buffers.\n",
2772 __func__);
2773 jme_stop(sc);
2774 return;
2775 }
2776 jme_init_tx_ring(sc);
2777 /* Initialize shadow status block. */
2778 jme_init_ssb(sc);
2779
2780 /* Reprogram the station address. */
2781 jme_set_macaddr(sc, if_getlladdr(sc->jme_ifp));
2782
2783 /*
2784 * Configure Tx queue.
2785 * Tx priority queue weight value : 0
2786 * Tx FIFO threshold for processing next packet : 16QW
2787 * Maximum Tx DMA length : 512
2788 * Allow Tx DMA burst.
2789 */
2790 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2791 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2792 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2793 sc->jme_txcsr |= sc->jme_tx_dma_size;
2794 sc->jme_txcsr |= TXCSR_DMA_BURST;
2795 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2796
2797 /* Set Tx descriptor counter. */
2798 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT);
2799
2800 /* Set Tx ring address to the hardware. */
2801 paddr = JME_TX_RING_ADDR(sc, 0);
2802 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2803 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2804
2805 /* Configure TxMAC parameters. */
2806 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2807 reg |= TXMAC_THRESH_1_PKT;
2808 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2809 CSR_WRITE_4(sc, JME_TXMAC, reg);
2810
2811 /*
2812 * Configure Rx queue.
2813 * FIFO full threshold for transmitting Tx pause packet : 128T
2814 * FIFO threshold for processing next packet : 128QW
2815 * Rx queue 0 select
2816 * Max Rx DMA length : 128
2817 * Rx descriptor retry : 32
2818 * Rx descriptor retry time gap : 256ns
2819 * Don't receive runt/bad frame.
2820 */
2821 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2822 /*
2823 * Since Rx FIFO size is 4K bytes, receiving frames larger
2824 * than 4K bytes will suffer from Rx FIFO overruns. So
2825 * decrease FIFO threshold to reduce the FIFO overruns for
2826 * frames larger than 4000 bytes.
2827 * For best performance of standard MTU sized frames use
2828 * maximum allowable FIFO threshold, 128QW. Note these do
2829 * not hold on chip full mask version >=2. For these
2830 * controllers 64QW and 128QW are not valid value.
2831 */
2832 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2)
2833 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2834 else {
2835 if ((if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2836 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
2837 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2838 else
2839 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2840 }
2841 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2842 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2843 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2844 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2845
2846 /* Set Rx descriptor counter. */
2847 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT);
2848
2849 /* Set Rx ring address to the hardware. */
2850 paddr = JME_RX_RING_ADDR(sc, 0);
2851 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2852 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2853
2854 /* Clear receive filter. */
2855 CSR_WRITE_4(sc, JME_RXMAC, 0);
2856 /* Set up the receive filter. */
2857 jme_set_filter(sc);
2858 jme_set_vlan(sc);
2859
2860 /*
2861 * Disable all WOL bits as WOL can interfere normal Rx
2862 * operation. Also clear WOL detection status bits.
2863 */
2864 reg = CSR_READ_4(sc, JME_PMCS);
2865 reg &= ~PMCS_WOL_ENB_MASK;
2866 CSR_WRITE_4(sc, JME_PMCS, reg);
2867
2868 reg = CSR_READ_4(sc, JME_RXMAC);
2869 /*
2870 * Pad 10bytes right before received frame. This will greatly
2871 * help Rx performance on strict-alignment architectures as
2872 * it does not need to copy the frame to align the payload.
2873 */
2874 reg |= RXMAC_PAD_10BYTES;
2875 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2876 reg |= RXMAC_CSUM_ENB;
2877 CSR_WRITE_4(sc, JME_RXMAC, reg);
2878
2879 /* Configure general purpose reg0 */
2880 reg = CSR_READ_4(sc, JME_GPREG0);
2881 reg &= ~GPREG0_PCC_UNIT_MASK;
2882 /* Set PCC timer resolution to micro-seconds unit. */
2883 reg |= GPREG0_PCC_UNIT_US;
2884 /*
2885 * Disable all shadow register posting as we have to read
2886 * JME_INTR_STATUS register in jme_int_task. Also it seems
2887 * that it's hard to synchronize interrupt status between
2888 * hardware and software with shadow posting due to
2889 * requirements of bus_dmamap_sync(9).
2890 */
2891 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2892 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2893 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2894 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2895 /* Disable posting of DW0. */
2896 reg &= ~GPREG0_POST_DW0_ENB;
2897 /* Clear PME message. */
2898 reg &= ~GPREG0_PME_ENB;
2899 /* Set PHY address. */
2900 reg &= ~GPREG0_PHY_ADDR_MASK;
2901 reg |= sc->jme_phyaddr;
2902 CSR_WRITE_4(sc, JME_GPREG0, reg);
2903
2904 /* Configure Tx queue 0 packet completion coalescing. */
2905 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2906 PCCTX_COAL_TO_MASK;
2907 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2908 PCCTX_COAL_PKT_MASK;
2909 reg |= PCCTX_COAL_TXQ0;
2910 CSR_WRITE_4(sc, JME_PCCTX, reg);
2911
2912 /* Configure Rx queue 0 packet completion coalescing. */
2913 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2914 PCCRX_COAL_TO_MASK;
2915 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2916 PCCRX_COAL_PKT_MASK;
2917 CSR_WRITE_4(sc, JME_PCCRX0, reg);
2918
2919 /*
2920 * Configure PCD(Packet Completion Deferring). It seems PCD
2921 * generates an interrupt when the time interval between two
2922 * back-to-back incoming/outgoing packet is long enough for
2923 * it to reach its timer value 0. The arrival of new packets
2924 * after timer has started causes the PCD timer to restart.
2925 * Unfortunately, it's not clear how PCD is useful at this
2926 * moment, so just use the same of PCC parameters.
2927 */
2928 if ((sc->jme_flags & JME_FLAG_PCCPCD) != 0) {
2929 sc->jme_rx_pcd_to = sc->jme_rx_coal_to;
2930 if (sc->jme_rx_coal_to > PCDRX_TO_MAX)
2931 sc->jme_rx_pcd_to = PCDRX_TO_MAX;
2932 sc->jme_tx_pcd_to = sc->jme_tx_coal_to;
2933 if (sc->jme_tx_coal_to > PCDTX_TO_MAX)
2934 sc->jme_tx_pcd_to = PCDTX_TO_MAX;
2935 reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT;
2936 reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT;
2937 CSR_WRITE_4(sc, PCDRX_REG(0), reg);
2938 reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT;
2939 reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT;
2940 CSR_WRITE_4(sc, JME_PCDTX, reg);
2941 }
2942
2943 /* Configure shadow status block but don't enable posting. */
2944 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2945 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2946 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2947
2948 /* Disable Timer 1 and Timer 2. */
2949 CSR_WRITE_4(sc, JME_TIMER1, 0);
2950 CSR_WRITE_4(sc, JME_TIMER2, 0);
2951
2952 /* Configure retry transmit period, retry limit value. */
2953 CSR_WRITE_4(sc, JME_TXTRHD,
2954 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2955 TXTRHD_RT_PERIOD_MASK) |
2956 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2957 TXTRHD_RT_LIMIT_SHIFT));
2958
2959 /* Disable RSS. */
2960 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2961
2962 /* Initialize the interrupt mask. */
2963 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2964 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2965
2966 /*
2967 * Enabling Tx/Rx DMA engines and Rx queue processing is
2968 * done after detection of valid link in jme_link_task.
2969 */
2970
2971 sc->jme_flags &= ~JME_FLAG_LINK;
2972 /* Set the current media. */
2973 mii_mediachg(mii);
2974
2975 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2976
2977 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2978 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2979 }
2980
2981 static void
jme_stop(struct jme_softc * sc)2982 jme_stop(struct jme_softc *sc)
2983 {
2984 if_t ifp;
2985 struct jme_txdesc *txd;
2986 struct jme_rxdesc *rxd;
2987 int i;
2988
2989 JME_LOCK_ASSERT(sc);
2990 /*
2991 * Mark the interface down and cancel the watchdog timer.
2992 */
2993 ifp = sc->jme_ifp;
2994 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2995 sc->jme_flags &= ~JME_FLAG_LINK;
2996 callout_stop(&sc->jme_tick_ch);
2997 sc->jme_watchdog_timer = 0;
2998
2999 /*
3000 * Disable interrupts.
3001 */
3002 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3003 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
3004
3005 /* Disable updating shadow status block. */
3006 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
3007 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
3008
3009 /* Stop receiver, transmitter. */
3010 jme_stop_rx(sc);
3011 jme_stop_tx(sc);
3012
3013 /* Reclaim Rx/Tx buffers that have been completed. */
3014 jme_rxintr(sc, JME_RX_RING_CNT);
3015 if (sc->jme_cdata.jme_rxhead != NULL)
3016 m_freem(sc->jme_cdata.jme_rxhead);
3017 JME_RXCHAIN_RESET(sc);
3018 jme_txeof(sc);
3019 /*
3020 * Free RX and TX mbufs still in the queues.
3021 */
3022 for (i = 0; i < JME_RX_RING_CNT; i++) {
3023 rxd = &sc->jme_cdata.jme_rxdesc[i];
3024 if (rxd->rx_m != NULL) {
3025 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag,
3026 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3027 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
3028 rxd->rx_dmamap);
3029 m_freem(rxd->rx_m);
3030 rxd->rx_m = NULL;
3031 }
3032 }
3033 for (i = 0; i < JME_TX_RING_CNT; i++) {
3034 txd = &sc->jme_cdata.jme_txdesc[i];
3035 if (txd->tx_m != NULL) {
3036 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag,
3037 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3038 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
3039 txd->tx_dmamap);
3040 m_freem(txd->tx_m);
3041 txd->tx_m = NULL;
3042 txd->tx_ndesc = 0;
3043 }
3044 }
3045 jme_stats_update(sc);
3046 jme_stats_save(sc);
3047 }
3048
3049 static void
jme_stop_tx(struct jme_softc * sc)3050 jme_stop_tx(struct jme_softc *sc)
3051 {
3052 uint32_t reg;
3053 int i;
3054
3055 reg = CSR_READ_4(sc, JME_TXCSR);
3056 if ((reg & TXCSR_TX_ENB) == 0)
3057 return;
3058 reg &= ~TXCSR_TX_ENB;
3059 CSR_WRITE_4(sc, JME_TXCSR, reg);
3060 for (i = JME_TIMEOUT; i > 0; i--) {
3061 DELAY(1);
3062 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
3063 break;
3064 }
3065 if (i == 0)
3066 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
3067 }
3068
3069 static void
jme_stop_rx(struct jme_softc * sc)3070 jme_stop_rx(struct jme_softc *sc)
3071 {
3072 uint32_t reg;
3073 int i;
3074
3075 reg = CSR_READ_4(sc, JME_RXCSR);
3076 if ((reg & RXCSR_RX_ENB) == 0)
3077 return;
3078 reg &= ~RXCSR_RX_ENB;
3079 CSR_WRITE_4(sc, JME_RXCSR, reg);
3080 for (i = JME_TIMEOUT; i > 0; i--) {
3081 DELAY(1);
3082 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
3083 break;
3084 }
3085 if (i == 0)
3086 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
3087 }
3088
3089 static void
jme_init_tx_ring(struct jme_softc * sc)3090 jme_init_tx_ring(struct jme_softc *sc)
3091 {
3092 struct jme_ring_data *rd;
3093 struct jme_txdesc *txd;
3094 int i;
3095
3096 sc->jme_cdata.jme_tx_prod = 0;
3097 sc->jme_cdata.jme_tx_cons = 0;
3098 sc->jme_cdata.jme_tx_cnt = 0;
3099
3100 rd = &sc->jme_rdata;
3101 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE);
3102 for (i = 0; i < JME_TX_RING_CNT; i++) {
3103 txd = &sc->jme_cdata.jme_txdesc[i];
3104 txd->tx_m = NULL;
3105 txd->tx_desc = &rd->jme_tx_ring[i];
3106 txd->tx_ndesc = 0;
3107 }
3108
3109 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
3110 sc->jme_cdata.jme_tx_ring_map,
3111 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3112 }
3113
3114 static void
jme_init_ssb(struct jme_softc * sc)3115 jme_init_ssb(struct jme_softc *sc)
3116 {
3117 struct jme_ring_data *rd;
3118
3119 rd = &sc->jme_rdata;
3120 bzero(rd->jme_ssb_block, JME_SSB_SIZE);
3121 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
3122 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3123 }
3124
3125 static int
jme_init_rx_ring(struct jme_softc * sc)3126 jme_init_rx_ring(struct jme_softc *sc)
3127 {
3128 struct jme_ring_data *rd;
3129 struct jme_rxdesc *rxd;
3130 int i;
3131
3132 sc->jme_cdata.jme_rx_cons = 0;
3133 JME_RXCHAIN_RESET(sc);
3134 sc->jme_morework = 0;
3135
3136 rd = &sc->jme_rdata;
3137 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE);
3138 for (i = 0; i < JME_RX_RING_CNT; i++) {
3139 rxd = &sc->jme_cdata.jme_rxdesc[i];
3140 rxd->rx_m = NULL;
3141 rxd->rx_desc = &rd->jme_rx_ring[i];
3142 if (jme_newbuf(sc, rxd) != 0)
3143 return (ENOBUFS);
3144 }
3145
3146 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
3147 sc->jme_cdata.jme_rx_ring_map,
3148 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3149
3150 return (0);
3151 }
3152
3153 static int
jme_newbuf(struct jme_softc * sc,struct jme_rxdesc * rxd)3154 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd)
3155 {
3156 struct jme_desc *desc;
3157 struct mbuf *m;
3158 bus_dma_segment_t segs[1];
3159 bus_dmamap_t map;
3160 int nsegs;
3161
3162 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3163 if (m == NULL)
3164 return (ENOBUFS);
3165 /*
3166 * JMC250 has 64bit boundary alignment limitation so jme(4)
3167 * takes advantage of 10 bytes padding feature of hardware
3168 * in order not to copy entire frame to align IP header on
3169 * 32bit boundary.
3170 */
3171 m->m_len = m->m_pkthdr.len = MCLBYTES;
3172
3173 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag,
3174 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3175 m_freem(m);
3176 return (ENOBUFS);
3177 }
3178 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3179
3180 if (rxd->rx_m != NULL) {
3181 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3182 BUS_DMASYNC_POSTREAD);
3183 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
3184 }
3185 map = rxd->rx_dmamap;
3186 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
3187 sc->jme_cdata.jme_rx_sparemap = map;
3188 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3189 BUS_DMASYNC_PREREAD);
3190 rxd->rx_m = m;
3191
3192 desc = rxd->rx_desc;
3193 desc->buflen = htole32(segs[0].ds_len);
3194 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr));
3195 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr));
3196 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
3197
3198 return (0);
3199 }
3200
3201 static void
jme_set_vlan(struct jme_softc * sc)3202 jme_set_vlan(struct jme_softc *sc)
3203 {
3204 if_t ifp;
3205 uint32_t reg;
3206
3207 JME_LOCK_ASSERT(sc);
3208
3209 ifp = sc->jme_ifp;
3210 reg = CSR_READ_4(sc, JME_RXMAC);
3211 reg &= ~RXMAC_VLAN_ENB;
3212 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
3213 reg |= RXMAC_VLAN_ENB;
3214 CSR_WRITE_4(sc, JME_RXMAC, reg);
3215 }
3216
3217 static u_int
jme_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)3218 jme_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
3219 {
3220 uint32_t crc, *mchash = arg;
3221
3222 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
3223
3224 /* Just want the 6 least significant bits. */
3225 crc &= 0x3f;
3226
3227 /* Set the corresponding bit in the hash table. */
3228 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3229
3230 return (1);
3231 }
3232
3233 static void
jme_set_filter(struct jme_softc * sc)3234 jme_set_filter(struct jme_softc *sc)
3235 {
3236 if_t ifp;
3237 uint32_t mchash[2];
3238 uint32_t rxcfg;
3239
3240 JME_LOCK_ASSERT(sc);
3241
3242 ifp = sc->jme_ifp;
3243
3244 rxcfg = CSR_READ_4(sc, JME_RXMAC);
3245 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3246 RXMAC_ALLMULTI);
3247 /* Always accept frames destined to our station address. */
3248 rxcfg |= RXMAC_UNICAST;
3249 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
3250 rxcfg |= RXMAC_BROADCAST;
3251 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3252 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
3253 rxcfg |= RXMAC_PROMISC;
3254 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
3255 rxcfg |= RXMAC_ALLMULTI;
3256 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3257 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3258 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3259 return;
3260 }
3261
3262 /*
3263 * Set up the multicast address filter by passing all multicast
3264 * addresses through a CRC generator, and then using the low-order
3265 * 6 bits as an index into the 64 bit multicast hash table. The
3266 * high order bits select the register, while the rest of the bits
3267 * select the bit within the register.
3268 */
3269 rxcfg |= RXMAC_MULTICAST;
3270 bzero(mchash, sizeof(mchash));
3271 if_foreach_llmaddr(ifp, jme_hash_maddr, &mchash);
3272
3273 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3274 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3275 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3276 }
3277
3278 static void
jme_stats_clear(struct jme_softc * sc)3279 jme_stats_clear(struct jme_softc *sc)
3280 {
3281
3282 JME_LOCK_ASSERT(sc);
3283
3284 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3285 return;
3286
3287 /* Disable and clear counters. */
3288 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3289 /* Activate hw counters. */
3290 CSR_WRITE_4(sc, JME_STATCSR, 0);
3291 CSR_READ_4(sc, JME_STATCSR);
3292 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats));
3293 }
3294
3295 static void
jme_stats_save(struct jme_softc * sc)3296 jme_stats_save(struct jme_softc *sc)
3297 {
3298
3299 JME_LOCK_ASSERT(sc);
3300
3301 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3302 return;
3303 /* Save current counters. */
3304 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats));
3305 /* Disable and clear counters. */
3306 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3307 }
3308
3309 static void
jme_stats_update(struct jme_softc * sc)3310 jme_stats_update(struct jme_softc *sc)
3311 {
3312 struct jme_hw_stats *stat, *ostat;
3313 uint32_t reg;
3314
3315 JME_LOCK_ASSERT(sc);
3316
3317 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3318 return;
3319 stat = &sc->jme_stats;
3320 ostat = &sc->jme_ostats;
3321 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);
3322 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);
3323 reg = CSR_READ_4(sc, JME_STAT_CRCMII);
3324 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >>
3325 STAT_RX_CRC_ERR_SHIFT;
3326 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >>
3327 STAT_RX_MII_ERR_SHIFT;
3328 reg = CSR_READ_4(sc, JME_STAT_RXERR);
3329 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >>
3330 STAT_RXERR_OFLOW_SHIFT;
3331 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >>
3332 STAT_RXERR_MPTY_SHIFT;
3333 reg = CSR_READ_4(sc, JME_STAT_FAIL);
3334 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT;
3335 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT;
3336
3337 /* Account for previous counters. */
3338 stat->rx_good_frames += ostat->rx_good_frames;
3339 stat->rx_crc_errs += ostat->rx_crc_errs;
3340 stat->rx_mii_errs += ostat->rx_mii_errs;
3341 stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
3342 stat->rx_desc_empty += ostat->rx_desc_empty;
3343 stat->rx_bad_frames += ostat->rx_bad_frames;
3344 stat->tx_good_frames += ostat->tx_good_frames;
3345 stat->tx_bad_frames += ostat->tx_bad_frames;
3346 }
3347
3348 static void
jme_phy_down(struct jme_softc * sc)3349 jme_phy_down(struct jme_softc *sc)
3350 {
3351 uint32_t reg;
3352
3353 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN);
3354 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) {
3355 reg = CSR_READ_4(sc, JME_PHYPOWDN);
3356 reg |= 0x0000000F;
3357 CSR_WRITE_4(sc, JME_PHYPOWDN, reg);
3358 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
3359 reg &= ~PE1_GIGA_PDOWN_MASK;
3360 reg |= PE1_GIGA_PDOWN_D3;
3361 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
3362 }
3363 }
3364
3365 static void
jme_phy_up(struct jme_softc * sc)3366 jme_phy_up(struct jme_softc *sc)
3367 {
3368 uint32_t reg;
3369 uint16_t bmcr;
3370
3371 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR);
3372 bmcr &= ~BMCR_PDOWN;
3373 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr);
3374 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) {
3375 reg = CSR_READ_4(sc, JME_PHYPOWDN);
3376 reg &= ~0x0000000F;
3377 CSR_WRITE_4(sc, JME_PHYPOWDN, reg);
3378 reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4);
3379 reg &= ~PE1_GIGA_PDOWN_MASK;
3380 reg |= PE1_GIGA_PDOWN_DIS;
3381 pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4);
3382 }
3383 }
3384
3385 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3386 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3387 {
3388 int error, value;
3389
3390 if (arg1 == NULL)
3391 return (EINVAL);
3392 value = *(int *)arg1;
3393 error = sysctl_handle_int(oidp, &value, 0, req);
3394 if (error || req->newptr == NULL)
3395 return (error);
3396 if (value < low || value > high)
3397 return (EINVAL);
3398 *(int *)arg1 = value;
3399
3400 return (0);
3401 }
3402
3403 static int
sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS)3404 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS)
3405 {
3406 return (sysctl_int_range(oidp, arg1, arg2, req,
3407 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX));
3408 }
3409
3410 static int
sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS)3411 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3412 {
3413 return (sysctl_int_range(oidp, arg1, arg2, req,
3414 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX));
3415 }
3416
3417 static int
sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS)3418 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS)
3419 {
3420 return (sysctl_int_range(oidp, arg1, arg2, req,
3421 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX));
3422 }
3423
3424 static int
sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS)3425 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3426 {
3427 return (sysctl_int_range(oidp, arg1, arg2, req,
3428 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX));
3429 }
3430
3431 static int
sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS)3432 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS)
3433 {
3434 return (sysctl_int_range(oidp, arg1, arg2, req,
3435 JME_PROC_MIN, JME_PROC_MAX));
3436 }
3437