1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_82599.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
47
48 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
50 bool autoneg_wait_to_complete);
51 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
53 u16 offset, u16 *data);
54 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
57 u8 dev_addr, u8 *data);
58 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
59 u8 dev_addr, u8 data);
60
ixgbe_init_mac_link_ops_82599(struct ixgbe_hw * hw)61 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
62 {
63 struct ixgbe_mac_info *mac = &hw->mac;
64
65 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
66
67 /*
68 * enable the laser control functions for SFP+ fiber
69 * and MNG not enabled
70 */
71 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
72 !ixgbe_mng_enabled(hw)) {
73 mac->ops.disable_tx_laser =
74 ixgbe_disable_tx_laser_multispeed_fiber;
75 mac->ops.enable_tx_laser =
76 ixgbe_enable_tx_laser_multispeed_fiber;
77 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;
78
79 } else {
80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
82 mac->ops.flap_tx_laser = NULL;
83 }
84
85 if (hw->phy.multispeed_fiber) {
86 /* Set up dual speed SFP+ support */
87 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
88 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
89 mac->ops.set_rate_select_speed =
90 ixgbe_set_hard_rate_select_speed;
91 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed)
92 mac->ops.set_rate_select_speed =
93 ixgbe_set_soft_rate_select_speed;
94 } else {
95 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
96 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
97 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
98 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
99 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;
100 } else {
101 mac->ops.setup_link = ixgbe_setup_mac_link_82599;
102 }
103 }
104 }
105
106 /**
107 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
108 * @hw: pointer to hardware structure
109 *
110 * Initialize any function pointers that were not able to be
111 * set during init_shared_code because the PHY/SFP type was
112 * not known. Perform the SFP init if necessary.
113 *
114 **/
ixgbe_init_phy_ops_82599(struct ixgbe_hw * hw)115 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
116 {
117 struct ixgbe_mac_info *mac = &hw->mac;
118 struct ixgbe_phy_info *phy = &hw->phy;
119 s32 ret_val = IXGBE_SUCCESS;
120 u32 esdp;
121
122 DEBUGFUNC("ixgbe_init_phy_ops_82599");
123
124 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
125 /* Store flag indicating I2C bus access control unit. */
126 hw->phy.qsfp_shared_i2c_bus = true;
127
128 /* Initialize access to QSFP+ I2C bus */
129 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
130 esdp |= IXGBE_ESDP_SDP0_DIR;
131 esdp &= ~IXGBE_ESDP_SDP1_DIR;
132 esdp &= ~IXGBE_ESDP_SDP0;
133 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
134 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
135 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
136 IXGBE_WRITE_FLUSH(hw);
137
138 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;
139 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;
140 }
141 /* Identify the PHY or SFP module */
142 ret_val = phy->ops.identify(hw);
143 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
144 goto init_phy_ops_out;
145
146 /* Setup function pointers based on detected SFP module and speeds */
147 ixgbe_init_mac_link_ops_82599(hw);
148 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
149 hw->phy.ops.reset = NULL;
150
151 /* If copper media, overwrite with copper function pointers */
152 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
153 mac->ops.setup_link = ixgbe_setup_copper_link_82599;
154 mac->ops.get_link_capabilities =
155 ixgbe_get_copper_link_capabilities_generic;
156 }
157
158 /* Set necessary function pointers based on PHY type */
159 switch (hw->phy.type) {
160 case ixgbe_phy_tn:
161 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
162 phy->ops.check_link = ixgbe_check_phy_link_tnx;
163 phy->ops.get_firmware_version =
164 ixgbe_get_phy_firmware_version_tnx;
165 break;
166 default:
167 break;
168 }
169 init_phy_ops_out:
170 return ret_val;
171 }
172
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw * hw)173 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
174 {
175 s32 ret_val = IXGBE_SUCCESS;
176 u16 list_offset, data_offset, data_value;
177
178 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
179
180 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
181 ixgbe_init_mac_link_ops_82599(hw);
182
183 hw->phy.ops.reset = NULL;
184
185 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
186 &data_offset);
187 if (ret_val != IXGBE_SUCCESS)
188 goto setup_sfp_out;
189
190 /* PHY config will finish before releasing the semaphore */
191 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
192 IXGBE_GSSR_MAC_CSR_SM);
193 if (ret_val != IXGBE_SUCCESS) {
194 ret_val = IXGBE_ERR_SWFW_SYNC;
195 goto setup_sfp_out;
196 }
197
198 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
199 goto setup_sfp_err;
200 while (data_value != 0xffff) {
201 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
202 IXGBE_WRITE_FLUSH(hw);
203 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
204 goto setup_sfp_err;
205 }
206
207 /* Release the semaphore */
208 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
209 /* Delay obtaining semaphore again to allow FW access
210 * prot_autoc_write uses the semaphore too.
211 */
212 msec_delay(hw->eeprom.semaphore_delay);
213
214 /* Restart DSP and set SFI mode */
215 ret_val = hw->mac.ops.prot_autoc_write(hw,
216 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
217 false);
218
219 if (ret_val) {
220 DEBUGOUT("sfp module setup not complete\n");
221 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
222 goto setup_sfp_out;
223 }
224
225 }
226
227 setup_sfp_out:
228 return ret_val;
229
230 setup_sfp_err:
231 /* Release the semaphore */
232 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
233 /* Delay obtaining semaphore again to allow FW access */
234 msec_delay(hw->eeprom.semaphore_delay);
235 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
236 "eeprom read at offset %d failed", data_offset);
237 return IXGBE_ERR_PHY;
238 }
239
240 /**
241 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
242 * @hw: pointer to hardware structure
243 * @locked: Return the if we locked for this read.
244 * @reg_val: Value we read from AUTOC
245 *
246 * For this part (82599) we need to wrap read-modify-writes with a possible
247 * FW/SW lock. It is assumed this lock will be freed with the next
248 * prot_autoc_write_82599().
249 */
prot_autoc_read_82599(struct ixgbe_hw * hw,bool * locked,u32 * reg_val)250 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
251 {
252 s32 ret_val;
253
254 *locked = false;
255 /* If LESM is on then we need to hold the SW/FW semaphore. */
256 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
257 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
258 IXGBE_GSSR_MAC_CSR_SM);
259 if (ret_val != IXGBE_SUCCESS)
260 return IXGBE_ERR_SWFW_SYNC;
261
262 *locked = true;
263 }
264
265 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
266 return IXGBE_SUCCESS;
267 }
268
269 /**
270 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
271 * @hw: pointer to hardware structure
272 * @autoc: value to write to AUTOC
273 * @locked: bool to indicate whether the SW/FW lock was already taken by
274 * previous proc_autoc_read_82599.
275 *
276 * This part (82599) may need to hold the SW/FW lock around all writes to
277 * AUTOC. Likewise after a write we need to do a pipeline reset.
278 */
prot_autoc_write_82599(struct ixgbe_hw * hw,u32 autoc,bool locked)279 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
280 {
281 s32 ret_val = IXGBE_SUCCESS;
282
283 /* Blocked by MNG FW so bail */
284 if (ixgbe_check_reset_blocked(hw))
285 goto out;
286
287 /* We only need to get the lock if:
288 * - We didn't do it already (in the read part of a read-modify-write)
289 * - LESM is enabled.
290 */
291 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
292 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
293 IXGBE_GSSR_MAC_CSR_SM);
294 if (ret_val != IXGBE_SUCCESS)
295 return IXGBE_ERR_SWFW_SYNC;
296
297 locked = true;
298 }
299
300 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
301 ret_val = ixgbe_reset_pipeline_82599(hw);
302
303 out:
304 /* Free the SW/FW semaphore as we either grabbed it here or
305 * already had it when this function was called.
306 */
307 if (locked)
308 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
309
310 return ret_val;
311 }
312
313 /**
314 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
315 * @hw: pointer to hardware structure
316 *
317 * Initialize the function pointers and assign the MAC type for 82599.
318 * Does not touch the hardware.
319 **/
320
ixgbe_init_ops_82599(struct ixgbe_hw * hw)321 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
322 {
323 struct ixgbe_mac_info *mac = &hw->mac;
324 struct ixgbe_phy_info *phy = &hw->phy;
325 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
326 s32 ret_val;
327 u16 i;
328
329 DEBUGFUNC("ixgbe_init_ops_82599");
330
331 ixgbe_init_phy_ops_generic(hw);
332 ret_val = ixgbe_init_ops_generic(hw);
333
334 /* PHY */
335 phy->ops.identify = ixgbe_identify_phy_82599;
336 phy->ops.init = ixgbe_init_phy_ops_82599;
337
338 /* MAC */
339 mac->ops.reset_hw = ixgbe_reset_hw_82599;
340 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
341 mac->ops.get_media_type = ixgbe_get_media_type_82599;
342 mac->ops.get_supported_physical_layer =
343 ixgbe_get_supported_physical_layer_82599;
344 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
345 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
346 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;
347 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;
348 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;
349 mac->ops.start_hw = ixgbe_start_hw_82599;
350 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
351 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
352 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
353 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
354 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
355 mac->ops.prot_autoc_read = prot_autoc_read_82599;
356 mac->ops.prot_autoc_write = prot_autoc_write_82599;
357
358 /* RAR, Multicast, VLAN */
359 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
360 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
361 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
362 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
363 mac->rar_highwater = 1;
364 mac->ops.set_vfta = ixgbe_set_vfta_generic;
365 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
366 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
367 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
368 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;
369 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
370 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
371
372 /* Link */
373 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;
374 mac->ops.check_link = ixgbe_check_mac_link_generic;
375 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
376 ixgbe_init_mac_link_ops_82599(hw);
377
378 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
379 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
380 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
381 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
382 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
383 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
384 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
385
386 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
387 & IXGBE_FWSM_MODE_MASK);
388
389 for (i = 0; i < 64; i++)
390 hw->mbx.ops[i].init_params = ixgbe_init_mbx_params_pf;
391
392 /* EEPROM */
393 eeprom->ops.read = ixgbe_read_eeprom_82599;
394 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
395
396 /* Manageability interface */
397 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
398
399 mac->ops.get_thermal_sensor_data =
400 ixgbe_get_thermal_sensor_data_generic;
401 mac->ops.init_thermal_sensor_thresh =
402 ixgbe_init_thermal_sensor_thresh_generic;
403
404 mac->ops.bypass_rw = ixgbe_bypass_rw_generic;
405 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic;
406 mac->ops.bypass_set = ixgbe_bypass_set_generic;
407 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic;
408
409 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
410
411 return ret_val;
412 }
413
414 /**
415 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
416 * @hw: pointer to hardware structure
417 * @speed: pointer to link speed
418 * @autoneg: true when autoneg or autotry is enabled
419 *
420 * Determines the link capabilities by reading the AUTOC register.
421 **/
ixgbe_get_link_capabilities_82599(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)422 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
423 ixgbe_link_speed *speed,
424 bool *autoneg)
425 {
426 s32 status = IXGBE_SUCCESS;
427 u32 autoc = 0;
428
429 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
430
431
432 /* Check if 1G SFP module. */
433 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
434 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
435 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
436 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
437 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
438 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
439 *speed = IXGBE_LINK_SPEED_1GB_FULL;
440 *autoneg = true;
441 goto out;
442 }
443
444 if (hw->phy.sfp_type == ixgbe_sfp_type_da_cu_core0 ||
445 hw->phy.sfp_type == ixgbe_sfp_type_da_cu_core1) {
446 *speed = IXGBE_LINK_SPEED_10GB_FULL;
447 *autoneg = true;
448
449 if (hw->phy.multispeed_fiber)
450 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
451
452 goto out;
453 }
454
455 /*
456 * Determine link capabilities based on the stored value of AUTOC,
457 * which represents EEPROM defaults. If AUTOC value has not
458 * been stored, use the current register values.
459 */
460 if (hw->mac.orig_link_settings_stored)
461 autoc = hw->mac.orig_autoc;
462 else
463 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
464
465 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
466 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
467 *speed = IXGBE_LINK_SPEED_1GB_FULL;
468 *autoneg = false;
469 break;
470
471 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
472 *speed = IXGBE_LINK_SPEED_10GB_FULL;
473 *autoneg = false;
474 break;
475
476 case IXGBE_AUTOC_LMS_1G_AN:
477 *speed = IXGBE_LINK_SPEED_1GB_FULL;
478 *autoneg = true;
479 break;
480
481 case IXGBE_AUTOC_LMS_10G_SERIAL:
482 *speed = IXGBE_LINK_SPEED_10GB_FULL;
483 *autoneg = false;
484 break;
485
486 case IXGBE_AUTOC_LMS_KX4_KX_KR:
487 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
488 *speed = IXGBE_LINK_SPEED_UNKNOWN;
489 if (autoc & IXGBE_AUTOC_KR_SUPP)
490 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
491 if (autoc & IXGBE_AUTOC_KX4_SUPP)
492 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
493 if (autoc & IXGBE_AUTOC_KX_SUPP)
494 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
495 *autoneg = true;
496 break;
497
498 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
499 *speed = IXGBE_LINK_SPEED_100_FULL;
500 if (autoc & IXGBE_AUTOC_KR_SUPP)
501 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
502 if (autoc & IXGBE_AUTOC_KX4_SUPP)
503 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
504 if (autoc & IXGBE_AUTOC_KX_SUPP)
505 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
506 *autoneg = true;
507 break;
508
509 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
510 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
511 *autoneg = false;
512 break;
513
514 default:
515 status = IXGBE_ERR_LINK_SETUP;
516 goto out;
517 break;
518 }
519
520 if (hw->phy.multispeed_fiber) {
521 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
522 IXGBE_LINK_SPEED_1GB_FULL;
523
524 /* QSFP must not enable full auto-negotiation
525 * Limited autoneg is enabled at 1G
526 */
527 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
528 *autoneg = false;
529 else
530 *autoneg = true;
531 }
532
533 out:
534 return status;
535 }
536
537 /**
538 * ixgbe_get_media_type_82599 - Get media type
539 * @hw: pointer to hardware structure
540 *
541 * Returns the media type (fiber, copper, backplane)
542 **/
ixgbe_get_media_type_82599(struct ixgbe_hw * hw)543 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
544 {
545 enum ixgbe_media_type media_type;
546
547 DEBUGFUNC("ixgbe_get_media_type_82599");
548
549 /* Detect if there is a copper PHY attached. */
550 switch (hw->phy.type) {
551 case ixgbe_phy_cu_unknown:
552 case ixgbe_phy_tn:
553 media_type = ixgbe_media_type_copper;
554 goto out;
555 default:
556 break;
557 }
558
559 switch (hw->device_id) {
560 case IXGBE_DEV_ID_82599_KX4:
561 case IXGBE_DEV_ID_82599_KX4_MEZZ:
562 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
563 case IXGBE_DEV_ID_82599_KR:
564 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
565 case IXGBE_DEV_ID_82599_XAUI_LOM:
566 /* Default device ID is mezzanine card KX/KX4 */
567 media_type = ixgbe_media_type_backplane;
568 break;
569 case IXGBE_DEV_ID_82599_SFP:
570 case IXGBE_DEV_ID_82599_SFP_FCOE:
571 case IXGBE_DEV_ID_82599_SFP_EM:
572 case IXGBE_DEV_ID_82599_SFP_SF2:
573 case IXGBE_DEV_ID_82599_SFP_SF_QP:
574 case IXGBE_DEV_ID_82599EN_SFP:
575 media_type = ixgbe_media_type_fiber;
576 break;
577 case IXGBE_DEV_ID_82599_CX4:
578 media_type = ixgbe_media_type_cx4;
579 break;
580 case IXGBE_DEV_ID_82599_T3_LOM:
581 media_type = ixgbe_media_type_copper;
582 break;
583 case IXGBE_DEV_ID_82599_LS:
584 media_type = ixgbe_media_type_fiber_lco;
585 break;
586 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
587 media_type = ixgbe_media_type_fiber_qsfp;
588 break;
589 case IXGBE_DEV_ID_82599_BYPASS:
590 media_type = ixgbe_media_type_fiber_fixed;
591 hw->phy.multispeed_fiber = true;
592 break;
593 default:
594 media_type = ixgbe_media_type_unknown;
595 break;
596 }
597 out:
598 return media_type;
599 }
600
601 /**
602 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
603 * @hw: pointer to hardware structure
604 *
605 * Disables link during D3 power down sequence.
606 *
607 **/
ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw * hw)608 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
609 {
610 u32 autoc2_reg;
611 u16 ee_ctrl_2 = 0;
612
613 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
614 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
615
616 if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
617 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
618 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
619 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
620 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
621 }
622 }
623
624 /**
625 * ixgbe_start_mac_link_82599 - Setup MAC link settings
626 * @hw: pointer to hardware structure
627 * @autoneg_wait_to_complete: true when waiting for completion is needed
628 *
629 * Configures link settings based on values in the ixgbe_hw struct.
630 * Restarts the link. Performs autonegotiation if needed.
631 **/
ixgbe_start_mac_link_82599(struct ixgbe_hw * hw,bool autoneg_wait_to_complete)632 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
633 bool autoneg_wait_to_complete)
634 {
635 u32 autoc_reg;
636 u32 links_reg;
637 u32 i;
638 s32 status = IXGBE_SUCCESS;
639 bool got_lock = false;
640
641 DEBUGFUNC("ixgbe_start_mac_link_82599");
642
643
644 /* reset_pipeline requires us to hold this lock as it writes to
645 * AUTOC.
646 */
647 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
648 status = hw->mac.ops.acquire_swfw_sync(hw,
649 IXGBE_GSSR_MAC_CSR_SM);
650 if (status != IXGBE_SUCCESS)
651 goto out;
652
653 got_lock = true;
654 }
655
656 /* Restart link */
657 ixgbe_reset_pipeline_82599(hw);
658
659 if (got_lock)
660 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
661
662 /* Only poll for autoneg to complete if specified to do so */
663 if (autoneg_wait_to_complete) {
664 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
665 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
666 IXGBE_AUTOC_LMS_KX4_KX_KR ||
667 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
668 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
669 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
670 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
671 links_reg = 0; /* Just in case Autoneg time = 0 */
672 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
673 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
674 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
675 break;
676 msec_delay(100);
677 }
678 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
679 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
680 DEBUGOUT("Autoneg did not complete.\n");
681 }
682 }
683 }
684
685 /* Add delay to filter out noises during initial link setup */
686 msec_delay(50);
687
688 out:
689 return status;
690 }
691
692 /**
693 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
694 * @hw: pointer to hardware structure
695 *
696 * The base drivers may require better control over SFP+ module
697 * PHY states. This includes selectively shutting down the Tx
698 * laser on the PHY, effectively halting physical link.
699 **/
ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw * hw)700 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
701 {
702 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
703
704 /* Blocked by MNG FW so bail */
705 if (ixgbe_check_reset_blocked(hw))
706 return;
707
708 /* Disable Tx laser; allow 100us to go dark per spec */
709 esdp_reg |= IXGBE_ESDP_SDP3;
710 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
711 IXGBE_WRITE_FLUSH(hw);
712 usec_delay(100);
713 }
714
715 /**
716 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
717 * @hw: pointer to hardware structure
718 *
719 * The base drivers may require better control over SFP+ module
720 * PHY states. This includes selectively turning on the Tx
721 * laser on the PHY, effectively starting physical link.
722 **/
ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw * hw)723 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
724 {
725 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
726
727 /* Enable Tx laser; allow 100ms to light up */
728 esdp_reg &= ~IXGBE_ESDP_SDP3;
729 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
730 IXGBE_WRITE_FLUSH(hw);
731 msec_delay(100);
732 }
733
734 /**
735 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
736 * @hw: pointer to hardware structure
737 *
738 * When the driver changes the link speeds that it can support,
739 * it sets autotry_restart to true to indicate that we need to
740 * initiate a new autotry session with the link partner. To do
741 * so, we set the speed then disable and re-enable the Tx laser, to
742 * alert the link partner that it also needs to restart autotry on its
743 * end. This is consistent with true clause 37 autoneg, which also
744 * involves a loss of signal.
745 **/
ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw * hw)746 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
747 {
748 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
749
750 /* Blocked by MNG FW so bail */
751 if (ixgbe_check_reset_blocked(hw))
752 return;
753
754 if (hw->mac.autotry_restart) {
755 ixgbe_disable_tx_laser_multispeed_fiber(hw);
756 ixgbe_enable_tx_laser_multispeed_fiber(hw);
757 hw->mac.autotry_restart = false;
758 }
759 }
760
761 /**
762 * ixgbe_set_hard_rate_select_speed - Set module link speed
763 * @hw: pointer to hardware structure
764 * @speed: link speed to set
765 *
766 * Set module link speed via RS0/RS1 rate select pins.
767 */
ixgbe_set_hard_rate_select_speed(struct ixgbe_hw * hw,ixgbe_link_speed speed)768 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
769 ixgbe_link_speed speed)
770 {
771 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
772
773 switch (speed) {
774 case IXGBE_LINK_SPEED_10GB_FULL:
775 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
776 break;
777 case IXGBE_LINK_SPEED_1GB_FULL:
778 esdp_reg &= ~IXGBE_ESDP_SDP5;
779 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
780 break;
781 default:
782 DEBUGOUT("Invalid fixed module speed\n");
783 return;
784 }
785
786 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
787 IXGBE_WRITE_FLUSH(hw);
788 }
789
790 /**
791 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
792 * @hw: pointer to hardware structure
793 * @speed: new link speed
794 * @autoneg_wait_to_complete: true when waiting for completion is needed
795 *
796 * Implements the Intel SmartSpeed algorithm.
797 **/
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)798 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
799 ixgbe_link_speed speed,
800 bool autoneg_wait_to_complete)
801 {
802 s32 status = IXGBE_SUCCESS;
803 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
804 s32 i, j;
805 bool link_up = false;
806 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
807
808 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
809
810 /* Set autoneg_advertised value based on input link speed */
811 hw->phy.autoneg_advertised = 0;
812
813 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
814 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
815
816 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
817 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
818
819 if (speed & IXGBE_LINK_SPEED_100_FULL)
820 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
821
822 /*
823 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
824 * autoneg advertisement if link is unable to be established at the
825 * highest negotiated rate. This can sometimes happen due to integrity
826 * issues with the physical media connection.
827 */
828
829 /* First, try to get link with full advertisement */
830 hw->phy.smart_speed_active = false;
831 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
832 status = ixgbe_setup_mac_link_82599(hw, speed,
833 autoneg_wait_to_complete);
834 if (status != IXGBE_SUCCESS)
835 goto out;
836
837 /*
838 * Wait for the controller to acquire link. Per IEEE 802.3ap,
839 * Section 73.10.2, we may have to wait up to 500ms if KR is
840 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
841 * Table 9 in the AN MAS.
842 */
843 for (i = 0; i < 5; i++) {
844 msec_delay(100);
845
846 /* If we have link, just jump out */
847 status = ixgbe_check_link(hw, &link_speed, &link_up,
848 false);
849 if (status != IXGBE_SUCCESS)
850 goto out;
851
852 if (link_up)
853 goto out;
854 }
855 }
856
857 /*
858 * We didn't get link. If we advertised KR plus one of KX4/KX
859 * (or BX4/BX), then disable KR and try again.
860 */
861 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
862 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
863 goto out;
864
865 /* Turn SmartSpeed on to disable KR support */
866 hw->phy.smart_speed_active = true;
867 status = ixgbe_setup_mac_link_82599(hw, speed,
868 autoneg_wait_to_complete);
869 if (status != IXGBE_SUCCESS)
870 goto out;
871
872 /*
873 * Wait for the controller to acquire link. 600ms will allow for
874 * the AN link_fail_inhibit_timer as well for multiple cycles of
875 * parallel detect, both 10g and 1g. This allows for the maximum
876 * connect attempts as defined in the AN MAS table 73-7.
877 */
878 for (i = 0; i < 6; i++) {
879 msec_delay(100);
880
881 /* If we have link, just jump out */
882 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
883 if (status != IXGBE_SUCCESS)
884 goto out;
885
886 if (link_up)
887 goto out;
888 }
889
890 /* We didn't get link. Turn SmartSpeed back off. */
891 hw->phy.smart_speed_active = false;
892 status = ixgbe_setup_mac_link_82599(hw, speed,
893 autoneg_wait_to_complete);
894
895 out:
896 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
897 DEBUGOUT("Smartspeed has downgraded the link speed "
898 "from the maximum advertised\n");
899 return status;
900 }
901
902 /**
903 * ixgbe_setup_mac_link_82599 - Set MAC link speed
904 * @hw: pointer to hardware structure
905 * @speed: new link speed
906 * @autoneg_wait_to_complete: true when waiting for completion is needed
907 *
908 * Set the link speed in the AUTOC register and restarts link.
909 **/
ixgbe_setup_mac_link_82599(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)910 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
911 ixgbe_link_speed speed,
912 bool autoneg_wait_to_complete)
913 {
914 bool autoneg = false;
915 s32 status = IXGBE_SUCCESS;
916 u32 pma_pmd_1g, link_mode;
917 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
918 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
919 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
920 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
921 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
922 u32 links_reg;
923 u32 i;
924 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
925
926 DEBUGFUNC("ixgbe_setup_mac_link_82599");
927
928 /* Check to see if speed passed in is supported. */
929 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
930 if (status)
931 goto out;
932
933 speed &= link_capabilities;
934
935 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
936 status = IXGBE_ERR_LINK_SETUP;
937 goto out;
938 }
939
940 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
941 if (hw->mac.orig_link_settings_stored)
942 orig_autoc = hw->mac.orig_autoc;
943 else
944 orig_autoc = autoc;
945
946 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
947 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
948
949 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
950 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
951 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
952 /* Set KX4/KX/KR support according to speed requested */
953 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
954 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
955 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
956 autoc |= IXGBE_AUTOC_KX4_SUPP;
957 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
958 (hw->phy.smart_speed_active == false))
959 autoc |= IXGBE_AUTOC_KR_SUPP;
960 }
961 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
962 autoc |= IXGBE_AUTOC_KX_SUPP;
963 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
964 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
965 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
966 /* Switch from 1G SFI to 10G SFI if requested */
967 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
968 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
969 autoc &= ~IXGBE_AUTOC_LMS_MASK;
970 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
971 }
972 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
973 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
974 /* Switch from 10G SFI to 1G SFI if requested */
975 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
976 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
977 autoc &= ~IXGBE_AUTOC_LMS_MASK;
978 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
979 autoc |= IXGBE_AUTOC_LMS_1G_AN;
980 else
981 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
982 }
983 }
984
985 if (autoc != current_autoc) {
986 /* Restart link */
987 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
988 if (status != IXGBE_SUCCESS)
989 goto out;
990
991 /* Only poll for autoneg to complete if specified to do so */
992 if (autoneg_wait_to_complete) {
993 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
994 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
995 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
996 links_reg = 0; /*Just in case Autoneg time=0*/
997 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
998 links_reg =
999 IXGBE_READ_REG(hw, IXGBE_LINKS);
1000 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1001 break;
1002 msec_delay(100);
1003 }
1004 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1005 status =
1006 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1007 DEBUGOUT("Autoneg did not complete.\n");
1008 }
1009 }
1010 }
1011
1012 /* Add delay to filter out noises during initial link setup */
1013 msec_delay(50);
1014 }
1015
1016 out:
1017 return status;
1018 }
1019
1020 /**
1021 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1022 * @hw: pointer to hardware structure
1023 * @speed: new link speed
1024 * @autoneg_wait_to_complete: true if waiting is needed to complete
1025 *
1026 * Restarts link on PHY and MAC based on settings passed in.
1027 **/
ixgbe_setup_copper_link_82599(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)1028 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1029 ixgbe_link_speed speed,
1030 bool autoneg_wait_to_complete)
1031 {
1032 s32 status;
1033
1034 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1035
1036 /* Setup the PHY according to input speed */
1037 status = hw->phy.ops.setup_link_speed(hw, speed,
1038 autoneg_wait_to_complete);
1039 /* Set up MAC */
1040 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1041
1042 return status;
1043 }
1044
1045 /**
1046 * ixgbe_reset_hw_82599 - Perform hardware reset
1047 * @hw: pointer to hardware structure
1048 *
1049 * Resets the hardware by resetting the transmit and receive units, masks
1050 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1051 * reset.
1052 **/
ixgbe_reset_hw_82599(struct ixgbe_hw * hw)1053 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1054 {
1055 ixgbe_link_speed link_speed;
1056 s32 status;
1057 u32 ctrl = 0;
1058 u32 i, autoc, autoc2;
1059 u32 curr_lms;
1060 bool link_up = false;
1061
1062 DEBUGFUNC("ixgbe_reset_hw_82599");
1063
1064 /* Call adapter stop to disable tx/rx and clear interrupts */
1065 status = hw->mac.ops.stop_adapter(hw);
1066 if (status != IXGBE_SUCCESS)
1067 goto reset_hw_out;
1068
1069 /* flush pending Tx transactions */
1070 ixgbe_clear_tx_pending(hw);
1071
1072 /* PHY ops must be identified and initialized prior to reset */
1073
1074 /* Identify PHY and related function pointers */
1075 status = hw->phy.ops.init(hw);
1076
1077 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1078 goto reset_hw_out;
1079
1080 /* Setup SFP module if there is one present. */
1081 if (hw->phy.sfp_setup_needed) {
1082 status = hw->mac.ops.setup_sfp(hw);
1083 hw->phy.sfp_setup_needed = false;
1084 }
1085
1086 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1087 goto reset_hw_out;
1088
1089 /* Reset PHY */
1090 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1091 hw->phy.ops.reset(hw);
1092
1093 /* remember AUTOC from before we reset */
1094 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1095
1096 mac_reset_top:
1097 /*
1098 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1099 * If link reset is used when link is up, it might reset the PHY when
1100 * mng is using it. If link is down or the flag to force full link
1101 * reset is set, then perform link reset.
1102 */
1103 ctrl = IXGBE_CTRL_LNK_RST;
1104 if (!hw->force_full_reset) {
1105 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1106 if (link_up)
1107 ctrl = IXGBE_CTRL_RST;
1108 }
1109
1110 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1111 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1112 IXGBE_WRITE_FLUSH(hw);
1113
1114 /* Poll for reset bit to self-clear meaning reset is complete */
1115 for (i = 0; i < 10; i++) {
1116 usec_delay(1);
1117 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1118 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1119 break;
1120 }
1121
1122 if (ctrl & IXGBE_CTRL_RST_MASK) {
1123 status = IXGBE_ERR_RESET_FAILED;
1124 DEBUGOUT("Reset polling failed to complete.\n");
1125 }
1126
1127 msec_delay(50);
1128
1129 /*
1130 * Double resets are required for recovery from certain error
1131 * conditions. Between resets, it is necessary to stall to
1132 * allow time for any pending HW events to complete.
1133 */
1134 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1135 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1136 goto mac_reset_top;
1137 }
1138
1139 /*
1140 * Store the original AUTOC/AUTOC2 values if they have not been
1141 * stored off yet. Otherwise restore the stored original
1142 * values since the reset operation sets back to defaults.
1143 */
1144 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1145 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1146
1147 /* Enable link if disabled in NVM */
1148 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1149 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1150 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1151 IXGBE_WRITE_FLUSH(hw);
1152 }
1153
1154 if (hw->mac.orig_link_settings_stored == false) {
1155 hw->mac.orig_autoc = autoc;
1156 hw->mac.orig_autoc2 = autoc2;
1157 hw->mac.orig_link_settings_stored = true;
1158 } else {
1159
1160 /* If MNG FW is running on a multi-speed device that
1161 * doesn't autoneg with out driver support we need to
1162 * leave LMS in the state it was before we MAC reset.
1163 * Likewise if we support WoL we don't want change the
1164 * LMS state.
1165 */
1166 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1167 hw->wol_enabled)
1168 hw->mac.orig_autoc =
1169 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1170 curr_lms;
1171
1172 if (autoc != hw->mac.orig_autoc) {
1173 status = hw->mac.ops.prot_autoc_write(hw,
1174 hw->mac.orig_autoc,
1175 false);
1176 if (status != IXGBE_SUCCESS)
1177 goto reset_hw_out;
1178 }
1179
1180 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1181 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1182 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1183 autoc2 |= (hw->mac.orig_autoc2 &
1184 IXGBE_AUTOC2_UPPER_MASK);
1185 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1186 }
1187 }
1188
1189 /* Store the permanent mac address */
1190 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1191
1192 /*
1193 * Store MAC address from RAR0, clear receive address registers, and
1194 * clear the multicast table. Also reset num_rar_entries to 128,
1195 * since we modify this value when programming the SAN MAC address.
1196 */
1197 hw->mac.num_rar_entries = 128;
1198 hw->mac.ops.init_rx_addrs(hw);
1199
1200 /* Store the permanent SAN mac address */
1201 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1202
1203 /* Add the SAN MAC address to the RAR only if it's a valid address */
1204 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1205 /* Save the SAN MAC RAR index */
1206 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1207
1208 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
1209 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1210
1211 /* clear VMDq pool/queue selection for this RAR */
1212 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
1213 IXGBE_CLEAR_VMDQ_ALL);
1214
1215 /* Reserve the last RAR for the SAN MAC address */
1216 hw->mac.num_rar_entries--;
1217 }
1218
1219 /* Store the alternative WWNN/WWPN prefix */
1220 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1221 &hw->mac.wwpn_prefix);
1222
1223 reset_hw_out:
1224 return status;
1225 }
1226
1227 /**
1228 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1229 * @hw: pointer to hardware structure
1230 * @fdircmd: current value of FDIRCMD register
1231 */
ixgbe_fdir_check_cmd_complete(struct ixgbe_hw * hw,u32 * fdircmd)1232 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1233 {
1234 int i;
1235
1236 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1237 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1238 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1239 return IXGBE_SUCCESS;
1240 usec_delay(10);
1241 }
1242
1243 return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1244 }
1245
1246 /**
1247 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1248 * @hw: pointer to hardware structure
1249 **/
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw * hw)1250 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1251 {
1252 s32 err;
1253 int i;
1254 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1255 u32 fdircmd;
1256 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1257
1258 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1259
1260 /*
1261 * Before starting reinitialization process,
1262 * FDIRCMD.CMD must be zero.
1263 */
1264 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1265 if (err) {
1266 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
1267 return err;
1268 }
1269
1270 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1271 IXGBE_WRITE_FLUSH(hw);
1272 /*
1273 * 82599 adapters flow director init flow cannot be restarted,
1274 * Workaround 82599 silicon errata by performing the following steps
1275 * before re-writing the FDIRCTRL control register with the same value.
1276 * - write 1 to bit 8 of FDIRCMD register &
1277 * - write 0 to bit 8 of FDIRCMD register
1278 */
1279 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1280 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1281 IXGBE_FDIRCMD_CLEARHT));
1282 IXGBE_WRITE_FLUSH(hw);
1283 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1284 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1285 ~IXGBE_FDIRCMD_CLEARHT));
1286 IXGBE_WRITE_FLUSH(hw);
1287 /*
1288 * Clear FDIR Hash register to clear any leftover hashes
1289 * waiting to be programmed.
1290 */
1291 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1292 IXGBE_WRITE_FLUSH(hw);
1293
1294 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1295 IXGBE_WRITE_FLUSH(hw);
1296
1297 /* Poll init-done after we write FDIRCTRL register */
1298 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1299 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1300 IXGBE_FDIRCTRL_INIT_DONE)
1301 break;
1302 msec_delay(1);
1303 }
1304 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1305 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1306 return IXGBE_ERR_FDIR_REINIT_FAILED;
1307 }
1308
1309 /* Clear FDIR statistics registers (read to clear) */
1310 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1311 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1312 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1313 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1314 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1315
1316 return IXGBE_SUCCESS;
1317 }
1318
1319 /**
1320 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1321 * @hw: pointer to hardware structure
1322 * @fdirctrl: value to write to flow director control register
1323 **/
ixgbe_fdir_enable_82599(struct ixgbe_hw * hw,u32 fdirctrl)1324 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1325 {
1326 int i;
1327
1328 DEBUGFUNC("ixgbe_fdir_enable_82599");
1329
1330 /* Prime the keys for hashing */
1331 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1332 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1333
1334 /*
1335 * Poll init-done after we write the register. Estimated times:
1336 * 10G: PBALLOC = 11b, timing is 60us
1337 * 1G: PBALLOC = 11b, timing is 600us
1338 * 100M: PBALLOC = 11b, timing is 6ms
1339 *
1340 * Multiple these timings by 4 if under full Rx load
1341 *
1342 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1343 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1344 * this might not finish in our poll time, but we can live with that
1345 * for now.
1346 */
1347 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1348 IXGBE_WRITE_FLUSH(hw);
1349 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1350 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1351 IXGBE_FDIRCTRL_INIT_DONE)
1352 break;
1353 msec_delay(1);
1354 }
1355
1356 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1357 DEBUGOUT("Flow Director poll time exceeded!\n");
1358 }
1359
1360 /**
1361 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1362 * @hw: pointer to hardware structure
1363 * @fdirctrl: value to write to flow director control register, initially
1364 * contains just the value of the Rx packet buffer allocation
1365 **/
ixgbe_init_fdir_signature_82599(struct ixgbe_hw * hw,u32 fdirctrl)1366 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1367 {
1368 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1369
1370 /*
1371 * Continue setup of fdirctrl register bits:
1372 * Move the flexible bytes to use the ethertype - shift 6 words
1373 * Set the maximum length per hash bucket to 0xA filters
1374 * Send interrupt when 64 filters are left
1375 */
1376 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1377 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1378 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1379
1380 /* write hashes and fdirctrl register, poll for completion */
1381 ixgbe_fdir_enable_82599(hw, fdirctrl);
1382
1383 return IXGBE_SUCCESS;
1384 }
1385
1386 /**
1387 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1388 * @hw: pointer to hardware structure
1389 * @fdirctrl: value to write to flow director control register, initially
1390 * contains just the value of the Rx packet buffer allocation
1391 * @cloud_mode: true - cloud mode, false - other mode
1392 **/
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw * hw,u32 fdirctrl,bool cloud_mode)1393 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1394 bool cloud_mode)
1395 {
1396 UNREFERENCED_1PARAMETER(cloud_mode);
1397 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1398
1399 /*
1400 * Continue setup of fdirctrl register bits:
1401 * Turn perfect match filtering on
1402 * Report hash in RSS field of Rx wb descriptor
1403 * Initialize the drop queue to queue 127
1404 * Move the flexible bytes to use the ethertype - shift 6 words
1405 * Set the maximum length per hash bucket to 0xA filters
1406 * Send interrupt when 64 (0x4 * 16) filters are left
1407 */
1408 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1409 IXGBE_FDIRCTRL_REPORT_STATUS |
1410 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1411 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1412 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1413 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1414
1415 if (cloud_mode)
1416 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
1417 IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
1418
1419 /* write hashes and fdirctrl register, poll for completion */
1420 ixgbe_fdir_enable_82599(hw, fdirctrl);
1421
1422 return IXGBE_SUCCESS;
1423 }
1424
1425 /**
1426 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
1427 * @hw: pointer to hardware structure
1428 * @dropqueue: Rx queue index used for the dropped packets
1429 **/
ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw * hw,u8 dropqueue)1430 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)
1431 {
1432 u32 fdirctrl;
1433
1434 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599");
1435 /* Clear init done bit and drop queue field */
1436 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1437 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE);
1438
1439 /* Set drop queue */
1440 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1441 if ((hw->mac.type == ixgbe_mac_X550) ||
1442 (hw->mac.type == ixgbe_mac_X550EM_x) ||
1443 (hw->mac.type == ixgbe_mac_X550EM_a))
1444 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
1445
1446 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1447 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1448 IXGBE_FDIRCMD_CLEARHT));
1449 IXGBE_WRITE_FLUSH(hw);
1450 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1451 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1452 ~IXGBE_FDIRCMD_CLEARHT));
1453 IXGBE_WRITE_FLUSH(hw);
1454
1455 /* write hashes and fdirctrl register, poll for completion */
1456 ixgbe_fdir_enable_82599(hw, fdirctrl);
1457 }
1458
1459 /*
1460 * These defines allow us to quickly generate all of the necessary instructions
1461 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1462 * for values 0 through 15
1463 */
1464 #define IXGBE_ATR_COMMON_HASH_KEY \
1465 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1466 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1467 do { \
1468 u32 n = (_n); \
1469 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1470 common_hash ^= lo_hash_dword >> n; \
1471 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1472 bucket_hash ^= lo_hash_dword >> n; \
1473 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1474 sig_hash ^= lo_hash_dword << (16 - n); \
1475 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1476 common_hash ^= hi_hash_dword >> n; \
1477 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1478 bucket_hash ^= hi_hash_dword >> n; \
1479 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1480 sig_hash ^= hi_hash_dword << (16 - n); \
1481 } while (0)
1482
1483 /**
1484 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1485 * @input: input bitstream to compute the hash on
1486 * @common: compressed common input dword
1487 *
1488 * This function is almost identical to the function above but contains
1489 * several optimizations such as unwinding all of the loops, letting the
1490 * compiler work out all of the conditional ifs since the keys are static
1491 * defines, and computing two keys at once since the hashed dword stream
1492 * will be the same for both keys.
1493 **/
ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,union ixgbe_atr_hash_dword common)1494 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1495 union ixgbe_atr_hash_dword common)
1496 {
1497 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1498 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1499
1500 /* record the flow_vm_vlan bits as they are a key part to the hash */
1501 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1502
1503 /* generate common hash dword */
1504 hi_hash_dword = IXGBE_NTOHL(common.dword);
1505
1506 /* low dword is word swapped version of common */
1507 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1508
1509 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1510 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1511
1512 /* Process bits 0 and 16 */
1513 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1514
1515 /*
1516 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1517 * delay this because bit 0 of the stream should not be processed
1518 * so we do not add the VLAN until after bit 0 was processed
1519 */
1520 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1521
1522 /* Process remaining 30 bit of the key */
1523 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1524 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1525 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1526 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1527 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1528 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1529 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1530 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1531 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1532 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1533 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1534 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1535 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1536 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1537 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1538
1539 /* combine common_hash result with signature and bucket hashes */
1540 bucket_hash ^= common_hash;
1541 bucket_hash &= IXGBE_ATR_HASH_MASK;
1542
1543 sig_hash ^= common_hash << 16;
1544 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1545
1546 /* return completed signature hash */
1547 return sig_hash ^ bucket_hash;
1548 }
1549
1550 /**
1551 * ixgbe_fdir_add_signature_filter_82599 - Adds a signature hash filter
1552 * @hw: pointer to hardware structure
1553 * @input: unique input dword
1554 * @common: compressed common input dword
1555 * @queue: queue index to direct traffic to
1556 *
1557 * Note that the tunnel bit in input must not be set when the hardware
1558 * tunneling support does not exist.
1559 **/
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw * hw,union ixgbe_atr_hash_dword input,union ixgbe_atr_hash_dword common,u8 queue)1560 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1561 union ixgbe_atr_hash_dword input,
1562 union ixgbe_atr_hash_dword common,
1563 u8 queue)
1564 {
1565 u64 fdirhashcmd;
1566 u8 flow_type;
1567 bool tunnel;
1568 u32 fdircmd;
1569
1570 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1571
1572 /*
1573 * Get the flow_type in order to program FDIRCMD properly
1574 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1575 * fifth is FDIRCMD.TUNNEL_FILTER
1576 */
1577 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
1578 flow_type = input.formatted.flow_type &
1579 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
1580 switch (flow_type) {
1581 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1582 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1583 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1584 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1585 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1586 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1587 break;
1588 default:
1589 DEBUGOUT(" Error on flow type input\n");
1590 return;
1591 }
1592
1593 /* configure FDIRCMD register */
1594 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1595 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1596 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1597 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1598 if (tunnel)
1599 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1600
1601 /*
1602 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1603 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1604 */
1605 fdirhashcmd = (u64)fdircmd << 32;
1606 fdirhashcmd |= (u64)ixgbe_atr_compute_sig_hash_82599(input, common);
1607 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1608
1609 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1610
1611 return;
1612 }
1613
1614 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1615 do { \
1616 u32 n = (_n); \
1617 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1618 bucket_hash ^= lo_hash_dword >> n; \
1619 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1620 bucket_hash ^= hi_hash_dword >> n; \
1621 } while (0)
1622
1623 /**
1624 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1625 * @input: input bitstream to compute the hash on
1626 * @input_mask: mask for the input bitstream
1627 *
1628 * This function serves two main purposes. First it applies the input_mask
1629 * to the atr_input resulting in a cleaned up atr_input data stream.
1630 * Secondly it computes the hash and stores it in the bkt_hash field at
1631 * the end of the input byte stream. This way it will be available for
1632 * future use without needing to recompute the hash.
1633 **/
ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input * input,union ixgbe_atr_input * input_mask)1634 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1635 union ixgbe_atr_input *input_mask)
1636 {
1637
1638 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1639 u32 bucket_hash = 0;
1640 u32 hi_dword = 0;
1641 u32 i = 0;
1642
1643 /* Apply masks to input data */
1644 for (i = 0; i < 14; i++)
1645 input->dword_stream[i] &= input_mask->dword_stream[i];
1646
1647 /* record the flow_vm_vlan bits as they are a key part to the hash */
1648 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1649
1650 /* generate common hash dword */
1651 for (i = 1; i <= 13; i++)
1652 hi_dword ^= input->dword_stream[i];
1653 hi_hash_dword = IXGBE_NTOHL(hi_dword);
1654
1655 /* low dword is word swapped version of common */
1656 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1657
1658 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1659 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1660
1661 /* Process bits 0 and 16 */
1662 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1663
1664 /*
1665 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1666 * delay this because bit 0 of the stream should not be processed
1667 * so we do not add the VLAN until after bit 0 was processed
1668 */
1669 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1670
1671 /* Process remaining 30 bit of the key */
1672 for (i = 1; i <= 15; i++)
1673 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1674
1675 /*
1676 * Limit hash to 13 bits since max bucket count is 8K.
1677 * Store result at the end of the input stream.
1678 */
1679 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1680 }
1681
1682 /**
1683 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1684 * @input_mask: mask to be bit swapped
1685 *
1686 * The source and destination port masks for flow director are bit swapped
1687 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1688 * generate a correctly swapped value we need to bit swap the mask and that
1689 * is what is accomplished by this function.
1690 **/
ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input * input_mask)1691 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1692 {
1693 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1694 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1695 mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port);
1696 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1697 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1698 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1699 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1700 }
1701
1702 /*
1703 * These two macros are meant to address the fact that we have registers
1704 * that are either all or in part big-endian. As a result on big-endian
1705 * systems we will end up byte swapping the value to little-endian before
1706 * it is byte swapped again and written to the hardware in the original
1707 * big-endian format.
1708 */
1709 #define IXGBE_STORE_AS_BE32(_value) \
1710 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1711 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1712
1713 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1714 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1715
1716 #define IXGBE_STORE_AS_BE16(_value) \
1717 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1718
ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw * hw,union ixgbe_atr_input * input_mask,bool cloud_mode)1719 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1720 union ixgbe_atr_input *input_mask, bool cloud_mode)
1721 {
1722 /* mask IPv6 since it is currently not supported */
1723 u32 fdirm = IXGBE_FDIRM_DIPv6;
1724 u32 fdirtcpm;
1725 u32 fdirip6m;
1726 UNREFERENCED_1PARAMETER(cloud_mode);
1727 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1728
1729 /*
1730 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1731 * are zero, then assume a full mask for that field. Also assume that
1732 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1733 * cannot be masked out in this implementation.
1734 *
1735 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1736 * point in time.
1737 */
1738
1739 /* verify bucket hash is cleared on hash generation */
1740 if (input_mask->formatted.bkt_hash)
1741 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1742
1743 /* Program FDIRM and verify partial masks */
1744 switch (input_mask->formatted.vm_pool & 0x7F) {
1745 case 0x0:
1746 fdirm |= IXGBE_FDIRM_POOL;
1747 case 0x7F:
1748 break;
1749 default:
1750 DEBUGOUT(" Error on vm pool mask\n");
1751 return IXGBE_ERR_CONFIG;
1752 }
1753
1754 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1755 case 0x0:
1756 fdirm |= IXGBE_FDIRM_L4P;
1757 if (input_mask->formatted.dst_port ||
1758 input_mask->formatted.src_port) {
1759 DEBUGOUT(" Error on src/dst port mask\n");
1760 return IXGBE_ERR_CONFIG;
1761 }
1762 case IXGBE_ATR_L4TYPE_MASK:
1763 break;
1764 default:
1765 DEBUGOUT(" Error on flow type mask\n");
1766 return IXGBE_ERR_CONFIG;
1767 }
1768
1769 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1770 case 0x0000:
1771 /* mask VLAN ID */
1772 fdirm |= IXGBE_FDIRM_VLANID;
1773 /* mask VLAN priority */
1774 fdirm |= IXGBE_FDIRM_VLANP;
1775 break;
1776 case 0x0FFF:
1777 /* mask VLAN priority */
1778 fdirm |= IXGBE_FDIRM_VLANP;
1779 break;
1780 case 0xE000:
1781 /* mask VLAN ID only */
1782 fdirm |= IXGBE_FDIRM_VLANID;
1783 /* fall through */
1784 case 0xEFFF:
1785 /* no VLAN fields masked */
1786 break;
1787 default:
1788 DEBUGOUT(" Error on VLAN mask\n");
1789 return IXGBE_ERR_CONFIG;
1790 }
1791
1792 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1793 case 0x0000:
1794 /* Mask Flex Bytes */
1795 fdirm |= IXGBE_FDIRM_FLEX;
1796 /* fall through */
1797 case 0xFFFF:
1798 break;
1799 default:
1800 DEBUGOUT(" Error on flexible byte mask\n");
1801 return IXGBE_ERR_CONFIG;
1802 }
1803
1804 if (cloud_mode) {
1805 fdirm |= IXGBE_FDIRM_L3P;
1806 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
1807 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
1808
1809 switch (input_mask->formatted.inner_mac[0] & 0xFF) {
1810 case 0x00:
1811 /* Mask inner MAC, fall through */
1812 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;
1813 case 0xFF:
1814 break;
1815 default:
1816 DEBUGOUT(" Error on inner_mac byte mask\n");
1817 return IXGBE_ERR_CONFIG;
1818 }
1819
1820 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
1821 case 0x0:
1822 /* Mask vxlan id */
1823 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;
1824 break;
1825 case 0x00FFFFFF:
1826 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
1827 break;
1828 case 0xFFFFFFFF:
1829 break;
1830 default:
1831 DEBUGOUT(" Error on TNI/VNI byte mask\n");
1832 return IXGBE_ERR_CONFIG;
1833 }
1834
1835 switch (input_mask->formatted.tunnel_type & 0xFFFF) {
1836 case 0x0:
1837 /* Mask turnnel type, fall through */
1838 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
1839 case 0xFFFF:
1840 break;
1841 default:
1842 DEBUGOUT(" Error on tunnel type byte mask\n");
1843 return IXGBE_ERR_CONFIG;
1844 }
1845 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1846
1847 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM,
1848 * FDIRSIP4M and FDIRDIP4M in cloud mode to allow
1849 * L3/L3 packets to tunnel.
1850 */
1851 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1852 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1853 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1854 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1855 switch (hw->mac.type) {
1856 case ixgbe_mac_X550:
1857 case ixgbe_mac_X550EM_x:
1858 case ixgbe_mac_X550EM_a:
1859 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
1860 break;
1861 default:
1862 break;
1863 }
1864 }
1865
1866 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1867 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1868
1869 if (!cloud_mode) {
1870 /* store the TCP/UDP port masks, bit reversed from port
1871 * layout */
1872 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1873
1874 /* write both the same so that UDP and TCP use the same mask */
1875 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1876 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1877 /* also use it for SCTP */
1878 switch (hw->mac.type) {
1879 case ixgbe_mac_X550:
1880 case ixgbe_mac_X550EM_x:
1881 case ixgbe_mac_X550EM_a:
1882 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1883 break;
1884 default:
1885 break;
1886 }
1887
1888 /* store source and destination IP masks (big-enian) */
1889 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1890 ~input_mask->formatted.src_ip[0]);
1891 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1892 ~input_mask->formatted.dst_ip[0]);
1893 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, 0xFFFFFFFF);
1894 }
1895 return IXGBE_SUCCESS;
1896 }
1897
ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw * hw,union ixgbe_atr_input * input,u16 soft_id,u8 queue,bool cloud_mode)1898 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1899 union ixgbe_atr_input *input,
1900 u16 soft_id, u8 queue, bool cloud_mode)
1901 {
1902 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1903 u32 addr_low, addr_high;
1904 u32 cloud_type = 0;
1905 s32 err;
1906 UNREFERENCED_1PARAMETER(cloud_mode);
1907
1908 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1909 if (!cloud_mode) {
1910 /* currently IPv6 is not supported, must be programmed with 0 */
1911 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1912 input->formatted.src_ip[0]);
1913 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1914 input->formatted.src_ip[1]);
1915 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1916 input->formatted.src_ip[2]);
1917
1918 /* record the source address (big-endian) */
1919 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
1920 input->formatted.src_ip[0]);
1921
1922 /* record the first 32 bits of the destination address
1923 * (big-endian) */
1924 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
1925 input->formatted.dst_ip[0]);
1926
1927 /* record source and destination port (little-endian)*/
1928 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1929 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1930 fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port);
1931 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1932 }
1933
1934 /* record VLAN (little-endian) and flex_bytes(big-endian) */
1935 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1936 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1937 fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id);
1938 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1939
1940 if (cloud_mode) {
1941 if (input->formatted.tunnel_type != 0)
1942 cloud_type = 0x80000000;
1943
1944 addr_low = ((u32)input->formatted.inner_mac[0] |
1945 ((u32)input->formatted.inner_mac[1] << 8) |
1946 ((u32)input->formatted.inner_mac[2] << 16) |
1947 ((u32)input->formatted.inner_mac[3] << 24));
1948 addr_high = ((u32)input->formatted.inner_mac[4] |
1949 ((u32)input->formatted.inner_mac[5] << 8));
1950 cloud_type |= addr_high;
1951 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
1952 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
1953 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
1954 }
1955
1956 /* configure FDIRHASH register */
1957 fdirhash = input->formatted.bkt_hash;
1958 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1959 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1960
1961 /*
1962 * flush all previous writes to make certain registers are
1963 * programmed prior to issuing the command
1964 */
1965 IXGBE_WRITE_FLUSH(hw);
1966
1967 /* configure FDIRCMD register */
1968 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1969 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1970 if (queue == IXGBE_FDIR_DROP_QUEUE)
1971 fdircmd |= IXGBE_FDIRCMD_DROP;
1972 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
1973 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1974 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1975 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1976 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1977
1978 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1979 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1980 if (err) {
1981 DEBUGOUT("Flow Director command did not complete!\n");
1982 return err;
1983 }
1984
1985 return IXGBE_SUCCESS;
1986 }
1987
ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw * hw,union ixgbe_atr_input * input,u16 soft_id)1988 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1989 union ixgbe_atr_input *input,
1990 u16 soft_id)
1991 {
1992 u32 fdirhash;
1993 u32 fdircmd;
1994 s32 err;
1995
1996 /* configure FDIRHASH register */
1997 fdirhash = input->formatted.bkt_hash;
1998 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1999 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2000
2001 /* flush hash to HW */
2002 IXGBE_WRITE_FLUSH(hw);
2003
2004 /* Query if filter is present */
2005 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
2006
2007 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
2008 if (err) {
2009 DEBUGOUT("Flow Director command did not complete!\n");
2010 return err;
2011 }
2012
2013 /* if filter exists in hardware then remove it */
2014 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
2015 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2016 IXGBE_WRITE_FLUSH(hw);
2017 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
2018 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
2019 }
2020
2021 return IXGBE_SUCCESS;
2022 }
2023
2024 /**
2025 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2026 * @hw: pointer to hardware structure
2027 * @input: input bitstream
2028 * @input_mask: mask for the input bitstream
2029 * @soft_id: software index for the filters
2030 * @queue: queue index to direct traffic to
2031 * @cloud_mode: unused
2032 *
2033 * Note that the caller to this function must lock before calling, since the
2034 * hardware writes must be protected from one another.
2035 **/
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw * hw,union ixgbe_atr_input * input,union ixgbe_atr_input * input_mask,u16 soft_id,u8 queue,bool cloud_mode)2036 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
2037 union ixgbe_atr_input *input,
2038 union ixgbe_atr_input *input_mask,
2039 u16 soft_id, u8 queue, bool cloud_mode)
2040 {
2041 s32 err = IXGBE_ERR_CONFIG;
2042 UNREFERENCED_1PARAMETER(cloud_mode);
2043
2044 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
2045
2046 /*
2047 * Check flow_type formatting, and bail out before we touch the hardware
2048 * if there's a configuration issue
2049 */
2050 switch (input->formatted.flow_type) {
2051 case IXGBE_ATR_FLOW_TYPE_IPV4:
2052 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
2053 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
2054 if (input->formatted.dst_port || input->formatted.src_port) {
2055 DEBUGOUT(" Error on src/dst port\n");
2056 return IXGBE_ERR_CONFIG;
2057 }
2058 break;
2059 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2060 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
2061 if (input->formatted.dst_port || input->formatted.src_port) {
2062 DEBUGOUT(" Error on src/dst port\n");
2063 return IXGBE_ERR_CONFIG;
2064 }
2065 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2066 IXGBE_ATR_L4TYPE_MASK;
2067 break;
2068 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2069 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
2070 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2071 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
2072 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2073 IXGBE_ATR_L4TYPE_MASK;
2074 break;
2075 default:
2076 DEBUGOUT(" Error on flow type input\n");
2077 return err;
2078 }
2079
2080 /* program input mask into the HW */
2081 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2082 if (err)
2083 return err;
2084
2085 /* apply mask and compute/store hash */
2086 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
2087
2088 /* program filters to filter memory */
2089 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2090 soft_id, queue, cloud_mode);
2091 }
2092
2093 /**
2094 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2095 * @hw: pointer to hardware structure
2096 * @reg: analog register to read
2097 * @val: read value
2098 *
2099 * Performs read operation to Omer analog register specified.
2100 **/
ixgbe_read_analog_reg8_82599(struct ixgbe_hw * hw,u32 reg,u8 * val)2101 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2102 {
2103 u32 core_ctl;
2104
2105 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2106
2107 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2108 (reg << 8));
2109 IXGBE_WRITE_FLUSH(hw);
2110 usec_delay(10);
2111 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2112 *val = (u8)core_ctl;
2113
2114 return IXGBE_SUCCESS;
2115 }
2116
2117 /**
2118 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2119 * @hw: pointer to hardware structure
2120 * @reg: atlas register to write
2121 * @val: value to write
2122 *
2123 * Performs write operation to Omer analog register specified.
2124 **/
ixgbe_write_analog_reg8_82599(struct ixgbe_hw * hw,u32 reg,u8 val)2125 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2126 {
2127 u32 core_ctl;
2128
2129 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2130
2131 core_ctl = (reg << 8) | val;
2132 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2133 IXGBE_WRITE_FLUSH(hw);
2134 usec_delay(10);
2135
2136 return IXGBE_SUCCESS;
2137 }
2138
2139 /**
2140 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2141 * @hw: pointer to hardware structure
2142 *
2143 * Starts the hardware using the generic start_hw function
2144 * and the generation start_hw function.
2145 * Then performs revision-specific operations, if any.
2146 **/
ixgbe_start_hw_82599(struct ixgbe_hw * hw)2147 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2148 {
2149 s32 ret_val = IXGBE_SUCCESS;
2150
2151 DEBUGFUNC("ixgbe_start_hw_82599");
2152
2153 ret_val = ixgbe_start_hw_generic(hw);
2154 if (ret_val != IXGBE_SUCCESS)
2155 goto out;
2156
2157 ixgbe_start_hw_gen2(hw);
2158
2159 /* We need to run link autotry after the driver loads */
2160 hw->mac.autotry_restart = true;
2161
2162 if (ret_val == IXGBE_SUCCESS)
2163 ret_val = ixgbe_verify_fw_version_82599(hw);
2164 out:
2165 return ret_val;
2166 }
2167
2168 /**
2169 * ixgbe_identify_phy_82599 - Get physical layer module
2170 * @hw: pointer to hardware structure
2171 *
2172 * Determines the physical layer module found on the current adapter.
2173 * If PHY already detected, maintains current PHY type in hw struct,
2174 * otherwise executes the PHY detection routine.
2175 **/
ixgbe_identify_phy_82599(struct ixgbe_hw * hw)2176 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2177 {
2178 s32 status;
2179
2180 DEBUGFUNC("ixgbe_identify_phy_82599");
2181
2182 /* Detect PHY if not unknown - returns success if already detected. */
2183 status = ixgbe_identify_phy_generic(hw);
2184 if (status != IXGBE_SUCCESS) {
2185 /* 82599 10GBASE-T requires an external PHY */
2186 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2187 return status;
2188 else
2189 status = ixgbe_identify_module_generic(hw);
2190 }
2191
2192 /* Set PHY type none if no PHY detected */
2193 if (hw->phy.type == ixgbe_phy_unknown) {
2194 hw->phy.type = ixgbe_phy_none;
2195 return IXGBE_SUCCESS;
2196 }
2197
2198 /* Return error if SFP module has been detected but is not supported */
2199 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2200 return IXGBE_ERR_SFP_NOT_SUPPORTED;
2201
2202 return status;
2203 }
2204
2205 /**
2206 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2207 * @hw: pointer to hardware structure
2208 *
2209 * Determines physical layer capabilities of the current configuration.
2210 **/
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw * hw)2211 u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2212 {
2213 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2214 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2215 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2216 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2217 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2218 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2219 u16 ext_ability = 0;
2220
2221 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2222
2223 hw->phy.ops.identify(hw);
2224
2225 switch (hw->phy.type) {
2226 case ixgbe_phy_tn:
2227 case ixgbe_phy_cu_unknown:
2228 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2229 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2230 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2231 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2232 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2233 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2234 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2235 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2236 goto out;
2237 default:
2238 break;
2239 }
2240
2241 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2242 case IXGBE_AUTOC_LMS_1G_AN:
2243 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2244 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2245 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2246 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2247 goto out;
2248 } else
2249 /* SFI mode so read SFP module */
2250 goto sfp_check;
2251 break;
2252 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2253 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2254 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2255 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2256 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2257 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2258 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2259 goto out;
2260 break;
2261 case IXGBE_AUTOC_LMS_10G_SERIAL:
2262 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2263 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2264 goto out;
2265 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2266 goto sfp_check;
2267 break;
2268 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2269 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2270 if (autoc & IXGBE_AUTOC_KX_SUPP)
2271 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2272 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2273 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2274 if (autoc & IXGBE_AUTOC_KR_SUPP)
2275 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2276 goto out;
2277 break;
2278 default:
2279 goto out;
2280 break;
2281 }
2282
2283 sfp_check:
2284 /* SFP check must be done last since DA modules are sometimes used to
2285 * test KR mode - we need to id KR mode correctly before SFP module.
2286 * Call identify_sfp because the pluggable module may have changed */
2287 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2288 out:
2289 return physical_layer;
2290 }
2291
2292 /**
2293 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2294 * @hw: pointer to hardware structure
2295 * @regval: register value to write to RXCTRL
2296 *
2297 * Enables the Rx DMA unit for 82599
2298 **/
ixgbe_enable_rx_dma_82599(struct ixgbe_hw * hw,u32 regval)2299 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2300 {
2301
2302 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2303
2304 /*
2305 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2306 * If traffic is incoming before we enable the Rx unit, it could hang
2307 * the Rx DMA unit. Therefore, make sure the security engine is
2308 * completely disabled prior to enabling the Rx unit.
2309 */
2310
2311 hw->mac.ops.disable_sec_rx_path(hw);
2312
2313 if (regval & IXGBE_RXCTRL_RXEN)
2314 ixgbe_enable_rx(hw);
2315 else
2316 ixgbe_disable_rx(hw);
2317
2318 hw->mac.ops.enable_sec_rx_path(hw);
2319
2320 return IXGBE_SUCCESS;
2321 }
2322
2323 /**
2324 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2325 * @hw: pointer to hardware structure
2326 *
2327 * Verifies that installed the firmware version is 0.6 or higher
2328 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2329 *
2330 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2331 * if the FW version is not supported.
2332 **/
ixgbe_verify_fw_version_82599(struct ixgbe_hw * hw)2333 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2334 {
2335 s32 status = IXGBE_ERR_EEPROM_VERSION;
2336 u16 fw_offset, fw_ptp_cfg_offset;
2337 u16 fw_version;
2338
2339 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2340
2341 /* firmware check is only necessary for SFI devices */
2342 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2343 status = IXGBE_SUCCESS;
2344 goto fw_version_out;
2345 }
2346
2347 /* get the offset to the Firmware Module block */
2348 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2349 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2350 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2351 return IXGBE_ERR_EEPROM_VERSION;
2352 }
2353
2354 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2355 goto fw_version_out;
2356
2357 /* get the offset to the Pass Through Patch Configuration block */
2358 if (hw->eeprom.ops.read(hw, (fw_offset +
2359 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2360 &fw_ptp_cfg_offset)) {
2361 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2362 "eeprom read at offset %d failed",
2363 fw_offset +
2364 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2365 return IXGBE_ERR_EEPROM_VERSION;
2366 }
2367
2368 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2369 goto fw_version_out;
2370
2371 /* get the firmware version */
2372 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2373 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2374 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2375 "eeprom read at offset %d failed",
2376 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2377 return IXGBE_ERR_EEPROM_VERSION;
2378 }
2379
2380 if (fw_version > 0x5)
2381 status = IXGBE_SUCCESS;
2382
2383 fw_version_out:
2384 return status;
2385 }
2386
2387 /**
2388 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2389 * @hw: pointer to hardware structure
2390 *
2391 * Returns true if the LESM FW module is present and enabled. Otherwise
2392 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2393 **/
ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw * hw)2394 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2395 {
2396 bool lesm_enabled = false;
2397 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2398 s32 status;
2399
2400 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2401
2402 /* get the offset to the Firmware Module block */
2403 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2404
2405 if ((status != IXGBE_SUCCESS) ||
2406 (fw_offset == 0) || (fw_offset == 0xFFFF))
2407 goto out;
2408
2409 /* get the offset to the LESM Parameters block */
2410 status = hw->eeprom.ops.read(hw, (fw_offset +
2411 IXGBE_FW_LESM_PARAMETERS_PTR),
2412 &fw_lesm_param_offset);
2413
2414 if ((status != IXGBE_SUCCESS) ||
2415 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2416 goto out;
2417
2418 /* get the LESM state word */
2419 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2420 IXGBE_FW_LESM_STATE_1),
2421 &fw_lesm_state);
2422
2423 if ((status == IXGBE_SUCCESS) &&
2424 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2425 lesm_enabled = true;
2426
2427 out:
2428 return lesm_enabled;
2429 }
2430
2431 /**
2432 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2433 * fastest available method
2434 *
2435 * @hw: pointer to hardware structure
2436 * @offset: offset of word in EEPROM to read
2437 * @words: number of words
2438 * @data: word(s) read from the EEPROM
2439 *
2440 * Retrieves 16 bit word(s) read from EEPROM
2441 **/
ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)2442 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2443 u16 words, u16 *data)
2444 {
2445 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2446 s32 ret_val = IXGBE_ERR_CONFIG;
2447
2448 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2449
2450 /*
2451 * If EEPROM is detected and can be addressed using 14 bits,
2452 * use EERD otherwise use bit bang
2453 */
2454 if ((eeprom->type == ixgbe_eeprom_spi) &&
2455 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2456 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2457 data);
2458 else
2459 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2460 words,
2461 data);
2462
2463 return ret_val;
2464 }
2465
2466 /**
2467 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2468 * fastest available method
2469 *
2470 * @hw: pointer to hardware structure
2471 * @offset: offset of word in the EEPROM to read
2472 * @data: word read from the EEPROM
2473 *
2474 * Reads a 16 bit word from the EEPROM
2475 **/
ixgbe_read_eeprom_82599(struct ixgbe_hw * hw,u16 offset,u16 * data)2476 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2477 u16 offset, u16 *data)
2478 {
2479 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2480 s32 ret_val = IXGBE_ERR_CONFIG;
2481
2482 DEBUGFUNC("ixgbe_read_eeprom_82599");
2483
2484 /*
2485 * If EEPROM is detected and can be addressed using 14 bits,
2486 * use EERD otherwise use bit bang
2487 */
2488 if ((eeprom->type == ixgbe_eeprom_spi) &&
2489 (offset <= IXGBE_EERD_MAX_ADDR))
2490 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2491 else
2492 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2493
2494 return ret_val;
2495 }
2496
2497 /**
2498 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2499 *
2500 * @hw: pointer to hardware structure
2501 *
2502 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2503 * full pipeline reset. This function assumes the SW/FW lock is held.
2504 **/
ixgbe_reset_pipeline_82599(struct ixgbe_hw * hw)2505 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2506 {
2507 s32 ret_val;
2508 u32 anlp1_reg = 0;
2509 u32 i, autoc_reg, autoc2_reg;
2510
2511 /* Enable link if disabled in NVM */
2512 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2513 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2514 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2515 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2516 IXGBE_WRITE_FLUSH(hw);
2517 }
2518
2519 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2520 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2521 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2522 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2523 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2524 /* Wait for AN to leave state 0 */
2525 for (i = 0; i < 10; i++) {
2526 msec_delay(4);
2527 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2528 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2529 break;
2530 }
2531
2532 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2533 DEBUGOUT("auto negotiation not completed\n");
2534 ret_val = IXGBE_ERR_RESET_FAILED;
2535 goto reset_pipeline_out;
2536 }
2537
2538 ret_val = IXGBE_SUCCESS;
2539
2540 reset_pipeline_out:
2541 /* Write AUTOC register with original LMS field and Restart_AN */
2542 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2543 IXGBE_WRITE_FLUSH(hw);
2544
2545 return ret_val;
2546 }
2547
2548 /**
2549 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2550 * @hw: pointer to hardware structure
2551 * @byte_offset: byte offset to read
2552 * @dev_addr: address to read from
2553 * @data: value read
2554 *
2555 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2556 * a specified device address.
2557 **/
ixgbe_read_i2c_byte_82599(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2558 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2559 u8 dev_addr, u8 *data)
2560 {
2561 u32 esdp;
2562 s32 status;
2563 s32 timeout = 200;
2564
2565 DEBUGFUNC("ixgbe_read_i2c_byte_82599");
2566
2567 if (hw->phy.qsfp_shared_i2c_bus == true) {
2568 /* Acquire I2C bus ownership. */
2569 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2570 esdp |= IXGBE_ESDP_SDP0;
2571 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2572 IXGBE_WRITE_FLUSH(hw);
2573
2574 while (timeout) {
2575 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2576 if (esdp & IXGBE_ESDP_SDP1)
2577 break;
2578
2579 msec_delay(5);
2580 timeout--;
2581 }
2582
2583 if (!timeout) {
2584 DEBUGOUT("Driver can't access resource,"
2585 " acquiring I2C bus timeout.\n");
2586 status = IXGBE_ERR_I2C;
2587 goto release_i2c_access;
2588 }
2589 }
2590
2591 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2592
2593 release_i2c_access:
2594
2595 if (hw->phy.qsfp_shared_i2c_bus == true) {
2596 /* Release I2C bus ownership. */
2597 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2598 esdp &= ~IXGBE_ESDP_SDP0;
2599 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2600 IXGBE_WRITE_FLUSH(hw);
2601 }
2602
2603 return status;
2604 }
2605
2606 /**
2607 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2608 * @hw: pointer to hardware structure
2609 * @byte_offset: byte offset to write
2610 * @dev_addr: address to read from
2611 * @data: value to write
2612 *
2613 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2614 * a specified device address.
2615 **/
ixgbe_write_i2c_byte_82599(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2616 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2617 u8 dev_addr, u8 data)
2618 {
2619 u32 esdp;
2620 s32 status;
2621 s32 timeout = 200;
2622
2623 DEBUGFUNC("ixgbe_write_i2c_byte_82599");
2624
2625 if (hw->phy.qsfp_shared_i2c_bus == true) {
2626 /* Acquire I2C bus ownership. */
2627 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2628 esdp |= IXGBE_ESDP_SDP0;
2629 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2630 IXGBE_WRITE_FLUSH(hw);
2631
2632 while (timeout) {
2633 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2634 if (esdp & IXGBE_ESDP_SDP1)
2635 break;
2636
2637 msec_delay(5);
2638 timeout--;
2639 }
2640
2641 if (!timeout) {
2642 DEBUGOUT("Driver can't access resource,"
2643 " acquiring I2C bus timeout.\n");
2644 status = IXGBE_ERR_I2C;
2645 goto release_i2c_access;
2646 }
2647 }
2648
2649 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2650
2651 release_i2c_access:
2652
2653 if (hw->phy.qsfp_shared_i2c_bus == true) {
2654 /* Release I2C bus ownership. */
2655 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2656 esdp &= ~IXGBE_ESDP_SDP0;
2657 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2658 IXGBE_WRITE_FLUSH(hw);
2659 }
2660
2661 return status;
2662 }
2663