xref: /titanic_51/usr/src/uts/common/io/ixgbe/core/ixgbe_x550.c (revision 7e579c3009252f0da48e48e80e1307bc5011b5fa)
1  /******************************************************************************
2  
3    Copyright (c) 2001-2015, Intel Corporation
4    All rights reserved.
5  
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32  ******************************************************************************/
33  /*$FreeBSD$*/
34  
35  #include "ixgbe_x550.h"
36  #include "ixgbe_x540.h"
37  #include "ixgbe_type.h"
38  #include "ixgbe_api.h"
39  #include "ixgbe_common.h"
40  #include "ixgbe_phy.h"
41  
42  static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
43  
44  /**
45   *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
46   *  @hw: pointer to hardware structure
47   *
48   *  Initialize the function pointers and assign the MAC type for X550.
49   *  Does not touch the hardware.
50   **/
51  s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
52  {
53  	struct ixgbe_mac_info *mac = &hw->mac;
54  	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
55  	s32 ret_val;
56  
57  	DEBUGFUNC("ixgbe_init_ops_X550");
58  
59  	ret_val = ixgbe_init_ops_X540(hw);
60  	mac->ops.dmac_config = ixgbe_dmac_config_X550;
61  	mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
62  	mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
63  	mac->ops.setup_eee = ixgbe_setup_eee_X550;
64  	mac->ops.set_source_address_pruning =
65  			ixgbe_set_source_address_pruning_X550;
66  	mac->ops.set_ethertype_anti_spoofing =
67  			ixgbe_set_ethertype_anti_spoofing_X550;
68  
69  	mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
70  	eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
71  	eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
72  	eeprom->ops.read = ixgbe_read_ee_hostif_X550;
73  	eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
74  	eeprom->ops.write = ixgbe_write_ee_hostif_X550;
75  	eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
76  	eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
77  	eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
78  
79  	mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
80  	mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
81  	mac->ops.mdd_event = ixgbe_mdd_event_X550;
82  	mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
83  	mac->ops.disable_rx = ixgbe_disable_rx_x550;
84  	if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
85  		hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
86  		hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
87  	}
88  	return ret_val;
89  }
90  
91  /**
92   * ixgbe_read_cs4227 - Read CS4227 register
93   * @hw: pointer to hardware structure
94   * @reg: register number to write
95   * @value: pointer to receive value read
96   *
97   * Returns status code
98   **/
99  static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
100  {
101  	return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
102  }
103  
104  /**
105   * ixgbe_write_cs4227 - Write CS4227 register
106   * @hw: pointer to hardware structure
107   * @reg: register number to write
108   * @value: value to write to register
109   *
110   * Returns status code
111   **/
112  static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
113  {
114  	return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);
115  }
116  
117  /**
118   * ixgbe_read_pe - Read register from port expander
119   * @hw: pointer to hardware structure
120   * @reg: register number to read
121   * @value: pointer to receive read value
122   *
123   * Returns status code
124   **/
125  static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
126  {
127  	s32 status;
128  
129  	status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
130  	if (status != IXGBE_SUCCESS)
131  		ERROR_REPORT2(IXGBE_ERROR_CAUTION,
132  			      "port expander access failed with %d\n", status);
133  	return status;
134  }
135  
136  /**
137   * ixgbe_write_pe - Write register to port expander
138   * @hw: pointer to hardware structure
139   * @reg: register number to write
140   * @value: value to write
141   *
142   * Returns status code
143   **/
144  static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
145  {
146  	s32 status;
147  
148  	status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
149  	if (status != IXGBE_SUCCESS)
150  		ERROR_REPORT2(IXGBE_ERROR_CAUTION,
151  			      "port expander access failed with %d\n", status);
152  	return status;
153  }
154  
155  /**
156   * ixgbe_reset_cs4227 - Reset CS4227 using port expander
157   * @hw: pointer to hardware structure
158   *
159   * This function assumes that the caller has acquired the proper semaphore.
160   * Returns error code
161   **/
162  static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
163  {
164  	s32 status;
165  	u32 retry;
166  	u16 value;
167  	u8 reg;
168  
169  	/* Trigger hard reset. */
170  	status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
171  	if (status != IXGBE_SUCCESS)
172  		return status;
173  	reg |= IXGBE_PE_BIT1;
174  	status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
175  	if (status != IXGBE_SUCCESS)
176  		return status;
177  
178  	status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
179  	if (status != IXGBE_SUCCESS)
180  		return status;
181  	reg &= ~IXGBE_PE_BIT1;
182  	status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
183  	if (status != IXGBE_SUCCESS)
184  		return status;
185  
186  	status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
187  	if (status != IXGBE_SUCCESS)
188  		return status;
189  	reg &= ~IXGBE_PE_BIT1;
190  	status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
191  	if (status != IXGBE_SUCCESS)
192  		return status;
193  
194  	usec_delay(IXGBE_CS4227_RESET_HOLD);
195  
196  	status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
197  	if (status != IXGBE_SUCCESS)
198  		return status;
199  	reg |= IXGBE_PE_BIT1;
200  	status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
201  	if (status != IXGBE_SUCCESS)
202  		return status;
203  
204  	/* Wait for the reset to complete. */
205  	msec_delay(IXGBE_CS4227_RESET_DELAY);
206  	for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
207  		status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
208  					   &value);
209  		if (status == IXGBE_SUCCESS &&
210  		    value == IXGBE_CS4227_EEPROM_LOAD_OK)
211  			break;
212  		msec_delay(IXGBE_CS4227_CHECK_DELAY);
213  	}
214  	if (retry == IXGBE_CS4227_RETRIES) {
215  		ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
216  			"CS4227 reset did not complete.");
217  		return IXGBE_ERR_PHY;
218  	}
219  
220  	status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
221  	if (status != IXGBE_SUCCESS ||
222  	    !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
223  		ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
224  			"CS4227 EEPROM did not load successfully.");
225  		return IXGBE_ERR_PHY;
226  	}
227  
228  	return IXGBE_SUCCESS;
229  }
230  
231  /**
232   * ixgbe_check_cs4227 - Check CS4227 and reset as needed
233   * @hw: pointer to hardware structure
234   **/
235  static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
236  {
237  	s32 status = IXGBE_SUCCESS;
238  	u32 swfw_mask = hw->phy.phy_semaphore_mask;
239  	u16 value = 0;
240  	u8 retry;
241  
242  	for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
243  		status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
244  		if (status != IXGBE_SUCCESS) {
245  			ERROR_REPORT2(IXGBE_ERROR_CAUTION,
246  				"semaphore failed with %d", status);
247  			msec_delay(IXGBE_CS4227_CHECK_DELAY);
248  			continue;
249  		}
250  
251  		/* Get status of reset flow. */
252  		status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
253  
254  		if (status == IXGBE_SUCCESS &&
255  		    value == IXGBE_CS4227_RESET_COMPLETE)
256  			goto out;
257  
258  		if (status != IXGBE_SUCCESS ||
259  		    value != IXGBE_CS4227_RESET_PENDING)
260  			break;
261  
262  		/* Reset is pending. Wait and check again. */
263  		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
264  		msec_delay(IXGBE_CS4227_CHECK_DELAY);
265  	}
266  
267  	/* If still pending, assume other instance failed. */
268  	if (retry == IXGBE_CS4227_RETRIES) {
269  		status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
270  		if (status != IXGBE_SUCCESS) {
271  			ERROR_REPORT2(IXGBE_ERROR_CAUTION,
272  				      "semaphore failed with %d", status);
273  			return;
274  		}
275  	}
276  
277  	/* Reset the CS4227. */
278  	status = ixgbe_reset_cs4227(hw);
279  	if (status != IXGBE_SUCCESS) {
280  		ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
281  			"CS4227 reset failed: %d", status);
282  		goto out;
283  	}
284  
285  	/* Reset takes so long, temporarily release semaphore in case the
286  	 * other driver instance is waiting for the reset indication.
287  	 */
288  	ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
289  			   IXGBE_CS4227_RESET_PENDING);
290  	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
291  	msec_delay(10);
292  	status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
293  	if (status != IXGBE_SUCCESS) {
294  		ERROR_REPORT2(IXGBE_ERROR_CAUTION,
295  			"semaphore failed with %d", status);
296  		return;
297  	}
298  
299  	/* Record completion for next time. */
300  	status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
301  		IXGBE_CS4227_RESET_COMPLETE);
302  
303  out:
304  	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
305  	msec_delay(hw->eeprom.semaphore_delay);
306  }
307  
308  /**
309   * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
310   * @hw: pointer to hardware structure
311   **/
312  static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
313  {
314  	u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
315  
316  	if (hw->bus.lan_id) {
317  		esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
318  		esdp |= IXGBE_ESDP_SDP1_DIR;
319  	}
320  	esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
321  	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
322  	IXGBE_WRITE_FLUSH(hw);
323  }
324  
325  /**
326   * ixgbe_identify_phy_x550em - Get PHY type based on device id
327   * @hw: pointer to hardware structure
328   *
329   * Returns error code
330   */
331  static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
332  {
333  	switch (hw->device_id) {
334  	case IXGBE_DEV_ID_X550EM_X_SFP:
335  		/* set up for CS4227 usage */
336  		hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
337  		ixgbe_setup_mux_ctl(hw);
338  		ixgbe_check_cs4227(hw);
339  
340  		return ixgbe_identify_module_generic(hw);
341  		break;
342  	case IXGBE_DEV_ID_X550EM_X_KX4:
343  		hw->phy.type = ixgbe_phy_x550em_kx4;
344  		break;
345  	case IXGBE_DEV_ID_X550EM_X_KR:
346  		hw->phy.type = ixgbe_phy_x550em_kr;
347  		break;
348  	case IXGBE_DEV_ID_X550EM_X_1G_T:
349  	case IXGBE_DEV_ID_X550EM_X_10G_T:
350  		return ixgbe_identify_phy_generic(hw);
351  	default:
352  		break;
353  	}
354  	return IXGBE_SUCCESS;
355  }
356  
357  static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
358  				     u32 device_type, u16 *phy_data)
359  {
360  	UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
361  	return IXGBE_NOT_IMPLEMENTED;
362  }
363  
364  static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
365  				      u32 device_type, u16 phy_data)
366  {
367  	UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
368  	return IXGBE_NOT_IMPLEMENTED;
369  }
370  
371  /**
372  *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
373  *  @hw: pointer to hardware structure
374  *
375  *  Initialize the function pointers and for MAC type X550EM.
376  *  Does not touch the hardware.
377  **/
378  s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
379  {
380  	struct ixgbe_mac_info *mac = &hw->mac;
381  	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
382  	struct ixgbe_phy_info *phy = &hw->phy;
383  	s32 ret_val;
384  
385  	DEBUGFUNC("ixgbe_init_ops_X550EM");
386  
387  	/* Similar to X550 so start there. */
388  	ret_val = ixgbe_init_ops_X550(hw);
389  
390  	/* Since this function eventually calls
391  	 * ixgbe_init_ops_540 by design, we are setting
392  	 * the pointers to NULL explicitly here to overwrite
393  	 * the values being set in the x540 function.
394  	 */
395  
396  	/* FCOE not supported in x550EM */
397  	mac->ops.get_san_mac_addr = NULL;
398  	mac->ops.set_san_mac_addr = NULL;
399  	mac->ops.get_wwn_prefix = NULL;
400  	mac->ops.get_fcoe_boot_status = NULL;
401  
402  	/* IPsec not supported in x550EM */
403  	mac->ops.disable_sec_rx_path = NULL;
404  	mac->ops.enable_sec_rx_path = NULL;
405  
406  	/* AUTOC register is not present in x550EM. */
407  	mac->ops.prot_autoc_read = NULL;
408  	mac->ops.prot_autoc_write = NULL;
409  
410  	/* X550EM bus type is internal*/
411  	hw->bus.type = ixgbe_bus_type_internal;
412  	mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
413  
414  	if (hw->mac.type == ixgbe_mac_X550EM_x) {
415  		mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
416  		mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
417  	}
418  
419  	mac->ops.get_media_type = ixgbe_get_media_type_X550em;
420  	mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
421  	mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
422  	mac->ops.reset_hw = ixgbe_reset_hw_X550em;
423  	mac->ops.get_supported_physical_layer =
424  				    ixgbe_get_supported_physical_layer_X550em;
425  
426  	if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
427  		mac->ops.setup_fc = ixgbe_setup_fc_generic;
428  	else
429  		mac->ops.setup_fc = ixgbe_setup_fc_X550em;
430  
431  	mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
432  	mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
433  
434  	if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
435  		mac->ops.setup_eee = NULL;
436  
437  	/* PHY */
438  	phy->ops.init = ixgbe_init_phy_ops_X550em;
439  	phy->ops.identify = ixgbe_identify_phy_x550em;
440  	if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
441  		phy->ops.set_phy_power = NULL;
442  
443  
444  	/* EEPROM */
445  	eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
446  	eeprom->ops.read = ixgbe_read_ee_hostif_X550;
447  	eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
448  	eeprom->ops.write = ixgbe_write_ee_hostif_X550;
449  	eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
450  	eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
451  	eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
452  	eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
453  
454  	return ret_val;
455  }
456  
457  /**
458   *  ixgbe_dmac_config_X550
459   *  @hw: pointer to hardware structure
460   *
461   *  Configure DMA coalescing. If enabling dmac, dmac is activated.
462   *  When disabling dmac, dmac enable dmac bit is cleared.
463   **/
464  s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
465  {
466  	u32 reg, high_pri_tc;
467  
468  	DEBUGFUNC("ixgbe_dmac_config_X550");
469  
470  	/* Disable DMA coalescing before configuring */
471  	reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
472  	reg &= ~IXGBE_DMACR_DMAC_EN;
473  	IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
474  
475  	/* Disable DMA Coalescing if the watchdog timer is 0 */
476  	if (!hw->mac.dmac_config.watchdog_timer)
477  		goto out;
478  
479  	ixgbe_dmac_config_tcs_X550(hw);
480  
481  	/* Configure DMA Coalescing Control Register */
482  	reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
483  
484  	/* Set the watchdog timer in units of 40.96 usec */
485  	reg &= ~IXGBE_DMACR_DMACWT_MASK;
486  	reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
487  
488  	reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
489  	/* If fcoe is enabled, set high priority traffic class */
490  	if (hw->mac.dmac_config.fcoe_en) {
491  		high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
492  		reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
493  			IXGBE_DMACR_HIGH_PRI_TC_MASK);
494  	}
495  	reg |= IXGBE_DMACR_EN_MNG_IND;
496  
497  	/* Enable DMA coalescing after configuration */
498  	reg |= IXGBE_DMACR_DMAC_EN;
499  	IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
500  
501  out:
502  	return IXGBE_SUCCESS;
503  }
504  
505  /**
506   *  ixgbe_dmac_config_tcs_X550
507   *  @hw: pointer to hardware structure
508   *
509   *  Configure DMA coalescing threshold per TC. The dmac enable bit must
510   *  be cleared before configuring.
511   **/
512  s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
513  {
514  	u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
515  
516  	DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
517  
518  	/* Configure DMA coalescing enabled */
519  	switch (hw->mac.dmac_config.link_speed) {
520  	case IXGBE_LINK_SPEED_100_FULL:
521  		pb_headroom = IXGBE_DMACRXT_100M;
522  		break;
523  	case IXGBE_LINK_SPEED_1GB_FULL:
524  		pb_headroom = IXGBE_DMACRXT_1G;
525  		break;
526  	default:
527  		pb_headroom = IXGBE_DMACRXT_10G;
528  		break;
529  	}
530  
531  	maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
532  			     IXGBE_MHADD_MFS_SHIFT) / 1024);
533  
534  	/* Set the per Rx packet buffer receive threshold */
535  	for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
536  		reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
537  		reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
538  
539  		if (tc < hw->mac.dmac_config.num_tcs) {
540  			/* Get Rx PB size */
541  			rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
542  			rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
543  				IXGBE_RXPBSIZE_SHIFT;
544  
545  			/* Calculate receive buffer threshold in kilobytes */
546  			if (rx_pb_size > pb_headroom)
547  				rx_pb_size = rx_pb_size - pb_headroom;
548  			else
549  				rx_pb_size = 0;
550  
551  			/* Minimum of MFS shall be set for DMCTH */
552  			reg |= (rx_pb_size > maxframe_size_kb) ?
553  				rx_pb_size : maxframe_size_kb;
554  		}
555  		IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
556  	}
557  	return IXGBE_SUCCESS;
558  }
559  
560  /**
561   *  ixgbe_dmac_update_tcs_X550
562   *  @hw: pointer to hardware structure
563   *
564   *  Disables dmac, updates per TC settings, and then enables dmac.
565   **/
566  s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
567  {
568  	u32 reg;
569  
570  	DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
571  
572  	/* Disable DMA coalescing before configuring */
573  	reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
574  	reg &= ~IXGBE_DMACR_DMAC_EN;
575  	IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
576  
577  	ixgbe_dmac_config_tcs_X550(hw);
578  
579  	/* Enable DMA coalescing after configuration */
580  	reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
581  	reg |= IXGBE_DMACR_DMAC_EN;
582  	IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
583  
584  	return IXGBE_SUCCESS;
585  }
586  
587  /**
588   *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
589   *  @hw: pointer to hardware structure
590   *
591   *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
592   *  ixgbe_hw struct in order to set up EEPROM access.
593   **/
594  s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
595  {
596  	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
597  	u32 eec;
598  	u16 eeprom_size;
599  
600  	DEBUGFUNC("ixgbe_init_eeprom_params_X550");
601  
602  	if (eeprom->type == ixgbe_eeprom_uninitialized) {
603  		eeprom->semaphore_delay = 10;
604  		eeprom->type = ixgbe_flash;
605  
606  		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
607  		eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
608  				    IXGBE_EEC_SIZE_SHIFT);
609  		eeprom->word_size = 1 << (eeprom_size +
610  					  IXGBE_EEPROM_WORD_SIZE_SHIFT);
611  
612  		DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
613  			  eeprom->type, eeprom->word_size);
614  	}
615  
616  	return IXGBE_SUCCESS;
617  }
618  
619  /**
620   *  ixgbe_setup_eee_X550 - Enable/disable EEE support
621   *  @hw: pointer to the HW structure
622   *  @enable_eee: boolean flag to enable EEE
623   *
624   *  Enable/disable EEE based on enable_eee flag.
625   *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
626   *  are modified.
627   *
628   **/
629  s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
630  {
631  	u32 eeer;
632  	u16 autoneg_eee_reg;
633  	u32 link_reg;
634  	s32 status;
635  	u32 fuse;
636  
637  	DEBUGFUNC("ixgbe_setup_eee_X550");
638  
639  	eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
640  	/* Enable or disable EEE per flag */
641  	if (enable_eee) {
642  		eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
643  
644  		if (hw->mac.type == ixgbe_mac_X550) {
645  			/* Advertise EEE capability */
646  			hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
647  				IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
648  
649  			autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
650  				IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
651  				IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
652  
653  			hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
654  				IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
655  		} else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
656  			/* Not supported on first revision. */
657  			fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
658  			if (!(fuse & IXGBE_FUSES0_REV1))
659  				return IXGBE_SUCCESS;
660  
661  			status = ixgbe_read_iosf_sb_reg_x550(hw,
662  				IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
663  				IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
664  			if (status != IXGBE_SUCCESS)
665  				return status;
666  
667  			link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
668  				    IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
669  
670  			/* Don't advertise FEC capability when EEE enabled. */
671  			link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
672  
673  			status = ixgbe_write_iosf_sb_reg_x550(hw,
674  				IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
675  				IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
676  			if (status != IXGBE_SUCCESS)
677  				return status;
678  		}
679  	} else {
680  		eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
681  
682  		if (hw->mac.type == ixgbe_mac_X550) {
683  			/* Disable advertised EEE capability */
684  			hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
685  				IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
686  
687  			autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
688  				IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
689  				IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
690  
691  			hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
692  				IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
693  		} else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
694  			status = ixgbe_read_iosf_sb_reg_x550(hw,
695  				IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
696  				IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
697  			if (status != IXGBE_SUCCESS)
698  				return status;
699  
700  			link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
701  				IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
702  
703  			/* Advertise FEC capability when EEE is disabled. */
704  			link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
705  
706  			status = ixgbe_write_iosf_sb_reg_x550(hw,
707  				IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
708  				IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
709  			if (status != IXGBE_SUCCESS)
710  				return status;
711  		}
712  	}
713  	IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
714  
715  	return IXGBE_SUCCESS;
716  }
717  
718  /**
719   * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
720   * @hw: pointer to hardware structure
721   * @enable: enable or disable source address pruning
722   * @pool: Rx pool to set source address pruning for
723   **/
724  void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
725  					   unsigned int pool)
726  {
727  	u64 pfflp;
728  
729  	/* max rx pool is 63 */
730  	if (pool > 63)
731  		return;
732  
733  	pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
734  	pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
735  
736  	if (enable)
737  		pfflp |= (1ULL << pool);
738  	else
739  		pfflp &= ~(1ULL << pool);
740  
741  	IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
742  	IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
743  }
744  
745  /**
746   *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
747   *  @hw: pointer to hardware structure
748   *  @enable: enable or disable switch for Ethertype anti-spoofing
749   *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
750   *
751   **/
752  void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
753  		bool enable, int vf)
754  {
755  	int vf_target_reg = vf >> 3;
756  	int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
757  	u32 pfvfspoof;
758  
759  	DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
760  
761  	pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
762  	if (enable)
763  		pfvfspoof |= (1 << vf_target_shift);
764  	else
765  		pfvfspoof &= ~(1 << vf_target_shift);
766  
767  	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
768  }
769  
770  /**
771   * ixgbe_iosf_wait - Wait for IOSF command completion
772   * @hw: pointer to hardware structure
773   * @ctrl: pointer to location to receive final IOSF control value
774   *
775   * Returns failing status on timeout
776   *
777   * Note: ctrl can be NULL if the IOSF control register value is not needed
778   **/
779  static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
780  {
781  	u32 i, command = 0;
782  
783  	/* Check every 10 usec to see if the address cycle completed.
784  	 * The SB IOSF BUSY bit will clear when the operation is
785  	 * complete
786  	 */
787  	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
788  		command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
789  		if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
790  			break;
791  		usec_delay(10);
792  	}
793  	if (ctrl)
794  		*ctrl = command;
795  	if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
796  		ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
797  		return IXGBE_ERR_PHY;
798  	}
799  
800  	return IXGBE_SUCCESS;
801  }
802  
803  /**
804   *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
805   *  device
806   *  @hw: pointer to hardware structure
807   *  @reg_addr: 32 bit PHY register to write
808   *  @device_type: 3 bit device type
809   *  @data: Data to write to the register
810   **/
811  s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
812  			    u32 device_type, u32 data)
813  {
814  	u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
815  	u32 command, error;
816  	s32 ret;
817  
818  	ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
819  	if (ret != IXGBE_SUCCESS)
820  		return ret;
821  
822  	ret = ixgbe_iosf_wait(hw, NULL);
823  	if (ret != IXGBE_SUCCESS)
824  		goto out;
825  
826  	command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
827  		   (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
828  
829  	/* Write IOSF control register */
830  	IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
831  
832  	/* Write IOSF data register */
833  	IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
834  
835  	ret = ixgbe_iosf_wait(hw, &command);
836  
837  	if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
838  		error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
839  			 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
840  		ERROR_REPORT2(IXGBE_ERROR_POLLING,
841  			      "Failed to write, error %x\n", error);
842  		ret = IXGBE_ERR_PHY;
843  	}
844  
845  out:
846  	ixgbe_release_swfw_semaphore(hw, gssr);
847  	return ret;
848  }
849  
850  /**
851   *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
852   *  device
853   *  @hw: pointer to hardware structure
854   *  @reg_addr: 32 bit PHY register to write
855   *  @device_type: 3 bit device type
856   *  @phy_data: Pointer to read data from the register
857   **/
858  s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
859  			   u32 device_type, u32 *data)
860  {
861  	u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
862  	u32 command, error;
863  	s32 ret;
864  
865  	ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
866  	if (ret != IXGBE_SUCCESS)
867  		return ret;
868  
869  	ret = ixgbe_iosf_wait(hw, NULL);
870  	if (ret != IXGBE_SUCCESS)
871  		goto out;
872  
873  	command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
874  		   (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
875  
876  	/* Write IOSF control register */
877  	IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
878  
879  	ret = ixgbe_iosf_wait(hw, &command);
880  
881  	if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
882  		error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
883  			 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
884  		ERROR_REPORT2(IXGBE_ERROR_POLLING,
885  				"Failed to read, error %x\n", error);
886  		ret = IXGBE_ERR_PHY;
887  	}
888  
889  	if (ret == IXGBE_SUCCESS)
890  		*data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
891  
892  out:
893  	ixgbe_release_swfw_semaphore(hw, gssr);
894  	return ret;
895  }
896  
897  /**
898   *  ixgbe_disable_mdd_X550
899   *  @hw: pointer to hardware structure
900   *
901   *  Disable malicious driver detection
902   **/
903  void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
904  {
905  	u32 reg;
906  
907  	DEBUGFUNC("ixgbe_disable_mdd_X550");
908  
909  	/* Disable MDD for TX DMA and interrupt */
910  	reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
911  	reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
912  	IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
913  
914  	/* Disable MDD for RX and interrupt */
915  	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
916  	reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
917  	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
918  }
919  
920  /**
921   *  ixgbe_enable_mdd_X550
922   *  @hw: pointer to hardware structure
923   *
924   *  Enable malicious driver detection
925   **/
926  void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
927  {
928  	u32 reg;
929  
930  	DEBUGFUNC("ixgbe_enable_mdd_X550");
931  
932  	/* Enable MDD for TX DMA and interrupt */
933  	reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
934  	reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
935  	IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
936  
937  	/* Enable MDD for RX and interrupt */
938  	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
939  	reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
940  	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
941  }
942  
943  /**
944   *  ixgbe_restore_mdd_vf_X550
945   *  @hw: pointer to hardware structure
946   *  @vf: vf index
947   *
948   *  Restore VF that was disabled during malicious driver detection event
949   **/
950  void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
951  {
952  	u32 idx, reg, num_qs, start_q, bitmask;
953  
954  	DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
955  
956  	/* Map VF to queues */
957  	reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
958  	switch (reg & IXGBE_MRQC_MRQE_MASK) {
959  	case IXGBE_MRQC_VMDQRT8TCEN:
960  		num_qs = 8;  /* 16 VFs / pools */
961  		bitmask = 0x000000FF;
962  		break;
963  	case IXGBE_MRQC_VMDQRSS32EN:
964  	case IXGBE_MRQC_VMDQRT4TCEN:
965  		num_qs = 4;  /* 32 VFs / pools */
966  		bitmask = 0x0000000F;
967  		break;
968  	default:	    /* 64 VFs / pools */
969  		num_qs = 2;
970  		bitmask = 0x00000003;
971  		break;
972  	}
973  	start_q = vf * num_qs;
974  
975  	/* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
976  	idx = start_q / 32;
977  	reg = 0;
978  	reg |= (bitmask << (start_q % 32));
979  	IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
980  	IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
981  }
982  
983  /**
984   *  ixgbe_mdd_event_X550
985   *  @hw: pointer to hardware structure
986   *  @vf_bitmap: vf bitmap of malicious vfs
987   *
988   *  Handle malicious driver detection event.
989   **/
990  void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
991  {
992  	u32 wqbr;
993  	u32 i, j, reg, q, shift, vf, idx;
994  
995  	DEBUGFUNC("ixgbe_mdd_event_X550");
996  
997  	/* figure out pool size for mapping to vf's */
998  	reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
999  	switch (reg & IXGBE_MRQC_MRQE_MASK) {
1000  	case IXGBE_MRQC_VMDQRT8TCEN:
1001  		shift = 3;  /* 16 VFs / pools */
1002  		break;
1003  	case IXGBE_MRQC_VMDQRSS32EN:
1004  	case IXGBE_MRQC_VMDQRT4TCEN:
1005  		shift = 2;  /* 32 VFs / pools */
1006  		break;
1007  	default:
1008  		shift = 1;  /* 64 VFs / pools */
1009  		break;
1010  	}
1011  
1012  	/* Read WQBR_TX and WQBR_RX and check for malicious queues */
1013  	for (i = 0; i < 4; i++) {
1014  		wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1015  		wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1016  
1017  		if (!wqbr)
1018  			continue;
1019  
1020  		/* Get malicious queue */
1021  		for (j = 0; j < 32 && wqbr; j++) {
1022  
1023  			if (!(wqbr & (1 << j)))
1024  				continue;
1025  
1026  			/* Get queue from bitmask */
1027  			q = j + (i * 32);
1028  
1029  			/* Map queue to vf */
1030  			vf = (q >> shift);
1031  
1032  			/* Set vf bit in vf_bitmap */
1033  			idx = vf / 32;
1034  			vf_bitmap[idx] |= (1 << (vf % 32));
1035  			wqbr &= ~(1 << j);
1036  		}
1037  	}
1038  }
1039  
1040  /**
1041   *  ixgbe_get_media_type_X550em - Get media type
1042   *  @hw: pointer to hardware structure
1043   *
1044   *  Returns the media type (fiber, copper, backplane)
1045   */
1046  enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1047  {
1048  	enum ixgbe_media_type media_type;
1049  
1050  	DEBUGFUNC("ixgbe_get_media_type_X550em");
1051  
1052  	/* Detect if there is a copper PHY attached. */
1053  	switch (hw->device_id) {
1054  	case IXGBE_DEV_ID_X550EM_X_KR:
1055  	case IXGBE_DEV_ID_X550EM_X_KX4:
1056  		media_type = ixgbe_media_type_backplane;
1057  		break;
1058  	case IXGBE_DEV_ID_X550EM_X_SFP:
1059  		media_type = ixgbe_media_type_fiber;
1060  		break;
1061  	case IXGBE_DEV_ID_X550EM_X_1G_T:
1062  	case IXGBE_DEV_ID_X550EM_X_10G_T:
1063  		media_type = ixgbe_media_type_copper;
1064  		break;
1065  	default:
1066  		media_type = ixgbe_media_type_unknown;
1067  		break;
1068  	}
1069  	return media_type;
1070  }
1071  
1072  /**
1073   *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1074   *  @hw: pointer to hardware structure
1075   *  @linear: TRUE if SFP module is linear
1076   */
1077  static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1078  {
1079  	DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1080  
1081  	switch (hw->phy.sfp_type) {
1082  	case ixgbe_sfp_type_not_present:
1083  		return IXGBE_ERR_SFP_NOT_PRESENT;
1084  	case ixgbe_sfp_type_da_cu_core0:
1085  	case ixgbe_sfp_type_da_cu_core1:
1086  		*linear = TRUE;
1087  		break;
1088  	case ixgbe_sfp_type_srlr_core0:
1089  	case ixgbe_sfp_type_srlr_core1:
1090  	case ixgbe_sfp_type_da_act_lmt_core0:
1091  	case ixgbe_sfp_type_da_act_lmt_core1:
1092  	case ixgbe_sfp_type_1g_sx_core0:
1093  	case ixgbe_sfp_type_1g_sx_core1:
1094  	case ixgbe_sfp_type_1g_lx_core0:
1095  	case ixgbe_sfp_type_1g_lx_core1:
1096  		*linear = FALSE;
1097  		break;
1098  	case ixgbe_sfp_type_unknown:
1099  	case ixgbe_sfp_type_1g_cu_core0:
1100  	case ixgbe_sfp_type_1g_cu_core1:
1101  	default:
1102  		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1103  	}
1104  
1105  	return IXGBE_SUCCESS;
1106  }
1107  
1108  /**
1109   *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1110   *  @hw: pointer to hardware structure
1111   *
1112   *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1113   **/
1114  s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1115  {
1116  	s32 status;
1117  	bool linear;
1118  
1119  	DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1120  
1121  	status = ixgbe_identify_module_generic(hw);
1122  
1123  	if (status != IXGBE_SUCCESS)
1124  		return status;
1125  
1126  	/* Check if SFP module is supported */
1127  	status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1128  
1129  	return status;
1130  }
1131  
1132  /**
1133   *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1134   *  @hw: pointer to hardware structure
1135   */
1136  s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1137  {
1138  	s32 status;
1139  	bool linear;
1140  
1141  	DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1142  
1143  	/* Check if SFP module is supported */
1144  	status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1145  
1146  	if (status != IXGBE_SUCCESS)
1147  		return status;
1148  
1149  	ixgbe_init_mac_link_ops_X550em(hw);
1150  	hw->phy.ops.reset = NULL;
1151  
1152  	return IXGBE_SUCCESS;
1153  }
1154  
1155  /**
1156   *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1157   *  @hw: pointer to hardware structure
1158   */
1159  void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1160  {
1161  	struct ixgbe_mac_info *mac = &hw->mac;
1162  
1163  	DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1164  
1165  	 switch (hw->mac.ops.get_media_type(hw)) {
1166  	 case ixgbe_media_type_fiber:
1167  		/* CS4227 does not support autoneg, so disable the laser control
1168  		 * functions for SFP+ fiber
1169  		 */
1170  		mac->ops.disable_tx_laser = NULL;
1171  		mac->ops.enable_tx_laser = NULL;
1172  		mac->ops.flap_tx_laser = NULL;
1173  		mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1174  		mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1175  		mac->ops.set_rate_select_speed =
1176  					ixgbe_set_soft_rate_select_speed;
1177  		break;
1178  	case ixgbe_media_type_copper:
1179  		mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1180  		mac->ops.check_link = ixgbe_check_link_t_X550em;
1181  		break;
1182  	default:
1183  		break;
1184  	 }
1185  }
1186  
1187  /**
1188   *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1189   *  @hw: pointer to hardware structure
1190   *  @speed: pointer to link speed
1191   *  @autoneg: TRUE when autoneg or autotry is enabled
1192   */
1193  s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1194  				       ixgbe_link_speed *speed,
1195  				       bool *autoneg)
1196  {
1197  	DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1198  
1199  	/* SFP */
1200  	if (hw->phy.media_type == ixgbe_media_type_fiber) {
1201  
1202  		/* CS4227 SFP must not enable auto-negotiation */
1203  		*autoneg = FALSE;
1204  
1205  		/* Check if 1G SFP module. */
1206  		if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1207  		    hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1208  		    || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1209  		    hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1210  			*speed = IXGBE_LINK_SPEED_1GB_FULL;
1211  			return IXGBE_SUCCESS;
1212  		}
1213  
1214  		/* Link capabilities are based on SFP */
1215  		if (hw->phy.multispeed_fiber)
1216  			*speed = IXGBE_LINK_SPEED_10GB_FULL |
1217  				 IXGBE_LINK_SPEED_1GB_FULL;
1218  		else
1219  			*speed = IXGBE_LINK_SPEED_10GB_FULL;
1220  	} else {
1221  		*speed = IXGBE_LINK_SPEED_10GB_FULL |
1222  			 IXGBE_LINK_SPEED_1GB_FULL;
1223  		*autoneg = TRUE;
1224  	}
1225  
1226  	return IXGBE_SUCCESS;
1227  }
1228  
1229  /**
1230   * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1231   * @hw: pointer to hardware structure
1232   * @lsc: pointer to boolean flag which indicates whether external Base T
1233   *       PHY interrupt is lsc
1234   *
1235   * Determime if external Base T PHY interrupt cause is high temperature
1236   * failure alarm or link status change.
1237   *
1238   * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1239   * failure alarm, else return PHY access status.
1240   */
1241  static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1242  {
1243  	u32 status;
1244  	u16 reg;
1245  
1246  	*lsc = FALSE;
1247  
1248  	/* Vendor alarm triggered */
1249  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1250  				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1251  				      &reg);
1252  
1253  	if (status != IXGBE_SUCCESS ||
1254  	    !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1255  		return status;
1256  
1257  	/* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1258  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1259  				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1260  				      &reg);
1261  
1262  	if (status != IXGBE_SUCCESS ||
1263  	    !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1264  	    IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1265  		return status;
1266  
1267  	/* Global alarm triggered */
1268  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1269  				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1270  				      &reg);
1271  
1272  	if (status != IXGBE_SUCCESS)
1273  		return status;
1274  
1275  	/* If high temperature failure, then return over temp error and exit */
1276  	if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1277  		/* power down the PHY in case the PHY FW didn't already */
1278  		ixgbe_set_copper_phy_power(hw, FALSE);
1279  		return IXGBE_ERR_OVERTEMP;
1280  	} else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1281  		/*  device fault alarm triggered */
1282  		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1283  					  IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1284  					  &reg);
1285  
1286  		if (status != IXGBE_SUCCESS)
1287  			return status;
1288  
1289  		/* if device fault was due to high temp alarm handle and exit */
1290  		if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1291  			/* power down the PHY in case the PHY FW didn't */
1292  			ixgbe_set_copper_phy_power(hw, FALSE);
1293  			return IXGBE_ERR_OVERTEMP;
1294  		}
1295  	}
1296  
1297  	/* Vendor alarm 2 triggered */
1298  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1299  				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1300  
1301  	if (status != IXGBE_SUCCESS ||
1302  	    !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1303  		return status;
1304  
1305  	/* link connect/disconnect event occurred */
1306  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1307  				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1308  
1309  	if (status != IXGBE_SUCCESS)
1310  		return status;
1311  
1312  	/* Indicate LSC */
1313  	if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1314  		*lsc = TRUE;
1315  
1316  	return IXGBE_SUCCESS;
1317  }
1318  
1319  /**
1320   * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1321   * @hw: pointer to hardware structure
1322   *
1323   * Enable link status change and temperature failure alarm for the external
1324   * Base T PHY
1325   *
1326   * Returns PHY access status
1327   */
1328  static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1329  {
1330  	u32 status;
1331  	u16 reg;
1332  	bool lsc;
1333  
1334  	/* Clear interrupt flags */
1335  	status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1336  
1337  	/* Enable link status change alarm */
1338  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1339  				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1340  
1341  	if (status != IXGBE_SUCCESS)
1342  		return status;
1343  
1344  	reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1345  
1346  	status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1347  				       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1348  
1349  	if (status != IXGBE_SUCCESS)
1350  		return status;
1351  
1352  	/* Enables high temperature failure alarm */
1353  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1354  				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1355  				      &reg);
1356  
1357  	if (status != IXGBE_SUCCESS)
1358  		return status;
1359  
1360  	reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;
1361  
1362  	status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1363  				       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1364  				       reg);
1365  
1366  	if (status != IXGBE_SUCCESS)
1367  		return status;
1368  
1369  	/* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1370  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1371  				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1372  				      &reg);
1373  
1374  	if (status != IXGBE_SUCCESS)
1375  		return status;
1376  
1377  	reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1378  		IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1379  
1380  	status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1381  				       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1382  				       reg);
1383  
1384  	if (status != IXGBE_SUCCESS)
1385  		return status;
1386  
1387  	/* Enable chip-wide vendor alarm */
1388  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1389  				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1390  				      &reg);
1391  
1392  	if (status != IXGBE_SUCCESS)
1393  		return status;
1394  
1395  	reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1396  
1397  	status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1398  				       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1399  				       reg);
1400  
1401  	return status;
1402  }
1403  
1404  /**
1405   *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1406   *  @hw: pointer to hardware structure
1407   *  @speed: link speed
1408   *
1409   *  Configures the integrated KR PHY.
1410   **/
1411  static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1412  				       ixgbe_link_speed speed)
1413  {
1414  	s32 status;
1415  	u32 reg_val;
1416  
1417  	status = ixgbe_read_iosf_sb_reg_x550(hw,
1418  		IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1419  		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1420  	if (status)
1421  		return status;
1422  
1423  	reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1424  	reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1425  		     IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1426  
1427  	/* Advertise 10G support. */
1428  	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1429  		reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1430  
1431  	/* Advertise 1G support. */
1432  	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1433  		reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1434  
1435  	/* Restart auto-negotiation. */
1436  	reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1437  	status = ixgbe_write_iosf_sb_reg_x550(hw,
1438  		IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1439  		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1440  
1441  	return status;
1442  }
1443  
1444  /**
1445   *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1446   *  @hw: pointer to hardware structure
1447   *
1448   *  Initialize any function pointers that were not able to be
1449   *  set during init_shared_code because the PHY/SFP type was
1450   *  not known.  Perform the SFP init if necessary.
1451   */
1452  s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1453  {
1454  	struct ixgbe_phy_info *phy = &hw->phy;
1455  	ixgbe_link_speed speed;
1456  	s32 ret_val;
1457  
1458  	DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1459  
1460  	hw->mac.ops.set_lan_id(hw);
1461  
1462  	if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1463  		phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1464  		ixgbe_setup_mux_ctl(hw);
1465  
1466  		/* Save NW management interface connected on board. This is used
1467  		 * to determine internal PHY mode.
1468  		 */
1469  		phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1470  		if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
1471  			speed = IXGBE_LINK_SPEED_10GB_FULL |
1472  				IXGBE_LINK_SPEED_1GB_FULL;
1473  		}
1474  		phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1475  	}
1476  
1477  	/* Identify the PHY or SFP module */
1478  	ret_val = phy->ops.identify(hw);
1479  	if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1480  		return ret_val;
1481  
1482  	/* Setup function pointers based on detected hardware */
1483  	ixgbe_init_mac_link_ops_X550em(hw);
1484  	if (phy->sfp_type != ixgbe_sfp_type_unknown)
1485  		phy->ops.reset = NULL;
1486  
1487  	/* Set functions pointers based on phy type */
1488  	switch (hw->phy.type) {
1489  	case ixgbe_phy_x550em_kx4:
1490  		phy->ops.setup_link = NULL;
1491  		phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1492  		phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1493  		break;
1494  	case ixgbe_phy_x550em_kr:
1495  		phy->ops.setup_link = ixgbe_setup_kr_x550em;
1496  		phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1497  		phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1498  		break;
1499  	case ixgbe_phy_x550em_ext_t:
1500  		/* Save NW management interface connected on board. This is used
1501  		 * to determine internal PHY mode
1502  		 */
1503  		phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1504  
1505  		/* If internal link mode is XFI, then setup iXFI internal link,
1506  		 * else setup KR now.
1507  		 */
1508  		if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1509  			phy->ops.setup_internal_link =
1510  					      ixgbe_setup_internal_phy_t_x550em;
1511  		} else {
1512  			speed = IXGBE_LINK_SPEED_10GB_FULL |
1513  				IXGBE_LINK_SPEED_1GB_FULL;
1514  			ret_val = ixgbe_setup_kr_speed_x550em(hw, speed);
1515  		}
1516  
1517  		/* setup SW LPLU only for first revision */
1518  		if (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,
1519  						       IXGBE_FUSES0_GROUP(0))))
1520  			phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1521  
1522  		phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1523  		phy->ops.reset = ixgbe_reset_phy_t_X550em;
1524  		break;
1525  	default:
1526  		break;
1527  	}
1528  	return ret_val;
1529  }
1530  
1531  /**
1532   *  ixgbe_reset_hw_X550em - Perform hardware reset
1533   *  @hw: pointer to hardware structure
1534   *
1535   *  Resets the hardware by resetting the transmit and receive units, masks
1536   *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1537   *  reset.
1538   */
1539  s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1540  {
1541  	ixgbe_link_speed link_speed;
1542  	s32 status;
1543  	u32 ctrl = 0;
1544  	u32 i;
1545  	u32 hlreg0;
1546  	bool link_up = FALSE;
1547  
1548  	DEBUGFUNC("ixgbe_reset_hw_X550em");
1549  
1550  	/* Call adapter stop to disable Tx/Rx and clear interrupts */
1551  	status = hw->mac.ops.stop_adapter(hw);
1552  	if (status != IXGBE_SUCCESS)
1553  		return status;
1554  
1555  	/* flush pending Tx transactions */
1556  	ixgbe_clear_tx_pending(hw);
1557  
1558  	if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
1559  		/* Config MDIO clock speed before the first MDIO PHY access */
1560  		hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1561  		hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1562  		IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1563  	}
1564  
1565  	/* PHY ops must be identified and initialized prior to reset */
1566  	status = hw->phy.ops.init(hw);
1567  
1568  	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1569  		return status;
1570  
1571  	/* start the external PHY */
1572  	if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1573  		status = ixgbe_init_ext_t_x550em(hw);
1574  		if (status)
1575  			return status;
1576  	}
1577  
1578  	/* Setup SFP module if there is one present. */
1579  	if (hw->phy.sfp_setup_needed) {
1580  		status = hw->mac.ops.setup_sfp(hw);
1581  		hw->phy.sfp_setup_needed = FALSE;
1582  	}
1583  
1584  	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1585  		return status;
1586  
1587  	/* Reset PHY */
1588  	if (!hw->phy.reset_disable && hw->phy.ops.reset)
1589  		hw->phy.ops.reset(hw);
1590  
1591  mac_reset_top:
1592  	/* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1593  	 * If link reset is used when link is up, it might reset the PHY when
1594  	 * mng is using it.  If link is down or the flag to force full link
1595  	 * reset is set, then perform link reset.
1596  	 */
1597  	ctrl = IXGBE_CTRL_LNK_RST;
1598  	if (!hw->force_full_reset) {
1599  		hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1600  		if (link_up)
1601  			ctrl = IXGBE_CTRL_RST;
1602  	}
1603  
1604  	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1605  	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1606  	IXGBE_WRITE_FLUSH(hw);
1607  
1608  	/* Poll for reset bit to self-clear meaning reset is complete */
1609  	for (i = 0; i < 10; i++) {
1610  		usec_delay(1);
1611  		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1612  		if (!(ctrl & IXGBE_CTRL_RST_MASK))
1613  			break;
1614  	}
1615  
1616  	if (ctrl & IXGBE_CTRL_RST_MASK) {
1617  		status = IXGBE_ERR_RESET_FAILED;
1618  		DEBUGOUT("Reset polling failed to complete.\n");
1619  	}
1620  
1621  	msec_delay(50);
1622  
1623  	/* Double resets are required for recovery from certain error
1624  	 * conditions.  Between resets, it is necessary to stall to
1625  	 * allow time for any pending HW events to complete.
1626  	 */
1627  	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1628  		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1629  		goto mac_reset_top;
1630  	}
1631  
1632  	/* Store the permanent mac address */
1633  	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1634  
1635  	/* Store MAC address from RAR0, clear receive address registers, and
1636  	 * clear the multicast table.  Also reset num_rar_entries to 128,
1637  	 * since we modify this value when programming the SAN MAC address.
1638  	 */
1639  	hw->mac.num_rar_entries = 128;
1640  	hw->mac.ops.init_rx_addrs(hw);
1641  
1642  	if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1643  		ixgbe_setup_mux_ctl(hw);
1644  
1645  	return status;
1646  }
1647  
1648  /**
1649   * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1650   * @hw: pointer to hardware structure
1651   */
1652  s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1653  {
1654  	u32 status;
1655  	u16 reg;
1656  
1657  	status = hw->phy.ops.read_reg(hw,
1658  				      IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1659  				      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1660  				      &reg);
1661  
1662  	if (status != IXGBE_SUCCESS)
1663  		return status;
1664  
1665  	/* If PHY FW reset completed bit is set then this is the first
1666  	 * SW instance after a power on so the PHY FW must be un-stalled.
1667  	 */
1668  	if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1669  		status = hw->phy.ops.read_reg(hw,
1670  					IXGBE_MDIO_GLOBAL_RES_PR_10,
1671  					IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1672  					&reg);
1673  
1674  		if (status != IXGBE_SUCCESS)
1675  			return status;
1676  
1677  		reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1678  
1679  		status = hw->phy.ops.write_reg(hw,
1680  					IXGBE_MDIO_GLOBAL_RES_PR_10,
1681  					IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1682  					reg);
1683  
1684  		if (status != IXGBE_SUCCESS)
1685  			return status;
1686  	}
1687  
1688  	return status;
1689  }
1690  
1691  /**
1692   *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1693   *  @hw: pointer to hardware structure
1694   *
1695   *  Configures the integrated KR PHY.
1696   **/
1697  s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1698  {
1699  	return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1700  }
1701  
1702  /**
1703   *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1704   *  @hw: pointer to hardware structure
1705   *
1706   *  Configure the external PHY and the integrated KR PHY for SFP support.
1707   **/
1708  s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1709  				    ixgbe_link_speed speed,
1710  				    bool autoneg_wait_to_complete)
1711  {
1712  	s32 ret_val;
1713  	u16 reg_slice, reg_val;
1714  	bool setup_linear = FALSE;
1715  	UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1716  
1717  	/* Check if SFP module is supported and linear */
1718  	ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1719  
1720  	/* If no SFP module present, then return success. Return success since
1721  	 * there is no reason to configure CS4227 and SFP not present error is
1722  	 * not excepted in the setup MAC link flow.
1723  	 */
1724  	if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1725  		return IXGBE_SUCCESS;
1726  
1727  	if (ret_val != IXGBE_SUCCESS)
1728  		return ret_val;
1729  
1730  	if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1731  		/* Configure CS4227 LINE side to 10G SR. */
1732  		reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1733  			    (hw->bus.lan_id << 12);
1734  		reg_val = IXGBE_CS4227_SPEED_10G;
1735  		ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1736  						   reg_val);
1737  
1738  		reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1739  			    (hw->bus.lan_id << 12);
1740  		reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1741  		ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1742  						   reg_val);
1743  
1744  		/* Configure CS4227 for HOST connection rate then type. */
1745  		reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1746  			    (hw->bus.lan_id << 12);
1747  		reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1748  		IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1749  		ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1750  						   reg_val);
1751  
1752  		reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1753  			    (hw->bus.lan_id << 12);
1754  		if (setup_linear)
1755  			reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1756  		else
1757  			reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1758  		ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1759  						   reg_val);
1760  
1761  		/* Setup XFI internal link. */
1762  		ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
1763  	} else {
1764  		/* Configure internal PHY for KR/KX. */
1765  		ixgbe_setup_kr_speed_x550em(hw, speed);
1766  
1767  		/* Configure CS4227 LINE side to proper mode. */
1768  		reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1769  			    (hw->bus.lan_id << 12);
1770  		if (setup_linear)
1771  			reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1772  		else
1773  			reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1774  		ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
1775  						   reg_val);
1776  	}
1777  	return ret_val;
1778  }
1779  
1780  /**
1781   *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1782   *  @hw: pointer to hardware structure
1783   *  @speed: the link speed to force
1784   *
1785   *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1786   *  internal and external PHY at a specific speed, without autonegotiation.
1787   **/
1788  static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1789  {
1790  	s32 status;
1791  	u32 reg_val;
1792  
1793  	/* Disable AN and force speed to 10G Serial. */
1794  	status = ixgbe_read_iosf_sb_reg_x550(hw,
1795  					IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1796  					IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1797  	if (status != IXGBE_SUCCESS)
1798  		return status;
1799  
1800  	reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1801  	reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1802  
1803  	/* Select forced link speed for internal PHY. */
1804  	switch (*speed) {
1805  	case IXGBE_LINK_SPEED_10GB_FULL:
1806  		reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1807  		break;
1808  	case IXGBE_LINK_SPEED_1GB_FULL:
1809  		reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1810  		break;
1811  	default:
1812  		/* Other link speeds are not supported by internal KR PHY. */
1813  		return IXGBE_ERR_LINK_SETUP;
1814  	}
1815  
1816  	status = ixgbe_write_iosf_sb_reg_x550(hw,
1817  					IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1818  					IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1819  	if (status != IXGBE_SUCCESS)
1820  		return status;
1821  
1822  	/* Disable training protocol FSM. */
1823  	status = ixgbe_read_iosf_sb_reg_x550(hw,
1824  				IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1825  				IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1826  	if (status != IXGBE_SUCCESS)
1827  		return status;
1828  	reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1829  	status = ixgbe_write_iosf_sb_reg_x550(hw,
1830  				IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1831  				IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1832  	if (status != IXGBE_SUCCESS)
1833  		return status;
1834  
1835  	/* Disable Flex from training TXFFE. */
1836  	status = ixgbe_read_iosf_sb_reg_x550(hw,
1837  				IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1838  				IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1839  	if (status != IXGBE_SUCCESS)
1840  		return status;
1841  	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1842  	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1843  	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1844  	status = ixgbe_write_iosf_sb_reg_x550(hw,
1845  				IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1846  				IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1847  	if (status != IXGBE_SUCCESS)
1848  		return status;
1849  	status = ixgbe_read_iosf_sb_reg_x550(hw,
1850  				IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1851  				IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1852  	if (status != IXGBE_SUCCESS)
1853  		return status;
1854  	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1855  	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1856  	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1857  	status = ixgbe_write_iosf_sb_reg_x550(hw,
1858  				IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1859  				IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1860  	if (status != IXGBE_SUCCESS)
1861  		return status;
1862  
1863  	/* Enable override for coefficients. */
1864  	status = ixgbe_read_iosf_sb_reg_x550(hw,
1865  				IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1866  				IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1867  	if (status != IXGBE_SUCCESS)
1868  		return status;
1869  	reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1870  	reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1871  	reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1872  	reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1873  	status = ixgbe_write_iosf_sb_reg_x550(hw,
1874  				IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1875  				IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1876  	if (status != IXGBE_SUCCESS)
1877  		return status;
1878  
1879  	/* Toggle port SW reset by AN reset. */
1880  	status = ixgbe_read_iosf_sb_reg_x550(hw,
1881  					IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1882  					IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1883  	if (status != IXGBE_SUCCESS)
1884  		return status;
1885  	reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1886  	status = ixgbe_write_iosf_sb_reg_x550(hw,
1887  					IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1888  					IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1889  
1890  	return status;
1891  }
1892  
1893  /**
1894   * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1895   * @hw: address of hardware structure
1896   * @link_up: address of boolean to indicate link status
1897   *
1898   * Returns error code if unable to get link status.
1899   */
1900  static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
1901  {
1902  	u32 ret;
1903  	u16 autoneg_status;
1904  
1905  	*link_up = FALSE;
1906  
1907  	/* read this twice back to back to indicate current status */
1908  	ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1909  				   IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1910  				   &autoneg_status);
1911  	if (ret != IXGBE_SUCCESS)
1912  		return ret;
1913  
1914  	ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1915  				   IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1916  				   &autoneg_status);
1917  	if (ret != IXGBE_SUCCESS)
1918  		return ret;
1919  
1920  	*link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
1921  
1922  	return IXGBE_SUCCESS;
1923  }
1924  
1925  /**
1926   * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1927   * @hw: point to hardware structure
1928   *
1929   * Configures the link between the integrated KR PHY and the external X557 PHY
1930   * The driver will call this function when it gets a link status change
1931   * interrupt from the X557 PHY. This function configures the link speed
1932   * between the PHYs to match the link speed of the BASE-T link.
1933   *
1934   * A return of a non-zero value indicates an error, and the base driver should
1935   * not report link up.
1936   */
1937  s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
1938  {
1939  	ixgbe_link_speed force_speed;
1940  	bool link_up;
1941  	u32 status;
1942  	u16 speed;
1943  
1944  	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1945  		return IXGBE_ERR_CONFIG;
1946  
1947  	/* If link is not up, then there is no setup necessary so return  */
1948  	status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1949  	if (status != IXGBE_SUCCESS)
1950  		return status;
1951  
1952  	if (!link_up)
1953  		return IXGBE_SUCCESS;
1954  
1955  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1956  				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1957  				      &speed);
1958  	if (status != IXGBE_SUCCESS)
1959  		return status;
1960  
1961  	/* If link is not still up, then no setup is necessary so return */
1962  	status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
1963  	if (status != IXGBE_SUCCESS)
1964  		return status;
1965  	if (!link_up)
1966  		return IXGBE_SUCCESS;
1967  
1968  	/* clear everything but the speed and duplex bits */
1969  	speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1970  
1971  	switch (speed) {
1972  	case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1973  		force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1974  		break;
1975  	case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1976  		force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1977  		break;
1978  	default:
1979  		/* Internal PHY does not support anything else */
1980  		return IXGBE_ERR_INVALID_LINK_SETTINGS;
1981  	}
1982  
1983  	return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1984  }
1985  
1986  /**
1987   *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1988   *  @hw: pointer to hardware structure
1989   *
1990   *  Configures the integrated KR PHY to use internal loopback mode.
1991   **/
1992  s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1993  {
1994  	s32 status;
1995  	u32 reg_val;
1996  
1997  	/* Disable AN and force speed to 10G Serial. */
1998  	status = ixgbe_read_iosf_sb_reg_x550(hw,
1999  		IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2000  		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2001  	if (status != IXGBE_SUCCESS)
2002  		return status;
2003  	reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2004  	reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2005  	reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2006  	status = ixgbe_write_iosf_sb_reg_x550(hw,
2007  		IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2008  		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2009  	if (status != IXGBE_SUCCESS)
2010  		return status;
2011  
2012  	/* Set near-end loopback clocks. */
2013  	status = ixgbe_read_iosf_sb_reg_x550(hw,
2014  		IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2015  		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2016  	if (status != IXGBE_SUCCESS)
2017  		return status;
2018  	reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2019  	reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2020  	status = ixgbe_write_iosf_sb_reg_x550(hw,
2021  		IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2022  		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2023  	if (status != IXGBE_SUCCESS)
2024  		return status;
2025  
2026  	/* Set loopback enable. */
2027  	status = ixgbe_read_iosf_sb_reg_x550(hw,
2028  		IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2029  		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2030  	if (status != IXGBE_SUCCESS)
2031  		return status;
2032  	reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2033  	status = ixgbe_write_iosf_sb_reg_x550(hw,
2034  		IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2035  		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2036  	if (status != IXGBE_SUCCESS)
2037  		return status;
2038  
2039  	/* Training bypass. */
2040  	status = ixgbe_read_iosf_sb_reg_x550(hw,
2041  		IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2042  		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2043  	if (status != IXGBE_SUCCESS)
2044  		return status;
2045  	reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2046  	status = ixgbe_write_iosf_sb_reg_x550(hw,
2047  		IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2048  		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2049  
2050  	return status;
2051  }
2052  
2053  /**
2054   *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2055   *  assuming that the semaphore is already obtained.
2056   *  @hw: pointer to hardware structure
2057   *  @offset: offset of  word in the EEPROM to read
2058   *  @data: word read from the EEPROM
2059   *
2060   *  Reads a 16 bit word from the EEPROM using the hostif.
2061   **/
2062  s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2063  				   u16 *data)
2064  {
2065  	s32 status;
2066  	struct ixgbe_hic_read_shadow_ram buffer;
2067  
2068  	DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2069  	buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2070  	buffer.hdr.req.buf_lenh = 0;
2071  	buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2072  	buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2073  
2074  	/* convert offset from words to bytes */
2075  	buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2076  	/* one word */
2077  	buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2078  
2079  	status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2080  					      sizeof(buffer),
2081  					      IXGBE_HI_COMMAND_TIMEOUT, FALSE);
2082  
2083  	if (status)
2084  		return status;
2085  
2086  	*data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2087  					  FW_NVM_DATA_OFFSET);
2088  
2089  	return 0;
2090  }
2091  
2092  /**
2093   *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2094   *  @hw: pointer to hardware structure
2095   *  @offset: offset of  word in the EEPROM to read
2096   *  @data: word read from the EEPROM
2097   *
2098   *  Reads a 16 bit word from the EEPROM using the hostif.
2099   **/
2100  s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2101  			      u16 *data)
2102  {
2103  	s32 status = IXGBE_SUCCESS;
2104  
2105  	DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2106  
2107  	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2108  	    IXGBE_SUCCESS) {
2109  		status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2110  		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2111  	} else {
2112  		status = IXGBE_ERR_SWFW_SYNC;
2113  	}
2114  
2115  	return status;
2116  }
2117  
2118  /**
2119   *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2120   *  @hw: pointer to hardware structure
2121   *  @offset: offset of  word in the EEPROM to read
2122   *  @words: number of words
2123   *  @data: word(s) read from the EEPROM
2124   *
2125   *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2126   **/
2127  s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2128  				     u16 offset, u16 words, u16 *data)
2129  {
2130  	struct ixgbe_hic_read_shadow_ram buffer;
2131  	u32 current_word = 0;
2132  	u16 words_to_read;
2133  	s32 status;
2134  	u32 i;
2135  
2136  	DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2137  
2138  	/* Take semaphore for the entire operation. */
2139  	status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2140  	if (status) {
2141  		DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2142  		return status;
2143  	}
2144  	while (words) {
2145  		if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2146  			words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2147  		else
2148  			words_to_read = words;
2149  
2150  		buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2151  		buffer.hdr.req.buf_lenh = 0;
2152  		buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2153  		buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2154  
2155  		/* convert offset from words to bytes */
2156  		buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2157  		buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2158  
2159  		status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2160  						      sizeof(buffer),
2161  						      IXGBE_HI_COMMAND_TIMEOUT,
2162  						      FALSE);
2163  
2164  		if (status) {
2165  			DEBUGOUT("Host interface command failed\n");
2166  			goto out;
2167  		}
2168  
2169  		for (i = 0; i < words_to_read; i++) {
2170  			u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2171  				  2 * i;
2172  			u32 value = IXGBE_READ_REG(hw, reg);
2173  
2174  			data[current_word] = (u16)(value & 0xffff);
2175  			current_word++;
2176  			i++;
2177  			if (i < words_to_read) {
2178  				value >>= 16;
2179  				data[current_word] = (u16)(value & 0xffff);
2180  				current_word++;
2181  			}
2182  		}
2183  		words -= words_to_read;
2184  	}
2185  
2186  out:
2187  	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2188  	return status;
2189  }
2190  
2191  /**
2192   *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2193   *  @hw: pointer to hardware structure
2194   *  @offset: offset of  word in the EEPROM to write
2195   *  @data: word write to the EEPROM
2196   *
2197   *  Write a 16 bit word to the EEPROM using the hostif.
2198   **/
2199  s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2200  				    u16 data)
2201  {
2202  	s32 status;
2203  	struct ixgbe_hic_write_shadow_ram buffer;
2204  
2205  	DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2206  
2207  	buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2208  	buffer.hdr.req.buf_lenh = 0;
2209  	buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2210  	buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2211  
2212  	 /* one word */
2213  	buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2214  	buffer.data = data;
2215  	buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2216  
2217  	status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2218  					      sizeof(buffer),
2219  					      IXGBE_HI_COMMAND_TIMEOUT, FALSE);
2220  
2221  	return status;
2222  }
2223  
2224  /**
2225   *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2226   *  @hw: pointer to hardware structure
2227   *  @offset: offset of  word in the EEPROM to write
2228   *  @data: word write to the EEPROM
2229   *
2230   *  Write a 16 bit word to the EEPROM using the hostif.
2231   **/
2232  s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2233  			       u16 data)
2234  {
2235  	s32 status = IXGBE_SUCCESS;
2236  
2237  	DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2238  
2239  	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2240  	    IXGBE_SUCCESS) {
2241  		status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2242  		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2243  	} else {
2244  		DEBUGOUT("write ee hostif failed to get semaphore");
2245  		status = IXGBE_ERR_SWFW_SYNC;
2246  	}
2247  
2248  	return status;
2249  }
2250  
2251  /**
2252   *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2253   *  @hw: pointer to hardware structure
2254   *  @offset: offset of  word in the EEPROM to write
2255   *  @words: number of words
2256   *  @data: word(s) write to the EEPROM
2257   *
2258   *  Write a 16 bit word(s) to the EEPROM using the hostif.
2259   **/
2260  s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2261  				      u16 offset, u16 words, u16 *data)
2262  {
2263  	s32 status = IXGBE_SUCCESS;
2264  	u32 i = 0;
2265  
2266  	DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2267  
2268  	/* Take semaphore for the entire operation. */
2269  	status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2270  	if (status != IXGBE_SUCCESS) {
2271  		DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2272  		goto out;
2273  	}
2274  
2275  	for (i = 0; i < words; i++) {
2276  		status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2277  							 data[i]);
2278  
2279  		if (status != IXGBE_SUCCESS) {
2280  			DEBUGOUT("Eeprom buffered write failed\n");
2281  			break;
2282  		}
2283  	}
2284  
2285  	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2286  out:
2287  
2288  	return status;
2289  }
2290  
2291  /**
2292   * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2293   * @hw: pointer to hardware structure
2294   * @ptr: pointer offset in eeprom
2295   * @size: size of section pointed by ptr, if 0 first word will be used as size
2296   * @csum: address of checksum to update
2297   *
2298   * Returns error status for any failure
2299   */
2300  static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2301  				   u16 size, u16 *csum, u16 *buffer,
2302  				   u32 buffer_size)
2303  {
2304  	u16 buf[256];
2305  	s32 status;
2306  	u16 length, bufsz, i, start;
2307  	u16 *local_buffer;
2308  
2309  	bufsz = sizeof(buf) / sizeof(buf[0]);
2310  
2311  	/* Read a chunk at the pointer location */
2312  	if (!buffer) {
2313  		status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2314  		if (status) {
2315  			DEBUGOUT("Failed to read EEPROM image\n");
2316  			return status;
2317  		}
2318  		local_buffer = buf;
2319  	} else {
2320  		if (buffer_size < ptr)
2321  			return  IXGBE_ERR_PARAM;
2322  		local_buffer = &buffer[ptr];
2323  	}
2324  
2325  	if (size) {
2326  		start = 0;
2327  		length = size;
2328  	} else {
2329  		start = 1;
2330  		length = local_buffer[0];
2331  
2332  		/* Skip pointer section if length is invalid. */
2333  		if (length == 0xFFFF || length == 0 ||
2334  		    (ptr + length) >= hw->eeprom.word_size)
2335  			return IXGBE_SUCCESS;
2336  	}
2337  
2338  	if (buffer && ((u32)start + (u32)length > buffer_size))
2339  		return IXGBE_ERR_PARAM;
2340  
2341  	for (i = start; length; i++, length--) {
2342  		if (i == bufsz && !buffer) {
2343  			ptr += bufsz;
2344  			i = 0;
2345  			if (length < bufsz)
2346  				bufsz = length;
2347  
2348  			/* Read a chunk at the pointer location */
2349  			status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2350  								  bufsz, buf);
2351  			if (status) {
2352  				DEBUGOUT("Failed to read EEPROM image\n");
2353  				return status;
2354  			}
2355  		}
2356  		*csum += local_buffer[i];
2357  	}
2358  	return IXGBE_SUCCESS;
2359  }
2360  
2361  /**
2362   *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2363   *  @hw: pointer to hardware structure
2364   *  @buffer: pointer to buffer containing calculated checksum
2365   *  @buffer_size: size of buffer
2366   *
2367   *  Returns a negative error code on error, or the 16-bit checksum
2368   **/
2369  s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2370  {
2371  	u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2372  	u16 *local_buffer;
2373  	s32 status;
2374  	u16 checksum = 0;
2375  	u16 pointer, i, size;
2376  
2377  	DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2378  
2379  	hw->eeprom.ops.init_params(hw);
2380  
2381  	if (!buffer) {
2382  		/* Read pointer area */
2383  		status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2384  						     IXGBE_EEPROM_LAST_WORD + 1,
2385  						     eeprom_ptrs);
2386  		if (status) {
2387  			DEBUGOUT("Failed to read EEPROM image\n");
2388  			return status;
2389  		}
2390  		local_buffer = eeprom_ptrs;
2391  	} else {
2392  		if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2393  			return IXGBE_ERR_PARAM;
2394  		local_buffer = buffer;
2395  	}
2396  
2397  	/*
2398  	 * For X550 hardware include 0x0-0x41 in the checksum, skip the
2399  	 * checksum word itself
2400  	 */
2401  	for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2402  		if (i != IXGBE_EEPROM_CHECKSUM)
2403  			checksum += local_buffer[i];
2404  
2405  	/*
2406  	 * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2407  	 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2408  	 */
2409  	for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2410  		if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2411  			continue;
2412  
2413  		pointer = local_buffer[i];
2414  
2415  		/* Skip pointer section if the pointer is invalid. */
2416  		if (pointer == 0xFFFF || pointer == 0 ||
2417  		    pointer >= hw->eeprom.word_size)
2418  			continue;
2419  
2420  		switch (i) {
2421  		case IXGBE_PCIE_GENERAL_PTR:
2422  			size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2423  			break;
2424  		case IXGBE_PCIE_CONFIG0_PTR:
2425  		case IXGBE_PCIE_CONFIG1_PTR:
2426  			size = IXGBE_PCIE_CONFIG_SIZE;
2427  			break;
2428  		default:
2429  			size = 0;
2430  			break;
2431  		}
2432  
2433  		status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2434  						buffer, buffer_size);
2435  		if (status)
2436  			return status;
2437  	}
2438  
2439  	checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2440  
2441  	return (s32)checksum;
2442  }
2443  
2444  /**
2445   *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2446   *  @hw: pointer to hardware structure
2447   *
2448   *  Returns a negative error code on error, or the 16-bit checksum
2449   **/
2450  s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2451  {
2452  	return ixgbe_calc_checksum_X550(hw, NULL, 0);
2453  }
2454  
2455  /**
2456   *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2457   *  @hw: pointer to hardware structure
2458   *  @checksum_val: calculated checksum
2459   *
2460   *  Performs checksum calculation and validates the EEPROM checksum.  If the
2461   *  caller does not need checksum_val, the value can be NULL.
2462   **/
2463  s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2464  {
2465  	s32 status;
2466  	u16 checksum;
2467  	u16 read_checksum = 0;
2468  
2469  	DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2470  
2471  	/* Read the first word from the EEPROM. If this times out or fails, do
2472  	 * not continue or we could be in for a very long wait while every
2473  	 * EEPROM read fails
2474  	 */
2475  	status = hw->eeprom.ops.read(hw, 0, &checksum);
2476  	if (status) {
2477  		DEBUGOUT("EEPROM read failed\n");
2478  		return status;
2479  	}
2480  
2481  	status = hw->eeprom.ops.calc_checksum(hw);
2482  	if (status < 0)
2483  		return status;
2484  
2485  	checksum = (u16)(status & 0xffff);
2486  
2487  	status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2488  					   &read_checksum);
2489  	if (status)
2490  		return status;
2491  
2492  	/* Verify read checksum from EEPROM is the same as
2493  	 * calculated checksum
2494  	 */
2495  	if (read_checksum != checksum) {
2496  		status = IXGBE_ERR_EEPROM_CHECKSUM;
2497  		ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2498  			     "Invalid EEPROM checksum");
2499  	}
2500  
2501  	/* If the user cares, return the calculated checksum */
2502  	if (checksum_val)
2503  		*checksum_val = checksum;
2504  
2505  	return status;
2506  }
2507  
2508  /**
2509   * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2510   * @hw: pointer to hardware structure
2511   *
2512   * After writing EEPROM to shadow RAM using EEWR register, software calculates
2513   * checksum and updates the EEPROM and instructs the hardware to update
2514   * the flash.
2515   **/
2516  s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2517  {
2518  	s32 status;
2519  	u16 checksum = 0;
2520  
2521  	DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2522  
2523  	/* Read the first word from the EEPROM. If this times out or fails, do
2524  	 * not continue or we could be in for a very long wait while every
2525  	 * EEPROM read fails
2526  	 */
2527  	status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2528  	if (status) {
2529  		DEBUGOUT("EEPROM read failed\n");
2530  		return status;
2531  	}
2532  
2533  	status = ixgbe_calc_eeprom_checksum_X550(hw);
2534  	if (status < 0)
2535  		return status;
2536  
2537  	checksum = (u16)(status & 0xffff);
2538  
2539  	status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2540  					    checksum);
2541  	if (status)
2542  		return status;
2543  
2544  	status = ixgbe_update_flash_X550(hw);
2545  
2546  	return status;
2547  }
2548  
2549  /**
2550   *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2551   *  @hw: pointer to hardware structure
2552   *
2553   *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2554   **/
2555  s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2556  {
2557  	s32 status = IXGBE_SUCCESS;
2558  	union ixgbe_hic_hdr2 buffer;
2559  
2560  	DEBUGFUNC("ixgbe_update_flash_X550");
2561  
2562  	buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2563  	buffer.req.buf_lenh = 0;
2564  	buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2565  	buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2566  
2567  	status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2568  					      sizeof(buffer),
2569  					      IXGBE_HI_COMMAND_TIMEOUT, FALSE);
2570  
2571  	return status;
2572  }
2573  
2574  /**
2575   *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2576   *  @hw: pointer to hardware structure
2577   *
2578   *  Determines physical layer capabilities of the current configuration.
2579   **/
2580  u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2581  {
2582  	u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2583  	u16 ext_ability = 0;
2584  
2585  	DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2586  
2587  	hw->phy.ops.identify(hw);
2588  
2589  	switch (hw->phy.type) {
2590  	case ixgbe_phy_x550em_kr:
2591  		physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2592  				 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2593  		break;
2594  	case ixgbe_phy_x550em_kx4:
2595  		physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2596  				 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2597  		break;
2598  	case ixgbe_phy_x550em_ext_t:
2599  		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2600  				     IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2601  				     &ext_ability);
2602  		if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2603  			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2604  		if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2605  			physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2606  		break;
2607  	default:
2608  		break;
2609  	}
2610  
2611  	if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2612  		physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2613  
2614  	return physical_layer;
2615  }
2616  
2617  /**
2618   * ixgbe_get_bus_info_x550em - Set PCI bus info
2619   * @hw: pointer to hardware structure
2620   *
2621   * Sets bus link width and speed to unknown because X550em is
2622   * not a PCI device.
2623   **/
2624  s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2625  {
2626  
2627  	DEBUGFUNC("ixgbe_get_bus_info_x550em");
2628  
2629  	hw->bus.width = ixgbe_bus_width_unknown;
2630  	hw->bus.speed = ixgbe_bus_speed_unknown;
2631  
2632  	hw->mac.ops.set_lan_id(hw);
2633  
2634  	return IXGBE_SUCCESS;
2635  }
2636  
2637  /**
2638   * ixgbe_disable_rx_x550 - Disable RX unit
2639   *
2640   * Enables the Rx DMA unit for x550
2641   **/
2642  void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2643  {
2644  	u32 rxctrl, pfdtxgswc;
2645  	s32 status;
2646  	struct ixgbe_hic_disable_rxen fw_cmd;
2647  
2648  	DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2649  
2650  	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2651  	if (rxctrl & IXGBE_RXCTRL_RXEN) {
2652  		pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2653  		if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2654  			pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2655  			IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2656  			hw->mac.set_lben = TRUE;
2657  		} else {
2658  			hw->mac.set_lben = FALSE;
2659  		}
2660  
2661  		fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2662  		fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2663  		fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2664  		fw_cmd.port_number = (u8)hw->bus.lan_id;
2665  
2666  		status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2667  					sizeof(struct ixgbe_hic_disable_rxen),
2668  					IXGBE_HI_COMMAND_TIMEOUT, TRUE);
2669  
2670  		/* If we fail - disable RX using register write */
2671  		if (status) {
2672  			rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2673  			if (rxctrl & IXGBE_RXCTRL_RXEN) {
2674  				rxctrl &= ~IXGBE_RXCTRL_RXEN;
2675  				IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2676  			}
2677  		}
2678  	}
2679  }
2680  
2681  /**
2682   * ixgbe_enter_lplu_x550em - Transition to low power states
2683   *  @hw: pointer to hardware structure
2684   *
2685   * Configures Low Power Link Up on transition to low power states
2686   * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2687   * X557 PHY immediately prior to entering LPLU.
2688   **/
2689  s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2690  {
2691  	u16 an_10g_cntl_reg, autoneg_reg, speed;
2692  	s32 status;
2693  	ixgbe_link_speed lcd_speed;
2694  	u32 save_autoneg;
2695  	bool link_up;
2696  
2697  	/* SW LPLU not required on later HW revisions. */
2698  	if (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))
2699  		return IXGBE_SUCCESS;
2700  
2701  	/* If blocked by MNG FW, then don't restart AN */
2702  	if (ixgbe_check_reset_blocked(hw))
2703  		return IXGBE_SUCCESS;
2704  
2705  	status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2706  	if (status != IXGBE_SUCCESS)
2707  		return status;
2708  
2709  	status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2710  
2711  	if (status != IXGBE_SUCCESS)
2712  		return status;
2713  
2714  	/* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2715  	 * disabled, then force link down by entering low power mode.
2716  	 */
2717  	if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2718  	    !(hw->wol_enabled || ixgbe_mng_present(hw)))
2719  		return ixgbe_set_copper_phy_power(hw, FALSE);
2720  
2721  	/* Determine LCD */
2722  	status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2723  
2724  	if (status != IXGBE_SUCCESS)
2725  		return status;
2726  
2727  	/* If no valid LCD link speed, then force link down and exit. */
2728  	if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2729  		return ixgbe_set_copper_phy_power(hw, FALSE);
2730  
2731  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2732  				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2733  				      &speed);
2734  
2735  	if (status != IXGBE_SUCCESS)
2736  		return status;
2737  
2738  	/* If no link now, speed is invalid so take link down */
2739  	status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2740  	if (status != IXGBE_SUCCESS)
2741  		return ixgbe_set_copper_phy_power(hw, FALSE);
2742  
2743  	/* clear everything but the speed bits */
2744  	speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2745  
2746  	/* If current speed is already LCD, then exit. */
2747  	if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2748  	     (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2749  	    ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2750  	     (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2751  		return status;
2752  
2753  	/* Clear AN completed indication */
2754  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2755  				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2756  				      &autoneg_reg);
2757  
2758  	if (status != IXGBE_SUCCESS)
2759  		return status;
2760  
2761  	status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2762  			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2763  			     &an_10g_cntl_reg);
2764  
2765  	if (status != IXGBE_SUCCESS)
2766  		return status;
2767  
2768  	status = hw->phy.ops.read_reg(hw,
2769  			     IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2770  			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2771  			     &autoneg_reg);
2772  
2773  	if (status != IXGBE_SUCCESS)
2774  		return status;
2775  
2776  	save_autoneg = hw->phy.autoneg_advertised;
2777  
2778  	/* Setup link at least common link speed */
2779  	status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE);
2780  
2781  	/* restore autoneg from before setting lplu speed */
2782  	hw->phy.autoneg_advertised = save_autoneg;
2783  
2784  	return status;
2785  }
2786  
2787  /**
2788   * ixgbe_get_lcd_x550em - Determine lowest common denominator
2789   *  @hw: pointer to hardware structure
2790   *  @lcd_speed: pointer to lowest common link speed
2791   *
2792   * Determine lowest common link speed with link partner.
2793   **/
2794  s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
2795  {
2796  	u16 an_lp_status;
2797  	s32 status;
2798  	u16 word = hw->eeprom.ctrl_word_3;
2799  
2800  	*lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2801  
2802  	status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2803  				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2804  				      &an_lp_status);
2805  
2806  	if (status != IXGBE_SUCCESS)
2807  		return status;
2808  
2809  	/* If link partner advertised 1G, return 1G */
2810  	if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2811  		*lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2812  		return status;
2813  	}
2814  
2815  	/* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2816  	if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2817  	    (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2818  		return status;
2819  
2820  	/* Link partner not capable of lower speeds, return 10G */
2821  	*lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2822  	return status;
2823  }
2824  
2825  /**
2826   *  ixgbe_setup_fc_X550em - Set up flow control
2827   *  @hw: pointer to hardware structure
2828   *
2829   *  Called at init time to set up flow control.
2830   **/
2831  s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
2832  {
2833  	s32 ret_val = IXGBE_SUCCESS;
2834  	u32 pause, asm_dir, reg_val;
2835  
2836  	DEBUGFUNC("ixgbe_setup_fc_X550em");
2837  
2838  	/* Validate the requested mode */
2839  	if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2840  		ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2841  			"ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2842  		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2843  		goto out;
2844  	}
2845  
2846  	/* 10gig parts do not have a word in the EEPROM to determine the
2847  	 * default flow control setting, so we explicitly set it to full.
2848  	 */
2849  	if (hw->fc.requested_mode == ixgbe_fc_default)
2850  		hw->fc.requested_mode = ixgbe_fc_full;
2851  
2852  	/* Determine PAUSE and ASM_DIR bits. */
2853  	switch (hw->fc.requested_mode) {
2854  	case ixgbe_fc_none:
2855  		pause = 0;
2856  		asm_dir = 0;
2857  		break;
2858  	case ixgbe_fc_tx_pause:
2859  		pause = 0;
2860  		asm_dir = 1;
2861  		break;
2862  	case ixgbe_fc_rx_pause:
2863  		/* Rx Flow control is enabled and Tx Flow control is
2864  		 * disabled by software override. Since there really
2865  		 * isn't a way to advertise that we are capable of RX
2866  		 * Pause ONLY, we will advertise that we support both
2867  		 * symmetric and asymmetric Rx PAUSE, as such we fall
2868  		 * through to the fc_full statement.  Later, we will
2869  		 * disable the adapter's ability to send PAUSE frames.
2870  		 */
2871  	case ixgbe_fc_full:
2872  		pause = 1;
2873  		asm_dir = 1;
2874  		break;
2875  	default:
2876  		ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2877  			"Flow control param set incorrectly\n");
2878  		ret_val = IXGBE_ERR_CONFIG;
2879  		goto out;
2880  	}
2881  
2882  	if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
2883  		ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
2884  			IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2885  			IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2886  		if (ret_val != IXGBE_SUCCESS)
2887  			goto out;
2888  		reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2889  			IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2890  		if (pause)
2891  			reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2892  		if (asm_dir)
2893  			reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2894  		ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
2895  			IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2896  			IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2897  
2898  		/* This device does not fully support AN. */
2899  		hw->fc.disable_fc_autoneg = TRUE;
2900  	}
2901  
2902  out:
2903  	return ret_val;
2904  }
2905  
2906  /**
2907   * ixgbe_set_mux - Set mux for port 1 access with CS4227
2908   * @hw: pointer to hardware structure
2909   * @state: set mux if 1, clear if 0
2910   */
2911  static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2912  {
2913  	u32 esdp;
2914  
2915  	if (!hw->bus.lan_id)
2916  		return;
2917  	esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2918  	if (state)
2919  		esdp |= IXGBE_ESDP_SDP1;
2920  	else
2921  		esdp &= ~IXGBE_ESDP_SDP1;
2922  	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2923  	IXGBE_WRITE_FLUSH(hw);
2924  }
2925  
2926  /**
2927   *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2928   *  @hw: pointer to hardware structure
2929   *  @mask: Mask to specify which semaphore to acquire
2930   *
2931   *  Acquires the SWFW semaphore and sets the I2C MUX
2932   **/
2933  s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2934  {
2935  	s32 status;
2936  
2937  	DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
2938  
2939  	status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2940  	if (status)
2941  		return status;
2942  
2943  	if (mask & IXGBE_GSSR_I2C_MASK)
2944  		ixgbe_set_mux(hw, 1);
2945  
2946  	return IXGBE_SUCCESS;
2947  }
2948  
2949  /**
2950   *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2951   *  @hw: pointer to hardware structure
2952   *  @mask: Mask to specify which semaphore to release
2953   *
2954   *  Releases the SWFW semaphore and sets the I2C MUX
2955   **/
2956  void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2957  {
2958  	DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
2959  
2960  	if (mask & IXGBE_GSSR_I2C_MASK)
2961  		ixgbe_set_mux(hw, 0);
2962  
2963  	ixgbe_release_swfw_sync_X540(hw, mask);
2964  }
2965  
2966  /**
2967   * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2968   * @hw: pointer to hardware structure
2969   *
2970   * Handle external Base T PHY interrupt. If high temperature
2971   * failure alarm then return error, else if link status change
2972   * then setup internal/external PHY link
2973   *
2974   * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2975   * failure alarm, else return PHY access status.
2976   */
2977  s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2978  {
2979  	bool lsc;
2980  	u32 status;
2981  
2982  	status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2983  
2984  	if (status != IXGBE_SUCCESS)
2985  		return status;
2986  
2987  	if (lsc)
2988  		return ixgbe_setup_internal_phy(hw);
2989  
2990  	return IXGBE_SUCCESS;
2991  }
2992  
2993  /**
2994   * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
2995   * @hw: pointer to hardware structure
2996   * @speed: new link speed
2997   * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
2998   *
2999   * Setup internal/external PHY link speed based on link speed, then set
3000   * external PHY auto advertised link speed.
3001   *
3002   * Returns error status for any failure
3003   **/
3004  s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3005  				  ixgbe_link_speed speed,
3006  				  bool autoneg_wait_to_complete)
3007  {
3008  	s32 status;
3009  	ixgbe_link_speed force_speed;
3010  
3011  	DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3012  
3013  	/* Setup internal/external PHY link speed to iXFI (10G), unless
3014  	 * only 1G is auto advertised then setup KX link.
3015  	 */
3016  	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3017  		force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3018  	else
3019  		force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3020  
3021  	/* If internal link mode is XFI, then setup XFI internal link. */
3022  	if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3023  		status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3024  
3025  		if (status != IXGBE_SUCCESS)
3026  			return status;
3027  	}
3028  
3029  	return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3030  }
3031  
3032  /**
3033   * ixgbe_check_link_t_X550em - Determine link and speed status
3034   * @hw: pointer to hardware structure
3035   * @speed: pointer to link speed
3036   * @link_up: TRUE when link is up
3037   * @link_up_wait_to_complete: bool used to wait for link up or not
3038   *
3039   * Check that both the MAC and X557 external PHY have link.
3040   **/
3041  s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3042  			      bool *link_up, bool link_up_wait_to_complete)
3043  {
3044  	u32 status;
3045  	u16 autoneg_status;
3046  
3047  	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3048  		return IXGBE_ERR_CONFIG;
3049  
3050  	status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3051  					      link_up_wait_to_complete);
3052  
3053  	/* If check link fails or MAC link is not up, then return */
3054  	if (status != IXGBE_SUCCESS || !(*link_up))
3055  		return status;
3056  
3057  	/* MAC link is up, so check external PHY link.
3058  	 * Read this twice back to back to indicate current status.
3059  	 */
3060  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3061  				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3062  				      &autoneg_status);
3063  
3064  	if (status != IXGBE_SUCCESS)
3065  		return status;
3066  
3067  	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3068  				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3069  				      &autoneg_status);
3070  
3071  	if (status != IXGBE_SUCCESS)
3072  		return status;
3073  
3074  	/* If external PHY link is not up, then indicate link not up */
3075  	if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3076  		*link_up = FALSE;
3077  
3078  	return IXGBE_SUCCESS;
3079  }
3080  
3081  /**
3082   *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3083   *  @hw: pointer to hardware structure
3084   **/
3085  s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3086  {
3087  	s32 status;
3088  
3089  	status = ixgbe_reset_phy_generic(hw);
3090  
3091  	if (status != IXGBE_SUCCESS)
3092  		return status;
3093  
3094  	/* Configure Link Status Alarm and Temperature Threshold interrupts */
3095  	return ixgbe_enable_lasi_ext_t_x550em(hw);
3096  }
3097  
3098  /**
3099   *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3100   *  @hw: pointer to hardware structure
3101   *  @led_idx: led number to turn on
3102   **/
3103  s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3104  {
3105  	u16 phy_data;
3106  
3107  	DEBUGFUNC("ixgbe_led_on_t_X550em");
3108  
3109  	if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3110  		return IXGBE_ERR_PARAM;
3111  
3112  	/* To turn on the LED, set mode to ON. */
3113  	ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3114  			   IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3115  	phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3116  	ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3117  			    IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3118  
3119  	return IXGBE_SUCCESS;
3120  }
3121  
3122  /**
3123   *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3124   *  @hw: pointer to hardware structure
3125   *  @led_idx: led number to turn off
3126   **/
3127  s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3128  {
3129  	u16 phy_data;
3130  
3131  	DEBUGFUNC("ixgbe_led_off_t_X550em");
3132  
3133  	if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3134  		return IXGBE_ERR_PARAM;
3135  
3136  	/* To turn on the LED, set mode to ON. */
3137  	ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3138  			   IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3139  	phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3140  	ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3141  			    IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3142  
3143  	return IXGBE_SUCCESS;
3144  }
3145  
3146