xref: /illumos-gate/usr/src/uts/common/io/ixgbe/core/ixgbe_x540.c (revision 48ed61a721b0db9229d5bad4d87f5b019867fbf1)
1 /******************************************************************************
2   SPDX-License-Identifier: BSD-3-Clause
3 
4   Copyright (c) 2001-2017, Intel Corporation
5   All rights reserved.
6 
7   Redistribution and use in source and binary forms, with or without
8   modification, are permitted provided that the following conditions are met:
9 
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11       this list of conditions and the following disclaimer.
12 
13    2. Redistributions in binary form must reproduce the above copyright
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15       documentation and/or other materials provided with the distribution.
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19       this software without specific prior written permission.
20 
21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 
33 ******************************************************************************/
34 /*$FreeBSD$*/
35 
36 #include "ixgbe_x540.h"
37 #include "ixgbe_type.h"
38 #include "ixgbe_api.h"
39 #include "ixgbe_common.h"
40 #include "ixgbe_phy.h"
41 
42 #define IXGBE_X540_MAX_TX_QUEUES	128
43 #define IXGBE_X540_MAX_RX_QUEUES	128
44 #define IXGBE_X540_RAR_ENTRIES		128
45 #define IXGBE_X540_MC_TBL_SIZE		128
46 #define IXGBE_X540_VFT_TBL_SIZE		128
47 #define IXGBE_X540_RX_PB_SIZE		384
48 
49 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
50 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
51 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
52 
53 /**
54  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
55  *  @hw: pointer to hardware structure
56  *
57  *  Initialize the function pointers and assign the MAC type for X540.
58  *  Does not touch the hardware.
59  **/
ixgbe_init_ops_X540(struct ixgbe_hw * hw)60 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
61 {
62 	struct ixgbe_mac_info *mac = &hw->mac;
63 	struct ixgbe_phy_info *phy = &hw->phy;
64 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
65 	s32 ret_val;
66 
67 	DEBUGFUNC("ixgbe_init_ops_X540");
68 
69 	ret_val = ixgbe_init_phy_ops_generic(hw);
70 	ret_val = ixgbe_init_ops_generic(hw);
71 
72 
73 	/* EEPROM */
74 	eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
75 	eeprom->ops.read = ixgbe_read_eerd_X540;
76 	eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
77 	eeprom->ops.write = ixgbe_write_eewr_X540;
78 	eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
79 	eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
80 	eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
81 	eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
82 
83 	/* PHY */
84 	phy->ops.init = ixgbe_init_phy_ops_generic;
85 	phy->ops.reset = NULL;
86 	phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
87 
88 	/* MAC */
89 	mac->ops.reset_hw = ixgbe_reset_hw_X540;
90 	mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
91 	mac->ops.get_media_type = ixgbe_get_media_type_X540;
92 	mac->ops.get_supported_physical_layer =
93 				    ixgbe_get_supported_physical_layer_X540;
94 	mac->ops.read_analog_reg8 = NULL;
95 	mac->ops.write_analog_reg8 = NULL;
96 	mac->ops.start_hw = ixgbe_start_hw_X540;
97 	mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
98 	mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
99 	mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
100 	mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
101 	mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
102 	mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
103 	mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
104 	mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;
105 	mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
106 	mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
107 
108 	/* RAR, Multicast, VLAN */
109 	mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
110 	mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
111 	mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
112 	mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
113 	mac->rar_highwater = 1;
114 	mac->ops.set_vfta = ixgbe_set_vfta_generic;
115 	mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
116 	mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
117 	mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
118 	mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
119 	mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
120 
121 	/* Link */
122 	mac->ops.get_link_capabilities =
123 				ixgbe_get_copper_link_capabilities_generic;
124 	mac->ops.setup_link = ixgbe_setup_mac_link_X540;
125 	mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
126 	mac->ops.check_link = ixgbe_check_mac_link_generic;
127 	mac->ops.bypass_rw = ixgbe_bypass_rw_generic;
128 	mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic;
129 	mac->ops.bypass_set = ixgbe_bypass_set_generic;
130 	mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic;
131 
132 
133 	mac->mcft_size		= IXGBE_X540_MC_TBL_SIZE;
134 	mac->vft_size		= IXGBE_X540_VFT_TBL_SIZE;
135 	mac->num_rar_entries	= IXGBE_X540_RAR_ENTRIES;
136 	mac->rx_pb_size		= IXGBE_X540_RX_PB_SIZE;
137 	mac->max_rx_queues	= IXGBE_X540_MAX_RX_QUEUES;
138 	mac->max_tx_queues	= IXGBE_X540_MAX_TX_QUEUES;
139 	mac->max_msix_vectors	= ixgbe_get_pcie_msix_count_generic(hw);
140 
141 	/*
142 	 * FWSM register
143 	 * ARC supported; valid only if manageability features are
144 	 * enabled.
145 	 */
146 	mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
147 				     & IXGBE_FWSM_MODE_MASK);
148 
149 	hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
150 
151 	/* LEDs */
152 	mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
153 	mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
154 
155 	/* Manageability interface */
156 	mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
157 
158 	mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
159 
160 	return ret_val;
161 }
162 
163 /**
164  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
165  *  @hw: pointer to hardware structure
166  *  @speed: pointer to link speed
167  *  @autoneg: TRUE when autoneg or autotry is enabled
168  *
169  *  Determines the link capabilities by reading the AUTOC register.
170  **/
ixgbe_get_link_capabilities_X540(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)171 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
172 				     ixgbe_link_speed *speed,
173 				     bool *autoneg)
174 {
175 	ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
176 
177 	return IXGBE_SUCCESS;
178 }
179 
180 /**
181  *  ixgbe_get_media_type_X540 - Get media type
182  *  @hw: pointer to hardware structure
183  *
184  *  Returns the media type (fiber, copper, backplane)
185  **/
ixgbe_get_media_type_X540(struct ixgbe_hw * hw)186 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
187 {
188 	UNREFERENCED_1PARAMETER(hw);
189 	return ixgbe_media_type_copper;
190 }
191 
192 /**
193  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
194  *  @hw: pointer to hardware structure
195  *  @speed: new link speed
196  *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
197  **/
ixgbe_setup_mac_link_X540(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)198 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
199 			      ixgbe_link_speed speed,
200 			      bool autoneg_wait_to_complete)
201 {
202 	DEBUGFUNC("ixgbe_setup_mac_link_X540");
203 	return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
204 }
205 
206 /**
207  *  ixgbe_reset_hw_X540 - Perform hardware reset
208  *  @hw: pointer to hardware structure
209  *
210  *  Resets the hardware by resetting the transmit and receive units, masks
211  *  and clears all interrupts, and perform a reset.
212  **/
ixgbe_reset_hw_X540(struct ixgbe_hw * hw)213 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
214 {
215 	s32 status;
216 	u32 ctrl, i;
217 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
218 
219 	DEBUGFUNC("ixgbe_reset_hw_X540");
220 
221 	/* Call adapter stop to disable tx/rx and clear interrupts */
222 	status = hw->mac.ops.stop_adapter(hw);
223 	if (status != IXGBE_SUCCESS)
224 		goto reset_hw_out;
225 
226 	/* flush pending Tx transactions */
227 	ixgbe_clear_tx_pending(hw);
228 
229 mac_reset_top:
230 	status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
231 	if (status != IXGBE_SUCCESS) {
232 		ERROR_REPORT2(IXGBE_ERROR_CAUTION,
233 			"semaphore failed with %d", status);
234 		return IXGBE_ERR_SWFW_SYNC;
235 	}
236 	ctrl = IXGBE_CTRL_RST;
237 	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
238 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
239 	IXGBE_WRITE_FLUSH(hw);
240 	hw->mac.ops.release_swfw_sync(hw, swfw_mask);
241 
242 	/* Poll for reset bit to self-clear indicating reset is complete */
243 	for (i = 0; i < 10; i++) {
244 		usec_delay(1);
245 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
246 		if (!(ctrl & IXGBE_CTRL_RST_MASK))
247 			break;
248 	}
249 
250 	if (ctrl & IXGBE_CTRL_RST_MASK) {
251 		status = IXGBE_ERR_RESET_FAILED;
252 		ERROR_REPORT1(IXGBE_ERROR_POLLING,
253 			     "Reset polling failed to complete.\n");
254 	}
255 	msec_delay(100);
256 
257 	/*
258 	 * Double resets are required for recovery from certain error
259 	 * conditions.  Between resets, it is necessary to stall to allow time
260 	 * for any pending HW events to complete.
261 	 */
262 	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
263 		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
264 		goto mac_reset_top;
265 	}
266 
267 	/* Set the Rx packet buffer size. */
268 	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
269 
270 	/* Store the permanent mac address */
271 	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
272 
273 	/*
274 	 * Store MAC address from RAR0, clear receive address registers, and
275 	 * clear the multicast table.  Also reset num_rar_entries to 128,
276 	 * since we modify this value when programming the SAN MAC address.
277 	 */
278 	hw->mac.num_rar_entries = 128;
279 	hw->mac.ops.init_rx_addrs(hw);
280 
281 	/* Store the permanent SAN mac address */
282 	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
283 
284 	/* Add the SAN MAC address to the RAR only if it's a valid address */
285 	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
286 		/* Save the SAN MAC RAR index */
287 		hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
288 
289 		hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
290 				    hw->mac.san_addr, 0, IXGBE_RAH_AV);
291 
292 		/* clear VMDq pool/queue selection for this RAR */
293 		hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
294 				       IXGBE_CLEAR_VMDQ_ALL);
295 
296 		/* Reserve the last RAR for the SAN MAC address */
297 		hw->mac.num_rar_entries--;
298 	}
299 
300 	/* Store the alternative WWNN/WWPN prefix */
301 	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
302 				   &hw->mac.wwpn_prefix);
303 
304 reset_hw_out:
305 	return status;
306 }
307 
308 /**
309  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
310  *  @hw: pointer to hardware structure
311  *
312  *  Starts the hardware using the generic start_hw function
313  *  and the generation start_hw function.
314  *  Then performs revision-specific operations, if any.
315  **/
ixgbe_start_hw_X540(struct ixgbe_hw * hw)316 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
317 {
318 	s32 ret_val = IXGBE_SUCCESS;
319 
320 	DEBUGFUNC("ixgbe_start_hw_X540");
321 
322 	ret_val = ixgbe_start_hw_generic(hw);
323 	if (ret_val != IXGBE_SUCCESS)
324 		goto out;
325 
326 	ret_val = ixgbe_start_hw_gen2(hw);
327 
328 out:
329 	return ret_val;
330 }
331 
332 /**
333  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
334  *  @hw: pointer to hardware structure
335  *
336  *  Determines physical layer capabilities of the current configuration.
337  **/
ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw * hw)338 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
339 {
340 	u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
341 	u16 ext_ability = 0;
342 
343 	DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
344 
345 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
346 	IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
347 	if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
348 		physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
349 	if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
350 		physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
351 	if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
352 		physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
353 
354 	return physical_layer;
355 }
356 
357 /**
358  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
359  *  @hw: pointer to hardware structure
360  *
361  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
362  *  ixgbe_hw struct in order to set up EEPROM access.
363  **/
ixgbe_init_eeprom_params_X540(struct ixgbe_hw * hw)364 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
365 {
366 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
367 	u32 eec;
368 	u16 eeprom_size;
369 
370 	DEBUGFUNC("ixgbe_init_eeprom_params_X540");
371 
372 	if (eeprom->type == ixgbe_eeprom_uninitialized) {
373 		eeprom->semaphore_delay = 10;
374 		eeprom->type = ixgbe_flash;
375 
376 		eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
377 		eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
378 				    IXGBE_EEC_SIZE_SHIFT);
379 		eeprom->word_size = 1 << (eeprom_size +
380 					  IXGBE_EEPROM_WORD_SIZE_SHIFT);
381 
382 		DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
383 			  eeprom->type, eeprom->word_size);
384 	}
385 
386 	return IXGBE_SUCCESS;
387 }
388 
389 /**
390  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
391  *  @hw: pointer to hardware structure
392  *  @offset: offset of  word in the EEPROM to read
393  *  @data: word read from the EEPROM
394  *
395  *  Reads a 16 bit word from the EEPROM using the EERD register.
396  **/
ixgbe_read_eerd_X540(struct ixgbe_hw * hw,u16 offset,u16 * data)397 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
398 {
399 	s32 status = IXGBE_SUCCESS;
400 
401 	DEBUGFUNC("ixgbe_read_eerd_X540");
402 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
403 	    IXGBE_SUCCESS) {
404 		status = ixgbe_read_eerd_generic(hw, offset, data);
405 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
406 	} else {
407 		status = IXGBE_ERR_SWFW_SYNC;
408 	}
409 
410 	return status;
411 }
412 
413 /**
414  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
415  *  @hw: pointer to hardware structure
416  *  @offset: offset of  word in the EEPROM to read
417  *  @words: number of words
418  *  @data: word(s) read from the EEPROM
419  *
420  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
421  **/
ixgbe_read_eerd_buffer_X540(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)422 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
423 				u16 offset, u16 words, u16 *data)
424 {
425 	s32 status = IXGBE_SUCCESS;
426 
427 	DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
428 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
429 	    IXGBE_SUCCESS) {
430 		status = ixgbe_read_eerd_buffer_generic(hw, offset,
431 							words, data);
432 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
433 	} else {
434 		status = IXGBE_ERR_SWFW_SYNC;
435 	}
436 
437 	return status;
438 }
439 
440 /**
441  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
442  *  @hw: pointer to hardware structure
443  *  @offset: offset of  word in the EEPROM to write
444  *  @data: word write to the EEPROM
445  *
446  *  Write a 16 bit word to the EEPROM using the EEWR register.
447  **/
ixgbe_write_eewr_X540(struct ixgbe_hw * hw,u16 offset,u16 data)448 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
449 {
450 	s32 status = IXGBE_SUCCESS;
451 
452 	DEBUGFUNC("ixgbe_write_eewr_X540");
453 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
454 	    IXGBE_SUCCESS) {
455 		status = ixgbe_write_eewr_generic(hw, offset, data);
456 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
457 	} else {
458 		status = IXGBE_ERR_SWFW_SYNC;
459 	}
460 
461 	return status;
462 }
463 
464 /**
465  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
466  *  @hw: pointer to hardware structure
467  *  @offset: offset of  word in the EEPROM to write
468  *  @words: number of words
469  *  @data: word(s) write to the EEPROM
470  *
471  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
472  **/
ixgbe_write_eewr_buffer_X540(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)473 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
474 				 u16 offset, u16 words, u16 *data)
475 {
476 	s32 status = IXGBE_SUCCESS;
477 
478 	DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
479 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
480 	    IXGBE_SUCCESS) {
481 		status = ixgbe_write_eewr_buffer_generic(hw, offset,
482 							 words, data);
483 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
484 	} else {
485 		status = IXGBE_ERR_SWFW_SYNC;
486 	}
487 
488 	return status;
489 }
490 
491 /**
492  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
493  *
494  *  This function does not use synchronization for EERD and EEWR. It can
495  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
496  *
497  *  @hw: pointer to hardware structure
498  *
499  *  Returns a negative error code on error, or the 16-bit checksum
500  **/
ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw * hw)501 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
502 {
503 	u16 i, j;
504 	u16 checksum = 0;
505 	u16 length = 0;
506 	u16 pointer = 0;
507 	u16 word = 0;
508 	u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
509 
510 	/* Do not use hw->eeprom.ops.read because we do not want to take
511 	 * the synchronization semaphores here. Instead use
512 	 * ixgbe_read_eerd_generic
513 	 */
514 
515 	DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
516 
517 	/* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the
518 	 * checksum itself
519 	 */
520 	for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
521 		if (ixgbe_read_eerd_generic(hw, i, &word)) {
522 			DEBUGOUT("EEPROM read failed\n");
523 			return IXGBE_ERR_EEPROM;
524 		}
525 		checksum += word;
526 	}
527 
528 	/* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
529 	 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
530 	 */
531 	for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
532 		if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
533 			continue;
534 
535 		if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
536 			DEBUGOUT("EEPROM read failed\n");
537 			return IXGBE_ERR_EEPROM;
538 		}
539 
540 		/* Skip pointer section if the pointer is invalid. */
541 		if (pointer == 0xFFFF || pointer == 0 ||
542 		    pointer >= hw->eeprom.word_size)
543 			continue;
544 
545 		if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
546 			DEBUGOUT("EEPROM read failed\n");
547 			return IXGBE_ERR_EEPROM;
548 		}
549 
550 		/* Skip pointer section if length is invalid. */
551 		if (length == 0xFFFF || length == 0 ||
552 		    (pointer + length) >= hw->eeprom.word_size)
553 			continue;
554 
555 		for (j = pointer + 1; j <= pointer + length; j++) {
556 			if (ixgbe_read_eerd_generic(hw, j, &word)) {
557 				DEBUGOUT("EEPROM read failed\n");
558 				return IXGBE_ERR_EEPROM;
559 			}
560 			checksum += word;
561 		}
562 	}
563 
564 	checksum = (u16)IXGBE_EEPROM_SUM - checksum;
565 
566 	return (s32)checksum;
567 }
568 
569 /**
570  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
571  *  @hw: pointer to hardware structure
572  *  @checksum_val: calculated checksum
573  *
574  *  Performs checksum calculation and validates the EEPROM checksum.  If the
575  *  caller does not need checksum_val, the value can be NULL.
576  **/
ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw * hw,u16 * checksum_val)577 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
578 					u16 *checksum_val)
579 {
580 	s32 status;
581 	u16 checksum;
582 	u16 read_checksum = 0;
583 
584 	DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
585 
586 	/* Read the first word from the EEPROM. If this times out or fails, do
587 	 * not continue or we could be in for a very long wait while every
588 	 * EEPROM read fails
589 	 */
590 	status = hw->eeprom.ops.read(hw, 0, &checksum);
591 	if (status) {
592 		DEBUGOUT("EEPROM read failed\n");
593 		return status;
594 	}
595 
596 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
597 		return IXGBE_ERR_SWFW_SYNC;
598 
599 	status = hw->eeprom.ops.calc_checksum(hw);
600 	if (status < 0)
601 		goto out;
602 
603 	checksum = (u16)(status & 0xffff);
604 
605 	/* Do not use hw->eeprom.ops.read because we do not want to take
606 	 * the synchronization semaphores twice here.
607 	 */
608 	status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
609 					 &read_checksum);
610 	if (status)
611 		goto out;
612 
613 	/* Verify read checksum from EEPROM is the same as
614 	 * calculated checksum
615 	 */
616 	if (read_checksum != checksum) {
617 		ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
618 			     "Invalid EEPROM checksum");
619 		status = IXGBE_ERR_EEPROM_CHECKSUM;
620 	}
621 
622 	/* If the user cares, return the calculated checksum */
623 	if (checksum_val)
624 		*checksum_val = checksum;
625 
626 out:
627 	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
628 
629 	return status;
630 }
631 
632 /**
633  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
634  * @hw: pointer to hardware structure
635  *
636  * After writing EEPROM to shadow RAM using EEWR register, software calculates
637  * checksum and updates the EEPROM and instructs the hardware to update
638  * the flash.
639  **/
ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw * hw)640 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
641 {
642 	s32 status;
643 	u16 checksum;
644 
645 	DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
646 
647 	/* Read the first word from the EEPROM. If this times out or fails, do
648 	 * not continue or we could be in for a very long wait while every
649 	 * EEPROM read fails
650 	 */
651 	status = hw->eeprom.ops.read(hw, 0, &checksum);
652 	if (status) {
653 		DEBUGOUT("EEPROM read failed\n");
654 		return status;
655 	}
656 
657 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
658 		return IXGBE_ERR_SWFW_SYNC;
659 
660 	status = hw->eeprom.ops.calc_checksum(hw);
661 	if (status < 0)
662 		goto out;
663 
664 	checksum = (u16)(status & 0xffff);
665 
666 	/* Do not use hw->eeprom.ops.write because we do not want to
667 	 * take the synchronization semaphores twice here.
668 	 */
669 	status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
670 	if (status)
671 		goto out;
672 
673 	status = ixgbe_update_flash_X540(hw);
674 
675 out:
676 	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
677 
678 	return status;
679 }
680 
681 /**
682  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
683  *  @hw: pointer to hardware structure
684  *
685  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
686  *  EEPROM from shadow RAM to the flash device.
687  **/
ixgbe_update_flash_X540(struct ixgbe_hw * hw)688 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
689 {
690 	u32 flup;
691 	s32 status;
692 
693 	DEBUGFUNC("ixgbe_update_flash_X540");
694 
695 	status = ixgbe_poll_flash_update_done_X540(hw);
696 	if (status == IXGBE_ERR_EEPROM) {
697 		DEBUGOUT("Flash update time out\n");
698 		goto out;
699 	}
700 
701 	flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
702 	IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
703 
704 	status = ixgbe_poll_flash_update_done_X540(hw);
705 	if (status == IXGBE_SUCCESS)
706 		DEBUGOUT("Flash update complete\n");
707 	else
708 		DEBUGOUT("Flash update time out\n");
709 
710 	if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
711 		flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
712 
713 		if (flup & IXGBE_EEC_SEC1VAL) {
714 			flup |= IXGBE_EEC_FLUP;
715 			IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
716 		}
717 
718 		status = ixgbe_poll_flash_update_done_X540(hw);
719 		if (status == IXGBE_SUCCESS)
720 			DEBUGOUT("Flash update complete\n");
721 		else
722 			DEBUGOUT("Flash update time out\n");
723 	}
724 out:
725 	return status;
726 }
727 
728 /**
729  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
730  *  @hw: pointer to hardware structure
731  *
732  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
733  *  flash update is done.
734  **/
ixgbe_poll_flash_update_done_X540(struct ixgbe_hw * hw)735 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
736 {
737 	u32 i;
738 	u32 reg;
739 	s32 status = IXGBE_ERR_EEPROM;
740 
741 	DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
742 
743 	for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
744 		reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
745 		if (reg & IXGBE_EEC_FLUDONE) {
746 			status = IXGBE_SUCCESS;
747 			break;
748 		}
749 		msec_delay(5);
750 	}
751 
752 	if (i == IXGBE_FLUDONE_ATTEMPTS)
753 		ERROR_REPORT1(IXGBE_ERROR_POLLING,
754 			     "Flash update status polling timed out");
755 
756 	return status;
757 }
758 
759 /**
760  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
761  *  @hw: pointer to hardware structure
762  *  @mask: Mask to specify which semaphore to acquire
763  *
764  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
765  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
766  **/
ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw * hw,u32 mask)767 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
768 {
769 	u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
770 	u32 fwmask = swmask << 5;
771 	u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
772 	u32 timeout = 200;
773 	u32 hwmask = 0;
774 	u32 swfw_sync;
775 	u32 i;
776 
777 	DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
778 
779 	if (swmask & IXGBE_GSSR_EEP_SM)
780 		hwmask |= IXGBE_GSSR_FLASH_SM;
781 
782 	/* SW only mask doesn't have FW bit pair */
783 	if (mask & IXGBE_GSSR_SW_MNG_SM)
784 		swmask |= IXGBE_GSSR_SW_MNG_SM;
785 
786 	swmask |= swi2c_mask;
787 	fwmask |= swi2c_mask << 2;
788 	if (hw->mac.type >= ixgbe_mac_X550)
789 		timeout = 1000;
790 
791 	for (i = 0; i < timeout; i++) {
792 		/* SW NVM semaphore bit is used for access to all
793 		 * SW_FW_SYNC bits (not just NVM)
794 		 */
795 		if (ixgbe_get_swfw_sync_semaphore(hw)) {
796 			DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n");
797 			return IXGBE_ERR_SWFW_SYNC;
798 		}
799 
800 		swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
801 		if (!(swfw_sync & (fwmask | swmask | hwmask))) {
802 			swfw_sync |= swmask;
803 			IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
804 					swfw_sync);
805 			ixgbe_release_swfw_sync_semaphore(hw);
806 			return IXGBE_SUCCESS;
807 		}
808 		/* Firmware currently using resource (fwmask), hardware
809 		 * currently using resource (hwmask), or other software
810 		 * thread currently using resource (swmask)
811 		 */
812 		ixgbe_release_swfw_sync_semaphore(hw);
813 		msec_delay(5);
814 	}
815 
816 	/* If the resource is not released by the FW/HW the SW can assume that
817 	 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
818 	 * of the requested resource(s) while ignoring the corresponding FW/HW
819 	 * bits in the SW_FW_SYNC register.
820 	 */
821 	if (ixgbe_get_swfw_sync_semaphore(hw)) {
822 		DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n");
823 		return IXGBE_ERR_SWFW_SYNC;
824 	}
825 	swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
826 	if (swfw_sync & (fwmask | hwmask)) {
827 		swfw_sync |= swmask;
828 		IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
829 		ixgbe_release_swfw_sync_semaphore(hw);
830 		msec_delay(5);
831 		return IXGBE_SUCCESS;
832 	}
833 	/* If the resource is not released by other SW the SW can assume that
834 	 * the other SW malfunctions. In that case the SW should clear all SW
835 	 * flags that it does not own and then repeat the whole process once
836 	 * again.
837 	 */
838 	if (swfw_sync & swmask) {
839 		u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
840 			    IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
841 			    IXGBE_GSSR_SW_MNG_SM;
842 
843 		if (swi2c_mask)
844 			rmask |= IXGBE_GSSR_I2C_MASK;
845 		ixgbe_release_swfw_sync_X540(hw, rmask);
846 		ixgbe_release_swfw_sync_semaphore(hw);
847 		DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n");
848 		return IXGBE_ERR_SWFW_SYNC;
849 	}
850 	ixgbe_release_swfw_sync_semaphore(hw);
851 	DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n");
852 
853 	return IXGBE_ERR_SWFW_SYNC;
854 }
855 
856 /**
857  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
858  *  @hw: pointer to hardware structure
859  *  @mask: Mask to specify which semaphore to release
860  *
861  *  Releases the SWFW semaphore through the SW_FW_SYNC register
862  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
863  **/
ixgbe_release_swfw_sync_X540(struct ixgbe_hw * hw,u32 mask)864 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
865 {
866 	u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
867 	u32 swfw_sync;
868 
869 	DEBUGFUNC("ixgbe_release_swfw_sync_X540");
870 
871 	if (mask & IXGBE_GSSR_I2C_MASK)
872 		swmask |= mask & IXGBE_GSSR_I2C_MASK;
873 	ixgbe_get_swfw_sync_semaphore(hw);
874 
875 	swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
876 	swfw_sync &= ~swmask;
877 	IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
878 
879 	ixgbe_release_swfw_sync_semaphore(hw);
880 	msec_delay(2);
881 }
882 
883 /**
884  *  ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
885  *  @hw: pointer to hardware structure
886  *
887  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
888  **/
ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw * hw)889 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
890 {
891 	s32 status = IXGBE_ERR_EEPROM;
892 	u32 timeout = 2000;
893 	u32 i;
894 	u32 swsm;
895 
896 	DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
897 
898 	/* Get SMBI software semaphore between device drivers first */
899 	for (i = 0; i < timeout; i++) {
900 		/*
901 		 * If the SMBI bit is 0 when we read it, then the bit will be
902 		 * set and we have the semaphore
903 		 */
904 		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
905 		if (!(swsm & IXGBE_SWSM_SMBI)) {
906 			status = IXGBE_SUCCESS;
907 			break;
908 		}
909 		usec_delay(50);
910 	}
911 
912 	/* Now get the semaphore between SW/FW through the REGSMP bit */
913 	if (status == IXGBE_SUCCESS) {
914 		for (i = 0; i < timeout; i++) {
915 			swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
916 			if (!(swsm & IXGBE_SWFW_REGSMP))
917 				break;
918 
919 			usec_delay(50);
920 		}
921 
922 		/*
923 		 * Release semaphores and return error if SW NVM semaphore
924 		 * was not granted because we don't have access to the EEPROM
925 		 */
926 		if (i >= timeout) {
927 			ERROR_REPORT1(IXGBE_ERROR_POLLING,
928 				"REGSMP Software NVM semaphore not granted.\n");
929 			ixgbe_release_swfw_sync_semaphore(hw);
930 			status = IXGBE_ERR_EEPROM;
931 		}
932 	} else {
933 		ERROR_REPORT1(IXGBE_ERROR_POLLING,
934 			     "Software semaphore SMBI between device drivers "
935 			     "not granted.\n");
936 	}
937 
938 	return status;
939 }
940 
941 /**
942  *  ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
943  *  @hw: pointer to hardware structure
944  *
945  *  This function clears hardware semaphore bits.
946  **/
ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw * hw)947 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
948 {
949 	u32 swsm;
950 
951 	DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
952 
953 	/* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
954 
955 	swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
956 	swsm &= ~IXGBE_SWFW_REGSMP;
957 	IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
958 
959 	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
960 	swsm &= ~IXGBE_SWSM_SMBI;
961 	IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
962 
963 	IXGBE_WRITE_FLUSH(hw);
964 }
965 
966 /**
967  *  ixgbe_init_swfw_sync_X540 - Release hardware semaphore
968  *  @hw: pointer to hardware structure
969  *
970  *  This function reset hardware semaphore bits for a semaphore that may
971  *  have be left locked due to a catastrophic failure.
972  **/
ixgbe_init_swfw_sync_X540(struct ixgbe_hw * hw)973 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
974 {
975 	u32 rmask;
976 
977 	/* First try to grab the semaphore but we don't need to bother
978 	 * looking to see whether we got the lock or not since we do
979 	 * the same thing regardless of whether we got the lock or not.
980 	 * We got the lock - we release it.
981 	 * We timeout trying to get the lock - we force its release.
982 	 */
983 	ixgbe_get_swfw_sync_semaphore(hw);
984 	ixgbe_release_swfw_sync_semaphore(hw);
985 
986 	/* Acquire and release all software resources. */
987 	rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
988 		IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
989 		IXGBE_GSSR_SW_MNG_SM;
990 
991 	rmask |= IXGBE_GSSR_I2C_MASK;
992 	ixgbe_acquire_swfw_sync_X540(hw, rmask);
993 	ixgbe_release_swfw_sync_X540(hw, rmask);
994 }
995 
996 /**
997  * ixgbe_blink_led_start_X540 - Blink LED based on index.
998  * @hw: pointer to hardware structure
999  * @index: led number to blink
1000  *
1001  * Devices that implement the version 2 interface:
1002  *   X540
1003  **/
ixgbe_blink_led_start_X540(struct ixgbe_hw * hw,u32 index)1004 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
1005 {
1006 	u32 macc_reg;
1007 	u32 ledctl_reg;
1008 	ixgbe_link_speed speed;
1009 	bool link_up;
1010 
1011 	DEBUGFUNC("ixgbe_blink_led_start_X540");
1012 
1013 	if (index > 3)
1014 		return IXGBE_ERR_PARAM;
1015 
1016 	/*
1017 	 * Link should be up in order for the blink bit in the LED control
1018 	 * register to work. Force link and speed in the MAC if link is down.
1019 	 * This will be reversed when we stop the blinking.
1020 	 */
1021 	hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
1022 	if (link_up == FALSE) {
1023 		macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1024 		macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
1025 		IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1026 	}
1027 	/* Set the LED to LINK_UP + BLINK. */
1028 	ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1029 	ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1030 	ledctl_reg |= IXGBE_LED_BLINK(index);
1031 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1032 	IXGBE_WRITE_FLUSH(hw);
1033 
1034 	return IXGBE_SUCCESS;
1035 }
1036 
1037 /**
1038  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
1039  * @hw: pointer to hardware structure
1040  * @index: led number to stop blinking
1041  *
1042  * Devices that implement the version 2 interface:
1043  *   X540
1044  **/
ixgbe_blink_led_stop_X540(struct ixgbe_hw * hw,u32 index)1045 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1046 {
1047 	u32 macc_reg;
1048 	u32 ledctl_reg;
1049 
1050 	if (index > 3)
1051 		return IXGBE_ERR_PARAM;
1052 
1053 	DEBUGFUNC("ixgbe_blink_led_stop_X540");
1054 
1055 	/* Restore the LED to its default value. */
1056 	ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1057 	ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1058 	ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1059 	ledctl_reg &= ~IXGBE_LED_BLINK(index);
1060 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1061 
1062 	/* Unforce link and speed in the MAC. */
1063 	macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1064 	macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1065 	IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1066 	IXGBE_WRITE_FLUSH(hw);
1067 
1068 	return IXGBE_SUCCESS;
1069 }
1070