1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
38
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
51 u8 *sff8472_data);
52
53 /**
54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
55 * @hw: pointer to the hardware structure
56 * @byte: byte to send
57 *
58 * Returns an error code on error.
59 */
ixgbe_out_i2c_byte_ack(struct ixgbe_hw * hw,u8 byte)60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
61 {
62 s32 status;
63
64 status = ixgbe_clock_out_i2c_byte(hw, byte);
65 if (status)
66 return status;
67 return ixgbe_get_i2c_ack(hw);
68 }
69
70 /**
71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
72 * @hw: pointer to the hardware structure
73 * @byte: pointer to a u8 to receive the byte
74 *
75 * Returns an error code on error.
76 */
ixgbe_in_i2c_byte_ack(struct ixgbe_hw * hw,u8 * byte)77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
78 {
79 ixgbe_clock_in_i2c_byte(hw, byte);
80 /* ACK */
81 return ixgbe_clock_out_i2c_bit(hw, false);
82 }
83
84 /**
85 * ixgbe_ones_comp_byte_add - Perform one's complement addition
86 * @add1: addend 1
87 * @add2: addend 2
88 *
89 * Returns one's complement 8-bit sum.
90 */
ixgbe_ones_comp_byte_add(u8 add1,u8 add2)91 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
92 {
93 u16 sum = add1 + add2;
94
95 sum = (sum & 0xFF) + (sum >> 8);
96 return sum & 0xFF;
97 }
98
99 /**
100 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
101 * @hw: pointer to the hardware structure
102 * @addr: I2C bus address to read from
103 * @reg: I2C device register to read from
104 * @val: pointer to location to receive read value
105 * @lock: true if to take and release semaphore
106 *
107 * Returns an error code on error.
108 */
ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val,bool lock)109 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
110 u16 *val, bool lock)
111 {
112 u32 swfw_mask = hw->phy.phy_semaphore_mask;
113 int max_retry = 3;
114 int retry = 0;
115 u8 csum_byte;
116 u8 high_bits;
117 u8 low_bits;
118 u8 reg_high;
119 u8 csum;
120
121 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
122 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
123 csum = ~csum;
124 do {
125 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
126 return IXGBE_ERR_SWFW_SYNC;
127 ixgbe_i2c_start(hw);
128 /* Device Address and write indication */
129 if (ixgbe_out_i2c_byte_ack(hw, addr))
130 goto fail;
131 /* Write bits 14:8 */
132 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
133 goto fail;
134 /* Write bits 7:0 */
135 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
136 goto fail;
137 /* Write csum */
138 if (ixgbe_out_i2c_byte_ack(hw, csum))
139 goto fail;
140 /* Re-start condition */
141 ixgbe_i2c_start(hw);
142 /* Device Address and read indication */
143 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
144 goto fail;
145 /* Get upper bits */
146 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
147 goto fail;
148 /* Get low bits */
149 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
150 goto fail;
151 /* Get csum */
152 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
153 /* NACK */
154 if (ixgbe_clock_out_i2c_bit(hw, false))
155 goto fail;
156 ixgbe_i2c_stop(hw);
157 if (lock)
158 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
159 *val = (high_bits << 8) | low_bits;
160 return 0;
161
162 fail:
163 ixgbe_i2c_bus_clear(hw);
164 if (lock)
165 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
166 if (retry < max_retry)
167 DEBUGOUT("I2C byte read combined error - Retrying.\n");
168 else
169 DEBUGOUT("I2C byte read combined error.\n");
170 retry++;
171 } while (retry <= max_retry);
172
173 return IXGBE_ERR_I2C;
174 }
175
176 /**
177 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
178 * @hw: pointer to the hardware structure
179 * @addr: I2C bus address to write to
180 * @reg: I2C device register to write to
181 * @val: value to write
182 * @lock: true if to take and release semaphore
183 *
184 * Returns an error code on error.
185 */
ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val,bool lock)186 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
187 u16 val, bool lock)
188 {
189 u32 swfw_mask = hw->phy.phy_semaphore_mask;
190 int max_retry = 1;
191 int retry = 0;
192 u8 reg_high;
193 u8 csum;
194
195 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
196 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
197 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
198 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
199 csum = ~csum;
200 do {
201 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
202 return IXGBE_ERR_SWFW_SYNC;
203 ixgbe_i2c_start(hw);
204 /* Device Address and write indication */
205 if (ixgbe_out_i2c_byte_ack(hw, addr))
206 goto fail;
207 /* Write bits 14:8 */
208 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
209 goto fail;
210 /* Write bits 7:0 */
211 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
212 goto fail;
213 /* Write data 15:8 */
214 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
215 goto fail;
216 /* Write data 7:0 */
217 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
218 goto fail;
219 /* Write csum */
220 if (ixgbe_out_i2c_byte_ack(hw, csum))
221 goto fail;
222 ixgbe_i2c_stop(hw);
223 if (lock)
224 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
225 return 0;
226
227 fail:
228 ixgbe_i2c_bus_clear(hw);
229 if (lock)
230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
231 if (retry < max_retry)
232 DEBUGOUT("I2C byte write combined error - Retrying.\n");
233 else
234 DEBUGOUT("I2C byte write combined error.\n");
235 retry++;
236 } while (retry <= max_retry);
237
238 return IXGBE_ERR_I2C;
239 }
240
241 /**
242 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
243 * @hw: pointer to the hardware structure
244 *
245 * Initialize the function pointers.
246 **/
ixgbe_init_phy_ops_generic(struct ixgbe_hw * hw)247 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
248 {
249 struct ixgbe_phy_info *phy = &hw->phy;
250
251 DEBUGFUNC("ixgbe_init_phy_ops_generic");
252
253 /* PHY */
254 phy->ops.identify = ixgbe_identify_phy_generic;
255 phy->ops.reset = ixgbe_reset_phy_generic;
256 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
257 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
258 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
259 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
260 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
261 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
262 phy->ops.check_link = NULL;
263 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
264 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
265 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
266 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
267 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
268 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
269 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
270 phy->ops.identify_sfp = ixgbe_identify_module_generic;
271 phy->sfp_type = ixgbe_sfp_type_unknown;
272 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
273 phy->ops.write_i2c_byte_unlocked =
274 ixgbe_write_i2c_byte_generic_unlocked;
275 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
276 return IXGBE_SUCCESS;
277 }
278
279 /**
280 * ixgbe_probe_phy - Probe a single address for a PHY
281 * @hw: pointer to hardware structure
282 * @phy_addr: PHY address to probe
283 *
284 * Returns true if PHY found
285 */
ixgbe_probe_phy(struct ixgbe_hw * hw,u16 phy_addr)286 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
287 {
288 u16 ext_ability = 0;
289
290 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
291 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
292 phy_addr);
293 return false;
294 }
295
296 if (ixgbe_get_phy_id(hw))
297 return false;
298
299 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
300
301 if (hw->phy.type == ixgbe_phy_unknown) {
302 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
303 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
304 if (ext_ability &
305 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
306 IXGBE_MDIO_PHY_1000BASET_ABILITY))
307 hw->phy.type = ixgbe_phy_cu_unknown;
308 else
309 hw->phy.type = ixgbe_phy_generic;
310 }
311
312 return true;
313 }
314
315 /**
316 * ixgbe_identify_phy_generic - Get physical layer module
317 * @hw: pointer to hardware structure
318 *
319 * Determines the physical layer module found on the current adapter.
320 **/
ixgbe_identify_phy_generic(struct ixgbe_hw * hw)321 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
322 {
323 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
324 u16 phy_addr;
325
326 DEBUGFUNC("ixgbe_identify_phy_generic");
327
328 if (!hw->phy.phy_semaphore_mask) {
329 if (hw->bus.lan_id)
330 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
331 else
332 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
333 }
334
335 if (hw->phy.type != ixgbe_phy_unknown)
336 return IXGBE_SUCCESS;
337
338 if (hw->phy.nw_mng_if_sel) {
339 phy_addr = (hw->phy.nw_mng_if_sel &
340 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
342 if (ixgbe_probe_phy(hw, phy_addr))
343 return IXGBE_SUCCESS;
344 else
345 return IXGBE_ERR_PHY_ADDR_INVALID;
346 }
347
348 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
349 if (ixgbe_probe_phy(hw, phy_addr)) {
350 status = IXGBE_SUCCESS;
351 break;
352 }
353 }
354
355 /* Certain media types do not have a phy so an address will not
356 * be found and the code will take this path. Caller has to
357 * decide if it is an error or not.
358 */
359 if (status != IXGBE_SUCCESS)
360 hw->phy.addr = 0;
361
362 return status;
363 }
364
365 /**
366 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
367 * @hw: pointer to the hardware structure
368 *
369 * This function checks the MMNGC.MNG_VETO bit to see if there are
370 * any constraints on link from manageability. For MAC's that don't
371 * have this bit just return faluse since the link can not be blocked
372 * via this method.
373 **/
ixgbe_check_reset_blocked(struct ixgbe_hw * hw)374 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
375 {
376 u32 mmngc;
377
378 DEBUGFUNC("ixgbe_check_reset_blocked");
379
380 /* If we don't have this bit, it can't be blocking */
381 if (hw->mac.type == ixgbe_mac_82598EB)
382 return false;
383
384 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
385 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
386 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
387 "MNG_VETO bit detected.\n");
388 return true;
389 }
390
391 return false;
392 }
393
394 /**
395 * ixgbe_validate_phy_addr - Determines phy address is valid
396 * @hw: pointer to hardware structure
397 * @phy_addr: PHY address
398 *
399 **/
ixgbe_validate_phy_addr(struct ixgbe_hw * hw,u32 phy_addr)400 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
401 {
402 u16 phy_id = 0;
403 bool valid = false;
404
405 DEBUGFUNC("ixgbe_validate_phy_addr");
406
407 hw->phy.addr = phy_addr;
408 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
409 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
410
411 if (phy_id != 0xFFFF && phy_id != 0x0)
412 valid = true;
413
414 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
415
416 return valid;
417 }
418
419 /**
420 * ixgbe_get_phy_id - Get the phy type
421 * @hw: pointer to hardware structure
422 *
423 **/
ixgbe_get_phy_id(struct ixgbe_hw * hw)424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
425 {
426 u32 status;
427 u16 phy_id_high = 0;
428 u16 phy_id_low = 0;
429
430 DEBUGFUNC("ixgbe_get_phy_id");
431
432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
433 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
434 &phy_id_high);
435
436 if (status == IXGBE_SUCCESS) {
437 hw->phy.id = (u32)(phy_id_high << 16);
438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
439 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
440 &phy_id_low);
441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
443 }
444 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
445 phy_id_high, phy_id_low);
446
447 return status;
448 }
449
450 /**
451 * ixgbe_get_phy_type_from_id - Get the phy type
452 * @phy_id: PHY ID information
453 *
454 **/
ixgbe_get_phy_type_from_id(u32 phy_id)455 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
456 {
457 enum ixgbe_phy_type phy_type;
458
459 DEBUGFUNC("ixgbe_get_phy_type_from_id");
460
461 switch (phy_id) {
462 case TN1010_PHY_ID:
463 phy_type = ixgbe_phy_tn;
464 break;
465 case X550_PHY_ID:
466 case X540_PHY_ID:
467 phy_type = ixgbe_phy_aq;
468 break;
469 case QT2022_PHY_ID:
470 phy_type = ixgbe_phy_qt;
471 break;
472 case ATH_PHY_ID:
473 phy_type = ixgbe_phy_nl;
474 break;
475 case X557_PHY_ID:
476 case X557_PHY_ID2:
477 phy_type = ixgbe_phy_x550em_ext_t;
478 break;
479 case IXGBE_M88E1500_E_PHY_ID:
480 case IXGBE_M88E1543_E_PHY_ID:
481 phy_type = ixgbe_phy_ext_1g_t;
482 break;
483 default:
484 phy_type = ixgbe_phy_unknown;
485 break;
486 }
487 return phy_type;
488 }
489
490 /**
491 * ixgbe_reset_phy_generic - Performs a PHY reset
492 * @hw: pointer to hardware structure
493 **/
ixgbe_reset_phy_generic(struct ixgbe_hw * hw)494 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
495 {
496 u32 i;
497 u16 ctrl = 0;
498 s32 status = IXGBE_SUCCESS;
499
500 DEBUGFUNC("ixgbe_reset_phy_generic");
501
502 if (hw->phy.type == ixgbe_phy_unknown)
503 status = ixgbe_identify_phy_generic(hw);
504
505 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
506 goto out;
507
508 /* Don't reset PHY if it's shut down due to overtemp. */
509 if (!hw->phy.reset_if_overtemp &&
510 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
511 goto out;
512
513 /* Blocked by MNG FW so bail */
514 if (ixgbe_check_reset_blocked(hw))
515 goto out;
516
517 /*
518 * Perform soft PHY reset to the PHY_XS.
519 * This will cause a soft reset to the PHY
520 */
521 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
522 IXGBE_MDIO_PHY_XS_DEV_TYPE,
523 IXGBE_MDIO_PHY_XS_RESET);
524
525 /*
526 * Poll for reset bit to self-clear indicating reset is complete.
527 * Some PHYs could take up to 3 seconds to complete and need about
528 * 1.7 usec delay after the reset is complete.
529 */
530 for (i = 0; i < 30; i++) {
531 msec_delay(100);
532 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
533 status = hw->phy.ops.read_reg(hw,
534 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
535 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
536 &ctrl);
537 if (status != IXGBE_SUCCESS)
538 return status;
539
540 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
541 usec_delay(2);
542 break;
543 }
544 } else {
545 status = hw->phy.ops.read_reg(hw,
546 IXGBE_MDIO_PHY_XS_CONTROL,
547 IXGBE_MDIO_PHY_XS_DEV_TYPE,
548 &ctrl);
549 if (status != IXGBE_SUCCESS)
550 return status;
551
552 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
553 usec_delay(2);
554 break;
555 }
556 }
557 }
558
559 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
560 status = IXGBE_ERR_RESET_FAILED;
561 ERROR_REPORT1(IXGBE_ERROR_POLLING,
562 "PHY reset polling failed to complete.\n");
563 }
564
565 out:
566 return status;
567 }
568
569 /**
570 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
571 * @hw: pointer to hardware structure
572 **/
ixgbe_restart_auto_neg(struct ixgbe_hw * hw)573 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
574 {
575 u16 autoneg_reg;
576
577 /* Check if PHY reset is blocked by MNG FW */
578 if (ixgbe_check_reset_blocked(hw))
579 return;
580
581 /* Restart PHY auto-negotiation. */
582 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
583 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
584 autoneg_reg |= IXGBE_MII_RESTART;
585 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
586 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
587 }
588
589 /**
590 * ixgbe_read_phy_reg_mdi - Reads a value from a specified PHY register without
591 * the SWFW lock
592 * @hw: pointer to hardware structure
593 * @reg_addr: 32 bit address of PHY register to read
594 * @device_type: 5 bit device type
595 * @phy_data: Pointer to read data from PHY register
596 **/
ixgbe_read_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)597 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
598 u16 *phy_data)
599 {
600 u32 i, data, command;
601
602 /* Setup and write the address cycle command */
603 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
604 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
605 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
606 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
607
608 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
609
610 /*
611 * Check every 10 usec to see if the address cycle completed.
612 * The MDI Command bit will clear when the operation is
613 * complete
614 */
615 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
616 usec_delay(10);
617
618 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
619 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
620 break;
621 }
622
623
624 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
625 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
626 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
627 return IXGBE_ERR_PHY;
628 }
629
630 /*
631 * Address cycle complete, setup and write the read
632 * command
633 */
634 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
635 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
636 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
637 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
638
639 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
640
641 /*
642 * Check every 10 usec to see if the address cycle
643 * completed. The MDI Command bit will clear when the
644 * operation is complete
645 */
646 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
647 usec_delay(10);
648
649 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
650 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
651 break;
652 }
653
654 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
655 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
656 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
657 return IXGBE_ERR_PHY;
658 }
659
660 /*
661 * Read operation is complete. Get the data
662 * from MSRWD
663 */
664 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
665 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
666 *phy_data = (u16)(data);
667
668 return IXGBE_SUCCESS;
669 }
670
671 /**
672 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
673 * using the SWFW lock - this function is needed in most cases
674 * @hw: pointer to hardware structure
675 * @reg_addr: 32 bit address of PHY register to read
676 * @device_type: 5 bit device type
677 * @phy_data: Pointer to read data from PHY register
678 **/
ixgbe_read_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)679 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
680 u32 device_type, u16 *phy_data)
681 {
682 s32 status;
683 u32 gssr = hw->phy.phy_semaphore_mask;
684
685 DEBUGFUNC("ixgbe_read_phy_reg_generic");
686
687 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
688 return IXGBE_ERR_SWFW_SYNC;
689
690 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
691
692 hw->mac.ops.release_swfw_sync(hw, gssr);
693
694 return status;
695 }
696
697 /**
698 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
699 * without SWFW lock
700 * @hw: pointer to hardware structure
701 * @reg_addr: 32 bit PHY register to write
702 * @device_type: 5 bit device type
703 * @phy_data: Data to write to the PHY register
704 **/
ixgbe_write_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)705 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
706 u32 device_type, u16 phy_data)
707 {
708 u32 i, command;
709
710 /* Put the data in the MDI single read and write data register*/
711 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
712
713 /* Setup and write the address cycle command */
714 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
715 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
716 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
717 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
718
719 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
720
721 /*
722 * Check every 10 usec to see if the address cycle completed.
723 * The MDI Command bit will clear when the operation is
724 * complete
725 */
726 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
727 usec_delay(10);
728
729 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
730 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
731 break;
732 }
733
734 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
735 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
736 return IXGBE_ERR_PHY;
737 }
738
739 /*
740 * Address cycle complete, setup and write the write
741 * command
742 */
743 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
744 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
745 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
746 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
747
748 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
749
750 /*
751 * Check every 10 usec to see if the address cycle
752 * completed. The MDI Command bit will clear when the
753 * operation is complete
754 */
755 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
756 usec_delay(10);
757
758 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
759 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
760 break;
761 }
762
763 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
764 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
765 return IXGBE_ERR_PHY;
766 }
767
768 return IXGBE_SUCCESS;
769 }
770
771 /**
772 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
773 * using SWFW lock- this function is needed in most cases
774 * @hw: pointer to hardware structure
775 * @reg_addr: 32 bit PHY register to write
776 * @device_type: 5 bit device type
777 * @phy_data: Data to write to the PHY register
778 **/
ixgbe_write_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)779 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
780 u32 device_type, u16 phy_data)
781 {
782 s32 status;
783 u32 gssr = hw->phy.phy_semaphore_mask;
784
785 DEBUGFUNC("ixgbe_write_phy_reg_generic");
786
787 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
788 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
789 phy_data);
790 hw->mac.ops.release_swfw_sync(hw, gssr);
791 } else {
792 status = IXGBE_ERR_SWFW_SYNC;
793 }
794
795 return status;
796 }
797
798 /**
799 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
800 * @hw: pointer to hardware structure
801 *
802 * Restart auto-negotiation and PHY and waits for completion.
803 **/
ixgbe_setup_phy_link_generic(struct ixgbe_hw * hw)804 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
805 {
806 s32 status = IXGBE_SUCCESS;
807 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
808 bool autoneg = false;
809 ixgbe_link_speed speed;
810
811 DEBUGFUNC("ixgbe_setup_phy_link_generic");
812
813 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
814
815 /* Set or unset auto-negotiation 10G advertisement */
816 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
817 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
818 &autoneg_reg);
819
820 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
822 (speed & IXGBE_LINK_SPEED_10GB_FULL))
823 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
824
825 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
827 autoneg_reg);
828
829 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
830 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
831 &autoneg_reg);
832
833 if (hw->mac.type == ixgbe_mac_X550) {
834 /* Set or unset auto-negotiation 5G advertisement */
835 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
836 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
837 (speed & IXGBE_LINK_SPEED_5GB_FULL))
838 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
839
840 /* Set or unset auto-negotiation 2.5G advertisement */
841 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
842 if ((hw->phy.autoneg_advertised &
843 IXGBE_LINK_SPEED_2_5GB_FULL) &&
844 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
845 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
846 }
847
848 /* Set or unset auto-negotiation 1G advertisement */
849 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
850 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
851 (speed & IXGBE_LINK_SPEED_1GB_FULL))
852 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
853
854 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
855 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
856 autoneg_reg);
857
858 /* Set or unset auto-negotiation 100M advertisement */
859 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
860 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
861 &autoneg_reg);
862
863 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
864 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
865 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
866 (speed & IXGBE_LINK_SPEED_100_FULL))
867 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
868
869 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
870 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
871 autoneg_reg);
872
873 ixgbe_restart_auto_neg(hw);
874 return status;
875 }
876
877 /**
878 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
879 * @hw: pointer to hardware structure
880 * @speed: new link speed
881 * @autoneg_wait_to_complete: unused
882 **/
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)883 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
884 ixgbe_link_speed speed,
885 bool autoneg_wait_to_complete)
886 {
887 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
888
889 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
890
891 /*
892 * Clear autoneg_advertised and set new values based on input link
893 * speed.
894 */
895 hw->phy.autoneg_advertised = 0;
896
897 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
898 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
899
900 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
901 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
902
903 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
904 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
905
906 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
907 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
908
909 if (speed & IXGBE_LINK_SPEED_100_FULL)
910 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
911
912 if (speed & IXGBE_LINK_SPEED_10_FULL)
913 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
914
915 /* Setup link based on the new speed settings */
916 ixgbe_setup_phy_link(hw);
917
918 return IXGBE_SUCCESS;
919 }
920
921 /**
922 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
923 * @hw: pointer to hardware structure
924 *
925 * Determines the supported link capabilities by reading the PHY auto
926 * negotiation register.
927 **/
ixgbe_get_copper_speeds_supported(struct ixgbe_hw * hw)928 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
929 {
930 s32 status;
931 u16 speed_ability;
932
933 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
934 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
935 &speed_ability);
936 if (status)
937 return status;
938
939 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
940 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
943 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
945
946 switch (hw->mac.type) {
947 case ixgbe_mac_X550:
948 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
949 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
950 break;
951 case ixgbe_mac_X550EM_x:
952 case ixgbe_mac_X550EM_a:
953 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
954 break;
955 default:
956 break;
957 }
958
959 return status;
960 }
961
962 /**
963 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
964 * @hw: pointer to hardware structure
965 * @speed: pointer to link speed
966 * @autoneg: boolean auto-negotiation value
967 **/
ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)968 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
969 ixgbe_link_speed *speed,
970 bool *autoneg)
971 {
972 s32 status = IXGBE_SUCCESS;
973
974 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
975
976 *autoneg = true;
977 if (!hw->phy.speeds_supported)
978 status = ixgbe_get_copper_speeds_supported(hw);
979
980 *speed = hw->phy.speeds_supported;
981 return status;
982 }
983
984 /**
985 * ixgbe_check_phy_link_tnx - Determine link and speed status
986 * @hw: pointer to hardware structure
987 * @speed: current link speed
988 * @link_up: true is link is up, false otherwise
989 *
990 * Reads the VS1 register to determine if link is up and the current speed for
991 * the PHY.
992 **/
ixgbe_check_phy_link_tnx(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up)993 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
994 bool *link_up)
995 {
996 s32 status = IXGBE_SUCCESS;
997 u32 time_out;
998 u32 max_time_out = 10;
999 u16 phy_link = 0;
1000 u16 phy_speed = 0;
1001 u16 phy_data = 0;
1002
1003 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1004
1005 /* Initialize speed and link to default case */
1006 *link_up = false;
1007 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1008
1009 /*
1010 * Check current speed and link status of the PHY register.
1011 * This is a vendor specific register and may have to
1012 * be changed for other copper PHYs.
1013 */
1014 for (time_out = 0; time_out < max_time_out; time_out++) {
1015 usec_delay(10);
1016 status = hw->phy.ops.read_reg(hw,
1017 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1018 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1019 &phy_data);
1020 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1021 phy_speed = phy_data &
1022 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1023 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1024 *link_up = true;
1025 if (phy_speed ==
1026 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1027 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1028 break;
1029 }
1030 }
1031
1032 return status;
1033 }
1034
1035 /**
1036 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1037 * @hw: pointer to hardware structure
1038 *
1039 * Restart auto-negotiation and PHY and waits for completion.
1040 **/
ixgbe_setup_phy_link_tnx(struct ixgbe_hw * hw)1041 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1042 {
1043 s32 status = IXGBE_SUCCESS;
1044 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1045 bool autoneg = false;
1046 ixgbe_link_speed speed;
1047
1048 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1049
1050 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1051
1052 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1053 /* Set or unset auto-negotiation 10G advertisement */
1054 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1055 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1056 &autoneg_reg);
1057
1058 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1059 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1060 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1061
1062 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1063 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1064 autoneg_reg);
1065 }
1066
1067 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1068 /* Set or unset auto-negotiation 1G advertisement */
1069 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1070 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1071 &autoneg_reg);
1072
1073 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1074 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1075 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1076
1077 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1078 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1079 autoneg_reg);
1080 }
1081
1082 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1083 /* Set or unset auto-negotiation 100M advertisement */
1084 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1086 &autoneg_reg);
1087
1088 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1089 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1090 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1091
1092 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1093 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1094 autoneg_reg);
1095 }
1096
1097 ixgbe_restart_auto_neg(hw);
1098 return status;
1099 }
1100
1101 /**
1102 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1103 * @hw: pointer to hardware structure
1104 * @firmware_version: pointer to the PHY Firmware Version
1105 **/
ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw * hw,u16 * firmware_version)1106 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1107 u16 *firmware_version)
1108 {
1109 s32 status;
1110
1111 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1112
1113 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1114 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1115 firmware_version);
1116
1117 return status;
1118 }
1119
1120 /**
1121 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1122 * @hw: pointer to hardware structure
1123 * @firmware_version: pointer to the PHY Firmware Version
1124 **/
ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw * hw,u16 * firmware_version)1125 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1126 u16 *firmware_version)
1127 {
1128 s32 status;
1129
1130 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1131
1132 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1133 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1134 firmware_version);
1135
1136 return status;
1137 }
1138
1139 /**
1140 * ixgbe_reset_phy_nl - Performs a PHY reset
1141 * @hw: pointer to hardware structure
1142 **/
ixgbe_reset_phy_nl(struct ixgbe_hw * hw)1143 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1144 {
1145 u16 phy_offset, control, eword, edata, block_crc;
1146 bool end_data = false;
1147 u16 list_offset, data_offset;
1148 u16 phy_data = 0;
1149 s32 ret_val = IXGBE_SUCCESS;
1150 u32 i;
1151
1152 DEBUGFUNC("ixgbe_reset_phy_nl");
1153
1154 /* Blocked by MNG FW so bail */
1155 if (ixgbe_check_reset_blocked(hw))
1156 goto out;
1157
1158 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1159 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1160
1161 /* reset the PHY and poll for completion */
1162 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1163 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1164 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1165
1166 for (i = 0; i < 100; i++) {
1167 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1168 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1169 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1170 break;
1171 msec_delay(10);
1172 }
1173
1174 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1175 DEBUGOUT("PHY reset did not complete.\n");
1176 ret_val = IXGBE_ERR_PHY;
1177 goto out;
1178 }
1179
1180 /* Get init offsets */
1181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1182 &data_offset);
1183 if (ret_val != IXGBE_SUCCESS)
1184 goto out;
1185
1186 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1187 data_offset++;
1188 while (!end_data) {
1189 /*
1190 * Read control word from PHY init contents offset
1191 */
1192 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1193 if (ret_val)
1194 goto err_eeprom;
1195 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1196 IXGBE_CONTROL_SHIFT_NL;
1197 edata = eword & IXGBE_DATA_MASK_NL;
1198 switch (control) {
1199 case IXGBE_DELAY_NL:
1200 data_offset++;
1201 DEBUGOUT1("DELAY: %d MS\n", edata);
1202 msec_delay(edata);
1203 break;
1204 case IXGBE_DATA_NL:
1205 DEBUGOUT("DATA:\n");
1206 data_offset++;
1207 ret_val = hw->eeprom.ops.read(hw, data_offset,
1208 &phy_offset);
1209 if (ret_val)
1210 goto err_eeprom;
1211 data_offset++;
1212 for (i = 0; i < edata; i++) {
1213 ret_val = hw->eeprom.ops.read(hw, data_offset,
1214 &eword);
1215 if (ret_val)
1216 goto err_eeprom;
1217 hw->phy.ops.write_reg(hw, phy_offset,
1218 IXGBE_TWINAX_DEV, eword);
1219 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1220 phy_offset);
1221 data_offset++;
1222 phy_offset++;
1223 }
1224 break;
1225 case IXGBE_CONTROL_NL:
1226 data_offset++;
1227 DEBUGOUT("CONTROL:\n");
1228 if (edata == IXGBE_CONTROL_EOL_NL) {
1229 DEBUGOUT("EOL\n");
1230 end_data = true;
1231 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1232 DEBUGOUT("SOL\n");
1233 } else {
1234 DEBUGOUT("Bad control value\n");
1235 ret_val = IXGBE_ERR_PHY;
1236 goto out;
1237 }
1238 break;
1239 default:
1240 DEBUGOUT("Bad control type\n");
1241 ret_val = IXGBE_ERR_PHY;
1242 goto out;
1243 }
1244 }
1245
1246 out:
1247 return ret_val;
1248
1249 err_eeprom:
1250 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1251 "eeprom read at offset %d failed", data_offset);
1252 return IXGBE_ERR_PHY;
1253 }
1254
1255 /**
1256 * ixgbe_identify_module_generic - Identifies module type
1257 * @hw: pointer to hardware structure
1258 *
1259 * Determines HW type and calls appropriate function.
1260 **/
ixgbe_identify_module_generic(struct ixgbe_hw * hw)1261 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1262 {
1263 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1264
1265 DEBUGFUNC("ixgbe_identify_module_generic");
1266
1267 switch (hw->mac.ops.get_media_type(hw)) {
1268 case ixgbe_media_type_fiber:
1269 status = ixgbe_identify_sfp_module_generic(hw);
1270 break;
1271
1272 case ixgbe_media_type_fiber_qsfp:
1273 status = ixgbe_identify_qsfp_module_generic(hw);
1274 break;
1275
1276 default:
1277 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1278 status = IXGBE_ERR_SFP_NOT_PRESENT;
1279 break;
1280 }
1281
1282 return status;
1283 }
1284
1285 /**
1286 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1287 * @hw: pointer to hardware structure
1288 *
1289 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1290 **/
ixgbe_identify_sfp_module_generic(struct ixgbe_hw * hw)1291 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1292 {
1293 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1294 u32 vendor_oui = 0;
1295 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1296 u8 identifier = 0;
1297 u8 comp_codes_1g = 0;
1298 u8 comp_codes_10g = 0;
1299 u8 oui_bytes[3] = {0, 0, 0};
1300 u8 cable_tech = 0;
1301 u8 cable_spec = 0;
1302 u16 enforce_sfp = 0;
1303 static bool warned_once = false;
1304
1305 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1306
1307 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1308 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1309 status = IXGBE_ERR_SFP_NOT_PRESENT;
1310 goto out;
1311 }
1312
1313 /* LAN ID is needed for I2C access */
1314 hw->mac.ops.set_lan_id(hw);
1315
1316 status = hw->phy.ops.read_i2c_eeprom(hw,
1317 IXGBE_SFF_IDENTIFIER,
1318 &identifier);
1319
1320 if (status != IXGBE_SUCCESS)
1321 goto err_read_i2c_eeprom;
1322
1323 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1324 hw->phy.type = ixgbe_phy_sfp_unsupported;
1325 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1326 } else {
1327 status = hw->phy.ops.read_i2c_eeprom(hw,
1328 IXGBE_SFF_1GBE_COMP_CODES,
1329 &comp_codes_1g);
1330
1331 if (status != IXGBE_SUCCESS)
1332 goto err_read_i2c_eeprom;
1333
1334 status = hw->phy.ops.read_i2c_eeprom(hw,
1335 IXGBE_SFF_10GBE_COMP_CODES,
1336 &comp_codes_10g);
1337
1338 if (status != IXGBE_SUCCESS)
1339 goto err_read_i2c_eeprom;
1340 status = hw->phy.ops.read_i2c_eeprom(hw,
1341 IXGBE_SFF_CABLE_TECHNOLOGY,
1342 &cable_tech);
1343
1344 if (status != IXGBE_SUCCESS)
1345 goto err_read_i2c_eeprom;
1346
1347 /* ID Module
1348 * =========
1349 * 0 SFP_DA_CU
1350 * 1 SFP_SR
1351 * 2 SFP_LR
1352 * 3 SFP_DA_CORE0 - 82599-specific
1353 * 4 SFP_DA_CORE1 - 82599-specific
1354 * 5 SFP_SR/LR_CORE0 - 82599-specific
1355 * 6 SFP_SR/LR_CORE1 - 82599-specific
1356 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1357 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1358 * 9 SFP_1g_cu_CORE0 - 82599-specific
1359 * 10 SFP_1g_cu_CORE1 - 82599-specific
1360 * 11 SFP_1g_sx_CORE0 - 82599-specific
1361 * 12 SFP_1g_sx_CORE1 - 82599-specific
1362 */
1363 if (hw->mac.type == ixgbe_mac_82598EB) {
1364 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1365 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1366 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1367 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1368 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1369 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1370 else
1371 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1372 } else {
1373 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1374 if (hw->bus.lan_id == 0)
1375 hw->phy.sfp_type =
1376 ixgbe_sfp_type_da_cu_core0;
1377 else
1378 hw->phy.sfp_type =
1379 ixgbe_sfp_type_da_cu_core1;
1380 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1381 hw->phy.ops.read_i2c_eeprom(
1382 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1383 &cable_spec);
1384 if (cable_spec &
1385 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1386 if (hw->bus.lan_id == 0)
1387 hw->phy.sfp_type =
1388 ixgbe_sfp_type_da_act_lmt_core0;
1389 else
1390 hw->phy.sfp_type =
1391 ixgbe_sfp_type_da_act_lmt_core1;
1392 } else {
1393 hw->phy.sfp_type =
1394 ixgbe_sfp_type_unknown;
1395 }
1396 } else if (comp_codes_10g &
1397 (IXGBE_SFF_10GBASESR_CAPABLE |
1398 IXGBE_SFF_10GBASELR_CAPABLE)) {
1399 if (hw->bus.lan_id == 0)
1400 hw->phy.sfp_type =
1401 ixgbe_sfp_type_srlr_core0;
1402 else
1403 hw->phy.sfp_type =
1404 ixgbe_sfp_type_srlr_core1;
1405 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1406 if (hw->bus.lan_id == 0)
1407 hw->phy.sfp_type =
1408 ixgbe_sfp_type_1g_cu_core0;
1409 else
1410 hw->phy.sfp_type =
1411 ixgbe_sfp_type_1g_cu_core1;
1412 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1413 if (hw->bus.lan_id == 0)
1414 hw->phy.sfp_type =
1415 ixgbe_sfp_type_1g_sx_core0;
1416 else
1417 hw->phy.sfp_type =
1418 ixgbe_sfp_type_1g_sx_core1;
1419 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1420 if (hw->bus.lan_id == 0)
1421 hw->phy.sfp_type =
1422 ixgbe_sfp_type_1g_lx_core0;
1423 else
1424 hw->phy.sfp_type =
1425 ixgbe_sfp_type_1g_lx_core1;
1426 } else if (comp_codes_1g & IXGBE_SFF_BASEBX10_CAPABLE) {
1427 if (hw->bus.lan_id == 0)
1428 hw->phy.sfp_type =
1429 ixgbe_sfp_type_1g_bx_core0;
1430 else
1431 hw->phy.sfp_type =
1432 ixgbe_sfp_type_1g_bx_core1;
1433 } else {
1434 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1435 }
1436 }
1437
1438 if (hw->phy.sfp_type != stored_sfp_type)
1439 hw->phy.sfp_setup_needed = true;
1440
1441 /* Determine if the SFP+ PHY is dual speed or not. */
1442 hw->phy.multispeed_fiber = false;
1443 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1444 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1445 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1446 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)) ||
1447 (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) ||
1448 (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE))
1449 hw->phy.multispeed_fiber = true;
1450
1451 /* Determine PHY vendor */
1452 if (hw->phy.type != ixgbe_phy_nl) {
1453 hw->phy.id = identifier;
1454 status = hw->phy.ops.read_i2c_eeprom(hw,
1455 IXGBE_SFF_VENDOR_OUI_BYTE0,
1456 &oui_bytes[0]);
1457
1458 if (status != IXGBE_SUCCESS)
1459 goto err_read_i2c_eeprom;
1460
1461 status = hw->phy.ops.read_i2c_eeprom(hw,
1462 IXGBE_SFF_VENDOR_OUI_BYTE1,
1463 &oui_bytes[1]);
1464
1465 if (status != IXGBE_SUCCESS)
1466 goto err_read_i2c_eeprom;
1467
1468 status = hw->phy.ops.read_i2c_eeprom(hw,
1469 IXGBE_SFF_VENDOR_OUI_BYTE2,
1470 &oui_bytes[2]);
1471
1472 if (status != IXGBE_SUCCESS)
1473 goto err_read_i2c_eeprom;
1474
1475 vendor_oui =
1476 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1477 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1478 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1479
1480 switch (vendor_oui) {
1481 case IXGBE_SFF_VENDOR_OUI_TYCO:
1482 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1483 hw->phy.type =
1484 ixgbe_phy_sfp_passive_tyco;
1485 break;
1486 case IXGBE_SFF_VENDOR_OUI_FTL:
1487 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1488 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1489 else
1490 hw->phy.type = ixgbe_phy_sfp_ftl;
1491 break;
1492 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1493 hw->phy.type = ixgbe_phy_sfp_avago;
1494 break;
1495 case IXGBE_SFF_VENDOR_OUI_INTEL:
1496 hw->phy.type = ixgbe_phy_sfp_intel;
1497 break;
1498 default:
1499 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1500 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1501 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1502 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1503 else
1504 hw->phy.type = ixgbe_phy_sfp_unknown;
1505 break;
1506 }
1507 }
1508
1509 /* Allow any DA cable vendor */
1510 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1511 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1512 status = IXGBE_SUCCESS;
1513 goto out;
1514 }
1515
1516 /* Verify supported 1G SFP modules */
1517 if (comp_codes_10g == 0 &&
1518 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1520 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1521 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1522 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1523 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1524 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1525 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {
1526 hw->phy.type = ixgbe_phy_sfp_unsupported;
1527 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1528 goto out;
1529 }
1530
1531 /* Anything else 82598-based is supported */
1532 if (hw->mac.type == ixgbe_mac_82598EB) {
1533 status = IXGBE_SUCCESS;
1534 goto out;
1535 }
1536
1537 ixgbe_get_device_caps(hw, &enforce_sfp);
1538 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1539 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1540 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1541 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1543 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1544 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1545 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1546 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {
1547 /* Make sure we're a supported PHY type */
1548 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1549 status = IXGBE_SUCCESS;
1550 } else {
1551 if (hw->allow_unsupported_sfp == true) {
1552 if (!warned_once)
1553 EWARN(hw,
1554 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1555 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1556 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1557 warned_once = true;
1558 status = IXGBE_SUCCESS;
1559 } else {
1560 DEBUGOUT
1561 ("SFP+ module not supported\n");
1562 hw->phy.type =
1563 ixgbe_phy_sfp_unsupported;
1564 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1565 }
1566 }
1567 } else {
1568 status = IXGBE_SUCCESS;
1569 }
1570 }
1571
1572 out:
1573 return status;
1574
1575 err_read_i2c_eeprom:
1576 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1577 if (hw->phy.type != ixgbe_phy_nl) {
1578 hw->phy.id = 0;
1579 hw->phy.type = ixgbe_phy_unknown;
1580 }
1581 return IXGBE_ERR_SFP_NOT_PRESENT;
1582 }
1583
1584 /**
1585 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1586 * @hw: pointer to hardware structure
1587 *
1588 * Determines physical layer capabilities of the current SFP.
1589 */
ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw * hw)1590 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1591 {
1592 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1593 u8 comp_codes_10g = 0;
1594 u8 comp_codes_1g = 0;
1595
1596 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1597
1598 hw->phy.ops.identify_sfp(hw);
1599 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1600 return physical_layer;
1601
1602 switch (hw->phy.type) {
1603 case ixgbe_phy_sfp_passive_tyco:
1604 case ixgbe_phy_sfp_passive_unknown:
1605 case ixgbe_phy_qsfp_passive_unknown:
1606 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1607 break;
1608 case ixgbe_phy_sfp_ftl_active:
1609 case ixgbe_phy_sfp_active_unknown:
1610 case ixgbe_phy_qsfp_active_unknown:
1611 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1612 break;
1613 case ixgbe_phy_sfp_avago:
1614 case ixgbe_phy_sfp_ftl:
1615 case ixgbe_phy_sfp_intel:
1616 case ixgbe_phy_sfp_unknown:
1617 hw->phy.ops.read_i2c_eeprom(hw,
1618 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1619 hw->phy.ops.read_i2c_eeprom(hw,
1620 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1621 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1622 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1623 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1624 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1625 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1626 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1627 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1628 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1629 else if (comp_codes_1g & IXGBE_SFF_BASEBX10_CAPABLE)
1630 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1631 break;
1632 case ixgbe_phy_qsfp_intel:
1633 case ixgbe_phy_qsfp_unknown:
1634 hw->phy.ops.read_i2c_eeprom(hw,
1635 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1636 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1637 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1638 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1639 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1640 break;
1641 default:
1642 break;
1643 }
1644
1645 return physical_layer;
1646 }
1647
1648 /**
1649 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1650 * @hw: pointer to hardware structure
1651 *
1652 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1653 **/
ixgbe_identify_qsfp_module_generic(struct ixgbe_hw * hw)1654 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1655 {
1656 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1657 u32 vendor_oui = 0;
1658 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1659 u8 identifier = 0;
1660 u8 comp_codes_1g = 0;
1661 u8 comp_codes_10g = 0;
1662 u8 oui_bytes[3] = {0, 0, 0};
1663 u16 enforce_sfp = 0;
1664 u8 connector = 0;
1665 u8 cable_length = 0;
1666 u8 device_tech = 0;
1667 bool active_cable = false;
1668 static bool warned_once = false;
1669
1670 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1671
1672 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1673 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1674 status = IXGBE_ERR_SFP_NOT_PRESENT;
1675 goto out;
1676 }
1677
1678 /* LAN ID is needed for I2C access */
1679 hw->mac.ops.set_lan_id(hw);
1680
1681 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1682 &identifier);
1683
1684 if (status != IXGBE_SUCCESS)
1685 goto err_read_i2c_eeprom;
1686
1687 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1688 hw->phy.type = ixgbe_phy_sfp_unsupported;
1689 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1690 goto out;
1691 }
1692
1693 hw->phy.id = identifier;
1694
1695 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1696 &comp_codes_10g);
1697
1698 if (status != IXGBE_SUCCESS)
1699 goto err_read_i2c_eeprom;
1700
1701 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1702 &comp_codes_1g);
1703
1704 if (status != IXGBE_SUCCESS)
1705 goto err_read_i2c_eeprom;
1706
1707 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1708 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1709 if (hw->bus.lan_id == 0)
1710 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1711 else
1712 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1713 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1714 IXGBE_SFF_10GBASELR_CAPABLE)) {
1715 if (hw->bus.lan_id == 0)
1716 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1717 else
1718 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1719 } else {
1720 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1721 active_cable = true;
1722
1723 if (!active_cable) {
1724 /* check for active DA cables that pre-date
1725 * SFF-8436 v3.6 */
1726 hw->phy.ops.read_i2c_eeprom(hw,
1727 IXGBE_SFF_QSFP_CONNECTOR,
1728 &connector);
1729
1730 hw->phy.ops.read_i2c_eeprom(hw,
1731 IXGBE_SFF_QSFP_CABLE_LENGTH,
1732 &cable_length);
1733
1734 hw->phy.ops.read_i2c_eeprom(hw,
1735 IXGBE_SFF_QSFP_DEVICE_TECH,
1736 &device_tech);
1737
1738 if ((connector ==
1739 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1740 (cable_length > 0) &&
1741 ((device_tech >> 4) ==
1742 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1743 active_cable = true;
1744 }
1745
1746 if (active_cable) {
1747 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1748 if (hw->bus.lan_id == 0)
1749 hw->phy.sfp_type =
1750 ixgbe_sfp_type_da_act_lmt_core0;
1751 else
1752 hw->phy.sfp_type =
1753 ixgbe_sfp_type_da_act_lmt_core1;
1754 } else {
1755 /* unsupported module type */
1756 hw->phy.type = ixgbe_phy_sfp_unsupported;
1757 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1758 goto out;
1759 }
1760 }
1761
1762 if (hw->phy.sfp_type != stored_sfp_type)
1763 hw->phy.sfp_setup_needed = true;
1764
1765 /* Determine if the QSFP+ PHY is dual speed or not. */
1766 hw->phy.multispeed_fiber = false;
1767 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1768 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1769 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1770 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1771 hw->phy.multispeed_fiber = true;
1772
1773 /* Determine PHY vendor for optical modules */
1774 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1775 IXGBE_SFF_10GBASELR_CAPABLE)) {
1776 status = hw->phy.ops.read_i2c_eeprom(hw,
1777 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1778 &oui_bytes[0]);
1779
1780 if (status != IXGBE_SUCCESS)
1781 goto err_read_i2c_eeprom;
1782
1783 status = hw->phy.ops.read_i2c_eeprom(hw,
1784 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1785 &oui_bytes[1]);
1786
1787 if (status != IXGBE_SUCCESS)
1788 goto err_read_i2c_eeprom;
1789
1790 status = hw->phy.ops.read_i2c_eeprom(hw,
1791 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1792 &oui_bytes[2]);
1793
1794 if (status != IXGBE_SUCCESS)
1795 goto err_read_i2c_eeprom;
1796
1797 vendor_oui =
1798 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1799 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1800 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1801
1802 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1803 hw->phy.type = ixgbe_phy_qsfp_intel;
1804 else
1805 hw->phy.type = ixgbe_phy_qsfp_unknown;
1806
1807 ixgbe_get_device_caps(hw, &enforce_sfp);
1808 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1809 /* Make sure we're a supported PHY type */
1810 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1811 status = IXGBE_SUCCESS;
1812 } else {
1813 if (hw->allow_unsupported_sfp == true) {
1814 if (!warned_once)
1815 EWARN(hw,
1816 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1817 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1818 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1819 warned_once = true;
1820 status = IXGBE_SUCCESS;
1821 } else {
1822 DEBUGOUT("QSFP module not supported\n");
1823 hw->phy.type =
1824 ixgbe_phy_sfp_unsupported;
1825 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1826 }
1827 }
1828 } else {
1829 status = IXGBE_SUCCESS;
1830 }
1831 }
1832
1833 out:
1834 return status;
1835
1836 err_read_i2c_eeprom:
1837 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1838 hw->phy.id = 0;
1839 hw->phy.type = ixgbe_phy_unknown;
1840
1841 return IXGBE_ERR_SFP_NOT_PRESENT;
1842 }
1843
1844 /**
1845 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1846 * @hw: pointer to hardware structure
1847 * @list_offset: offset to the SFP ID list
1848 * @data_offset: offset to the SFP data block
1849 *
1850 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1851 * so it returns the offsets to the phy init sequence block.
1852 **/
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw * hw,u16 * list_offset,u16 * data_offset)1853 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1854 u16 *list_offset,
1855 u16 *data_offset)
1856 {
1857 u16 sfp_id;
1858 u16 sfp_type = hw->phy.sfp_type;
1859
1860 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1861
1862 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1863 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1864
1865 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1866 return IXGBE_ERR_SFP_NOT_PRESENT;
1867
1868 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1869 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1870 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1871
1872 /*
1873 * Limiting active cables and 1G Phys must be initialized as
1874 * SR modules
1875 */
1876 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1877 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1878 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1879 sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1880 sfp_type == ixgbe_sfp_type_1g_bx_core0)
1881 sfp_type = ixgbe_sfp_type_srlr_core0;
1882 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1883 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1884 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1885 sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1886 sfp_type == ixgbe_sfp_type_1g_bx_core1)
1887 sfp_type = ixgbe_sfp_type_srlr_core1;
1888
1889 /* Read offset to PHY init contents */
1890 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1891 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1892 "eeprom read at offset %d failed",
1893 IXGBE_PHY_INIT_OFFSET_NL);
1894 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1895 }
1896
1897 if ((!*list_offset) || (*list_offset == 0xFFFF))
1898 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1899
1900 /* Shift offset to first ID word */
1901 (*list_offset)++;
1902
1903 /*
1904 * Find the matching SFP ID in the EEPROM
1905 * and program the init sequence
1906 */
1907 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1908 goto err_phy;
1909
1910 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1911 if (sfp_id == sfp_type) {
1912 (*list_offset)++;
1913 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1914 goto err_phy;
1915 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1916 DEBUGOUT("SFP+ module not supported\n");
1917 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1918 } else {
1919 break;
1920 }
1921 } else {
1922 (*list_offset) += 2;
1923 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1924 goto err_phy;
1925 }
1926 }
1927
1928 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1929 DEBUGOUT("No matching SFP+ module found\n");
1930 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1931 }
1932
1933 return IXGBE_SUCCESS;
1934
1935 err_phy:
1936 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1937 "eeprom read at offset %d failed", *list_offset);
1938 return IXGBE_ERR_PHY;
1939 }
1940
1941 /**
1942 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1943 * @hw: pointer to hardware structure
1944 * @byte_offset: EEPROM byte offset to read
1945 * @eeprom_data: value read
1946 *
1947 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1948 **/
ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)1949 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1950 u8 *eeprom_data)
1951 {
1952 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1953
1954 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1955 IXGBE_I2C_EEPROM_DEV_ADDR,
1956 eeprom_data);
1957 }
1958
1959 /**
1960 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1961 * @hw: pointer to hardware structure
1962 * @byte_offset: byte offset at address 0xA2
1963 * @sff8472_data: value read
1964 *
1965 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1966 **/
ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)1967 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1968 u8 *sff8472_data)
1969 {
1970 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1971 IXGBE_I2C_EEPROM_DEV_ADDR2,
1972 sff8472_data);
1973 }
1974
1975 /**
1976 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1977 * @hw: pointer to hardware structure
1978 * @byte_offset: EEPROM byte offset to write
1979 * @eeprom_data: value to write
1980 *
1981 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1982 **/
ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 eeprom_data)1983 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1984 u8 eeprom_data)
1985 {
1986 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1987
1988 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1989 IXGBE_I2C_EEPROM_DEV_ADDR,
1990 eeprom_data);
1991 }
1992
1993 /**
1994 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1995 * @hw: pointer to hardware structure
1996 * @offset: eeprom offset to be read
1997 * @addr: I2C address to be read
1998 */
ixgbe_is_sfp_probe(struct ixgbe_hw * hw,u8 offset,u8 addr)1999 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2000 {
2001 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2002 offset == IXGBE_SFF_IDENTIFIER &&
2003 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2004 return true;
2005 return false;
2006 }
2007
2008 /**
2009 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2010 * @hw: pointer to hardware structure
2011 * @byte_offset: byte offset to read
2012 * @dev_addr: address to read from
2013 * @data: value read
2014 * @lock: true if to take and release semaphore
2015 *
2016 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2017 * a specified device address.
2018 **/
ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data,bool lock)2019 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2020 u8 dev_addr, u8 *data, bool lock)
2021 {
2022 s32 status;
2023 u32 max_retry = 10;
2024 u32 retry = 0;
2025 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2026 bool nack = 1;
2027 *data = 0;
2028
2029 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2030
2031 if (hw->mac.type >= ixgbe_mac_X550)
2032 max_retry = 3;
2033 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2034 max_retry = IXGBE_SFP_DETECT_RETRIES;
2035
2036 do {
2037 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2038 return IXGBE_ERR_SWFW_SYNC;
2039
2040 ixgbe_i2c_start(hw);
2041
2042 /* Device Address and write indication */
2043 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2044 if (status != IXGBE_SUCCESS)
2045 goto fail;
2046
2047 status = ixgbe_get_i2c_ack(hw);
2048 if (status != IXGBE_SUCCESS)
2049 goto fail;
2050
2051 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2052 if (status != IXGBE_SUCCESS)
2053 goto fail;
2054
2055 status = ixgbe_get_i2c_ack(hw);
2056 if (status != IXGBE_SUCCESS)
2057 goto fail;
2058
2059 ixgbe_i2c_start(hw);
2060
2061 /* Device Address and read indication */
2062 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2063 if (status != IXGBE_SUCCESS)
2064 goto fail;
2065
2066 status = ixgbe_get_i2c_ack(hw);
2067 if (status != IXGBE_SUCCESS)
2068 goto fail;
2069
2070 ixgbe_clock_in_i2c_byte(hw, data);
2071
2072 status = ixgbe_clock_out_i2c_bit(hw, nack);
2073 if (status != IXGBE_SUCCESS)
2074 goto fail;
2075
2076 ixgbe_i2c_stop(hw);
2077 if (lock)
2078 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2079 return IXGBE_SUCCESS;
2080
2081 fail:
2082 ixgbe_i2c_bus_clear(hw);
2083 if (lock) {
2084 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2085 msec_delay(100);
2086 }
2087 if (retry < max_retry)
2088 DEBUGOUT("I2C byte read error - Retrying.\n");
2089 else
2090 DEBUGOUT("I2C byte read error.\n");
2091 retry++;
2092 } while (retry <= max_retry);
2093
2094 return status;
2095 }
2096
2097 /**
2098 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2099 * @hw: pointer to hardware structure
2100 * @byte_offset: byte offset to read
2101 * @dev_addr: address to read from
2102 * @data: value read
2103 *
2104 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2105 * a specified device address.
2106 **/
ixgbe_read_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2107 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2108 u8 dev_addr, u8 *data)
2109 {
2110 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2111 data, true);
2112 }
2113
2114 /**
2115 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2116 * @hw: pointer to hardware structure
2117 * @byte_offset: byte offset to read
2118 * @dev_addr: address to read from
2119 * @data: value read
2120 *
2121 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2122 * a specified device address.
2123 **/
ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2124 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2125 u8 dev_addr, u8 *data)
2126 {
2127 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2128 data, false);
2129 }
2130
2131 /**
2132 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2133 * @hw: pointer to hardware structure
2134 * @byte_offset: byte offset to write
2135 * @dev_addr: address to write to
2136 * @data: value to write
2137 * @lock: true if to take and release semaphore
2138 *
2139 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2140 * a specified device address.
2141 **/
ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data,bool lock)2142 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2143 u8 dev_addr, u8 data, bool lock)
2144 {
2145 s32 status;
2146 u32 max_retry = 1;
2147 u32 retry = 0;
2148 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2149
2150 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2151
2152 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2153 IXGBE_SUCCESS)
2154 return IXGBE_ERR_SWFW_SYNC;
2155
2156 do {
2157 ixgbe_i2c_start(hw);
2158
2159 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2160 if (status != IXGBE_SUCCESS)
2161 goto fail;
2162
2163 status = ixgbe_get_i2c_ack(hw);
2164 if (status != IXGBE_SUCCESS)
2165 goto fail;
2166
2167 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2168 if (status != IXGBE_SUCCESS)
2169 goto fail;
2170
2171 status = ixgbe_get_i2c_ack(hw);
2172 if (status != IXGBE_SUCCESS)
2173 goto fail;
2174
2175 status = ixgbe_clock_out_i2c_byte(hw, data);
2176 if (status != IXGBE_SUCCESS)
2177 goto fail;
2178
2179 status = ixgbe_get_i2c_ack(hw);
2180 if (status != IXGBE_SUCCESS)
2181 goto fail;
2182
2183 ixgbe_i2c_stop(hw);
2184 if (lock)
2185 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2186 return IXGBE_SUCCESS;
2187
2188 fail:
2189 ixgbe_i2c_bus_clear(hw);
2190 if (retry < max_retry)
2191 DEBUGOUT("I2C byte write error - Retrying.\n");
2192 else
2193 DEBUGOUT("I2C byte write error.\n");
2194 retry++;
2195 } while (retry <= max_retry);
2196
2197 if (lock)
2198 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2199
2200 return status;
2201 }
2202
2203 /**
2204 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2205 * @hw: pointer to hardware structure
2206 * @byte_offset: byte offset to write
2207 * @dev_addr: address to write to
2208 * @data: value to write
2209 *
2210 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2211 * a specified device address.
2212 **/
ixgbe_write_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2213 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2214 u8 dev_addr, u8 data)
2215 {
2216 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2217 data, true);
2218 }
2219
2220 /**
2221 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2222 * @hw: pointer to hardware structure
2223 * @byte_offset: byte offset to write
2224 * @dev_addr: address to write to
2225 * @data: value to write
2226 *
2227 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2228 * a specified device address.
2229 **/
ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2230 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2231 u8 dev_addr, u8 data)
2232 {
2233 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2234 data, false);
2235 }
2236
2237 /**
2238 * ixgbe_i2c_start - Sets I2C start condition
2239 * @hw: pointer to hardware structure
2240 *
2241 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2242 * Set bit-bang mode on X550 hardware.
2243 **/
ixgbe_i2c_start(struct ixgbe_hw * hw)2244 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2245 {
2246 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2247
2248 DEBUGFUNC("ixgbe_i2c_start");
2249
2250 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2251
2252 /* Start condition must begin with data and clock high */
2253 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2254 ixgbe_raise_i2c_clk(hw, &i2cctl);
2255
2256 /* Setup time for start condition (4.7us) */
2257 usec_delay(IXGBE_I2C_T_SU_STA);
2258
2259 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2260
2261 /* Hold time for start condition (4us) */
2262 usec_delay(IXGBE_I2C_T_HD_STA);
2263
2264 ixgbe_lower_i2c_clk(hw, &i2cctl);
2265
2266 /* Minimum low period of clock is 4.7 us */
2267 usec_delay(IXGBE_I2C_T_LOW);
2268
2269 }
2270
2271 /**
2272 * ixgbe_i2c_stop - Sets I2C stop condition
2273 * @hw: pointer to hardware structure
2274 *
2275 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2276 * Disables bit-bang mode and negates data output enable on X550
2277 * hardware.
2278 **/
ixgbe_i2c_stop(struct ixgbe_hw * hw)2279 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2280 {
2281 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2282 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2283 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2284 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2285
2286 DEBUGFUNC("ixgbe_i2c_stop");
2287
2288 /* Stop condition must begin with data low and clock high */
2289 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2290 ixgbe_raise_i2c_clk(hw, &i2cctl);
2291
2292 /* Setup time for stop condition (4us) */
2293 usec_delay(IXGBE_I2C_T_SU_STO);
2294
2295 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2296
2297 /* bus free time between stop and start (4.7us)*/
2298 usec_delay(IXGBE_I2C_T_BUF);
2299
2300 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2301 i2cctl &= ~bb_en_bit;
2302 i2cctl |= data_oe_bit | clk_oe_bit;
2303 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2304 IXGBE_WRITE_FLUSH(hw);
2305 }
2306 }
2307
2308 /**
2309 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2310 * @hw: pointer to hardware structure
2311 * @data: data byte to clock in
2312 *
2313 * Clocks in one byte data via I2C data/clock
2314 **/
ixgbe_clock_in_i2c_byte(struct ixgbe_hw * hw,u8 * data)2315 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2316 {
2317 s32 i;
2318 bool bit = 0;
2319
2320 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2321
2322 *data = 0;
2323 for (i = 7; i >= 0; i--) {
2324 ixgbe_clock_in_i2c_bit(hw, &bit);
2325 *data |= bit << i;
2326 }
2327 }
2328
2329 /**
2330 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2331 * @hw: pointer to hardware structure
2332 * @data: data byte clocked out
2333 *
2334 * Clocks out one byte data via I2C data/clock
2335 **/
ixgbe_clock_out_i2c_byte(struct ixgbe_hw * hw,u8 data)2336 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2337 {
2338 s32 status = IXGBE_SUCCESS;
2339 s32 i;
2340 u32 i2cctl;
2341 bool bit;
2342
2343 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2344
2345 for (i = 7; i >= 0; i--) {
2346 bit = (data >> i) & 0x1;
2347 status = ixgbe_clock_out_i2c_bit(hw, bit);
2348
2349 if (status != IXGBE_SUCCESS)
2350 break;
2351 }
2352
2353 /* Release SDA line (set high) */
2354 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2355 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2356 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2357 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2358 IXGBE_WRITE_FLUSH(hw);
2359
2360 return status;
2361 }
2362
2363 /**
2364 * ixgbe_get_i2c_ack - Polls for I2C ACK
2365 * @hw: pointer to hardware structure
2366 *
2367 * Clocks in/out one bit via I2C data/clock
2368 **/
ixgbe_get_i2c_ack(struct ixgbe_hw * hw)2369 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2370 {
2371 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2372 s32 status = IXGBE_SUCCESS;
2373 u32 i = 0;
2374 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2375 u32 timeout = 10;
2376 bool ack = 1;
2377
2378 DEBUGFUNC("ixgbe_get_i2c_ack");
2379
2380 if (data_oe_bit) {
2381 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2382 i2cctl |= data_oe_bit;
2383 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2384 IXGBE_WRITE_FLUSH(hw);
2385 }
2386 ixgbe_raise_i2c_clk(hw, &i2cctl);
2387
2388 /* Minimum high period of clock is 4us */
2389 usec_delay(IXGBE_I2C_T_HIGH);
2390
2391 /* Poll for ACK. Note that ACK in I2C spec is
2392 * transition from 1 to 0 */
2393 for (i = 0; i < timeout; i++) {
2394 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2395 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2396
2397 usec_delay(1);
2398 if (!ack)
2399 break;
2400 }
2401
2402 if (ack) {
2403 DEBUGOUT("I2C ack was not received.\n");
2404 status = IXGBE_ERR_I2C;
2405 }
2406
2407 ixgbe_lower_i2c_clk(hw, &i2cctl);
2408
2409 /* Minimum low period of clock is 4.7 us */
2410 usec_delay(IXGBE_I2C_T_LOW);
2411
2412 return status;
2413 }
2414
2415 /**
2416 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2417 * @hw: pointer to hardware structure
2418 * @data: read data value
2419 *
2420 * Clocks in one bit via I2C data/clock
2421 **/
ixgbe_clock_in_i2c_bit(struct ixgbe_hw * hw,bool * data)2422 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2423 {
2424 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2425 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2426
2427 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2428
2429 if (data_oe_bit) {
2430 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2431 i2cctl |= data_oe_bit;
2432 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2433 IXGBE_WRITE_FLUSH(hw);
2434 }
2435 ixgbe_raise_i2c_clk(hw, &i2cctl);
2436
2437 /* Minimum high period of clock is 4us */
2438 usec_delay(IXGBE_I2C_T_HIGH);
2439
2440 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2441 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2442
2443 ixgbe_lower_i2c_clk(hw, &i2cctl);
2444
2445 /* Minimum low period of clock is 4.7 us */
2446 usec_delay(IXGBE_I2C_T_LOW);
2447 }
2448
2449 /**
2450 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2451 * @hw: pointer to hardware structure
2452 * @data: data value to write
2453 *
2454 * Clocks out one bit via I2C data/clock
2455 **/
ixgbe_clock_out_i2c_bit(struct ixgbe_hw * hw,bool data)2456 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2457 {
2458 s32 status;
2459 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2460
2461 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2462
2463 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2464 if (status == IXGBE_SUCCESS) {
2465 ixgbe_raise_i2c_clk(hw, &i2cctl);
2466
2467 /* Minimum high period of clock is 4us */
2468 usec_delay(IXGBE_I2C_T_HIGH);
2469
2470 ixgbe_lower_i2c_clk(hw, &i2cctl);
2471
2472 /* Minimum low period of clock is 4.7 us.
2473 * This also takes care of the data hold time.
2474 */
2475 usec_delay(IXGBE_I2C_T_LOW);
2476 } else {
2477 status = IXGBE_ERR_I2C;
2478 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2479 "I2C data was not set to %X\n", data);
2480 }
2481
2482 return status;
2483 }
2484
2485 /**
2486 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2487 * @hw: pointer to hardware structure
2488 * @i2cctl: Current value of I2CCTL register
2489 *
2490 * Raises the I2C clock line '0'->'1'
2491 * Negates the I2C clock output enable on X550 hardware.
2492 **/
ixgbe_raise_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2493 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2494 {
2495 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2496 u32 i = 0;
2497 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2498 u32 i2cctl_r = 0;
2499
2500 DEBUGFUNC("ixgbe_raise_i2c_clk");
2501
2502 if (clk_oe_bit) {
2503 *i2cctl |= clk_oe_bit;
2504 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2505 }
2506
2507 for (i = 0; i < timeout; i++) {
2508 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2509
2510 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2511 IXGBE_WRITE_FLUSH(hw);
2512 /* SCL rise time (1000ns) */
2513 usec_delay(IXGBE_I2C_T_RISE);
2514
2515 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2516 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2517 break;
2518 }
2519 }
2520
2521 /**
2522 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2523 * @hw: pointer to hardware structure
2524 * @i2cctl: Current value of I2CCTL register
2525 *
2526 * Lowers the I2C clock line '1'->'0'
2527 * Asserts the I2C clock output enable on X550 hardware.
2528 **/
ixgbe_lower_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2529 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2530 {
2531 DEBUGFUNC("ixgbe_lower_i2c_clk");
2532
2533 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2534 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2535
2536 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2537 IXGBE_WRITE_FLUSH(hw);
2538
2539 /* SCL fall time (300ns) */
2540 usec_delay(IXGBE_I2C_T_FALL);
2541 }
2542
2543 /**
2544 * ixgbe_set_i2c_data - Sets the I2C data bit
2545 * @hw: pointer to hardware structure
2546 * @i2cctl: Current value of I2CCTL register
2547 * @data: I2C data value (0 or 1) to set
2548 *
2549 * Sets the I2C data bit
2550 * Asserts the I2C data output enable on X550 hardware.
2551 **/
ixgbe_set_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl,bool data)2552 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2553 {
2554 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2555 s32 status = IXGBE_SUCCESS;
2556
2557 DEBUGFUNC("ixgbe_set_i2c_data");
2558
2559 if (data)
2560 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2561 else
2562 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2563 *i2cctl &= ~data_oe_bit;
2564
2565 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2566 IXGBE_WRITE_FLUSH(hw);
2567
2568 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2569 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2570
2571 if (!data) /* Can't verify data in this case */
2572 return IXGBE_SUCCESS;
2573 if (data_oe_bit) {
2574 *i2cctl |= data_oe_bit;
2575 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2576 IXGBE_WRITE_FLUSH(hw);
2577 }
2578
2579 /* Verify data was set correctly */
2580 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2581 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2582 status = IXGBE_ERR_I2C;
2583 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2584 "Error - I2C data was not set to %X.\n",
2585 data);
2586 }
2587
2588 return status;
2589 }
2590
2591 /**
2592 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2593 * @hw: pointer to hardware structure
2594 * @i2cctl: Current value of I2CCTL register
2595 *
2596 * Returns the I2C data bit value
2597 * Negates the I2C data output enable on X550 hardware.
2598 **/
ixgbe_get_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl)2599 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2600 {
2601 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2602 bool data;
2603
2604 DEBUGFUNC("ixgbe_get_i2c_data");
2605
2606 if (data_oe_bit) {
2607 *i2cctl |= data_oe_bit;
2608 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2609 IXGBE_WRITE_FLUSH(hw);
2610 usec_delay(IXGBE_I2C_T_FALL);
2611 }
2612
2613 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2614 data = 1;
2615 else
2616 data = 0;
2617
2618 return data;
2619 }
2620
2621 /**
2622 * ixgbe_i2c_bus_clear - Clears the I2C bus
2623 * @hw: pointer to hardware structure
2624 *
2625 * Clears the I2C bus by sending nine clock pulses.
2626 * Used when data line is stuck low.
2627 **/
ixgbe_i2c_bus_clear(struct ixgbe_hw * hw)2628 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2629 {
2630 u32 i2cctl;
2631 u32 i;
2632
2633 DEBUGFUNC("ixgbe_i2c_bus_clear");
2634
2635 ixgbe_i2c_start(hw);
2636 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2637
2638 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2639
2640 for (i = 0; i < 9; i++) {
2641 ixgbe_raise_i2c_clk(hw, &i2cctl);
2642
2643 /* Min high period of clock is 4us */
2644 usec_delay(IXGBE_I2C_T_HIGH);
2645
2646 ixgbe_lower_i2c_clk(hw, &i2cctl);
2647
2648 /* Min low period of clock is 4.7us*/
2649 usec_delay(IXGBE_I2C_T_LOW);
2650 }
2651
2652 ixgbe_i2c_start(hw);
2653
2654 /* Put the i2c bus back to default state */
2655 ixgbe_i2c_stop(hw);
2656 }
2657
2658 /**
2659 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2660 * @hw: pointer to hardware structure
2661 *
2662 * Checks if the LASI temp alarm status was triggered due to overtemp
2663 **/
ixgbe_tn_check_overtemp(struct ixgbe_hw * hw)2664 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2665 {
2666 s32 status = IXGBE_SUCCESS;
2667 u16 phy_data = 0;
2668
2669 DEBUGFUNC("ixgbe_tn_check_overtemp");
2670
2671 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2672 goto out;
2673
2674 /* Check that the LASI temp alarm status was triggered */
2675 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2676 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2677
2678 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2679 goto out;
2680
2681 status = IXGBE_ERR_OVERTEMP;
2682 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2683 out:
2684 return status;
2685 }
2686
2687 /**
2688 * ixgbe_set_copper_phy_power - Control power for copper phy
2689 * @hw: pointer to hardware structure
2690 * @on: true for on, false for off
2691 */
ixgbe_set_copper_phy_power(struct ixgbe_hw * hw,bool on)2692 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2693 {
2694 u32 status;
2695 u16 reg;
2696
2697 if (!on && ixgbe_mng_present(hw))
2698 return 0;
2699
2700 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2701 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2702 ®);
2703 if (status)
2704 return status;
2705
2706 if (on) {
2707 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2708 } else {
2709 if (ixgbe_check_reset_blocked(hw))
2710 return 0;
2711 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2712 }
2713
2714 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2715 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2716 reg);
2717 return status;
2718 }
2719