xref: /titanic_41/usr/src/uts/common/io/ixgbe/ixgbe_common.c (revision 536df542129698c6bedf6f515d0d547d89268c55)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2012, Intel Corporation
4   All rights reserved.
5 
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32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
34 
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #include "ixgbe_api.h"
38 
39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 					u16 count);
46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50 
51 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
52 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
53 					 u16 *san_mac_offset);
54 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 					     u16 words, u16 *data);
56 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 					      u16 words, u16 *data);
58 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
59 						 u16 offset);
60 
61 /**
62  *  ixgbe_init_ops_generic - Inits function ptrs
63  *  @hw: pointer to the hardware structure
64  *
65  *  Initialize the function pointers.
66  **/
ixgbe_init_ops_generic(struct ixgbe_hw * hw)67 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
68 {
69 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
70 	struct ixgbe_mac_info *mac = &hw->mac;
71 	u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
72 
73 	DEBUGFUNC("ixgbe_init_ops_generic");
74 
75 	/* EEPROM */
76 	eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
77 	/* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
78 	if (eec & IXGBE_EEC_PRES) {
79 		eeprom->ops.read = &ixgbe_read_eerd_generic;
80 		eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
81 	} else {
82 		eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
83 		eeprom->ops.read_buffer =
84 				 &ixgbe_read_eeprom_buffer_bit_bang_generic;
85 	}
86 	eeprom->ops.write = &ixgbe_write_eeprom_generic;
87 	eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
88 	eeprom->ops.validate_checksum =
89 				      &ixgbe_validate_eeprom_checksum_generic;
90 	eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
91 	eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
92 
93 	/* MAC */
94 	mac->ops.init_hw = &ixgbe_init_hw_generic;
95 	mac->ops.reset_hw = NULL;
96 	mac->ops.start_hw = &ixgbe_start_hw_generic;
97 	mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
98 	mac->ops.get_media_type = NULL;
99 	mac->ops.get_supported_physical_layer = NULL;
100 	mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
101 	mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
102 	mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
103 	mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
104 	mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
105 	mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
106 	mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
107 
108 	/* LEDs */
109 	mac->ops.led_on = &ixgbe_led_on_generic;
110 	mac->ops.led_off = &ixgbe_led_off_generic;
111 	mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
112 	mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
113 
114 	/* RAR, Multicast, VLAN */
115 	mac->ops.set_rar = &ixgbe_set_rar_generic;
116 	mac->ops.clear_rar = &ixgbe_clear_rar_generic;
117 	mac->ops.insert_mac_addr = NULL;
118 	mac->ops.set_vmdq = NULL;
119 	mac->ops.clear_vmdq = NULL;
120 	mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
121 	mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
122 	mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
123 	mac->ops.enable_mc = &ixgbe_enable_mc_generic;
124 	mac->ops.disable_mc = &ixgbe_disable_mc_generic;
125 	mac->ops.clear_vfta = NULL;
126 	mac->ops.set_vfta = NULL;
127 	mac->ops.set_vlvf = NULL;
128 	mac->ops.init_uta_tables = NULL;
129 
130 	/* Flow Control */
131 	mac->ops.fc_enable = &ixgbe_fc_enable_generic;
132 
133 	/* Link */
134 	mac->ops.get_link_capabilities = NULL;
135 	mac->ops.setup_link = NULL;
136 	mac->ops.check_link = NULL;
137 
138 	return IXGBE_SUCCESS;
139 }
140 
141 /**
142  *  ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
143  *  control
144  *  @hw: pointer to hardware structure
145  *
146  *  There are several phys that do not support autoneg flow control. This
147  *  function check the device id to see if the associated phy supports
148  *  autoneg flow control.
149  **/
ixgbe_device_supports_autoneg_fc(struct ixgbe_hw * hw)150 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
151 {
152 
153 	DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
154 
155 	switch (hw->device_id) {
156 	case IXGBE_DEV_ID_X540T:
157 	case IXGBE_DEV_ID_X540T1:
158 		return IXGBE_SUCCESS;
159 	case IXGBE_DEV_ID_82599_T3_LOM:
160 		return IXGBE_SUCCESS;
161 	default:
162 		return IXGBE_ERR_FC_NOT_SUPPORTED;
163 	}
164 }
165 
166 /**
167  *  ixgbe_setup_fc - Set up flow control
168  *  @hw: pointer to hardware structure
169  *
170  *  Called at init time to set up flow control.
171  **/
ixgbe_setup_fc(struct ixgbe_hw * hw)172 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
173 {
174 	s32 ret_val = IXGBE_SUCCESS;
175 	u32 reg = 0, reg_bp = 0;
176 	u16 reg_cu = 0;
177 
178 	DEBUGFUNC("ixgbe_setup_fc");
179 
180 	/*
181 	 * Validate the requested mode.  Strict IEEE mode does not allow
182 	 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
183 	 */
184 	if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
185 		DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
186 		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
187 		goto out;
188 	}
189 
190 	/*
191 	 * 10gig parts do not have a word in the EEPROM to determine the
192 	 * default flow control setting, so we explicitly set it to full.
193 	 */
194 	if (hw->fc.requested_mode == ixgbe_fc_default)
195 		hw->fc.requested_mode = ixgbe_fc_full;
196 
197 	/*
198 	 * Set up the 1G and 10G flow control advertisement registers so the
199 	 * HW will be able to do fc autoneg once the cable is plugged in.  If
200 	 * we link at 10G, the 1G advertisement is harmless and vice versa.
201 	 */
202 	switch (hw->phy.media_type) {
203 	case ixgbe_media_type_fiber:
204 	case ixgbe_media_type_backplane:
205 		reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
206 		reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
207 		break;
208 	case ixgbe_media_type_copper:
209 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
210 				     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg_cu);
211 		break;
212 	default:
213 		break;
214 	}
215 
216 	/*
217 	 * The possible values of fc.requested_mode are:
218 	 * 0: Flow control is completely disabled
219 	 * 1: Rx flow control is enabled (we can receive pause frames,
220 	 *    but not send pause frames).
221 	 * 2: Tx flow control is enabled (we can send pause frames but
222 	 *    we do not support receiving pause frames).
223 	 * 3: Both Rx and Tx flow control (symmetric) are enabled.
224 	 * other: Invalid.
225 	 */
226 	switch (hw->fc.requested_mode) {
227 	case ixgbe_fc_none:
228 		/* Flow control completely disabled by software override. */
229 		reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
230 		if (hw->phy.media_type == ixgbe_media_type_backplane)
231 			reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
232 				    IXGBE_AUTOC_ASM_PAUSE);
233 		else if (hw->phy.media_type == ixgbe_media_type_copper)
234 			reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
235 		break;
236 	case ixgbe_fc_tx_pause:
237 		/*
238 		 * Tx Flow control is enabled, and Rx Flow control is
239 		 * disabled by software override.
240 		 */
241 		reg |= IXGBE_PCS1GANA_ASM_PAUSE;
242 		reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
243 		if (hw->phy.media_type == ixgbe_media_type_backplane) {
244 			reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
245 			reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
246 		} else if (hw->phy.media_type == ixgbe_media_type_copper) {
247 			reg_cu |= IXGBE_TAF_ASM_PAUSE;
248 			reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
249 		}
250 		break;
251 	case ixgbe_fc_rx_pause:
252 		/*
253 		 * Rx Flow control is enabled and Tx Flow control is
254 		 * disabled by software override. Since there really
255 		 * isn't a way to advertise that we are capable of RX
256 		 * Pause ONLY, we will advertise that we support both
257 		 * symmetric and asymmetric Rx PAUSE, as such we fall
258 		 * through to the fc_full statement.  Later, we will
259 		 * disable the adapter's ability to send PAUSE frames.
260 		 */
261 	case ixgbe_fc_full:
262 		/* Flow control (both Rx and Tx) is enabled by SW override. */
263 		reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
264 		if (hw->phy.media_type == ixgbe_media_type_backplane)
265 			reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
266 				  IXGBE_AUTOC_ASM_PAUSE;
267 		else if (hw->phy.media_type == ixgbe_media_type_copper)
268 			reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
269 		break;
270 	default:
271 		DEBUGOUT("Flow control param set incorrectly\n");
272 		ret_val = IXGBE_ERR_CONFIG;
273 		goto out;
274 	}
275 
276 	if (hw->mac.type != ixgbe_mac_X540) {
277 		/*
278 		 * Enable auto-negotiation between the MAC & PHY;
279 		 * the MAC will advertise clause 37 flow control.
280 		 */
281 		IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
282 		reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
283 
284 		/* Disable AN timeout */
285 		if (hw->fc.strict_ieee)
286 			reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
287 
288 		IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
289 		DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
290 	}
291 
292 	/*
293 	 * AUTOC restart handles negotiation of 1G and 10G on backplane
294 	 * and copper. There is no need to set the PCS1GCTL register.
295 	 *
296 	 */
297 	if (hw->phy.media_type == ixgbe_media_type_backplane) {
298 		reg_bp |= IXGBE_AUTOC_AN_RESTART;
299 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
300 	} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
301 		    (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
302 		hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
303 				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
304 	}
305 
306 	DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
307 out:
308 	return ret_val;
309 }
310 
311 /**
312  *  ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
313  *  @hw: pointer to hardware structure
314  *
315  *  Starts the hardware by filling the bus info structure and media type, clears
316  *  all on chip counters, initializes receive address registers, multicast
317  *  table, VLAN filter table, calls routine to set up link and flow control
318  *  settings, and leaves transmit and receive units disabled and uninitialized
319  **/
ixgbe_start_hw_generic(struct ixgbe_hw * hw)320 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
321 {
322 	s32 ret_val;
323 	u32 ctrl_ext;
324 
325 	DEBUGFUNC("ixgbe_start_hw_generic");
326 
327 	/* Set the media type */
328 	hw->phy.media_type = hw->mac.ops.get_media_type(hw);
329 
330 	/* PHY ops initialization must be done in reset_hw() */
331 
332 	/* Clear the VLAN filter table */
333 	hw->mac.ops.clear_vfta(hw);
334 
335 	/* Clear statistics registers */
336 	hw->mac.ops.clear_hw_cntrs(hw);
337 
338 	/* Set No Snoop Disable */
339 	ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
340 	ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
341 	IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
342 	IXGBE_WRITE_FLUSH(hw);
343 
344 	/* Setup flow control */
345 	ret_val = ixgbe_setup_fc(hw);
346 	if (ret_val != IXGBE_SUCCESS)
347 		goto out;
348 
349 	/* Clear adapter stopped flag */
350 	hw->adapter_stopped = FALSE;
351 
352 out:
353 	return ret_val;
354 }
355 
356 /**
357  *  ixgbe_start_hw_gen2 - Init sequence for common device family
358  *  @hw: pointer to hw structure
359  *
360  * Performs the init sequence common to the second generation
361  * of 10 GbE devices.
362  * Devices in the second generation:
363  *     82599
364  *     X540
365  **/
ixgbe_start_hw_gen2(struct ixgbe_hw * hw)366 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
367 {
368 	u32 i;
369 	u32 regval;
370 
371 	/* Clear the rate limiters */
372 	for (i = 0; i < hw->mac.max_tx_queues; i++) {
373 		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
374 		IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
375 	}
376 	IXGBE_WRITE_FLUSH(hw);
377 
378 	/* Disable relaxed ordering */
379 	for (i = 0; i < hw->mac.max_tx_queues; i++) {
380 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
381 		regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
382 		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
383 	}
384 
385 	for (i = 0; i < hw->mac.max_rx_queues; i++) {
386 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
387 		regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
388 			    IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
389 		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
390 	}
391 
392 	return IXGBE_SUCCESS;
393 }
394 
395 /**
396  *  ixgbe_init_hw_generic - Generic hardware initialization
397  *  @hw: pointer to hardware structure
398  *
399  *  Initialize the hardware by resetting the hardware, filling the bus info
400  *  structure and media type, clears all on chip counters, initializes receive
401  *  address registers, multicast table, VLAN filter table, calls routine to set
402  *  up link and flow control settings, and leaves transmit and receive units
403  *  disabled and uninitialized
404  **/
ixgbe_init_hw_generic(struct ixgbe_hw * hw)405 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
406 {
407 	s32 status;
408 
409 	DEBUGFUNC("ixgbe_init_hw_generic");
410 
411 	/* Reset the hardware */
412 	status = hw->mac.ops.reset_hw(hw);
413 
414 	if (status == IXGBE_SUCCESS) {
415 		/* Start the HW */
416 		status = hw->mac.ops.start_hw(hw);
417 	}
418 
419 	return status;
420 }
421 
422 /**
423  *  ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
424  *  @hw: pointer to hardware structure
425  *
426  *  Clears all hardware statistics counters by reading them from the hardware
427  *  Statistics counters are clear on read.
428  **/
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw * hw)429 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
430 {
431 	u16 i = 0;
432 
433 	DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
434 
435 	(void) IXGBE_READ_REG(hw, IXGBE_CRCERRS);
436 	(void) IXGBE_READ_REG(hw, IXGBE_ILLERRC);
437 	(void) IXGBE_READ_REG(hw, IXGBE_ERRBC);
438 	(void) IXGBE_READ_REG(hw, IXGBE_MSPDC);
439 	for (i = 0; i < 8; i++)
440 		(void) IXGBE_READ_REG(hw, IXGBE_MPC(i));
441 
442 	(void) IXGBE_READ_REG(hw, IXGBE_MLFC);
443 	(void) IXGBE_READ_REG(hw, IXGBE_MRFC);
444 	(void) IXGBE_READ_REG(hw, IXGBE_RLEC);
445 	(void) IXGBE_READ_REG(hw, IXGBE_LXONTXC);
446 	(void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
447 	if (hw->mac.type >= ixgbe_mac_82599EB) {
448 		(void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
449 		(void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
450 	} else {
451 		(void) IXGBE_READ_REG(hw, IXGBE_LXONRXC);
452 		(void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
453 	}
454 
455 	for (i = 0; i < 8; i++) {
456 		(void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
457 		(void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
458 		if (hw->mac.type >= ixgbe_mac_82599EB) {
459 			(void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
460 			(void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
461 		} else {
462 			(void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
463 			(void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
464 		}
465 	}
466 	if (hw->mac.type >= ixgbe_mac_82599EB)
467 		for (i = 0; i < 8; i++)
468 			(void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
469 	(void) IXGBE_READ_REG(hw, IXGBE_PRC64);
470 	(void) IXGBE_READ_REG(hw, IXGBE_PRC127);
471 	(void) IXGBE_READ_REG(hw, IXGBE_PRC255);
472 	(void) IXGBE_READ_REG(hw, IXGBE_PRC511);
473 	(void) IXGBE_READ_REG(hw, IXGBE_PRC1023);
474 	(void) IXGBE_READ_REG(hw, IXGBE_PRC1522);
475 	(void) IXGBE_READ_REG(hw, IXGBE_GPRC);
476 	(void) IXGBE_READ_REG(hw, IXGBE_BPRC);
477 	(void) IXGBE_READ_REG(hw, IXGBE_MPRC);
478 	(void) IXGBE_READ_REG(hw, IXGBE_GPTC);
479 	(void) IXGBE_READ_REG(hw, IXGBE_GORCL);
480 	(void) IXGBE_READ_REG(hw, IXGBE_GORCH);
481 	(void) IXGBE_READ_REG(hw, IXGBE_GOTCL);
482 	(void) IXGBE_READ_REG(hw, IXGBE_GOTCH);
483 	if (hw->mac.type == ixgbe_mac_82598EB)
484 		for (i = 0; i < 8; i++)
485 			(void) IXGBE_READ_REG(hw, IXGBE_RNBC(i));
486 	(void) IXGBE_READ_REG(hw, IXGBE_RUC);
487 	(void) IXGBE_READ_REG(hw, IXGBE_RFC);
488 	(void) IXGBE_READ_REG(hw, IXGBE_ROC);
489 	(void) IXGBE_READ_REG(hw, IXGBE_RJC);
490 	(void) IXGBE_READ_REG(hw, IXGBE_MNGPRC);
491 	(void) IXGBE_READ_REG(hw, IXGBE_MNGPDC);
492 	(void) IXGBE_READ_REG(hw, IXGBE_MNGPTC);
493 	(void) IXGBE_READ_REG(hw, IXGBE_TORL);
494 	(void) IXGBE_READ_REG(hw, IXGBE_TORH);
495 	(void) IXGBE_READ_REG(hw, IXGBE_TPR);
496 	(void) IXGBE_READ_REG(hw, IXGBE_TPT);
497 	(void) IXGBE_READ_REG(hw, IXGBE_PTC64);
498 	(void) IXGBE_READ_REG(hw, IXGBE_PTC127);
499 	(void) IXGBE_READ_REG(hw, IXGBE_PTC255);
500 	(void) IXGBE_READ_REG(hw, IXGBE_PTC511);
501 	(void) IXGBE_READ_REG(hw, IXGBE_PTC1023);
502 	(void) IXGBE_READ_REG(hw, IXGBE_PTC1522);
503 	(void) IXGBE_READ_REG(hw, IXGBE_MPTC);
504 	(void) IXGBE_READ_REG(hw, IXGBE_BPTC);
505 	for (i = 0; i < 16; i++) {
506 		(void) IXGBE_READ_REG(hw, IXGBE_QPRC(i));
507 		(void) IXGBE_READ_REG(hw, IXGBE_QPTC(i));
508 		if (hw->mac.type >= ixgbe_mac_82599EB) {
509 			(void) IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
510 			(void) IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
511 			(void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
512 			(void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
513 			(void) IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
514 		} else {
515 			(void) IXGBE_READ_REG(hw, IXGBE_QBRC(i));
516 			(void) IXGBE_READ_REG(hw, IXGBE_QBTC(i));
517 		}
518 	}
519 
520 	if (hw->mac.type == ixgbe_mac_X540) {
521 		if (hw->phy.id == 0)
522 			(void) ixgbe_identify_phy(hw);
523 		hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
524 				     IXGBE_MDIO_PCS_DEV_TYPE, &i);
525 		hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
526 				     IXGBE_MDIO_PCS_DEV_TYPE, &i);
527 		hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
528 				     IXGBE_MDIO_PCS_DEV_TYPE, &i);
529 		hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
530 				     IXGBE_MDIO_PCS_DEV_TYPE, &i);
531 	}
532 
533 	return IXGBE_SUCCESS;
534 }
535 
536 /**
537  *  ixgbe_read_pba_string_generic - Reads part number string from EEPROM
538  *  @hw: pointer to hardware structure
539  *  @pba_num: stores the part number string from the EEPROM
540  *  @pba_num_size: part number string buffer length
541  *
542  *  Reads the part number string from the EEPROM.
543  **/
ixgbe_read_pba_string_generic(struct ixgbe_hw * hw,u8 * pba_num,u32 pba_num_size)544 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
545 				  u32 pba_num_size)
546 {
547 	s32 ret_val;
548 	u16 data;
549 	u16 pba_ptr;
550 	u16 offset;
551 	u16 length;
552 
553 	DEBUGFUNC("ixgbe_read_pba_string_generic");
554 
555 	if (pba_num == NULL) {
556 		DEBUGOUT("PBA string buffer was null\n");
557 		return IXGBE_ERR_INVALID_ARGUMENT;
558 	}
559 
560 	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
561 	if (ret_val) {
562 		DEBUGOUT("NVM Read Error\n");
563 		return ret_val;
564 	}
565 
566 	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
567 	if (ret_val) {
568 		DEBUGOUT("NVM Read Error\n");
569 		return ret_val;
570 	}
571 
572 	/*
573 	 * if data is not ptr guard the PBA must be in legacy format which
574 	 * means pba_ptr is actually our second data word for the PBA number
575 	 * and we can decode it into an ascii string
576 	 */
577 	if (data != IXGBE_PBANUM_PTR_GUARD) {
578 		DEBUGOUT("NVM PBA number is not stored as string\n");
579 
580 		/* we will need 11 characters to store the PBA */
581 		if (pba_num_size < 11) {
582 			DEBUGOUT("PBA string buffer too small\n");
583 			return IXGBE_ERR_NO_SPACE;
584 		}
585 
586 		/* extract hex string from data and pba_ptr */
587 		pba_num[0] = (data >> 12) & 0xF;
588 		pba_num[1] = (data >> 8) & 0xF;
589 		pba_num[2] = (data >> 4) & 0xF;
590 		pba_num[3] = data & 0xF;
591 		pba_num[4] = (pba_ptr >> 12) & 0xF;
592 		pba_num[5] = (pba_ptr >> 8) & 0xF;
593 		pba_num[6] = '-';
594 		pba_num[7] = 0;
595 		pba_num[8] = (pba_ptr >> 4) & 0xF;
596 		pba_num[9] = pba_ptr & 0xF;
597 
598 		/* put a null character on the end of our string */
599 		pba_num[10] = '\0';
600 
601 		/* switch all the data but the '-' to hex char */
602 		for (offset = 0; offset < 10; offset++) {
603 			if (pba_num[offset] < 0xA)
604 				pba_num[offset] += '0';
605 			else if (pba_num[offset] < 0x10)
606 				pba_num[offset] += 'A' - 0xA;
607 		}
608 
609 		return IXGBE_SUCCESS;
610 	}
611 
612 	ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
613 	if (ret_val) {
614 		DEBUGOUT("NVM Read Error\n");
615 		return ret_val;
616 	}
617 
618 	if (length == 0xFFFF || length == 0) {
619 		DEBUGOUT("NVM PBA number section invalid length\n");
620 		return IXGBE_ERR_PBA_SECTION;
621 	}
622 
623 	/* check if pba_num buffer is big enough */
624 	if (pba_num_size  < (((u32)length * 2) - 1)) {
625 		DEBUGOUT("PBA string buffer too small\n");
626 		return IXGBE_ERR_NO_SPACE;
627 	}
628 
629 	/* trim pba length from start of string */
630 	pba_ptr++;
631 	length--;
632 
633 	for (offset = 0; offset < length; offset++) {
634 		ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
635 		if (ret_val) {
636 			DEBUGOUT("NVM Read Error\n");
637 			return ret_val;
638 		}
639 		pba_num[offset * 2] = (u8)(data >> 8);
640 		pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
641 	}
642 	pba_num[offset * 2] = '\0';
643 
644 	return IXGBE_SUCCESS;
645 }
646 
647 /**
648  *  ixgbe_read_pba_num_generic - Reads part number from EEPROM
649  *  @hw: pointer to hardware structure
650  *  @pba_num: stores the part number from the EEPROM
651  *
652  *  Reads the part number from the EEPROM.
653  **/
ixgbe_read_pba_num_generic(struct ixgbe_hw * hw,u32 * pba_num)654 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
655 {
656 	s32 ret_val;
657 	u16 data;
658 
659 	DEBUGFUNC("ixgbe_read_pba_num_generic");
660 
661 	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
662 	if (ret_val) {
663 		DEBUGOUT("NVM Read Error\n");
664 		return ret_val;
665 	} else if (data == IXGBE_PBANUM_PTR_GUARD) {
666 		DEBUGOUT("NVM Not supported\n");
667 		return IXGBE_NOT_IMPLEMENTED;
668 	}
669 	*pba_num = (u32)(data << 16);
670 
671 	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
672 	if (ret_val) {
673 		DEBUGOUT("NVM Read Error\n");
674 		return ret_val;
675 	}
676 	*pba_num |= data;
677 
678 	return IXGBE_SUCCESS;
679 }
680 
681 /**
682  *  ixgbe_get_mac_addr_generic - Generic get MAC address
683  *  @hw: pointer to hardware structure
684  *  @mac_addr: Adapter MAC address
685  *
686  *  Reads the adapter's MAC address from first Receive Address Register (RAR0)
687  *  A reset of the adapter must be performed prior to calling this function
688  *  in order for the MAC address to have been loaded from the EEPROM into RAR0
689  **/
ixgbe_get_mac_addr_generic(struct ixgbe_hw * hw,u8 * mac_addr)690 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
691 {
692 	u32 rar_high;
693 	u32 rar_low;
694 	u16 i;
695 
696 	DEBUGFUNC("ixgbe_get_mac_addr_generic");
697 
698 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
699 	rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
700 
701 	for (i = 0; i < 4; i++)
702 		mac_addr[i] = (u8)(rar_low >> (i*8));
703 
704 	for (i = 0; i < 2; i++)
705 		mac_addr[i+4] = (u8)(rar_high >> (i*8));
706 
707 	return IXGBE_SUCCESS;
708 }
709 
710 /**
711  *  ixgbe_get_bus_info_generic - Generic set PCI bus info
712  *  @hw: pointer to hardware structure
713  *
714  *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
715  **/
ixgbe_get_bus_info_generic(struct ixgbe_hw * hw)716 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
717 {
718 	struct ixgbe_mac_info *mac = &hw->mac;
719 	u16 link_status;
720 
721 	DEBUGFUNC("ixgbe_get_bus_info_generic");
722 
723 	hw->bus.type = ixgbe_bus_type_pci_express;
724 
725 	/* Get the negotiated link width and speed from PCI config space */
726 	link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
727 
728 	switch (link_status & IXGBE_PCI_LINK_WIDTH) {
729 	case IXGBE_PCI_LINK_WIDTH_1:
730 		hw->bus.width = ixgbe_bus_width_pcie_x1;
731 		break;
732 	case IXGBE_PCI_LINK_WIDTH_2:
733 		hw->bus.width = ixgbe_bus_width_pcie_x2;
734 		break;
735 	case IXGBE_PCI_LINK_WIDTH_4:
736 		hw->bus.width = ixgbe_bus_width_pcie_x4;
737 		break;
738 	case IXGBE_PCI_LINK_WIDTH_8:
739 		hw->bus.width = ixgbe_bus_width_pcie_x8;
740 		break;
741 	default:
742 		hw->bus.width = ixgbe_bus_width_unknown;
743 		break;
744 	}
745 
746 	switch (link_status & IXGBE_PCI_LINK_SPEED) {
747 	case IXGBE_PCI_LINK_SPEED_2500:
748 		hw->bus.speed = ixgbe_bus_speed_2500;
749 		break;
750 	case IXGBE_PCI_LINK_SPEED_5000:
751 		hw->bus.speed = ixgbe_bus_speed_5000;
752 		break;
753 	case IXGBE_PCI_LINK_SPEED_8000:
754 		hw->bus.speed = ixgbe_bus_speed_8000;
755 		break;
756 	default:
757 		hw->bus.speed = ixgbe_bus_speed_unknown;
758 		break;
759 	}
760 
761 	mac->ops.set_lan_id(hw);
762 
763 	return IXGBE_SUCCESS;
764 }
765 
766 /**
767  *  ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
768  *  @hw: pointer to the HW structure
769  *
770  *  Determines the LAN function id by reading memory-mapped registers
771  *  and swaps the port value if requested.
772  **/
ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw * hw)773 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
774 {
775 	struct ixgbe_bus_info *bus = &hw->bus;
776 	u32 reg;
777 
778 	DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
779 
780 	reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
781 	bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
782 	bus->lan_id = bus->func;
783 
784 	/* check for a port swap */
785 	reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
786 	if (reg & IXGBE_FACTPS_LFS)
787 		bus->func ^= 0x1;
788 }
789 
790 /**
791  *  ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
792  *  @hw: pointer to hardware structure
793  *
794  *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
795  *  disables transmit and receive units. The adapter_stopped flag is used by
796  *  the shared code and drivers to determine if the adapter is in a stopped
797  *  state and should not touch the hardware.
798  **/
ixgbe_stop_adapter_generic(struct ixgbe_hw * hw)799 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
800 {
801 	u32 reg_val;
802 	u16 i;
803 
804 	DEBUGFUNC("ixgbe_stop_adapter_generic");
805 
806 	/*
807 	 * Set the adapter_stopped flag so other driver functions stop touching
808 	 * the hardware
809 	 */
810 	hw->adapter_stopped = TRUE;
811 
812 	/* Disable the receive unit */
813 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
814 
815 	/* Clear interrupt mask to stop interrupts from being generated */
816 	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
817 
818 	/* Clear any pending interrupts, flush previous writes */
819 	(void) IXGBE_READ_REG(hw, IXGBE_EICR);
820 
821 	/* Disable the transmit unit.  Each queue must be disabled. */
822 	for (i = 0; i < hw->mac.max_tx_queues; i++)
823 		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
824 
825 	/* Disable the receive unit by stopping each queue */
826 	for (i = 0; i < hw->mac.max_rx_queues; i++) {
827 		reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
828 		reg_val &= ~IXGBE_RXDCTL_ENABLE;
829 		reg_val |= IXGBE_RXDCTL_SWFLSH;
830 		IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
831 	}
832 
833 	/* flush all queues disables */
834 	IXGBE_WRITE_FLUSH(hw);
835 	msec_delay(2);
836 
837 	/*
838 	 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
839 	 * access and verify no pending requests
840 	 */
841 	return ixgbe_disable_pcie_master(hw);
842 }
843 
844 /**
845  *  ixgbe_led_on_generic - Turns on the software controllable LEDs.
846  *  @hw: pointer to hardware structure
847  *  @index: led number to turn on
848  **/
ixgbe_led_on_generic(struct ixgbe_hw * hw,u32 index)849 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
850 {
851 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
852 
853 	DEBUGFUNC("ixgbe_led_on_generic");
854 
855 	/* To turn on the LED, set mode to ON. */
856 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
857 	led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
858 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
859 	IXGBE_WRITE_FLUSH(hw);
860 
861 	return IXGBE_SUCCESS;
862 }
863 
864 /**
865  *  ixgbe_led_off_generic - Turns off the software controllable LEDs.
866  *  @hw: pointer to hardware structure
867  *  @index: led number to turn off
868  **/
ixgbe_led_off_generic(struct ixgbe_hw * hw,u32 index)869 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
870 {
871 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
872 
873 	DEBUGFUNC("ixgbe_led_off_generic");
874 
875 	/* To turn off the LED, set mode to OFF. */
876 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
877 	led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
878 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
879 	IXGBE_WRITE_FLUSH(hw);
880 
881 	return IXGBE_SUCCESS;
882 }
883 
884 /**
885  *  ixgbe_init_eeprom_params_generic - Initialize EEPROM params
886  *  @hw: pointer to hardware structure
887  *
888  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
889  *  ixgbe_hw struct in order to set up EEPROM access.
890  **/
ixgbe_init_eeprom_params_generic(struct ixgbe_hw * hw)891 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
892 {
893 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
894 	u32 eec;
895 	u16 eeprom_size;
896 
897 	DEBUGFUNC("ixgbe_init_eeprom_params_generic");
898 
899 	if (eeprom->type == ixgbe_eeprom_uninitialized) {
900 		eeprom->type = ixgbe_eeprom_none;
901 		/* Set default semaphore delay to 10ms which is a well
902 		 * tested value */
903 		eeprom->semaphore_delay = 10;
904 		/* Clear EEPROM page size, it will be initialized as needed */
905 		eeprom->word_page_size = 0;
906 
907 		/*
908 		 * Check for EEPROM present first.
909 		 * If not present leave as none
910 		 */
911 		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
912 		if (eec & IXGBE_EEC_PRES) {
913 			eeprom->type = ixgbe_eeprom_spi;
914 
915 			/*
916 			 * SPI EEPROM is assumed here.  This code would need to
917 			 * change if a future EEPROM is not SPI.
918 			 */
919 			eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
920 					    IXGBE_EEC_SIZE_SHIFT);
921 			eeprom->word_size = 1 << (eeprom_size +
922 					     IXGBE_EEPROM_WORD_SIZE_SHIFT);
923 		}
924 
925 		if (eec & IXGBE_EEC_ADDR_SIZE)
926 			eeprom->address_bits = 16;
927 		else
928 			eeprom->address_bits = 8;
929 		DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
930 			  "%d\n", eeprom->type, eeprom->word_size,
931 			  eeprom->address_bits);
932 	}
933 
934 	return IXGBE_SUCCESS;
935 }
936 
937 /**
938  *  ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
939  *  @hw: pointer to hardware structure
940  *  @offset: offset within the EEPROM to write
941  *  @words: number of word(s)
942  *  @data: 16 bit word(s) to write to EEPROM
943  *
944  *  Reads 16 bit word(s) from EEPROM through bit-bang method
945  **/
ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)946 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
947 					       u16 words, u16 *data)
948 {
949 	s32 status = IXGBE_SUCCESS;
950 	u16 i, count;
951 
952 	DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
953 
954 	hw->eeprom.ops.init_params(hw);
955 
956 	if (words == 0) {
957 		status = IXGBE_ERR_INVALID_ARGUMENT;
958 		goto out;
959 	}
960 
961 	if (offset + words > hw->eeprom.word_size) {
962 		status = IXGBE_ERR_EEPROM;
963 		goto out;
964 	}
965 
966 	/*
967 	 * The EEPROM page size cannot be queried from the chip. We do lazy
968 	 * initialization. It is worth to do that when we write large buffer.
969 	 */
970 	if ((hw->eeprom.word_page_size == 0) &&
971 	    (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
972 		status = ixgbe_detect_eeprom_page_size_generic(hw, offset);
973 	if (status != IXGBE_SUCCESS)
974 		goto out;
975 
976 	/*
977 	 * We cannot hold synchronization semaphores for too long
978 	 * to avoid other entity starvation. However it is more efficient
979 	 * to read in bursts than synchronizing access for each word.
980 	 */
981 	for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
982 		count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
983 			IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
984 		status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
985 							    count, &data[i]);
986 
987 		if (status != IXGBE_SUCCESS)
988 			break;
989 	}
990 
991 out:
992 	return status;
993 }
994 
995 /**
996  *  ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
997  *  @hw: pointer to hardware structure
998  *  @offset: offset within the EEPROM to be written to
999  *  @words: number of word(s)
1000  *  @data: 16 bit word(s) to be written to the EEPROM
1001  *
1002  *  If ixgbe_eeprom_update_checksum is not called after this function, the
1003  *  EEPROM will most likely contain an invalid checksum.
1004  **/
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1005 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1006 					      u16 words, u16 *data)
1007 {
1008 	s32 status;
1009 	u16 word;
1010 	u16 page_size;
1011 	u16 i;
1012 	u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1013 
1014 	DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1015 
1016 	/* Prepare the EEPROM for writing  */
1017 	status = ixgbe_acquire_eeprom(hw);
1018 
1019 	if (status == IXGBE_SUCCESS) {
1020 		if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1021 			ixgbe_release_eeprom(hw);
1022 			status = IXGBE_ERR_EEPROM;
1023 		}
1024 	}
1025 
1026 	if (status == IXGBE_SUCCESS) {
1027 		for (i = 0; i < words; i++) {
1028 			ixgbe_standby_eeprom(hw);
1029 
1030 			/*  Send the WRITE ENABLE command (8 bit opcode )  */
1031 			ixgbe_shift_out_eeprom_bits(hw,
1032 						   IXGBE_EEPROM_WREN_OPCODE_SPI,
1033 						   IXGBE_EEPROM_OPCODE_BITS);
1034 
1035 			ixgbe_standby_eeprom(hw);
1036 
1037 			/*
1038 			 * Some SPI eeproms use the 8th address bit embedded
1039 			 * in the opcode
1040 			 */
1041 			if ((hw->eeprom.address_bits == 8) &&
1042 			    ((offset + i) >= 128))
1043 				write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1044 
1045 			/* Send the Write command (8-bit opcode + addr) */
1046 			ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1047 						    IXGBE_EEPROM_OPCODE_BITS);
1048 			ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1049 						    hw->eeprom.address_bits);
1050 
1051 			page_size = hw->eeprom.word_page_size;
1052 
1053 			/* Send the data in burst via SPI*/
1054 			do {
1055 				word = data[i];
1056 				word = (word >> 8) | (word << 8);
1057 				ixgbe_shift_out_eeprom_bits(hw, word, 16);
1058 
1059 				if (page_size == 0)
1060 					break;
1061 
1062 				/* do not wrap around page */
1063 				if (((offset + i) & (page_size - 1)) ==
1064 				    (page_size - 1))
1065 					break;
1066 			} while (++i < words);
1067 
1068 			ixgbe_standby_eeprom(hw);
1069 			msec_delay(10);
1070 		}
1071 		/* Done with writing - release the EEPROM */
1072 		ixgbe_release_eeprom(hw);
1073 	}
1074 
1075 	return status;
1076 }
1077 
1078 /**
1079  *  ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1080  *  @hw: pointer to hardware structure
1081  *  @offset: offset within the EEPROM to be written to
1082  *  @data: 16 bit word to be written to the EEPROM
1083  *
1084  *  If ixgbe_eeprom_update_checksum is not called after this function, the
1085  *  EEPROM will most likely contain an invalid checksum.
1086  **/
ixgbe_write_eeprom_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1087 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1088 {
1089 	s32 status;
1090 
1091 	DEBUGFUNC("ixgbe_write_eeprom_generic");
1092 
1093 	hw->eeprom.ops.init_params(hw);
1094 
1095 	if (offset >= hw->eeprom.word_size) {
1096 		status = IXGBE_ERR_EEPROM;
1097 		goto out;
1098 	}
1099 
1100 	status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1101 
1102 out:
1103 	return status;
1104 }
1105 
1106 /**
1107  *  ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1108  *  @hw: pointer to hardware structure
1109  *  @offset: offset within the EEPROM to be read
1110  *  @data: read 16 bit words(s) from EEPROM
1111  *  @words: number of word(s)
1112  *
1113  *  Reads 16 bit word(s) from EEPROM through bit-bang method
1114  **/
ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1115 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1116 					      u16 words, u16 *data)
1117 {
1118 	s32 status = IXGBE_SUCCESS;
1119 	u16 i, count;
1120 
1121 	DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1122 
1123 	hw->eeprom.ops.init_params(hw);
1124 
1125 	if (words == 0) {
1126 		status = IXGBE_ERR_INVALID_ARGUMENT;
1127 		goto out;
1128 	}
1129 
1130 	if (offset + words > hw->eeprom.word_size) {
1131 		status = IXGBE_ERR_EEPROM;
1132 		goto out;
1133 	}
1134 
1135 	/*
1136 	 * We cannot hold synchronization semaphores for too long
1137 	 * to avoid other entity starvation. However it is more efficient
1138 	 * to read in bursts than synchronizing access for each word.
1139 	 */
1140 	for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1141 		count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1142 			IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1143 
1144 		status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1145 							   count, &data[i]);
1146 
1147 		if (status != IXGBE_SUCCESS)
1148 			break;
1149 	}
1150 
1151 out:
1152 	return status;
1153 }
1154 
1155 /**
1156  *  ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1157  *  @hw: pointer to hardware structure
1158  *  @offset: offset within the EEPROM to be read
1159  *  @words: number of word(s)
1160  *  @data: read 16 bit word(s) from EEPROM
1161  *
1162  *  Reads 16 bit word(s) from EEPROM through bit-bang method
1163  **/
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1164 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1165 					     u16 words, u16 *data)
1166 {
1167 	s32 status;
1168 	u16 word_in;
1169 	u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1170 	u16 i;
1171 
1172 	DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1173 
1174 	/* Prepare the EEPROM for reading  */
1175 	status = ixgbe_acquire_eeprom(hw);
1176 
1177 	if (status == IXGBE_SUCCESS) {
1178 		if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1179 			ixgbe_release_eeprom(hw);
1180 			status = IXGBE_ERR_EEPROM;
1181 		}
1182 	}
1183 
1184 	if (status == IXGBE_SUCCESS) {
1185 		for (i = 0; i < words; i++) {
1186 			ixgbe_standby_eeprom(hw);
1187 			/*
1188 			 * Some SPI eeproms use the 8th address bit embedded
1189 			 * in the opcode
1190 			 */
1191 			if ((hw->eeprom.address_bits == 8) &&
1192 			    ((offset + i) >= 128))
1193 				read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1194 
1195 			/* Send the READ command (opcode + addr) */
1196 			ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1197 						    IXGBE_EEPROM_OPCODE_BITS);
1198 			ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1199 						    hw->eeprom.address_bits);
1200 
1201 			/* Read the data. */
1202 			word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1203 			data[i] = (word_in >> 8) | (word_in << 8);
1204 		}
1205 
1206 		/* End this read operation */
1207 		ixgbe_release_eeprom(hw);
1208 	}
1209 
1210 	return status;
1211 }
1212 
1213 /**
1214  *  ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1215  *  @hw: pointer to hardware structure
1216  *  @offset: offset within the EEPROM to be read
1217  *  @data: read 16 bit value from EEPROM
1218  *
1219  *  Reads 16 bit value from EEPROM through bit-bang method
1220  **/
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1221 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1222 				       u16 *data)
1223 {
1224 	s32 status;
1225 
1226 	DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1227 
1228 	hw->eeprom.ops.init_params(hw);
1229 
1230 	if (offset >= hw->eeprom.word_size) {
1231 		status = IXGBE_ERR_EEPROM;
1232 		goto out;
1233 	}
1234 
1235 	status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1236 
1237 out:
1238 	return status;
1239 }
1240 
1241 /**
1242  *  ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1243  *  @hw: pointer to hardware structure
1244  *  @offset: offset of word in the EEPROM to read
1245  *  @words: number of word(s)
1246  *  @data: 16 bit word(s) from the EEPROM
1247  *
1248  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
1249  **/
ixgbe_read_eerd_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1250 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1251 				   u16 words, u16 *data)
1252 {
1253 	u32 eerd;
1254 	s32 status = IXGBE_SUCCESS;
1255 	u32 i;
1256 
1257 	DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1258 
1259 	hw->eeprom.ops.init_params(hw);
1260 
1261 	if (words == 0) {
1262 		status = IXGBE_ERR_INVALID_ARGUMENT;
1263 		goto out;
1264 	}
1265 
1266 	if (offset >= hw->eeprom.word_size) {
1267 		status = IXGBE_ERR_EEPROM;
1268 		goto out;
1269 	}
1270 
1271 	for (i = 0; i < words; i++) {
1272 		eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1273 		       IXGBE_EEPROM_RW_REG_START;
1274 
1275 		IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1276 		status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1277 
1278 		if (status == IXGBE_SUCCESS) {
1279 			data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1280 				   IXGBE_EEPROM_RW_REG_DATA);
1281 		} else {
1282 			DEBUGOUT("Eeprom read timed out\n");
1283 			goto out;
1284 		}
1285 	}
1286 out:
1287 	return status;
1288 }
1289 
1290 /**
1291  *  ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1292  *  @hw: pointer to hardware structure
1293  *  @offset: offset within the EEPROM to be used as a scratch pad
1294  *
1295  *  Discover EEPROM page size by writing marching data at given offset.
1296  *  This function is called only when we are writing a new large buffer
1297  *  at given offset so the data would be overwritten anyway.
1298  **/
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw * hw,u16 offset)1299 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1300 						 u16 offset)
1301 {
1302 	u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1303 	s32 status = IXGBE_SUCCESS;
1304 	u16 i;
1305 
1306 	DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1307 
1308 	for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1309 		data[i] = i;
1310 
1311 	hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1312 	status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1313 					     IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1314 	hw->eeprom.word_page_size = 0;
1315 	if (status != IXGBE_SUCCESS)
1316 		goto out;
1317 
1318 	status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1319 	if (status != IXGBE_SUCCESS)
1320 		goto out;
1321 
1322 	/*
1323 	 * When writing in burst more than the actual page size
1324 	 * EEPROM address wraps around current page.
1325 	 */
1326 	hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1327 
1328 	DEBUGOUT1("Detected EEPROM page size = %d words.",
1329 		  hw->eeprom.word_page_size);
1330 out:
1331 	return status;
1332 }
1333 
1334 /**
1335  *  ixgbe_read_eerd_generic - Read EEPROM word using EERD
1336  *  @hw: pointer to hardware structure
1337  *  @offset: offset of  word in the EEPROM to read
1338  *  @data: word read from the EEPROM
1339  *
1340  *  Reads a 16 bit word from the EEPROM using the EERD register.
1341  **/
ixgbe_read_eerd_generic(struct ixgbe_hw * hw,u16 offset,u16 * data)1342 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1343 {
1344 	return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1345 }
1346 
1347 /**
1348  *  ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1349  *  @hw: pointer to hardware structure
1350  *  @offset: offset of  word in the EEPROM to write
1351  *  @words: number of word(s)
1352  *  @data: word(s) write to the EEPROM
1353  *
1354  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
1355  **/
ixgbe_write_eewr_buffer_generic(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1356 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1357 				    u16 words, u16 *data)
1358 {
1359 	u32 eewr;
1360 	s32 status = IXGBE_SUCCESS;
1361 	u16 i;
1362 
1363 	DEBUGFUNC("ixgbe_write_eewr_generic");
1364 
1365 	hw->eeprom.ops.init_params(hw);
1366 
1367 	if (words == 0) {
1368 		status = IXGBE_ERR_INVALID_ARGUMENT;
1369 		goto out;
1370 	}
1371 
1372 	if (offset >= hw->eeprom.word_size) {
1373 		status = IXGBE_ERR_EEPROM;
1374 		goto out;
1375 	}
1376 
1377 	for (i = 0; i < words; i++) {
1378 		eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1379 			(data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1380 			IXGBE_EEPROM_RW_REG_START;
1381 
1382 		status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1383 		if (status != IXGBE_SUCCESS) {
1384 			DEBUGOUT("Eeprom write EEWR timed out\n");
1385 			goto out;
1386 		}
1387 
1388 		IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1389 
1390 		status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1391 		if (status != IXGBE_SUCCESS) {
1392 			DEBUGOUT("Eeprom write EEWR timed out\n");
1393 			goto out;
1394 		}
1395 	}
1396 
1397 out:
1398 	return status;
1399 }
1400 
1401 /**
1402  *  ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1403  *  @hw: pointer to hardware structure
1404  *  @offset: offset of  word in the EEPROM to write
1405  *  @data: word write to the EEPROM
1406  *
1407  *  Write a 16 bit word to the EEPROM using the EEWR register.
1408  **/
ixgbe_write_eewr_generic(struct ixgbe_hw * hw,u16 offset,u16 data)1409 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1410 {
1411 	return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1412 }
1413 
1414 /**
1415  *  ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1416  *  @hw: pointer to hardware structure
1417  *  @ee_reg: EEPROM flag for polling
1418  *
1419  *  Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1420  *  read or write is done respectively.
1421  **/
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw * hw,u32 ee_reg)1422 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1423 {
1424 	u32 i;
1425 	u32 reg;
1426 	s32 status = IXGBE_ERR_EEPROM;
1427 
1428 	DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1429 
1430 	for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1431 		if (ee_reg == IXGBE_NVM_POLL_READ)
1432 			reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1433 		else
1434 			reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1435 
1436 		if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1437 			status = IXGBE_SUCCESS;
1438 			break;
1439 		}
1440 		usec_delay(5);
1441 	}
1442 	return status;
1443 }
1444 
1445 /**
1446  *  ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1447  *  @hw: pointer to hardware structure
1448  *
1449  *  Prepares EEPROM for access using bit-bang method. This function should
1450  *  be called before issuing a command to the EEPROM.
1451  **/
ixgbe_acquire_eeprom(struct ixgbe_hw * hw)1452 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1453 {
1454 	s32 status = IXGBE_SUCCESS;
1455 	u32 eec;
1456 	u32 i;
1457 
1458 	DEBUGFUNC("ixgbe_acquire_eeprom");
1459 
1460 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1461 	    != IXGBE_SUCCESS)
1462 		status = IXGBE_ERR_SWFW_SYNC;
1463 
1464 	if (status == IXGBE_SUCCESS) {
1465 		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1466 
1467 		/* Request EEPROM Access */
1468 		eec |= IXGBE_EEC_REQ;
1469 		IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1470 
1471 		for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1472 			eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1473 			if (eec & IXGBE_EEC_GNT)
1474 				break;
1475 			usec_delay(5);
1476 		}
1477 
1478 		/* Release if grant not acquired */
1479 		if (!(eec & IXGBE_EEC_GNT)) {
1480 			eec &= ~IXGBE_EEC_REQ;
1481 			IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1482 			DEBUGOUT("Could not acquire EEPROM grant\n");
1483 
1484 			hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1485 			status = IXGBE_ERR_EEPROM;
1486 		}
1487 
1488 		/* Setup EEPROM for Read/Write */
1489 		if (status == IXGBE_SUCCESS) {
1490 			/* Clear CS and SK */
1491 			eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1492 			IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1493 			IXGBE_WRITE_FLUSH(hw);
1494 			usec_delay(1);
1495 		}
1496 	}
1497 	return status;
1498 }
1499 
1500 /**
1501  *  ixgbe_get_eeprom_semaphore - Get hardware semaphore
1502  *  @hw: pointer to hardware structure
1503  *
1504  *  Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1505  **/
ixgbe_get_eeprom_semaphore(struct ixgbe_hw * hw)1506 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1507 {
1508 	s32 status = IXGBE_ERR_EEPROM;
1509 	u32 timeout = 2000;
1510 	u32 i;
1511 	u32 swsm;
1512 
1513 	DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1514 
1515 
1516 	/* Get SMBI software semaphore between device drivers first */
1517 	for (i = 0; i < timeout; i++) {
1518 		/*
1519 		 * If the SMBI bit is 0 when we read it, then the bit will be
1520 		 * set and we have the semaphore
1521 		 */
1522 		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1523 		if (!(swsm & IXGBE_SWSM_SMBI)) {
1524 			status = IXGBE_SUCCESS;
1525 			break;
1526 		}
1527 		usec_delay(50);
1528 	}
1529 
1530 	if (i == timeout) {
1531 		DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1532 			 "not granted.\n");
1533 		/*
1534 		 * this release is particularly important because our attempts
1535 		 * above to get the semaphore may have succeeded, and if there
1536 		 * was a timeout, we should unconditionally clear the semaphore
1537 		 * bits to free the driver to make progress
1538 		 */
1539 		ixgbe_release_eeprom_semaphore(hw);
1540 
1541 		usec_delay(50);
1542 		/*
1543 		 * one last try
1544 		 * If the SMBI bit is 0 when we read it, then the bit will be
1545 		 * set and we have the semaphore
1546 		 */
1547 		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1548 		if (!(swsm & IXGBE_SWSM_SMBI))
1549 			status = IXGBE_SUCCESS;
1550 	}
1551 
1552 	/* Now get the semaphore between SW/FW through the SWESMBI bit */
1553 	if (status == IXGBE_SUCCESS) {
1554 		for (i = 0; i < timeout; i++) {
1555 			swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1556 
1557 			/* Set the SW EEPROM semaphore bit to request access */
1558 			swsm |= IXGBE_SWSM_SWESMBI;
1559 			IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1560 
1561 			/*
1562 			 * If we set the bit successfully then we got the
1563 			 * semaphore.
1564 			 */
1565 			swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1566 			if (swsm & IXGBE_SWSM_SWESMBI)
1567 				break;
1568 
1569 			usec_delay(50);
1570 		}
1571 
1572 		/*
1573 		 * Release semaphores and return error if SW EEPROM semaphore
1574 		 * was not granted because we don't have access to the EEPROM
1575 		 */
1576 		if (i >= timeout) {
1577 			DEBUGOUT("SWESMBI Software EEPROM semaphore "
1578 				 "not granted.\n");
1579 			ixgbe_release_eeprom_semaphore(hw);
1580 			status = IXGBE_ERR_EEPROM;
1581 		}
1582 	} else {
1583 		DEBUGOUT("Software semaphore SMBI between device drivers "
1584 			 "not granted.\n");
1585 	}
1586 
1587 	return status;
1588 }
1589 
1590 /**
1591  *  ixgbe_release_eeprom_semaphore - Release hardware semaphore
1592  *  @hw: pointer to hardware structure
1593  *
1594  *  This function clears hardware semaphore bits.
1595  **/
ixgbe_release_eeprom_semaphore(struct ixgbe_hw * hw)1596 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1597 {
1598 	u32 swsm;
1599 
1600 	DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1601 
1602 	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1603 
1604 	/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1605 	swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1606 	IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1607 	IXGBE_WRITE_FLUSH(hw);
1608 }
1609 
1610 /**
1611  *  ixgbe_ready_eeprom - Polls for EEPROM ready
1612  *  @hw: pointer to hardware structure
1613  **/
ixgbe_ready_eeprom(struct ixgbe_hw * hw)1614 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1615 {
1616 	s32 status = IXGBE_SUCCESS;
1617 	u16 i;
1618 	u8 spi_stat_reg;
1619 
1620 	DEBUGFUNC("ixgbe_ready_eeprom");
1621 
1622 	/*
1623 	 * Read "Status Register" repeatedly until the LSB is cleared.  The
1624 	 * EEPROM will signal that the command has been completed by clearing
1625 	 * bit 0 of the internal status register.  If it's not cleared within
1626 	 * 5 milliseconds, then error out.
1627 	 */
1628 	for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1629 		ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1630 					    IXGBE_EEPROM_OPCODE_BITS);
1631 		spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1632 		if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1633 			break;
1634 
1635 		usec_delay(5);
1636 		ixgbe_standby_eeprom(hw);
1637 	};
1638 
1639 	/*
1640 	 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1641 	 * devices (and only 0-5mSec on 5V devices)
1642 	 */
1643 	if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1644 		DEBUGOUT("SPI EEPROM Status error\n");
1645 		status = IXGBE_ERR_EEPROM;
1646 	}
1647 
1648 	return status;
1649 }
1650 
1651 /**
1652  *  ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1653  *  @hw: pointer to hardware structure
1654  **/
ixgbe_standby_eeprom(struct ixgbe_hw * hw)1655 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1656 {
1657 	u32 eec;
1658 
1659 	DEBUGFUNC("ixgbe_standby_eeprom");
1660 
1661 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1662 
1663 	/* Toggle CS to flush commands */
1664 	eec |= IXGBE_EEC_CS;
1665 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1666 	IXGBE_WRITE_FLUSH(hw);
1667 	usec_delay(1);
1668 	eec &= ~IXGBE_EEC_CS;
1669 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1670 	IXGBE_WRITE_FLUSH(hw);
1671 	usec_delay(1);
1672 }
1673 
1674 /**
1675  *  ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1676  *  @hw: pointer to hardware structure
1677  *  @data: data to send to the EEPROM
1678  *  @count: number of bits to shift out
1679  **/
ixgbe_shift_out_eeprom_bits(struct ixgbe_hw * hw,u16 data,u16 count)1680 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1681 					u16 count)
1682 {
1683 	u32 eec;
1684 	u32 mask;
1685 	u32 i;
1686 
1687 	DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1688 
1689 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1690 
1691 	/*
1692 	 * Mask is used to shift "count" bits of "data" out to the EEPROM
1693 	 * one bit at a time.  Determine the starting bit based on count
1694 	 */
1695 	mask = 0x01 << (count - 1);
1696 
1697 	for (i = 0; i < count; i++) {
1698 		/*
1699 		 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1700 		 * "1", and then raising and then lowering the clock (the SK
1701 		 * bit controls the clock input to the EEPROM).  A "0" is
1702 		 * shifted out to the EEPROM by setting "DI" to "0" and then
1703 		 * raising and then lowering the clock.
1704 		 */
1705 		if (data & mask)
1706 			eec |= IXGBE_EEC_DI;
1707 		else
1708 			eec &= ~IXGBE_EEC_DI;
1709 
1710 		IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1711 		IXGBE_WRITE_FLUSH(hw);
1712 
1713 		usec_delay(1);
1714 
1715 		ixgbe_raise_eeprom_clk(hw, &eec);
1716 		ixgbe_lower_eeprom_clk(hw, &eec);
1717 
1718 		/*
1719 		 * Shift mask to signify next bit of data to shift in to the
1720 		 * EEPROM
1721 		 */
1722 		mask = mask >> 1;
1723 	};
1724 
1725 	/* We leave the "DI" bit set to "0" when we leave this routine. */
1726 	eec &= ~IXGBE_EEC_DI;
1727 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1728 	IXGBE_WRITE_FLUSH(hw);
1729 }
1730 
1731 /**
1732  *  ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1733  *  @hw: pointer to hardware structure
1734  **/
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw * hw,u16 count)1735 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1736 {
1737 	u32 eec;
1738 	u32 i;
1739 	u16 data = 0;
1740 
1741 	DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1742 
1743 	/*
1744 	 * In order to read a register from the EEPROM, we need to shift
1745 	 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1746 	 * the clock input to the EEPROM (setting the SK bit), and then reading
1747 	 * the value of the "DO" bit.  During this "shifting in" process the
1748 	 * "DI" bit should always be clear.
1749 	 */
1750 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1751 
1752 	eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1753 
1754 	for (i = 0; i < count; i++) {
1755 		data = data << 1;
1756 		ixgbe_raise_eeprom_clk(hw, &eec);
1757 
1758 		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1759 
1760 		eec &= ~(IXGBE_EEC_DI);
1761 		if (eec & IXGBE_EEC_DO)
1762 			data |= 1;
1763 
1764 		ixgbe_lower_eeprom_clk(hw, &eec);
1765 	}
1766 
1767 	return data;
1768 }
1769 
1770 /**
1771  *  ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1772  *  @hw: pointer to hardware structure
1773  *  @eec: EEC register's current value
1774  **/
ixgbe_raise_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)1775 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1776 {
1777 	DEBUGFUNC("ixgbe_raise_eeprom_clk");
1778 
1779 	/*
1780 	 * Raise the clock input to the EEPROM
1781 	 * (setting the SK bit), then delay
1782 	 */
1783 	*eec = *eec | IXGBE_EEC_SK;
1784 	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1785 	IXGBE_WRITE_FLUSH(hw);
1786 	usec_delay(1);
1787 }
1788 
1789 /**
1790  *  ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1791  *  @hw: pointer to hardware structure
1792  *  @eecd: EECD's current value
1793  **/
ixgbe_lower_eeprom_clk(struct ixgbe_hw * hw,u32 * eec)1794 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1795 {
1796 	DEBUGFUNC("ixgbe_lower_eeprom_clk");
1797 
1798 	/*
1799 	 * Lower the clock input to the EEPROM (clearing the SK bit), then
1800 	 * delay
1801 	 */
1802 	*eec = *eec & ~IXGBE_EEC_SK;
1803 	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1804 	IXGBE_WRITE_FLUSH(hw);
1805 	usec_delay(1);
1806 }
1807 
1808 /**
1809  *  ixgbe_release_eeprom - Release EEPROM, release semaphores
1810  *  @hw: pointer to hardware structure
1811  **/
ixgbe_release_eeprom(struct ixgbe_hw * hw)1812 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1813 {
1814 	u32 eec;
1815 
1816 	DEBUGFUNC("ixgbe_release_eeprom");
1817 
1818 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1819 
1820 	eec |= IXGBE_EEC_CS;  /* Pull CS high */
1821 	eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1822 
1823 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1824 	IXGBE_WRITE_FLUSH(hw);
1825 
1826 	usec_delay(1);
1827 
1828 	/* Stop requesting EEPROM access */
1829 	eec &= ~IXGBE_EEC_REQ;
1830 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1831 
1832 	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1833 
1834 	/* Delay before attempt to obtain semaphore again to allow FW access */
1835 	msec_delay(hw->eeprom.semaphore_delay);
1836 }
1837 
1838 /**
1839  *  ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1840  *  @hw: pointer to hardware structure
1841  **/
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw * hw)1842 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1843 {
1844 	u16 i;
1845 	u16 j;
1846 	u16 checksum = 0;
1847 	u16 length = 0;
1848 	u16 pointer = 0;
1849 	u16 word = 0;
1850 
1851 	DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
1852 
1853 	/* Include 0x0-0x3F in the checksum */
1854 	for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1855 		if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
1856 			DEBUGOUT("EEPROM read failed\n");
1857 			break;
1858 		}
1859 		checksum += word;
1860 	}
1861 
1862 	/* Include all data from pointers except for the fw pointer */
1863 	for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1864 		hw->eeprom.ops.read(hw, i, &pointer);
1865 
1866 		/* Make sure the pointer seems valid */
1867 		if (pointer != 0xFFFF && pointer != 0) {
1868 			hw->eeprom.ops.read(hw, pointer, &length);
1869 
1870 			if (length != 0xFFFF && length != 0) {
1871 				for (j = pointer+1; j <= pointer+length; j++) {
1872 					hw->eeprom.ops.read(hw, j, &word);
1873 					checksum += word;
1874 				}
1875 			}
1876 		}
1877 	}
1878 
1879 	checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1880 
1881 	return checksum;
1882 }
1883 
1884 /**
1885  *  ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1886  *  @hw: pointer to hardware structure
1887  *  @checksum_val: calculated checksum
1888  *
1889  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1890  *  caller does not need checksum_val, the value can be NULL.
1891  **/
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw * hw,u16 * checksum_val)1892 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1893 					   u16 *checksum_val)
1894 {
1895 	s32 status;
1896 	u16 checksum;
1897 	u16 read_checksum = 0;
1898 
1899 	DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
1900 
1901 	/*
1902 	 * Read the first word from the EEPROM. If this times out or fails, do
1903 	 * not continue or we could be in for a very long wait while every
1904 	 * EEPROM read fails
1905 	 */
1906 	status = hw->eeprom.ops.read(hw, 0, &checksum);
1907 
1908 	if (status == IXGBE_SUCCESS) {
1909 		checksum = hw->eeprom.ops.calc_checksum(hw);
1910 
1911 		hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1912 
1913 		/*
1914 		 * Verify read checksum from EEPROM is the same as
1915 		 * calculated checksum
1916 		 */
1917 		if (read_checksum != checksum)
1918 			status = IXGBE_ERR_EEPROM_CHECKSUM;
1919 
1920 		/* If the user cares, return the calculated checksum */
1921 		if (checksum_val)
1922 			*checksum_val = checksum;
1923 	} else {
1924 		DEBUGOUT("EEPROM read failed\n");
1925 	}
1926 
1927 	return status;
1928 }
1929 
1930 /**
1931  *  ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1932  *  @hw: pointer to hardware structure
1933  **/
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw * hw)1934 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1935 {
1936 	s32 status;
1937 	u16 checksum;
1938 
1939 	DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
1940 
1941 	/*
1942 	 * Read the first word from the EEPROM. If this times out or fails, do
1943 	 * not continue or we could be in for a very long wait while every
1944 	 * EEPROM read fails
1945 	 */
1946 	status = hw->eeprom.ops.read(hw, 0, &checksum);
1947 
1948 	if (status == IXGBE_SUCCESS) {
1949 		checksum = hw->eeprom.ops.calc_checksum(hw);
1950 		status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1951 					      checksum);
1952 	} else {
1953 		DEBUGOUT("EEPROM read failed\n");
1954 	}
1955 
1956 	return status;
1957 }
1958 
1959 /**
1960  *  ixgbe_validate_mac_addr - Validate MAC address
1961  *  @mac_addr: pointer to MAC address.
1962  *
1963  *  Tests a MAC address to ensure it is a valid Individual Address
1964  **/
ixgbe_validate_mac_addr(u8 * mac_addr)1965 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1966 {
1967 	s32 status = IXGBE_SUCCESS;
1968 
1969 	DEBUGFUNC("ixgbe_validate_mac_addr");
1970 
1971 	/* Make sure it is not a multicast address */
1972 	if (IXGBE_IS_MULTICAST(mac_addr)) {
1973 		DEBUGOUT("MAC address is multicast\n");
1974 		status = IXGBE_ERR_INVALID_MAC_ADDR;
1975 	/* Not a broadcast address */
1976 	} else if (IXGBE_IS_BROADCAST(mac_addr)) {
1977 		DEBUGOUT("MAC address is broadcast\n");
1978 		status = IXGBE_ERR_INVALID_MAC_ADDR;
1979 	/* Reject the zero address */
1980 	} else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1981 		   mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1982 		DEBUGOUT("MAC address is all zeros\n");
1983 		status = IXGBE_ERR_INVALID_MAC_ADDR;
1984 	}
1985 	return status;
1986 }
1987 
1988 /**
1989  *  ixgbe_set_rar_generic - Set Rx address register
1990  *  @hw: pointer to hardware structure
1991  *  @index: Receive address register to write
1992  *  @addr: Address to put into receive address register
1993  *  @vmdq: VMDq "set" or "pool" index
1994  *  @enable_addr: set flag that address is active
1995  *
1996  *  Puts an ethernet address into a receive address register.
1997  **/
ixgbe_set_rar_generic(struct ixgbe_hw * hw,u32 index,u8 * addr,u32 vmdq,u32 enable_addr)1998 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1999 			  u32 enable_addr)
2000 {
2001 	u32 rar_low, rar_high;
2002 	u32 rar_entries = hw->mac.num_rar_entries;
2003 
2004 	DEBUGFUNC("ixgbe_set_rar_generic");
2005 
2006 	/* Make sure we are using a valid rar index range */
2007 	if (index >= rar_entries) {
2008 		DEBUGOUT1("RAR index %d is out of range.\n", index);
2009 		return IXGBE_ERR_INVALID_ARGUMENT;
2010 	}
2011 
2012 	/* setup VMDq pool selection before this RAR gets enabled */
2013 	hw->mac.ops.set_vmdq(hw, index, vmdq);
2014 
2015 	/*
2016 	 * HW expects these in little endian so we reverse the byte
2017 	 * order from network order (big endian) to little endian
2018 	 */
2019 	rar_low = ((u32)addr[0] |
2020 		   ((u32)addr[1] << 8) |
2021 		   ((u32)addr[2] << 16) |
2022 		   ((u32)addr[3] << 24));
2023 	/*
2024 	 * Some parts put the VMDq setting in the extra RAH bits,
2025 	 * so save everything except the lower 16 bits that hold part
2026 	 * of the address and the address valid bit.
2027 	 */
2028 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2029 	rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2030 	rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2031 
2032 	if (enable_addr != 0)
2033 		rar_high |= IXGBE_RAH_AV;
2034 
2035 	IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2036 	IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2037 
2038 	return IXGBE_SUCCESS;
2039 }
2040 
2041 /**
2042  *  ixgbe_clear_rar_generic - Remove Rx address register
2043  *  @hw: pointer to hardware structure
2044  *  @index: Receive address register to write
2045  *
2046  *  Clears an ethernet address from a receive address register.
2047  **/
ixgbe_clear_rar_generic(struct ixgbe_hw * hw,u32 index)2048 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2049 {
2050 	u32 rar_high;
2051 	u32 rar_entries = hw->mac.num_rar_entries;
2052 
2053 	DEBUGFUNC("ixgbe_clear_rar_generic");
2054 
2055 	/* Make sure we are using a valid rar index range */
2056 	if (index >= rar_entries) {
2057 		DEBUGOUT1("RAR index %d is out of range.\n", index);
2058 		return IXGBE_ERR_INVALID_ARGUMENT;
2059 	}
2060 
2061 	/*
2062 	 * Some parts put the VMDq setting in the extra RAH bits,
2063 	 * so save everything except the lower 16 bits that hold part
2064 	 * of the address and the address valid bit.
2065 	 */
2066 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2067 	rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2068 
2069 	IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2070 	IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2071 
2072 	/* clear VMDq pool/queue selection for this RAR */
2073 	hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2074 
2075 	return IXGBE_SUCCESS;
2076 }
2077 
2078 /**
2079  *  ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2080  *  @hw: pointer to hardware structure
2081  *
2082  *  Places the MAC address in receive address register 0 and clears the rest
2083  *  of the receive address registers. Clears the multicast table. Assumes
2084  *  the receiver is in reset when the routine is called.
2085  **/
ixgbe_init_rx_addrs_generic(struct ixgbe_hw * hw)2086 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2087 {
2088 	u32 i;
2089 	u32 rar_entries = hw->mac.num_rar_entries;
2090 
2091 	DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2092 
2093 	/*
2094 	 * If the current mac address is valid, assume it is a software override
2095 	 * to the permanent address.
2096 	 * Otherwise, use the permanent address from the eeprom.
2097 	 */
2098 	if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2099 	    IXGBE_ERR_INVALID_MAC_ADDR) {
2100 		/* Get the MAC address from the RAR0 for later reference */
2101 		hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2102 
2103 		DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2104 			  hw->mac.addr[0], hw->mac.addr[1],
2105 			  hw->mac.addr[2]);
2106 		DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2107 			  hw->mac.addr[4], hw->mac.addr[5]);
2108 	} else {
2109 		/* Setup the receive address. */
2110 		DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2111 		DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2112 			  hw->mac.addr[0], hw->mac.addr[1],
2113 			  hw->mac.addr[2]);
2114 		DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2115 			  hw->mac.addr[4], hw->mac.addr[5]);
2116 
2117 		hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2118 
2119 		/* clear VMDq pool/queue selection for RAR 0 */
2120 		hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2121 	}
2122 	hw->addr_ctrl.overflow_promisc = 0;
2123 
2124 	hw->addr_ctrl.rar_used_count = 1;
2125 
2126 	/* Zero out the other receive addresses. */
2127 	DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2128 	for (i = 1; i < rar_entries; i++) {
2129 		IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2130 		IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2131 	}
2132 
2133 	/* Clear the MTA */
2134 	hw->addr_ctrl.mta_in_use = 0;
2135 	IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2136 
2137 	DEBUGOUT(" Clearing MTA\n");
2138 	for (i = 0; i < hw->mac.mcft_size; i++)
2139 		IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2140 
2141 	/* Should always be IXGBE_SUCCESS. */
2142 	return ixgbe_init_uta_tables(hw);
2143 }
2144 
2145 /**
2146  *  ixgbe_add_uc_addr - Adds a secondary unicast address.
2147  *  @hw: pointer to hardware structure
2148  *  @addr: new address
2149  *
2150  *  Adds it to unused receive address register or goes into promiscuous mode.
2151  **/
ixgbe_add_uc_addr(struct ixgbe_hw * hw,u8 * addr,u32 vmdq)2152 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2153 {
2154 	u32 rar_entries = hw->mac.num_rar_entries;
2155 	u32 rar;
2156 
2157 	DEBUGFUNC("ixgbe_add_uc_addr");
2158 
2159 	DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2160 		  addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2161 
2162 	/*
2163 	 * Place this address in the RAR if there is room,
2164 	 * else put the controller into promiscuous mode
2165 	 */
2166 	if (hw->addr_ctrl.rar_used_count < rar_entries) {
2167 		rar = hw->addr_ctrl.rar_used_count;
2168 		hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2169 		DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2170 		hw->addr_ctrl.rar_used_count++;
2171 	} else {
2172 		hw->addr_ctrl.overflow_promisc++;
2173 	}
2174 
2175 	DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2176 }
2177 
2178 /**
2179  *  ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2180  *  @hw: pointer to hardware structure
2181  *  @addr_list: the list of new addresses
2182  *  @addr_count: number of addresses
2183  *  @next: iterator function to walk the address list
2184  *
2185  *  The given list replaces any existing list.  Clears the secondary addrs from
2186  *  receive address registers.  Uses unused receive address registers for the
2187  *  first secondary addresses, and falls back to promiscuous mode as needed.
2188  *
2189  *  Drivers using secondary unicast addresses must set user_set_promisc when
2190  *  manually putting the device into promiscuous mode.
2191  **/
ixgbe_update_uc_addr_list_generic(struct ixgbe_hw * hw,u8 * addr_list,u32 addr_count,ixgbe_mc_addr_itr next)2192 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2193 				      u32 addr_count, ixgbe_mc_addr_itr next)
2194 {
2195 	u8 *addr;
2196 	u32 i;
2197 	u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2198 	u32 uc_addr_in_use;
2199 	u32 fctrl;
2200 	u32 vmdq;
2201 
2202 	DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2203 
2204 	/*
2205 	 * Clear accounting of old secondary address list,
2206 	 * don't count RAR[0]
2207 	 */
2208 	uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2209 	hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2210 	hw->addr_ctrl.overflow_promisc = 0;
2211 
2212 	/* Zero out the other receive addresses */
2213 	DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2214 	for (i = 0; i < uc_addr_in_use; i++) {
2215 		IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2216 		IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2217 	}
2218 
2219 	/* Add the new addresses */
2220 	for (i = 0; i < addr_count; i++) {
2221 		DEBUGOUT(" Adding the secondary addresses:\n");
2222 		addr = next(hw, &addr_list, &vmdq);
2223 		ixgbe_add_uc_addr(hw, addr, vmdq);
2224 	}
2225 
2226 	if (hw->addr_ctrl.overflow_promisc) {
2227 		/* enable promisc if not already in overflow or set by user */
2228 		if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2229 			DEBUGOUT(" Entering address overflow promisc mode\n");
2230 			fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2231 			fctrl |= IXGBE_FCTRL_UPE;
2232 			IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2233 		}
2234 	} else {
2235 		/* only disable if set by overflow, not by user */
2236 		if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2237 			DEBUGOUT(" Leaving address overflow promisc mode\n");
2238 			fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2239 			fctrl &= ~IXGBE_FCTRL_UPE;
2240 			IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2241 		}
2242 	}
2243 
2244 	DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2245 	return IXGBE_SUCCESS;
2246 }
2247 
2248 /**
2249  *  ixgbe_mta_vector - Determines bit-vector in multicast table to set
2250  *  @hw: pointer to hardware structure
2251  *  @mc_addr: the multicast address
2252  *
2253  *  Extracts the 12 bits, from a multicast address, to determine which
2254  *  bit-vector to set in the multicast table. The hardware uses 12 bits, from
2255  *  incoming rx multicast addresses, to determine the bit-vector to check in
2256  *  the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2257  *  by the MO field of the MCSTCTRL. The MO field is set during initialization
2258  *  to mc_filter_type.
2259  **/
ixgbe_mta_vector(struct ixgbe_hw * hw,u8 * mc_addr)2260 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2261 {
2262 	u32 vector = 0;
2263 
2264 	DEBUGFUNC("ixgbe_mta_vector");
2265 
2266 	switch (hw->mac.mc_filter_type) {
2267 	case 0:   /* use bits [47:36] of the address */
2268 		vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2269 		break;
2270 	case 1:   /* use bits [46:35] of the address */
2271 		vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2272 		break;
2273 	case 2:   /* use bits [45:34] of the address */
2274 		vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2275 		break;
2276 	case 3:   /* use bits [43:32] of the address */
2277 		vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2278 		break;
2279 	default:  /* Invalid mc_filter_type */
2280 		DEBUGOUT("MC filter type param set incorrectly\n");
2281 		ASSERT(0);
2282 		break;
2283 	}
2284 
2285 	/* vector can only be 12-bits or boundary will be exceeded */
2286 	vector &= 0xFFF;
2287 	return vector;
2288 }
2289 
2290 /**
2291  *  ixgbe_set_mta - Set bit-vector in multicast table
2292  *  @hw: pointer to hardware structure
2293  *  @hash_value: Multicast address hash value
2294  *
2295  *  Sets the bit-vector in the multicast table.
2296  **/
ixgbe_set_mta(struct ixgbe_hw * hw,u8 * mc_addr)2297 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2298 {
2299 	u32 vector;
2300 	u32 vector_bit;
2301 	u32 vector_reg;
2302 
2303 	DEBUGFUNC("ixgbe_set_mta");
2304 
2305 	hw->addr_ctrl.mta_in_use++;
2306 
2307 	vector = ixgbe_mta_vector(hw, mc_addr);
2308 	DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2309 
2310 	/*
2311 	 * The MTA is a register array of 128 32-bit registers. It is treated
2312 	 * like an array of 4096 bits.  We want to set bit
2313 	 * BitArray[vector_value]. So we figure out what register the bit is
2314 	 * in, read it, OR in the new bit, then write back the new value.  The
2315 	 * register is determined by the upper 7 bits of the vector value and
2316 	 * the bit within that register are determined by the lower 5 bits of
2317 	 * the value.
2318 	 */
2319 	vector_reg = (vector >> 5) & 0x7F;
2320 	vector_bit = vector & 0x1F;
2321 	hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2322 }
2323 
2324 /**
2325  *  ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2326  *  @hw: pointer to hardware structure
2327  *  @mc_addr_list: the list of new multicast addresses
2328  *  @mc_addr_count: number of addresses
2329  *  @next: iterator function to walk the multicast address list
2330  *  @clear: flag, when set clears the table beforehand
2331  *
2332  *  When the clear flag is set, the given list replaces any existing list.
2333  *  Hashes the given addresses into the multicast table.
2334  **/
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw * hw,u8 * mc_addr_list,u32 mc_addr_count,ixgbe_mc_addr_itr next,bool clear)2335 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2336 				      u32 mc_addr_count, ixgbe_mc_addr_itr next,
2337 				      bool clear)
2338 {
2339 	u32 i;
2340 	u32 vmdq;
2341 
2342 	DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2343 
2344 	/*
2345 	 * Set the new number of MC addresses that we are being requested to
2346 	 * use.
2347 	 */
2348 	hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2349 	hw->addr_ctrl.mta_in_use = 0;
2350 
2351 	/* Clear mta_shadow */
2352 	if (clear) {
2353 		DEBUGOUT(" Clearing MTA\n");
2354 		(void) memset(&hw->mac.mta_shadow, 0,
2355 		    sizeof(hw->mac.mta_shadow));
2356 	}
2357 
2358 	/* Update mta_shadow */
2359 	for (i = 0; i < mc_addr_count; i++) {
2360 		DEBUGOUT(" Adding the multicast addresses:\n");
2361 		ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2362 	}
2363 
2364 	/* Enable mta */
2365 	for (i = 0; i < hw->mac.mcft_size; i++)
2366 		IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2367 				      hw->mac.mta_shadow[i]);
2368 
2369 	if (hw->addr_ctrl.mta_in_use > 0)
2370 		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2371 				IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2372 
2373 	DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2374 	return IXGBE_SUCCESS;
2375 }
2376 
2377 /**
2378  *  ixgbe_enable_mc_generic - Enable multicast address in RAR
2379  *  @hw: pointer to hardware structure
2380  *
2381  *  Enables multicast address in RAR and the use of the multicast hash table.
2382  **/
ixgbe_enable_mc_generic(struct ixgbe_hw * hw)2383 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2384 {
2385 	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2386 
2387 	DEBUGFUNC("ixgbe_enable_mc_generic");
2388 
2389 	if (a->mta_in_use > 0)
2390 		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2391 				hw->mac.mc_filter_type);
2392 
2393 	return IXGBE_SUCCESS;
2394 }
2395 
2396 /**
2397  *  ixgbe_disable_mc_generic - Disable multicast address in RAR
2398  *  @hw: pointer to hardware structure
2399  *
2400  *  Disables multicast address in RAR and the use of the multicast hash table.
2401  **/
ixgbe_disable_mc_generic(struct ixgbe_hw * hw)2402 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2403 {
2404 	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2405 
2406 	DEBUGFUNC("ixgbe_disable_mc_generic");
2407 
2408 	if (a->mta_in_use > 0)
2409 		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2410 
2411 	return IXGBE_SUCCESS;
2412 }
2413 
2414 /**
2415  *  ixgbe_fc_enable_generic - Enable flow control
2416  *  @hw: pointer to hardware structure
2417  *
2418  *  Enable flow control according to the current settings.
2419  **/
ixgbe_fc_enable_generic(struct ixgbe_hw * hw)2420 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2421 {
2422 	s32 ret_val = IXGBE_SUCCESS;
2423 	u32 mflcn_reg, fccfg_reg;
2424 	u32 reg;
2425 	u32 fcrtl, fcrth;
2426 	int i;
2427 
2428 	DEBUGFUNC("ixgbe_fc_enable_generic");
2429 
2430 	/* Validate the water mark configuration */
2431 	if (!hw->fc.pause_time) {
2432 		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2433 		goto out;
2434 	}
2435 
2436 	/* Low water mark of zero causes XOFF floods */
2437 	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2438 		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2439 		    hw->fc.high_water[i]) {
2440 			if (!hw->fc.low_water[i] ||
2441 			    hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2442 				DEBUGOUT("Invalid water mark configuration\n");
2443 				ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2444 				goto out;
2445 			}
2446 		}
2447 	}
2448 
2449 	/* Negotiate the fc mode to use */
2450 	ixgbe_fc_autoneg(hw);
2451 
2452 	/* Disable any previous flow control settings */
2453 	mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2454 	mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2455 
2456 	fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2457 	fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2458 
2459 	/*
2460 	 * The possible values of fc.current_mode are:
2461 	 * 0: Flow control is completely disabled
2462 	 * 1: Rx flow control is enabled (we can receive pause frames,
2463 	 *    but not send pause frames).
2464 	 * 2: Tx flow control is enabled (we can send pause frames but
2465 	 *    we do not support receiving pause frames).
2466 	 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2467 	 * other: Invalid.
2468 	 */
2469 	switch (hw->fc.current_mode) {
2470 	case ixgbe_fc_none:
2471 		/*
2472 		 * Flow control is disabled by software override or autoneg.
2473 		 * The code below will actually disable it in the HW.
2474 		 */
2475 		break;
2476 	case ixgbe_fc_rx_pause:
2477 		/*
2478 		 * Rx Flow control is enabled and Tx Flow control is
2479 		 * disabled by software override. Since there really
2480 		 * isn't a way to advertise that we are capable of RX
2481 		 * Pause ONLY, we will advertise that we support both
2482 		 * symmetric and asymmetric Rx PAUSE.  Later, we will
2483 		 * disable the adapter's ability to send PAUSE frames.
2484 		 */
2485 		mflcn_reg |= IXGBE_MFLCN_RFCE;
2486 		break;
2487 	case ixgbe_fc_tx_pause:
2488 		/*
2489 		 * Tx Flow control is enabled, and Rx Flow control is
2490 		 * disabled by software override.
2491 		 */
2492 		fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2493 		break;
2494 	case ixgbe_fc_full:
2495 		/* Flow control (both Rx and Tx) is enabled by SW override. */
2496 		mflcn_reg |= IXGBE_MFLCN_RFCE;
2497 		fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2498 		break;
2499 	default:
2500 		DEBUGOUT("Flow control param set incorrectly\n");
2501 		ret_val = IXGBE_ERR_CONFIG;
2502 		goto out;
2503 	}
2504 
2505 	/* Set 802.3x based flow control settings. */
2506 	mflcn_reg |= IXGBE_MFLCN_DPF;
2507 	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2508 	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2509 
2510 
2511 	/* Set up and enable Rx high/low water mark thresholds, enable XON. */
2512 	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2513 		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2514 		    hw->fc.high_water[i]) {
2515 			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2516 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2517 			fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2518 		} else {
2519 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2520 			/*
2521 			 * In order to prevent Tx hangs when the internal Tx
2522 			 * switch is enabled we must set the high water mark
2523 			 * to the maximum FCRTH value.  This allows the Tx
2524 			 * switch to function even under heavy Rx workloads.
2525 			 */
2526 			fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2527 		}
2528 
2529 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2530 	}
2531 
2532 	/* Configure pause time (2 TCs per register) */
2533 	reg = hw->fc.pause_time * 0x00010001;
2534 	for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2535 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2536 
2537 	/* Configure flow control refresh threshold value */
2538 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2539 
2540 out:
2541 	return ret_val;
2542 }
2543 
2544 /**
2545  *  ixgbe_negotiate_fc - Negotiate flow control
2546  *  @hw: pointer to hardware structure
2547  *  @adv_reg: flow control advertised settings
2548  *  @lp_reg: link partner's flow control settings
2549  *  @adv_sym: symmetric pause bit in advertisement
2550  *  @adv_asm: asymmetric pause bit in advertisement
2551  *  @lp_sym: symmetric pause bit in link partner advertisement
2552  *  @lp_asm: asymmetric pause bit in link partner advertisement
2553  *
2554  *  Find the intersection between advertised settings and link partner's
2555  *  advertised settings
2556  **/
ixgbe_negotiate_fc(struct ixgbe_hw * hw,u32 adv_reg,u32 lp_reg,u32 adv_sym,u32 adv_asm,u32 lp_sym,u32 lp_asm)2557 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2558 			      u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2559 {
2560 	if ((!(adv_reg)) ||  (!(lp_reg)))
2561 		return IXGBE_ERR_FC_NOT_NEGOTIATED;
2562 
2563 	if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2564 		/*
2565 		 * Now we need to check if the user selected Rx ONLY
2566 		 * of pause frames.  In this case, we had to advertise
2567 		 * FULL flow control because we could not advertise RX
2568 		 * ONLY. Hence, we must now check to see if we need to
2569 		 * turn OFF the TRANSMISSION of PAUSE frames.
2570 		 */
2571 		if (hw->fc.requested_mode == ixgbe_fc_full) {
2572 			hw->fc.current_mode = ixgbe_fc_full;
2573 			DEBUGOUT("Flow Control = FULL.\n");
2574 		} else {
2575 			hw->fc.current_mode = ixgbe_fc_rx_pause;
2576 			DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2577 		}
2578 	} else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2579 		   (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2580 		hw->fc.current_mode = ixgbe_fc_tx_pause;
2581 		DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2582 	} else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2583 		   !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2584 		hw->fc.current_mode = ixgbe_fc_rx_pause;
2585 		DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2586 	} else {
2587 		hw->fc.current_mode = ixgbe_fc_none;
2588 		DEBUGOUT("Flow Control = NONE.\n");
2589 	}
2590 	return IXGBE_SUCCESS;
2591 }
2592 
2593 /**
2594  *  ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2595  *  @hw: pointer to hardware structure
2596  *
2597  *  Enable flow control according on 1 gig fiber.
2598  **/
ixgbe_fc_autoneg_fiber(struct ixgbe_hw * hw)2599 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2600 {
2601 	u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2602 	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2603 
2604 	/*
2605 	 * On multispeed fiber at 1g, bail out if
2606 	 * - link is up but AN did not complete, or if
2607 	 * - link is up and AN completed but timed out
2608 	 */
2609 
2610 	linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2611 	if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2612 	    (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2613 		goto out;
2614 
2615 	pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2616 	pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2617 
2618 	ret_val =  ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2619 				      pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2620 				      IXGBE_PCS1GANA_ASM_PAUSE,
2621 				      IXGBE_PCS1GANA_SYM_PAUSE,
2622 				      IXGBE_PCS1GANA_ASM_PAUSE);
2623 
2624 out:
2625 	return ret_val;
2626 }
2627 
2628 /**
2629  *  ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2630  *  @hw: pointer to hardware structure
2631  *
2632  *  Enable flow control according to IEEE clause 37.
2633  **/
ixgbe_fc_autoneg_backplane(struct ixgbe_hw * hw)2634 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2635 {
2636 	u32 links2, anlp1_reg, autoc_reg, links;
2637 	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2638 
2639 	/*
2640 	 * On backplane, bail out if
2641 	 * - backplane autoneg was not completed, or if
2642 	 * - we are 82599 and link partner is not AN enabled
2643 	 */
2644 	links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2645 	if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2646 		goto out;
2647 
2648 	if (hw->mac.type == ixgbe_mac_82599EB) {
2649 		links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2650 		if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2651 			goto out;
2652 	}
2653 	/*
2654 	 * Read the 10g AN autoc and LP ability registers and resolve
2655 	 * local flow control settings accordingly
2656 	 */
2657 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2658 	anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2659 
2660 	ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2661 		anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2662 		IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2663 
2664 out:
2665 	return ret_val;
2666 }
2667 
2668 /**
2669  *  ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2670  *  @hw: pointer to hardware structure
2671  *
2672  *  Enable flow control according to IEEE clause 37.
2673  **/
ixgbe_fc_autoneg_copper(struct ixgbe_hw * hw)2674 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2675 {
2676 	u16 technology_ability_reg = 0;
2677 	u16 lp_technology_ability_reg = 0;
2678 
2679 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2680 			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2681 			     &technology_ability_reg);
2682 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2683 			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2684 			     &lp_technology_ability_reg);
2685 
2686 	return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2687 				  (u32)lp_technology_ability_reg,
2688 				  IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2689 				  IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2690 }
2691 
2692 /**
2693  *  ixgbe_fc_autoneg - Configure flow control
2694  *  @hw: pointer to hardware structure
2695  *
2696  *  Compares our advertised flow control capabilities to those advertised by
2697  *  our link partner, and determines the proper flow control mode to use.
2698  **/
ixgbe_fc_autoneg(struct ixgbe_hw * hw)2699 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2700 {
2701 	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2702 	ixgbe_link_speed speed;
2703 	bool link_up;
2704 
2705 	DEBUGFUNC("ixgbe_fc_autoneg");
2706 
2707 	/*
2708 	 * AN should have completed when the cable was plugged in.
2709 	 * Look for reasons to bail out.  Bail out if:
2710 	 * - FC autoneg is disabled, or if
2711 	 * - link is not up.
2712 	 */
2713 	if (hw->fc.disable_fc_autoneg)
2714 		goto out;
2715 
2716 	hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2717 	if (!link_up)
2718 		goto out;
2719 
2720 	switch (hw->phy.media_type) {
2721 	/* Autoneg flow control on fiber adapters */
2722 	case ixgbe_media_type_fiber:
2723 		if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2724 			ret_val = ixgbe_fc_autoneg_fiber(hw);
2725 		break;
2726 
2727 	/* Autoneg flow control on backplane adapters */
2728 	case ixgbe_media_type_backplane:
2729 		ret_val = ixgbe_fc_autoneg_backplane(hw);
2730 		break;
2731 
2732 	/* Autoneg flow control on copper adapters */
2733 	case ixgbe_media_type_copper:
2734 		if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
2735 			ret_val = ixgbe_fc_autoneg_copper(hw);
2736 		break;
2737 
2738 	default:
2739 		break;
2740 	}
2741 
2742 out:
2743 	if (ret_val == IXGBE_SUCCESS) {
2744 		hw->fc.fc_was_autonegged = TRUE;
2745 	} else {
2746 		hw->fc.fc_was_autonegged = FALSE;
2747 		hw->fc.current_mode = hw->fc.requested_mode;
2748 	}
2749 }
2750 
2751 /**
2752  *  ixgbe_disable_pcie_master - Disable PCI-express master access
2753  *  @hw: pointer to hardware structure
2754  *
2755  *  Disables PCI-Express master access and verifies there are no pending
2756  *  requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2757  *  bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
2758  *  is returned signifying master requests disabled.
2759  **/
ixgbe_disable_pcie_master(struct ixgbe_hw * hw)2760 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2761 {
2762 	s32 status = IXGBE_SUCCESS;
2763 	u32 i;
2764 
2765 	DEBUGFUNC("ixgbe_disable_pcie_master");
2766 
2767 	/* Always set this bit to ensure any future transactions are blocked */
2768 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2769 
2770 	/* Exit if master requets are blocked */
2771 	if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2772 		goto out;
2773 
2774 	/* Poll for master request bit to clear */
2775 	for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2776 		usec_delay(100);
2777 		if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2778 			goto out;
2779 	}
2780 
2781 	/*
2782 	 * Two consecutive resets are required via CTRL.RST per datasheet
2783 	 * 5.2.5.3.2 Master Disable.  We set a flag to inform the reset routine
2784 	 * of this need.  The first reset prevents new master requests from
2785 	 * being issued by our device.  We then must wait 1usec or more for any
2786 	 * remaining completions from the PCIe bus to trickle in, and then reset
2787 	 * again to clear out any effects they may have had on our device.
2788 	 */
2789 	DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
2790 	hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2791 
2792 	/*
2793 	 * Before proceeding, make sure that the PCIe block does not have
2794 	 * transactions pending.
2795 	 */
2796 	for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2797 		usec_delay(100);
2798 		if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2799 		    IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2800 			goto out;
2801 	}
2802 
2803 	DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
2804 	status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2805 
2806 out:
2807 	return status;
2808 }
2809 
2810 /**
2811  *  ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2812  *  @hw: pointer to hardware structure
2813  *  @mask: Mask to specify which semaphore to acquire
2814  *
2815  *  Acquires the SWFW semaphore through the GSSR register for the specified
2816  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
2817  **/
ixgbe_acquire_swfw_sync(struct ixgbe_hw * hw,u16 mask)2818 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2819 {
2820 	u32 gssr;
2821 	u32 swmask = mask;
2822 	u32 fwmask = mask << 5;
2823 	s32 timeout = 200;
2824 
2825 	DEBUGFUNC("ixgbe_acquire_swfw_sync");
2826 
2827 	while (timeout) {
2828 		/*
2829 		 * SW EEPROM semaphore bit is used for access to all
2830 		 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2831 		 */
2832 		if (ixgbe_get_eeprom_semaphore(hw))
2833 			return IXGBE_ERR_SWFW_SYNC;
2834 
2835 		gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2836 		if (!(gssr & (fwmask | swmask)))
2837 			break;
2838 
2839 		/*
2840 		 * Firmware currently using resource (fwmask) or other software
2841 		 * thread currently using resource (swmask)
2842 		 */
2843 		ixgbe_release_eeprom_semaphore(hw);
2844 		msec_delay(5);
2845 		timeout--;
2846 	}
2847 
2848 	if (!timeout) {
2849 		DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2850 		return IXGBE_ERR_SWFW_SYNC;
2851 	}
2852 
2853 	gssr |= swmask;
2854 	IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2855 
2856 	ixgbe_release_eeprom_semaphore(hw);
2857 	return IXGBE_SUCCESS;
2858 }
2859 
2860 /**
2861  *  ixgbe_release_swfw_sync - Release SWFW semaphore
2862  *  @hw: pointer to hardware structure
2863  *  @mask: Mask to specify which semaphore to release
2864  *
2865  *  Releases the SWFW semaphore through the GSSR register for the specified
2866  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
2867  **/
ixgbe_release_swfw_sync(struct ixgbe_hw * hw,u16 mask)2868 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2869 {
2870 	u32 gssr;
2871 	u32 swmask = mask;
2872 
2873 	DEBUGFUNC("ixgbe_release_swfw_sync");
2874 
2875 	(void) ixgbe_get_eeprom_semaphore(hw);
2876 
2877 	gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2878 	gssr &= ~swmask;
2879 	IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2880 
2881 	ixgbe_release_eeprom_semaphore(hw);
2882 }
2883 
2884 /**
2885  *  ixgbe_disable_sec_rx_path_generic - Stops the receive data path
2886  *  @hw: pointer to hardware structure
2887  *
2888  *  Stops the receive data path and waits for the HW to internally empty
2889  *  the Rx security block
2890  **/
ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw * hw)2891 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
2892 {
2893 #define IXGBE_MAX_SECRX_POLL 40
2894 
2895 	int i;
2896 	int secrxreg;
2897 
2898 	DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
2899 
2900 
2901 	secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2902 	secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2903 	IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2904 	for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2905 		secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2906 		if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2907 			break;
2908 		else
2909 			/* Use interrupt-safe sleep just in case */
2910 			usec_delay(1000);
2911 	}
2912 
2913 	/* For informational purposes only */
2914 	if (i >= IXGBE_MAX_SECRX_POLL)
2915 		DEBUGOUT("Rx unit being enabled before security "
2916 			 "path fully disabled.  Continuing with init.\n");
2917 
2918 	return IXGBE_SUCCESS;
2919 }
2920 
2921 /**
2922  *  ixgbe_enable_sec_rx_path_generic - Enables the receive data path
2923  *  @hw: pointer to hardware structure
2924  *
2925  *  Enables the receive data path.
2926  **/
ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw * hw)2927 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
2928 {
2929 	int secrxreg;
2930 
2931 	DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
2932 
2933 	secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2934 	secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2935 	IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2936 	IXGBE_WRITE_FLUSH(hw);
2937 
2938 	return IXGBE_SUCCESS;
2939 }
2940 
2941 /**
2942  *  ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2943  *  @hw: pointer to hardware structure
2944  *  @regval: register value to write to RXCTRL
2945  *
2946  *  Enables the Rx DMA unit
2947  **/
ixgbe_enable_rx_dma_generic(struct ixgbe_hw * hw,u32 regval)2948 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2949 {
2950 	DEBUGFUNC("ixgbe_enable_rx_dma_generic");
2951 
2952 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2953 
2954 	return IXGBE_SUCCESS;
2955 }
2956 
2957 /**
2958  *  ixgbe_blink_led_start_generic - Blink LED based on index.
2959  *  @hw: pointer to hardware structure
2960  *  @index: led number to blink
2961  **/
ixgbe_blink_led_start_generic(struct ixgbe_hw * hw,u32 index)2962 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2963 {
2964 	ixgbe_link_speed speed = 0;
2965 	bool link_up = 0;
2966 	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2967 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2968 
2969 	DEBUGFUNC("ixgbe_blink_led_start_generic");
2970 
2971 	/*
2972 	 * Link must be up to auto-blink the LEDs;
2973 	 * Force it if link is down.
2974 	 */
2975 	hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2976 
2977 	if (!link_up) {
2978 		autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2979 		autoc_reg |= IXGBE_AUTOC_FLU;
2980 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2981 		IXGBE_WRITE_FLUSH(hw);
2982 		msec_delay(10);
2983 	}
2984 
2985 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
2986 	led_reg |= IXGBE_LED_BLINK(index);
2987 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2988 	IXGBE_WRITE_FLUSH(hw);
2989 
2990 	return IXGBE_SUCCESS;
2991 }
2992 
2993 /**
2994  *  ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2995  *  @hw: pointer to hardware structure
2996  *  @index: led number to stop blinking
2997  **/
ixgbe_blink_led_stop_generic(struct ixgbe_hw * hw,u32 index)2998 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2999 {
3000 	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3001 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3002 
3003 	DEBUGFUNC("ixgbe_blink_led_stop_generic");
3004 
3005 
3006 	autoc_reg &= ~IXGBE_AUTOC_FLU;
3007 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3008 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3009 
3010 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
3011 	led_reg &= ~IXGBE_LED_BLINK(index);
3012 	led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3013 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3014 	IXGBE_WRITE_FLUSH(hw);
3015 
3016 	return IXGBE_SUCCESS;
3017 }
3018 
3019 /**
3020  *  ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3021  *  @hw: pointer to hardware structure
3022  *  @san_mac_offset: SAN MAC address offset
3023  *
3024  *  This function will read the EEPROM location for the SAN MAC address
3025  *  pointer, and returns the value at that location.  This is used in both
3026  *  get and set mac_addr routines.
3027  **/
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw * hw,u16 * san_mac_offset)3028 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3029 					 u16 *san_mac_offset)
3030 {
3031 	DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3032 
3033 	/*
3034 	 * First read the EEPROM pointer to see if the MAC addresses are
3035 	 * available.
3036 	 */
3037 	hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
3038 
3039 	return IXGBE_SUCCESS;
3040 }
3041 
3042 /**
3043  *  ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3044  *  @hw: pointer to hardware structure
3045  *  @san_mac_addr: SAN MAC address
3046  *
3047  *  Reads the SAN MAC address from the EEPROM, if it's available.  This is
3048  *  per-port, so set_lan_id() must be called before reading the addresses.
3049  *  set_lan_id() is called by identify_sfp(), but this cannot be relied
3050  *  upon for non-SFP connections, so we must call it here.
3051  **/
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw * hw,u8 * san_mac_addr)3052 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3053 {
3054 	u16 san_mac_data, san_mac_offset;
3055 	u8 i;
3056 
3057 	DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3058 
3059 	/*
3060 	 * First read the EEPROM pointer to see if the MAC addresses are
3061 	 * available.  If they're not, no point in calling set_lan_id() here.
3062 	 */
3063 	(void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3064 
3065 	if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3066 		/*
3067 		 * No addresses available in this EEPROM.  It's not an
3068 		 * error though, so just wipe the local address and return.
3069 		 */
3070 		for (i = 0; i < 6; i++)
3071 			san_mac_addr[i] = 0xFF;
3072 
3073 		goto san_mac_addr_out;
3074 	}
3075 
3076 	/* make sure we know which port we need to program */
3077 	hw->mac.ops.set_lan_id(hw);
3078 	/* apply the port offset to the address offset */
3079 	(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3080 			 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3081 	for (i = 0; i < 3; i++) {
3082 		hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
3083 		san_mac_addr[i * 2] = (u8)(san_mac_data);
3084 		san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3085 		san_mac_offset++;
3086 	}
3087 
3088 san_mac_addr_out:
3089 	return IXGBE_SUCCESS;
3090 }
3091 
3092 /**
3093  *  ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3094  *  @hw: pointer to hardware structure
3095  *  @san_mac_addr: SAN MAC address
3096  *
3097  *  Write a SAN MAC address to the EEPROM.
3098  **/
ixgbe_set_san_mac_addr_generic(struct ixgbe_hw * hw,u8 * san_mac_addr)3099 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3100 {
3101 	s32 status = IXGBE_SUCCESS;
3102 	u16 san_mac_data, san_mac_offset;
3103 	u8 i;
3104 
3105 	DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3106 
3107 	/* Look for SAN mac address pointer.  If not defined, return */
3108 	(void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3109 
3110 	if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3111 		status = IXGBE_ERR_NO_SAN_ADDR_PTR;
3112 		goto san_mac_addr_out;
3113 	}
3114 
3115 	/* Make sure we know which port we need to write */
3116 	hw->mac.ops.set_lan_id(hw);
3117 	/* Apply the port offset to the address offset */
3118 	(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3119 			 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3120 
3121 	for (i = 0; i < 3; i++) {
3122 		san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3123 		san_mac_data |= (u16)(san_mac_addr[i * 2]);
3124 		hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3125 		san_mac_offset++;
3126 	}
3127 
3128 san_mac_addr_out:
3129 	return status;
3130 }
3131 
3132 /**
3133  *  ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3134  *  @hw: pointer to hardware structure
3135  *
3136  *  Read PCIe configuration space, and get the MSI-X vector count from
3137  *  the capabilities table.
3138  **/
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw * hw)3139 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3140 {
3141 	u16 msix_count = 1;
3142 	u16 max_msix_count;
3143 	u16 pcie_offset;
3144 
3145 	switch (hw->mac.type) {
3146 	case ixgbe_mac_82598EB:
3147 		pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3148 		max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3149 		break;
3150 	case ixgbe_mac_82599EB:
3151 	case ixgbe_mac_X540:
3152 		pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3153 		max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3154 		break;
3155 	default:
3156 		return msix_count;
3157 	}
3158 
3159 	DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3160 	msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3161 	msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3162 
3163 	/* MSI-X count is zero-based in HW */
3164 	msix_count++;
3165 
3166 	if (msix_count > max_msix_count)
3167 		msix_count = max_msix_count;
3168 
3169 	return msix_count;
3170 }
3171 
3172 /**
3173  *  ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3174  *  @hw: pointer to hardware structure
3175  *  @addr: Address to put into receive address register
3176  *  @vmdq: VMDq pool to assign
3177  *
3178  *  Puts an ethernet address into a receive address register, or
3179  *  finds the rar that it is aleady in; adds to the pool list
3180  **/
ixgbe_insert_mac_addr_generic(struct ixgbe_hw * hw,u8 * addr,u32 vmdq)3181 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3182 {
3183 	static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3184 	u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3185 	u32 rar;
3186 	u32 rar_low, rar_high;
3187 	u32 addr_low, addr_high;
3188 
3189 	DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3190 
3191 	/* swap bytes for HW little endian */
3192 	addr_low  = addr[0] | (addr[1] << 8)
3193 			    | (addr[2] << 16)
3194 			    | (addr[3] << 24);
3195 	addr_high = addr[4] | (addr[5] << 8);
3196 
3197 	/*
3198 	 * Either find the mac_id in rar or find the first empty space.
3199 	 * rar_highwater points to just after the highest currently used
3200 	 * rar in order to shorten the search.  It grows when we add a new
3201 	 * rar to the top.
3202 	 */
3203 	for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3204 		rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3205 
3206 		if (((IXGBE_RAH_AV & rar_high) == 0)
3207 		    && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3208 			first_empty_rar = rar;
3209 		} else if ((rar_high & 0xFFFF) == addr_high) {
3210 			rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3211 			if (rar_low == addr_low)
3212 				break;    /* found it already in the rars */
3213 		}
3214 	}
3215 
3216 	if (rar < hw->mac.rar_highwater) {
3217 		/* already there so just add to the pool bits */
3218 		(void) ixgbe_set_vmdq(hw, rar, vmdq);
3219 	} else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3220 		/* stick it into first empty RAR slot we found */
3221 		rar = first_empty_rar;
3222 		(void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3223 	} else if (rar == hw->mac.rar_highwater) {
3224 		/* add it to the top of the list and inc the highwater mark */
3225 		(void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3226 		hw->mac.rar_highwater++;
3227 	} else if (rar >= hw->mac.num_rar_entries) {
3228 		return IXGBE_ERR_INVALID_MAC_ADDR;
3229 	}
3230 
3231 	/*
3232 	 * If we found rar[0], make sure the default pool bit (we use pool 0)
3233 	 * remains cleared to be sure default pool packets will get delivered
3234 	 */
3235 	if (rar == 0)
3236 		(void) ixgbe_clear_vmdq(hw, rar, 0);
3237 
3238 	return rar;
3239 }
3240 
3241 /**
3242  *  ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3243  *  @hw: pointer to hardware struct
3244  *  @rar: receive address register index to disassociate
3245  *  @vmdq: VMDq pool index to remove from the rar
3246  **/
ixgbe_clear_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)3247 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3248 {
3249 	u32 mpsar_lo, mpsar_hi;
3250 	u32 rar_entries = hw->mac.num_rar_entries;
3251 
3252 	DEBUGFUNC("ixgbe_clear_vmdq_generic");
3253 
3254 	/* Make sure we are using a valid rar index range */
3255 	if (rar >= rar_entries) {
3256 		DEBUGOUT1("RAR index %d is out of range.\n", rar);
3257 		return IXGBE_ERR_INVALID_ARGUMENT;
3258 	}
3259 
3260 	mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3261 	mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3262 
3263 	if (!mpsar_lo && !mpsar_hi)
3264 		goto done;
3265 
3266 	if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3267 		if (mpsar_lo) {
3268 			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3269 			mpsar_lo = 0;
3270 		}
3271 		if (mpsar_hi) {
3272 			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3273 			mpsar_hi = 0;
3274 		}
3275 	} else if (vmdq < 32) {
3276 		mpsar_lo &= ~(1 << vmdq);
3277 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3278 	} else {
3279 		mpsar_hi &= ~(1 << (vmdq - 32));
3280 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3281 	}
3282 
3283 	/* was that the last pool using this rar? */
3284 	if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3285 		hw->mac.ops.clear_rar(hw, rar);
3286 done:
3287 	return IXGBE_SUCCESS;
3288 }
3289 
3290 /**
3291  *  ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3292  *  @hw: pointer to hardware struct
3293  *  @rar: receive address register index to associate with a VMDq index
3294  *  @vmdq: VMDq pool index
3295  **/
ixgbe_set_vmdq_generic(struct ixgbe_hw * hw,u32 rar,u32 vmdq)3296 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3297 {
3298 	u32 mpsar;
3299 	u32 rar_entries = hw->mac.num_rar_entries;
3300 
3301 	DEBUGFUNC("ixgbe_set_vmdq_generic");
3302 
3303 	/* Make sure we are using a valid rar index range */
3304 	if (rar >= rar_entries) {
3305 		DEBUGOUT1("RAR index %d is out of range.\n", rar);
3306 		return IXGBE_ERR_INVALID_ARGUMENT;
3307 	}
3308 
3309 	if (vmdq < 32) {
3310 		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3311 		mpsar |= 1 << vmdq;
3312 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3313 	} else {
3314 		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3315 		mpsar |= 1 << (vmdq - 32);
3316 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3317 	}
3318 	return IXGBE_SUCCESS;
3319 }
3320 
3321 /**
3322  *  This function should only be involved in the IOV mode.
3323  *  In IOV mode, Default pool is next pool after the number of
3324  *  VFs advertized and not 0.
3325  *  MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3326  *
3327  *  ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3328  *  @hw: pointer to hardware struct
3329  *  @vmdq: VMDq pool index
3330  **/
ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw * hw,u32 vmdq)3331 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3332 {
3333 	u32 rar = hw->mac.san_mac_rar_index;
3334 
3335 	DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3336 
3337 	if (vmdq < 32) {
3338 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3339 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3340 	} else {
3341 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3342 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3343 	}
3344 
3345 	return IXGBE_SUCCESS;
3346 }
3347 
3348 /**
3349  *  ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3350  *  @hw: pointer to hardware structure
3351  **/
ixgbe_init_uta_tables_generic(struct ixgbe_hw * hw)3352 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3353 {
3354 	int i;
3355 
3356 	DEBUGFUNC("ixgbe_init_uta_tables_generic");
3357 	DEBUGOUT(" Clearing UTA\n");
3358 
3359 	for (i = 0; i < 128; i++)
3360 		IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3361 
3362 	return IXGBE_SUCCESS;
3363 }
3364 
3365 /**
3366  *  ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3367  *  @hw: pointer to hardware structure
3368  *  @vlan: VLAN id to write to VLAN filter
3369  *
3370  *  return the VLVF index where this VLAN id should be placed
3371  *
3372  **/
ixgbe_find_vlvf_slot(struct ixgbe_hw * hw,u32 vlan)3373 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3374 {
3375 	u32 bits = 0;
3376 	u32 first_empty_slot = 0;
3377 	s32 regindex;
3378 
3379 	/* short cut the special case */
3380 	if (vlan == 0)
3381 		return 0;
3382 
3383 	/*
3384 	  * Search for the vlan id in the VLVF entries. Save off the first empty
3385 	  * slot found along the way
3386 	  */
3387 	for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3388 		bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3389 		if (!bits && !(first_empty_slot))
3390 			first_empty_slot = regindex;
3391 		else if ((bits & 0x0FFF) == vlan)
3392 			break;
3393 	}
3394 
3395 	/*
3396 	  * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3397 	  * in the VLVF. Else use the first empty VLVF register for this
3398 	  * vlan id.
3399 	  */
3400 	if (regindex >= IXGBE_VLVF_ENTRIES) {
3401 		if (first_empty_slot)
3402 			regindex = first_empty_slot;
3403 		else {
3404 			DEBUGOUT("No space in VLVF.\n");
3405 			regindex = IXGBE_ERR_NO_SPACE;
3406 		}
3407 	}
3408 
3409 	return regindex;
3410 }
3411 
3412 /**
3413  *  ixgbe_set_vfta_generic - Set VLAN filter table
3414  *  @hw: pointer to hardware structure
3415  *  @vlan: VLAN id to write to VLAN filter
3416  *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
3417  *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
3418  *
3419  *  Turn on/off specified VLAN in the VLAN filter table.
3420  **/
ixgbe_set_vfta_generic(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on)3421 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3422 			   bool vlan_on)
3423 {
3424 	s32 regindex;
3425 	u32 bitindex;
3426 	u32 vfta;
3427 	u32 targetbit;
3428 	s32 ret_val = IXGBE_SUCCESS;
3429 	bool vfta_changed = FALSE;
3430 
3431 	DEBUGFUNC("ixgbe_set_vfta_generic");
3432 
3433 	if (vlan > 4095)
3434 		return IXGBE_ERR_PARAM;
3435 
3436 	/*
3437 	 * this is a 2 part operation - first the VFTA, then the
3438 	 * VLVF and VLVFB if VT Mode is set
3439 	 * We don't write the VFTA until we know the VLVF part succeeded.
3440 	 */
3441 
3442 	/* Part 1
3443 	 * The VFTA is a bitstring made up of 128 32-bit registers
3444 	 * that enable the particular VLAN id, much like the MTA:
3445 	 *    bits[11-5]: which register
3446 	 *    bits[4-0]:  which bit in the register
3447 	 */
3448 	regindex = (vlan >> 5) & 0x7F;
3449 	bitindex = vlan & 0x1F;
3450 	targetbit = (1 << bitindex);
3451 	vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3452 
3453 	if (vlan_on) {
3454 		if (!(vfta & targetbit)) {
3455 			vfta |= targetbit;
3456 			vfta_changed = TRUE;
3457 		}
3458 	} else {
3459 		if ((vfta & targetbit)) {
3460 			vfta &= ~targetbit;
3461 			vfta_changed = TRUE;
3462 		}
3463 	}
3464 
3465 	/* Part 2
3466 	 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3467 	 */
3468 	ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3469 					 &vfta_changed);
3470 	if (ret_val != IXGBE_SUCCESS)
3471 		return ret_val;
3472 
3473 	if (vfta_changed)
3474 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3475 
3476 	return IXGBE_SUCCESS;
3477 }
3478 
3479 /**
3480  *  ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3481  *  @hw: pointer to hardware structure
3482  *  @vlan: VLAN id to write to VLAN filter
3483  *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
3484  *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
3485  *  @vfta_changed: pointer to boolean flag which indicates whether VFTA
3486  *                 should be changed
3487  *
3488  *  Turn on/off specified bit in VLVF table.
3489  **/
ixgbe_set_vlvf_generic(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,bool * vfta_changed)3490 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3491 			    bool vlan_on, bool *vfta_changed)
3492 {
3493 	u32 vt;
3494 
3495 	DEBUGFUNC("ixgbe_set_vlvf_generic");
3496 
3497 	if (vlan > 4095)
3498 		return IXGBE_ERR_PARAM;
3499 
3500 	/* If VT Mode is set
3501 	 *   Either vlan_on
3502 	 *     make sure the vlan is in VLVF
3503 	 *     set the vind bit in the matching VLVFB
3504 	 *   Or !vlan_on
3505 	 *     clear the pool bit and possibly the vind
3506 	 */
3507 	vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3508 	if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3509 		s32 vlvf_index;
3510 		u32 bits;
3511 
3512 		vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3513 		if (vlvf_index < 0)
3514 			return vlvf_index;
3515 
3516 		if (vlan_on) {
3517 			/* set the pool bit */
3518 			if (vind < 32) {
3519 				bits = IXGBE_READ_REG(hw,
3520 						IXGBE_VLVFB(vlvf_index * 2));
3521 				bits |= (1 << vind);
3522 				IXGBE_WRITE_REG(hw,
3523 						IXGBE_VLVFB(vlvf_index * 2),
3524 						bits);
3525 			} else {
3526 				bits = IXGBE_READ_REG(hw,
3527 					IXGBE_VLVFB((vlvf_index * 2) + 1));
3528 				bits |= (1 << (vind - 32));
3529 				IXGBE_WRITE_REG(hw,
3530 					IXGBE_VLVFB((vlvf_index * 2) + 1),
3531 					bits);
3532 			}
3533 		} else {
3534 			/* clear the pool bit */
3535 			if (vind < 32) {
3536 				bits = IXGBE_READ_REG(hw,
3537 						IXGBE_VLVFB(vlvf_index * 2));
3538 				bits &= ~(1 << vind);
3539 				IXGBE_WRITE_REG(hw,
3540 						IXGBE_VLVFB(vlvf_index * 2),
3541 						bits);
3542 				bits |= IXGBE_READ_REG(hw,
3543 					IXGBE_VLVFB((vlvf_index * 2) + 1));
3544 			} else {
3545 				bits = IXGBE_READ_REG(hw,
3546 					IXGBE_VLVFB((vlvf_index * 2) + 1));
3547 				bits &= ~(1 << (vind - 32));
3548 				IXGBE_WRITE_REG(hw,
3549 					IXGBE_VLVFB((vlvf_index * 2) + 1),
3550 					bits);
3551 				bits |= IXGBE_READ_REG(hw,
3552 						IXGBE_VLVFB(vlvf_index * 2));
3553 			}
3554 		}
3555 
3556 		/*
3557 		 * If there are still bits set in the VLVFB registers
3558 		 * for the VLAN ID indicated we need to see if the
3559 		 * caller is requesting that we clear the VFTA entry bit.
3560 		 * If the caller has requested that we clear the VFTA
3561 		 * entry bit but there are still pools/VFs using this VLAN
3562 		 * ID entry then ignore the request.  We're not worried
3563 		 * about the case where we're turning the VFTA VLAN ID
3564 		 * entry bit on, only when requested to turn it off as
3565 		 * there may be multiple pools and/or VFs using the
3566 		 * VLAN ID entry.  In that case we cannot clear the
3567 		 * VFTA bit until all pools/VFs using that VLAN ID have also
3568 		 * been cleared.  This will be indicated by "bits" being
3569 		 * zero.
3570 		 */
3571 		if (bits) {
3572 			IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3573 					(IXGBE_VLVF_VIEN | vlan));
3574 			if ((!vlan_on) && (vfta_changed != NULL)) {
3575 				/* someone wants to clear the vfta entry
3576 				 * but some pools/VFs are still using it.
3577 				 * Ignore it. */
3578 				*vfta_changed = FALSE;
3579 			}
3580 		} else
3581 			IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3582 	}
3583 
3584 	return IXGBE_SUCCESS;
3585 }
3586 
3587 /**
3588  *  ixgbe_clear_vfta_generic - Clear VLAN filter table
3589  *  @hw: pointer to hardware structure
3590  *
3591  *  Clears the VLAN filer table, and the VMDq index associated with the filter
3592  **/
ixgbe_clear_vfta_generic(struct ixgbe_hw * hw)3593 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3594 {
3595 	u32 offset;
3596 
3597 	DEBUGFUNC("ixgbe_clear_vfta_generic");
3598 
3599 	for (offset = 0; offset < hw->mac.vft_size; offset++)
3600 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3601 
3602 	for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3603 		IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3604 		IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3605 		IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
3606 	}
3607 
3608 	return IXGBE_SUCCESS;
3609 }
3610 
3611 /**
3612  *  ixgbe_check_mac_link_generic - Determine link and speed status
3613  *  @hw: pointer to hardware structure
3614  *  @speed: pointer to link speed
3615  *  @link_up: TRUE when link is up
3616  *  @link_up_wait_to_complete: bool used to wait for link up or not
3617  *
3618  *  Reads the links register to determine if link is up and the current speed
3619  **/
ixgbe_check_mac_link_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up,bool link_up_wait_to_complete)3620 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3621 				 bool *link_up, bool link_up_wait_to_complete)
3622 {
3623 	u32 links_reg, links_orig;
3624 	u32 i;
3625 
3626 	DEBUGFUNC("ixgbe_check_mac_link_generic");
3627 
3628 	/* clear the old state */
3629 	links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3630 
3631 	links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3632 
3633 	if (links_orig != links_reg) {
3634 		DEBUGOUT2("LINKS changed from %08X to %08X\n",
3635 			  links_orig, links_reg);
3636 	}
3637 
3638 	if (link_up_wait_to_complete) {
3639 		for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3640 			if (links_reg & IXGBE_LINKS_UP) {
3641 				*link_up = TRUE;
3642 				break;
3643 			} else {
3644 				*link_up = FALSE;
3645 			}
3646 			msec_delay(100);
3647 			links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3648 		}
3649 	} else {
3650 		if (links_reg & IXGBE_LINKS_UP)
3651 			*link_up = TRUE;
3652 		else
3653 			*link_up = FALSE;
3654 	}
3655 
3656 	if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3657 	    IXGBE_LINKS_SPEED_10G_82599)
3658 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
3659 	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3660 		 IXGBE_LINKS_SPEED_1G_82599)
3661 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
3662 	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3663 		 IXGBE_LINKS_SPEED_100_82599)
3664 		*speed = IXGBE_LINK_SPEED_100_FULL;
3665 	else
3666 		*speed = IXGBE_LINK_SPEED_UNKNOWN;
3667 
3668 	return IXGBE_SUCCESS;
3669 }
3670 
3671 /**
3672  *  ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3673  *  the EEPROM
3674  *  @hw: pointer to hardware structure
3675  *  @wwnn_prefix: the alternative WWNN prefix
3676  *  @wwpn_prefix: the alternative WWPN prefix
3677  *
3678  *  This function will read the EEPROM from the alternative SAN MAC address
3679  *  block to check the support for the alternative WWNN/WWPN prefix support.
3680  **/
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw * hw,u16 * wwnn_prefix,u16 * wwpn_prefix)3681 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3682 				 u16 *wwpn_prefix)
3683 {
3684 	u16 offset, caps;
3685 	u16 alt_san_mac_blk_offset;
3686 
3687 	DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
3688 
3689 	/* clear output first */
3690 	*wwnn_prefix = 0xFFFF;
3691 	*wwpn_prefix = 0xFFFF;
3692 
3693 	/* check if alternative SAN MAC is supported */
3694 	hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3695 			    &alt_san_mac_blk_offset);
3696 
3697 	if ((alt_san_mac_blk_offset == 0) ||
3698 	    (alt_san_mac_blk_offset == 0xFFFF))
3699 		goto wwn_prefix_out;
3700 
3701 	/* check capability in alternative san mac address block */
3702 	offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3703 	hw->eeprom.ops.read(hw, offset, &caps);
3704 	if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3705 		goto wwn_prefix_out;
3706 
3707 	/* get the corresponding prefix for WWNN/WWPN */
3708 	offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3709 	hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3710 
3711 	offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3712 	hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3713 
3714 wwn_prefix_out:
3715 	return IXGBE_SUCCESS;
3716 }
3717 
3718 /**
3719  *  ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
3720  *  @hw: pointer to hardware structure
3721  *  @bs: the fcoe boot status
3722  *
3723  *  This function will read the FCOE boot status from the iSCSI FCOE block
3724  **/
ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw * hw,u16 * bs)3725 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
3726 {
3727 	u16 offset, caps, flags;
3728 	s32 status;
3729 
3730 	DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
3731 
3732 	/* clear output first */
3733 	*bs = ixgbe_fcoe_bootstatus_unavailable;
3734 
3735 	/* check if FCOE IBA block is present */
3736 	offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
3737 	status = hw->eeprom.ops.read(hw, offset, &caps);
3738 	if (status != IXGBE_SUCCESS)
3739 		goto out;
3740 
3741 	if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
3742 		goto out;
3743 
3744 	/* check if iSCSI FCOE block is populated */
3745 	status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
3746 	if (status != IXGBE_SUCCESS)
3747 		goto out;
3748 
3749 	if ((offset == 0) || (offset == 0xFFFF))
3750 		goto out;
3751 
3752 	/* read fcoe flags in iSCSI FCOE block */
3753 	offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
3754 	status = hw->eeprom.ops.read(hw, offset, &flags);
3755 	if (status != IXGBE_SUCCESS)
3756 		goto out;
3757 
3758 	if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
3759 		*bs = ixgbe_fcoe_bootstatus_enabled;
3760 	else
3761 		*bs = ixgbe_fcoe_bootstatus_disabled;
3762 
3763 out:
3764 	return status;
3765 }
3766 
3767 /**
3768  *  ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3769  *  @hw: pointer to hardware structure
3770  *  @enable: enable or disable switch for anti-spoofing
3771  *  @pf: Physical Function pool - do not enable anti-spoofing for the PF
3772  *
3773  **/
ixgbe_set_mac_anti_spoofing(struct ixgbe_hw * hw,bool enable,int pf)3774 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3775 {
3776 	int j;
3777 	int pf_target_reg = pf >> 3;
3778 	int pf_target_shift = pf % 8;
3779 	u32 pfvfspoof = 0;
3780 
3781 	if (hw->mac.type == ixgbe_mac_82598EB)
3782 		return;
3783 
3784 	if (enable)
3785 		pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3786 
3787 	/*
3788 	 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3789 	 * MAC anti-spoof enables in each register array element.
3790 	 */
3791 	for (j = 0; j < pf_target_reg; j++)
3792 		IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3793 
3794 	/*
3795 	 * The PF should be allowed to spoof so that it can support
3796 	 * emulation mode NICs.  Do not set the bits assigned to the PF
3797 	 */
3798 	pfvfspoof &= (1 << pf_target_shift) - 1;
3799 	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3800 
3801 	/*
3802 	 * Remaining pools belong to the PF so they do not need to have
3803 	 * anti-spoofing enabled.
3804 	 */
3805 	for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3806 		IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
3807 }
3808 
3809 /**
3810  *  ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3811  *  @hw: pointer to hardware structure
3812  *  @enable: enable or disable switch for VLAN anti-spoofing
3813  *  @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3814  *
3815  **/
ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw * hw,bool enable,int vf)3816 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3817 {
3818 	int vf_target_reg = vf >> 3;
3819 	int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3820 	u32 pfvfspoof;
3821 
3822 	if (hw->mac.type == ixgbe_mac_82598EB)
3823 		return;
3824 
3825 	pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3826 	if (enable)
3827 		pfvfspoof |= (1 << vf_target_shift);
3828 	else
3829 		pfvfspoof &= ~(1 << vf_target_shift);
3830 	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3831 }
3832 
3833 /**
3834  *  ixgbe_get_device_caps_generic - Get additional device capabilities
3835  *  @hw: pointer to hardware structure
3836  *  @device_caps: the EEPROM word with the extra device capabilities
3837  *
3838  *  This function will read the EEPROM location for the device capabilities,
3839  *  and return the word through device_caps.
3840  **/
ixgbe_get_device_caps_generic(struct ixgbe_hw * hw,u16 * device_caps)3841 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3842 {
3843 	DEBUGFUNC("ixgbe_get_device_caps_generic");
3844 
3845 	hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3846 
3847 	return IXGBE_SUCCESS;
3848 }
3849 
3850 /**
3851  *  ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
3852  *  @hw: pointer to hardware structure
3853  *
3854  **/
ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw * hw)3855 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
3856 {
3857 	u32 regval;
3858 	u32 i;
3859 
3860 	DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
3861 
3862 	/* Enable relaxed ordering */
3863 	for (i = 0; i < hw->mac.max_tx_queues; i++) {
3864 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
3865 		regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3866 		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
3867 	}
3868 
3869 	for (i = 0; i < hw->mac.max_rx_queues; i++) {
3870 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
3871 		regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
3872 			  IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
3873 		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
3874 	}
3875 
3876 }
3877 
3878 /**
3879  *  ixgbe_calculate_checksum - Calculate checksum for buffer
3880  *  @buffer: pointer to EEPROM
3881  *  @length: size of EEPROM to calculate a checksum for
3882  *  Calculates the checksum for some buffer on a specified length.  The
3883  *  checksum calculated is returned.
3884  **/
ixgbe_calculate_checksum(u8 * buffer,u32 length)3885 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3886 {
3887 	u32 i;
3888 	u8 sum = 0;
3889 
3890 	DEBUGFUNC("ixgbe_calculate_checksum");
3891 
3892 	if (!buffer)
3893 		return 0;
3894 
3895 	for (i = 0; i < length; i++)
3896 		sum += buffer[i];
3897 
3898 	return (u8) (0 - sum);
3899 }
3900 
3901 /**
3902  *  ixgbe_host_interface_command - Issue command to manageability block
3903  *  @hw: pointer to the HW structure
3904  *  @buffer: contains the command to write and where the return status will
3905  *   be placed
3906  *  @length: length of buffer, must be multiple of 4 bytes
3907  *
3908  *  Communicates with the manageability block.  On success return IXGBE_SUCCESS
3909  *  else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3910  **/
ixgbe_host_interface_command(struct ixgbe_hw * hw,u32 * buffer,u32 length)3911 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3912 					u32 length)
3913 {
3914 	u32 hicr, i, bi;
3915 	u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3916 	u8 buf_len, dword_len;
3917 
3918 	s32 ret_val = IXGBE_SUCCESS;
3919 
3920 	DEBUGFUNC("ixgbe_host_interface_command");
3921 
3922 	if (length == 0 || length & 0x3 ||
3923 	    length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3924 		DEBUGOUT("Buffer length failure.\n");
3925 		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3926 		goto out;
3927 	}
3928 
3929 	/* Check that the host interface is enabled. */
3930 	hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3931 	if ((hicr & IXGBE_HICR_EN) == 0) {
3932 		DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
3933 		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3934 		goto out;
3935 	}
3936 
3937 	/* Calculate length in DWORDs */
3938 	dword_len = length >> 2;
3939 
3940 	/*
3941 	 * The device driver writes the relevant command block
3942 	 * into the ram area.
3943 	 */
3944 	for (i = 0; i < dword_len; i++)
3945 		IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3946 				      i, IXGBE_CPU_TO_LE32(buffer[i]));
3947 
3948 	/* Setting this bit tells the ARC that a new command is pending. */
3949 	IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3950 
3951 	for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3952 		hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3953 		if (!(hicr & IXGBE_HICR_C))
3954 			break;
3955 		msec_delay(1);
3956 	}
3957 
3958 	/* Check command successful completion. */
3959 	if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3960 	    (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3961 		DEBUGOUT("Command has failed with no status valid.\n");
3962 		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3963 		goto out;
3964 	}
3965 
3966 	/* Calculate length in DWORDs */
3967 	dword_len = hdr_size >> 2;
3968 
3969 	/* first pull in the header so we know the buffer length */
3970 	for (bi = 0; bi < dword_len; bi++) {
3971 		buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3972 		buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]);
3973 	}
3974 
3975 	/* If there is any thing in data position pull it in */
3976 	buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3977 	if (buf_len == 0)
3978 		goto out;
3979 
3980 	if (length < (buf_len + hdr_size)) {
3981 		DEBUGOUT("Buffer not large enough for reply message.\n");
3982 		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3983 		goto out;
3984 	}
3985 
3986 	/* Calculate length in DWORDs, add 3 for odd lengths */
3987 	dword_len = (buf_len + 3) >> 2;
3988 
3989 	/* Pull in the rest of the buffer (bi is where we left off)*/
3990 	for (; bi <= dword_len; bi++) {
3991 		buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3992 		buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]);
3993 	}
3994 
3995 out:
3996 	return ret_val;
3997 }
3998 
3999 /**
4000  *  ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4001  *  @hw: pointer to the HW structure
4002  *  @maj: driver version major number
4003  *  @min: driver version minor number
4004  *  @build: driver version build number
4005  *  @sub: driver version sub build number
4006  *
4007  *  Sends driver version number to firmware through the manageability
4008  *  block.  On success return IXGBE_SUCCESS
4009  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4010  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4011  **/
ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw * hw,u8 maj,u8 min,u8 build,u8 sub)4012 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4013 				 u8 build, u8 sub)
4014 {
4015 	struct ixgbe_hic_drv_info fw_cmd;
4016 	int i;
4017 	s32 ret_val = IXGBE_SUCCESS;
4018 
4019 	DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4020 
4021 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4022 	    != IXGBE_SUCCESS) {
4023 		ret_val = IXGBE_ERR_SWFW_SYNC;
4024 		goto out;
4025 	}
4026 
4027 	fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4028 	fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4029 	fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4030 	fw_cmd.port_num = (u8)hw->bus.func;
4031 	fw_cmd.ver_maj = maj;
4032 	fw_cmd.ver_min = min;
4033 	fw_cmd.ver_build = build;
4034 	fw_cmd.ver_sub = sub;
4035 	fw_cmd.hdr.checksum = 0;
4036 	fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4037 				(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4038 	fw_cmd.pad = 0;
4039 	fw_cmd.pad2 = 0;
4040 
4041 	for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4042 		/* LINTED */
4043 		ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4044 						       sizeof(fw_cmd));
4045 		if (ret_val != IXGBE_SUCCESS)
4046 			continue;
4047 
4048 		if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4049 		    FW_CEM_RESP_STATUS_SUCCESS)
4050 			ret_val = IXGBE_SUCCESS;
4051 		else
4052 			ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4053 
4054 		break;
4055 	}
4056 
4057 	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4058 out:
4059 	return ret_val;
4060 }
4061 
4062 /**
4063  * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4064  * @hw: pointer to hardware structure
4065  * @num_pb: number of packet buffers to allocate
4066  * @headroom: reserve n KB of headroom
4067  * @strategy: packet buffer allocation strategy
4068  **/
ixgbe_set_rxpba_generic(struct ixgbe_hw * hw,int num_pb,u32 headroom,int strategy)4069 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4070 			     int strategy)
4071 {
4072 	u32 pbsize = hw->mac.rx_pb_size;
4073 	int i = 0;
4074 	u32 rxpktsize, txpktsize, txpbthresh;
4075 
4076 	/* Reserve headroom */
4077 	pbsize -= headroom;
4078 
4079 	if (!num_pb)
4080 		num_pb = 1;
4081 
4082 	/* Divide remaining packet buffer space amongst the number of packet
4083 	 * buffers requested using supplied strategy.
4084 	 */
4085 	switch (strategy) {
4086 	case PBA_STRATEGY_WEIGHTED:
4087 		/* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4088 		 * buffer with 5/8 of the packet buffer space.
4089 		 */
4090 		rxpktsize = (pbsize * 5) / (num_pb * 4);
4091 		pbsize -= rxpktsize * (num_pb / 2);
4092 		rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4093 		for (; i < (num_pb / 2); i++)
4094 			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4095 		/* Fall through to configure remaining packet buffers */
4096 		/* FALLTHRU */
4097 	case PBA_STRATEGY_EQUAL:
4098 		rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4099 		for (; i < num_pb; i++)
4100 			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4101 		break;
4102 	default:
4103 		break;
4104 	}
4105 
4106 	/* Only support an equally distributed Tx packet buffer strategy. */
4107 	txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4108 	txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4109 	for (i = 0; i < num_pb; i++) {
4110 		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4111 		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4112 	}
4113 
4114 	/* Clear unused TCs, if any, to zero buffer size*/
4115 	for (; i < IXGBE_MAX_PB; i++) {
4116 		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4117 		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4118 		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4119 	}
4120 }
4121 
4122 /**
4123  * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4124  * @hw: pointer to the hardware structure
4125  *
4126  * The 82599 and x540 MACs can experience issues if TX work is still pending
4127  * when a reset occurs.  This function prevents this by flushing the PCIe
4128  * buffers on the system.
4129  **/
ixgbe_clear_tx_pending(struct ixgbe_hw * hw)4130 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4131 {
4132 	u32 gcr_ext, hlreg0;
4133 
4134 	/*
4135 	 * If double reset is not requested then all transactions should
4136 	 * already be clear and as such there is no work to do
4137 	 */
4138 	if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4139 		return;
4140 
4141 	/*
4142 	 * Set loopback enable to prevent any transmits from being sent
4143 	 * should the link come up.  This assumes that the RXCTRL.RXEN bit
4144 	 * has already been cleared.
4145 	 */
4146 	hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4147 	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4148 
4149 	/* initiate cleaning flow for buffers in the PCIe transaction layer */
4150 	gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4151 	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4152 			gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4153 
4154 	/* Flush all writes and allow 20usec for all transactions to clear */
4155 	IXGBE_WRITE_FLUSH(hw);
4156 	usec_delay(20);
4157 
4158 	/* restore previous register values */
4159 	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4160 	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4161 }
4162 
4163