1 /*****************************************************************************
2
3 Copyright (c) 2001-2017, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 *****************************************************************************/
33
34 #include "opt_inet.h"
35 #include "opt_inet6.h"
36 #include "opt_rss.h"
37
38 #include "ixgbe.h"
39 #include "mdio_if.h"
40 #include "ixgbe_sriov.h"
41 #include "ifdi_if.h"
42 #include "if_ix_mdio_hw.h"
43 #include "if_ix_mdio.h"
44
45 #include <net/netmap.h>
46 #include <dev/mdio/mdio.h>
47 #include <dev/netmap/netmap_kern.h>
48
49 /************************************************************************
50 * Driver version
51 ************************************************************************/
52 static const char ixgbe_driver_version[] = "5.0.1-k";
53
54 /* Bound one admin-task invocation while still coalescing new requests. */
55 #define IXGBE_ADMIN_TASK_BUDGET 8
56
57 /************************************************************************
58 * PCI Device ID Table
59 *
60 * Used by probe to select devices to load on
61 * Last field stores an index into ixgbe_strings
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
65 ************************************************************************/
66 static const pci_vendor_info_t ixgbe_vendor_info_array[] =
67 {
68 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT,
69 "Intel(R) 82598EB AF (Dual Fiber)"),
70 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT,
71 "Intel(R) 82598EB AF (Fiber)"),
72 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4,
73 "Intel(R) 82598EB AT (CX4)"),
74 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT,
75 "Intel(R) 82598EB AT"),
76 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2,
77 "Intel(R) 82598EB AT2"),
78 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598, "Intel(R) 82598"),
79 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT,
80 "Intel(R) 82598EB AF DA (Dual Fiber)"),
81 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT,
82 "Intel(R) 82598EB AT (Dual CX4)"),
83 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR,
84 "Intel(R) 82598EB AF (Dual Fiber LR)"),
85 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM,
86 "Intel(R) 82598EB AF (Dual Fiber SR)"),
87 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM,
88 "Intel(R) 82598EB LOM"),
89 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX,
90 "Intel(R) 82598EB BX Backplane"),
91 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4,
92 "Intel(R) X520 82599 (KX4)"),
93 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ,
94 "Intel(R) X520 82599 (KX4 Mezzanine)"),
95 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP,
96 "Intel(R) X520 82599ES (SFI/SFP+)"),
97 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR,
98 "Intel(R) X520 82599ES (KR Backplane)"),
99 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM,
100 "Intel(R) X520-P2 82599 (SFP+)"),
101 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM,
102 "Intel(R) X520 82599 (XAUI/BX4)"),
103 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4,
104 "Intel(R) X520 82599 (Dual CX4)"),
105 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM,
106 "Intel(R) X520-T 82599 LOM"),
107 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS,
108 "Intel(R) X520 82599 LS"),
109 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE,
110 "Intel(R) X520 82599 (Combined Backplane)"),
111 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE,
112 "Intel(R) X520 82599 (Backplane w/FCoE)"),
113 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2,
114 "Intel(R) X520 82599 (Dual SFP+)"),
115 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE,
116 "Intel(R) X520 82599 (Dual SFP+ w/FCoE)"),
117 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP,
118 "Intel(R) X520-1 82599EN (SFP+)"),
119 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP,
120 "Intel(R) X520-4 82599 (Quad SFP+)"),
121 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP,
122 "Intel(R) X520-Q1 82599 (QSFP+)"),
123 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T,
124 "Intel(R) X540-AT2"),
125 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, "Intel(R) X540-T1"),
126 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T, "Intel(R) X550-T2"),
127 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1, "Intel(R) X550-T1"),
128 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR,
129 "Intel(R) X552 (KR Backplane)"),
130 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4,
131 "Intel(R) X552 (KX4 Backplane)"),
132 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T,
133 "Intel(R) X552/X557-AT (10GBASE-T)"),
134 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T,
135 "Intel(R) X552 (1000BASE-T)"),
136 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP,
137 "Intel(R) X552 (SFP+)"),
138 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI,
139 "Intel(R) X552 (XFI Backplane)"),
140 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR,
141 "Intel(R) X553 (KR Backplane)"),
142 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L,
143 "Intel(R) X553 L (KR Backplane)"),
144 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP,
145 "Intel(R) X553 (SFP+)"),
146 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N,
147 "Intel(R) X553 N (SFP+)"),
148 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP,
149 "Intel(R) X553 (QSFP+)"),
150 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N,
151 "Intel(R) X553 N (QSFP+)"),
152 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII,
153 "Intel(R) X553 (1GbE SGMII)"),
154 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L,
155 "Intel(R) X553 L (1GbE SGMII)"),
156 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T,
157 "Intel(R) X553/X557-AT (10GBASE-T)"),
158 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T,
159 "Intel(R) X553 (1GbE)"),
160 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L,
161 "Intel(R) X553 L (1GbE)"),
162 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_BYPASS,
163 "Intel(R) X540-T2 (Bypass)"),
164 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS,
165 "Intel(R) X520 82599 (Bypass)"),
166 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_BACKPLANE,
167 "Intel(R) E610 (Backplane)"),
168 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SFP,
169 "Intel(R) E610 (SFP)"),
170 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_2_5G_T,
171 "Intel(R) E610 (2.5 GbE)"),
172 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_10G_T,
173 "Intel(R) E610 (10 GbE)"),
174 PVID(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_E610_SGMII,
175 "Intel(R) E610 (SGMII)"),
176 /* required last entry */
177 PVID_END
178 };
179
180 static void *ixgbe_register(device_t);
181 static int ixgbe_if_attach_pre(if_ctx_t);
182 static int ixgbe_if_attach_post(if_ctx_t);
183 static int ixgbe_if_detach(if_ctx_t);
184 static int ixgbe_if_power_prepare(if_ctx_t, enum iflib_power_event);
185 static int ixgbe_if_shutdown(if_ctx_t);
186 static int ixgbe_if_suspend(if_ctx_t);
187 static int ixgbe_if_resume(if_ctx_t);
188 #ifdef PCI_IOV
189 static int ixgbe_device_iov_init(device_t, uint16_t, const nvlist_t *);
190 #endif
191
192 static void ixgbe_if_stop(if_ctx_t);
193 void ixgbe_if_enable_intr(if_ctx_t);
194 static void ixgbe_if_disable_intr(if_ctx_t);
195 static void ixgbe_link_intr_enable(if_ctx_t);
196 static int ixgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
197 static void ixgbe_if_media_status(if_ctx_t, struct ifmediareq *);
198 static int ixgbe_if_media_change(if_ctx_t);
199 static int ixgbe_if_msix_intr_assign(if_ctx_t, int);
200 static int ixgbe_if_mtu_set(if_ctx_t, uint32_t);
201 static void ixgbe_if_crcstrip_set(if_ctx_t, int, int);
202 static void ixgbe_if_multi_set(if_ctx_t);
203 static int ixgbe_if_promisc_set(if_ctx_t, int);
204 static int ixgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
205 int);
206 static int ixgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
207 int);
208 static void ixgbe_if_queues_free(if_ctx_t);
209 static void ixgbe_if_timer(if_ctx_t, uint16_t);
210 static const char *ixgbe_link_speed_to_str(u32 link_speed);
211 static void ixgbe_if_update_admin_status(if_ctx_t);
212 static void ixgbe_if_vlan_register(if_ctx_t, u16);
213 static void ixgbe_if_vlan_unregister(if_ctx_t, u16);
214 static int ixgbe_if_i2c_req(if_ctx_t, struct ifi2creq *);
215 static bool ixgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
216 static void ixgbe_if_led_func(if_ctx_t, int);
217 static void ixgbe_led_restore(struct ixgbe_softc *);
218 int ixgbe_intr(void *);
219
220 static int ixgbe_if_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data);
221
222 /************************************************************************
223 * Function prototypes
224 ************************************************************************/
225 static uint64_t ixgbe_if_get_counter(if_ctx_t, ift_counter);
226
227 static void ixgbe_enable_queue(struct ixgbe_softc *, u32);
228 static void ixgbe_disable_queue(struct ixgbe_softc *, u32);
229 static void ixgbe_add_device_sysctls(if_ctx_t);
230 static int ixgbe_allocate_pci_resources(if_ctx_t);
231 static int ixgbe_setup_low_power_mode(if_ctx_t);
232
233 static void ixgbe_config_dmac(struct ixgbe_softc *);
234 static void ixgbe_configure_ivars(struct ixgbe_softc *);
235 static void ixgbe_set_ivar(struct ixgbe_softc *, u8, u8, s8);
236 static u8 *ixgbe_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *);
237 static bool ixgbe_sfp_probe(if_ctx_t);
238
239 static void ixgbe_free_pci_resources(if_ctx_t);
240
241 static int ixgbe_msix_link(void *);
242 static int ixgbe_msix_que(void *);
243 static void ixgbe_initialize_rss_mapping(struct ixgbe_softc *);
244 static void ixgbe_initialize_receive_units(if_ctx_t);
245 static void ixgbe_initialize_transmit_units(if_ctx_t);
246
247 static int ixgbe_setup_interface(if_ctx_t);
248 static void ixgbe_init_device_features(struct ixgbe_softc *);
249 static void ixgbe_check_fan_failure(struct ixgbe_softc *, u32, bool);
250 static void ixgbe_sbuf_fw_version(struct ixgbe_hw *, struct sbuf *);
251 static void ixgbe_print_fw_version(if_ctx_t);
252 static void ixgbe_add_media_types(if_ctx_t);
253 static void ixgbe_update_stats_counters(struct ixgbe_softc *);
254 static void ixgbe_config_link(if_ctx_t);
255 static void ixgbe_get_slot_info(struct ixgbe_softc *);
256 static void ixgbe_fw_mode_timer(void *);
257 static void ixgbe_fw_mode_timer_pause(struct ixgbe_softc *);
258 static void ixgbe_fw_mode_timer_resume(struct ixgbe_softc *);
259 static void ixgbe_configure_wakeup(if_ctx_t);
260 static void ixgbe_configure_wakeup_mta(if_ctx_t);
261 static void ixgbe_prepare_wakeup(if_ctx_t, bool);
262 static void ixgbe_enable_rx_drop(struct ixgbe_softc *);
263 static void ixgbe_disable_rx_drop(struct ixgbe_softc *);
264
265 static void ixgbe_add_hw_stats(struct ixgbe_softc *);
266 static int ixgbe_set_flowcntl(struct ixgbe_softc *, int);
267 static int ixgbe_set_advertise(struct ixgbe_softc *, int);
268 static int ixgbe_get_default_advertise(struct ixgbe_softc *);
269 static void ixgbe_config_gpie(struct ixgbe_softc *);
270 static void ixgbe_config_delay_values(struct ixgbe_softc *);
271
272 static void ixgbe_add_debug_sysctls(struct ixgbe_softc *sc);
273 static void ixgbe_add_debug_dump_sysctls(struct ixgbe_softc *sc);
274 static int ixgbe_debug_dump_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd);
275 static u8 ixgbe_debug_dump_print_cluster(struct ixgbe_softc *sc,
276 struct sbuf *sbuf, u8 cluster_id);
277 static int ixgbe_nvm_access_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd);
278
279 /* Sysctl handlers */
280 static int ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS);
281 static int ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS);
282 static int ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS);
283 static int ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS);
284 static int ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS);
285 static int ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS);
286 static int ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS);
287 #ifdef IXGBE_DEBUG
288 static int ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS);
289 static int ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS);
290 #endif
291 static int ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS);
292 static int ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS);
293 static int ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS);
294 static int ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS);
295 static int ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS);
296 static int ixgbe_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS);
297
298 static int ixgbe_sysctl_debug_dump_set_clusters(SYSCTL_HANDLER_ARGS);
299 static int ixgbe_sysctl_dump_debug_dump(SYSCTL_HANDLER_ARGS);
300
301 /* Deferred interrupt tasklets */
302 static void ixgbe_handle_msf(void *);
303 static bool ixgbe_handle_mod(void *);
304 static void ixgbe_handle_phy(void *);
305 static u32 ixgbe_handle_fw_event(void *);
306
307 static int ixgbe_enable_lse(struct ixgbe_softc *sc);
308 static int ixgbe_disable_lse(struct ixgbe_softc *sc);
309
310 /************************************************************************
311 * FreeBSD Device Interface Entry Points
312 ************************************************************************/
313 static device_method_t ix_methods[] = {
314 /* Device interface */
315 DEVMETHOD(device_register, ixgbe_register),
316 DEVMETHOD(device_probe, iflib_device_probe),
317 DEVMETHOD(device_attach, iflib_device_attach),
318 DEVMETHOD(device_detach, iflib_device_detach),
319 DEVMETHOD(device_shutdown, iflib_device_shutdown),
320 DEVMETHOD(device_suspend, iflib_device_suspend),
321 DEVMETHOD(device_resume, iflib_device_resume),
322 #ifdef PCI_IOV
323 DEVMETHOD(pci_iov_init, ixgbe_device_iov_init),
324 DEVMETHOD(pci_iov_uninit, iflib_device_iov_uninit_restart),
325 DEVMETHOD(pci_iov_add_vf, iflib_device_iov_add_vf),
326 #endif /* PCI_IOV */
327 DEVMETHOD(bus_add_child, device_add_child_ordered),
328 DEVMETHOD(mdio_readreg, ixgbe_mdio_readreg_c22),
329 DEVMETHOD(mdio_writereg, ixgbe_mdio_writereg_c22),
330
331 DEVMETHOD_END
332 };
333
334 static driver_t ix_driver = {
335 "ix", ix_methods, sizeof(struct ixgbe_softc),
336 };
337
338 DRIVER_MODULE(mdio, ix, mdio_driver, 0, 0); /* needs to happen before ix */
339 DRIVER_MODULE_ORDERED(ix, pci, ix_driver, NULL, NULL, SI_ORDER_ANY); /* needs to be last */
340 IFLIB_PNP_INFO(pci, ix_driver, ixgbe_vendor_info_array);
341 MODULE_DEPEND(ix, pci, 1, 1, 1);
342 MODULE_DEPEND(ix, ether, 1, 1, 1);
343 MODULE_DEPEND(ix, iflib, 1, 1, 1);
344 MODULE_DEPEND(ix, mdio, 1, 1, 1);
345
346 #ifdef PCI_IOV
347 static int
ixgbe_device_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * params)348 ixgbe_device_iov_init(device_t dev, uint16_t num_vfs,
349 const nvlist_t *params)
350 {
351 struct ixgbe_softc *sc;
352 if_ctx_t ctx;
353 int error;
354
355 ctx = device_get_softc(dev);
356 sc = iflib_get_softc(ctx);
357 error = ixgbe_iov_validate(sc, num_vfs);
358 if (error != 0)
359 return (error);
360 return (iflib_device_iov_init_restart(dev, num_vfs, params));
361 }
362 #endif
363
364 static device_method_t ixgbe_if_methods[] = {
365 DEVMETHOD(ifdi_attach_pre, ixgbe_if_attach_pre),
366 DEVMETHOD(ifdi_attach_post, ixgbe_if_attach_post),
367 DEVMETHOD(ifdi_detach, ixgbe_if_detach),
368 DEVMETHOD(ifdi_power_prepare, ixgbe_if_power_prepare),
369 DEVMETHOD(ifdi_shutdown, ixgbe_if_shutdown),
370 DEVMETHOD(ifdi_suspend, ixgbe_if_suspend),
371 DEVMETHOD(ifdi_resume, ixgbe_if_resume),
372 DEVMETHOD(ifdi_init, ixgbe_if_init),
373 DEVMETHOD(ifdi_stop, ixgbe_if_stop),
374 DEVMETHOD(ifdi_msix_intr_assign, ixgbe_if_msix_intr_assign),
375 DEVMETHOD(ifdi_intr_enable, ixgbe_if_enable_intr),
376 DEVMETHOD(ifdi_intr_disable, ixgbe_if_disable_intr),
377 DEVMETHOD(ifdi_link_intr_enable, ixgbe_link_intr_enable),
378 DEVMETHOD(ifdi_tx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable),
379 DEVMETHOD(ifdi_rx_queue_intr_enable, ixgbe_if_rx_queue_intr_enable),
380 DEVMETHOD(ifdi_tx_queues_alloc, ixgbe_if_tx_queues_alloc),
381 DEVMETHOD(ifdi_rx_queues_alloc, ixgbe_if_rx_queues_alloc),
382 DEVMETHOD(ifdi_queues_free, ixgbe_if_queues_free),
383 DEVMETHOD(ifdi_update_admin_status, ixgbe_if_update_admin_status),
384 DEVMETHOD(ifdi_multi_set, ixgbe_if_multi_set),
385 DEVMETHOD(ifdi_mtu_set, ixgbe_if_mtu_set),
386 DEVMETHOD(ifdi_crcstrip_set, ixgbe_if_crcstrip_set),
387 DEVMETHOD(ifdi_media_status, ixgbe_if_media_status),
388 DEVMETHOD(ifdi_media_change, ixgbe_if_media_change),
389 DEVMETHOD(ifdi_promisc_set, ixgbe_if_promisc_set),
390 DEVMETHOD(ifdi_timer, ixgbe_if_timer),
391 DEVMETHOD(ifdi_vlan_register, ixgbe_if_vlan_register),
392 DEVMETHOD(ifdi_vlan_unregister, ixgbe_if_vlan_unregister),
393 DEVMETHOD(ifdi_get_counter, ixgbe_if_get_counter),
394 DEVMETHOD(ifdi_i2c_req, ixgbe_if_i2c_req),
395 DEVMETHOD(ifdi_needs_restart, ixgbe_if_needs_restart),
396 DEVMETHOD(ifdi_priv_ioctl, ixgbe_if_priv_ioctl),
397 DEVMETHOD(ifdi_led_func, ixgbe_if_led_func),
398 #ifdef PCI_IOV
399 DEVMETHOD(ifdi_iov_init, ixgbe_if_iov_init),
400 DEVMETHOD(ifdi_iov_uninit, ixgbe_if_iov_uninit),
401 DEVMETHOD(ifdi_iov_vf_add, ixgbe_if_iov_vf_add),
402 DEVMETHOD(ifdi_vf_status, ixgbe_if_vf_status),
403 #endif /* PCI_IOV */
404 DEVMETHOD_END
405 };
406
407 /*
408 * TUNEABLE PARAMETERS:
409 */
410
411 static SYSCTL_NODE(_hw, OID_AUTO, ix, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
412 "IXGBE driver parameters");
413 static driver_t ixgbe_if_driver = {
414 "ixgbe_if", ixgbe_if_methods, sizeof(struct ixgbe_softc)
415 };
416
417 static int ixgbe_max_interrupt_rate = (4000000 / IXGBE_LOW_LATENCY);
418 SYSCTL_INT(_hw_ix, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
419 &ixgbe_max_interrupt_rate, 0, "Maximum interrupts per second");
420
421 /* Flow control setting, default to full */
422 static int ixgbe_flow_control = ixgbe_fc_full;
423 SYSCTL_INT(_hw_ix, OID_AUTO, flow_control, CTLFLAG_RDTUN,
424 &ixgbe_flow_control, 0, "Default flow control used for all adapters");
425
426 /* Advertise Speed, default to 0 (auto) */
427 static int ixgbe_advertise_speed = 0;
428 SYSCTL_INT(_hw_ix, OID_AUTO, advertise_speed, CTLFLAG_RDTUN,
429 &ixgbe_advertise_speed, 0, "Default advertised speed for all adapters");
430
431 /*
432 * Smart speed setting, default to on
433 * this only works as a compile option
434 * right now as its during attach, set
435 * this to 'ixgbe_smart_speed_off' to
436 * disable.
437 */
438 static int ixgbe_smart_speed = ixgbe_smart_speed_on;
439
440 /*
441 * MSI-X should be the default for best performance,
442 * but this allows it to be forced off for testing.
443 */
444 static int ixgbe_enable_msix = 1;
445 SYSCTL_INT(_hw_ix, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixgbe_enable_msix,
446 0,
447 "Enable MSI-X interrupts");
448
449 /*
450 * Defining this on will allow the use
451 * of unsupported SFP+ modules, note that
452 * doing so you are on your own :)
453 */
454 static int allow_unsupported_sfp = false;
455 SYSCTL_INT(_hw_ix, OID_AUTO, unsupported_sfp, CTLFLAG_RDTUN,
456 &allow_unsupported_sfp, 0,
457 "Allow unsupported SFP modules...use at your own risk");
458
459 /*
460 * Not sure if Flow Director is fully baked,
461 * so we'll default to turning it off.
462 */
463 static int ixgbe_enable_fdir = 0;
464 SYSCTL_INT(_hw_ix, OID_AUTO, enable_fdir, CTLFLAG_RDTUN, &ixgbe_enable_fdir,
465 0,
466 "Enable Flow Director");
467
468 /* Receive-Side Scaling */
469 static int ixgbe_enable_rss = 1;
470 SYSCTL_INT(_hw_ix, OID_AUTO, enable_rss, CTLFLAG_RDTUN, &ixgbe_enable_rss,
471 0,
472 "Enable Receive-Side Scaling (RSS)");
473
474 /*
475 * AIM: Adaptive Interrupt Moderation
476 * which means that the interrupt rate
477 * is varied over time based on the
478 * traffic for that interrupt vector
479 */
480 static int ixgbe_enable_aim = false;
481 SYSCTL_INT(_hw_ix, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &ixgbe_enable_aim,
482 0,
483 "Enable adaptive interrupt moderation");
484
485 #if 0
486 /* Keep running tab on them for sanity check */
487 static int ixgbe_total_ports;
488 #endif
489
490 MALLOC_DEFINE(M_IXGBE, "ix", "ix driver allocations");
491
492 /*
493 * For Flow Director: this is the number of TX packets we sample
494 * for the filter pool, this means every 20th packet will be probed.
495 *
496 * This feature can be disabled by setting this to 0.
497 */
498 static int atr_sample_rate = 20;
499
500 extern struct if_txrx ixgbe_txrx;
501
502 static struct if_shared_ctx ixgbe_sctx_init = {
503 .isc_magic = IFLIB_MAGIC,
504 .isc_q_align = PAGE_SIZE,/* max(DBA_ALIGN, PAGE_SIZE) */
505 .isc_tx_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header),
506 .isc_tx_maxsegsize = PAGE_SIZE,
507 .isc_tso_maxsize = IXGBE_TSO_SIZE + sizeof(struct ether_vlan_header),
508 .isc_tso_maxsegsize = PAGE_SIZE,
509 .isc_rx_maxsize = PAGE_SIZE*4,
510 .isc_rx_nsegments = 1,
511 .isc_rx_maxsegsize = PAGE_SIZE*4,
512 .isc_nfl = 1,
513 .isc_ntxqs = 1,
514 .isc_nrxqs = 1,
515
516 .isc_admin_intrcnt = 1,
517 .isc_vendor_info = ixgbe_vendor_info_array,
518 .isc_driver_version = ixgbe_driver_version,
519 .isc_driver = &ixgbe_if_driver,
520 .isc_flags = IFLIB_TSO_INIT_IP,
521
522 .isc_nrxd_min = {MIN_RXD},
523 .isc_ntxd_min = {MIN_TXD},
524 .isc_nrxd_max = {MAX_RXD},
525 .isc_ntxd_max = {MAX_TXD},
526 .isc_nrxd_default = {DEFAULT_RXD},
527 .isc_ntxd_default = {DEFAULT_TXD},
528 };
529
530 /************************************************************************
531 * ixgbe_if_tx_queues_alloc
532 ************************************************************************/
533 static int
ixgbe_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int ntxqs,int ntxqsets)534 ixgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
535 int ntxqs, int ntxqsets)
536 {
537 struct ixgbe_softc *sc = iflib_get_softc(ctx);
538 if_softc_ctx_t scctx = sc->shared;
539 struct ix_tx_queue *que;
540 int i, j, error;
541
542 MPASS(sc->num_tx_queues > 0);
543 MPASS(sc->num_tx_queues == ntxqsets);
544 MPASS(ntxqs == 1);
545
546 /* Allocate queue structure memory */
547 sc->tx_queues =
548 (struct ix_tx_queue *)malloc(sizeof(struct ix_tx_queue) *
549 ntxqsets, M_IXGBE, M_NOWAIT | M_ZERO);
550 if (!sc->tx_queues) {
551 device_printf(iflib_get_dev(ctx),
552 "Unable to allocate TX ring memory\n");
553 return (ENOMEM);
554 }
555
556 for (i = 0, que = sc->tx_queues; i < ntxqsets; i++, que++) {
557 struct tx_ring *txr = &que->txr;
558
559 /* In case SR-IOV is enabled, align the index properly */
560 txr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, i);
561
562 txr->sc = que->sc = sc;
563
564 /* Allocate report status array */
565 txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) *
566 scctx->isc_ntxd[0], M_IXGBE, M_NOWAIT | M_ZERO);
567 if (txr->tx_rsq == NULL) {
568 error = ENOMEM;
569 goto fail;
570 }
571 for (j = 0; j < scctx->isc_ntxd[0]; j++)
572 txr->tx_rsq[j] = QIDX_INVALID;
573 /* get virtual and physical address of the hardware queues */
574 txr->tail = IXGBE_TDT(txr->me);
575 txr->tx_base = (union ixgbe_adv_tx_desc *)vaddrs[i];
576 txr->tx_paddr = paddrs[i];
577
578 txr->bytes = 0;
579 txr->total_packets = 0;
580
581 /* Set the rate at which we sample packets */
582 if (sc->feat_en & IXGBE_FEATURE_FDIR)
583 txr->atr_sample = atr_sample_rate;
584
585 }
586
587 device_printf(iflib_get_dev(ctx), "allocated for %d queues\n",
588 sc->num_tx_queues);
589
590 return (0);
591
592 fail:
593 ixgbe_if_queues_free(ctx);
594
595 return (error);
596 } /* ixgbe_if_tx_queues_alloc */
597
598 /************************************************************************
599 * ixgbe_if_rx_queues_alloc
600 ************************************************************************/
601 static int
ixgbe_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int nrxqs,int nrxqsets)602 ixgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
603 int nrxqs, int nrxqsets)
604 {
605 struct ixgbe_softc *sc = iflib_get_softc(ctx);
606 struct ix_rx_queue *que;
607 int i;
608
609 MPASS(sc->num_rx_queues > 0);
610 MPASS(sc->num_rx_queues == nrxqsets);
611 MPASS(nrxqs == 1);
612
613 /* Allocate queue structure memory */
614 sc->rx_queues =
615 (struct ix_rx_queue *)malloc(sizeof(struct ix_rx_queue)*nrxqsets,
616 M_IXGBE, M_NOWAIT | M_ZERO);
617 if (!sc->rx_queues) {
618 device_printf(iflib_get_dev(ctx),
619 "Unable to allocate TX ring memory\n");
620 return (ENOMEM);
621 }
622
623 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) {
624 struct rx_ring *rxr = &que->rxr;
625
626 /* In case SR-IOV is enabled, align the index properly */
627 rxr->me = ixgbe_vf_que_index(sc->iov_mode, sc->pool, i);
628
629 rxr->sc = que->sc = sc;
630
631 /* get the virtual and physical address of the hw queues */
632 rxr->tail = IXGBE_RDT(rxr->me);
633 rxr->rx_base = (union ixgbe_adv_rx_desc *)vaddrs[i];
634 rxr->rx_paddr = paddrs[i];
635 rxr->bytes = 0;
636 rxr->que = que;
637 }
638
639 device_printf(iflib_get_dev(ctx), "allocated for %d rx queues\n",
640 sc->num_rx_queues);
641
642 return (0);
643 } /* ixgbe_if_rx_queues_alloc */
644
645 /************************************************************************
646 * ixgbe_if_queues_free
647 ************************************************************************/
648 static void
ixgbe_if_queues_free(if_ctx_t ctx)649 ixgbe_if_queues_free(if_ctx_t ctx)
650 {
651 struct ixgbe_softc *sc = iflib_get_softc(ctx);
652 struct ix_tx_queue *tx_que = sc->tx_queues;
653 struct ix_rx_queue *rx_que = sc->rx_queues;
654 int i;
655
656 if (tx_que != NULL) {
657 for (i = 0; i < sc->num_tx_queues; i++, tx_que++) {
658 struct tx_ring *txr = &tx_que->txr;
659 if (txr->tx_rsq == NULL)
660 break;
661
662 free(txr->tx_rsq, M_IXGBE);
663 txr->tx_rsq = NULL;
664 }
665
666 free(sc->tx_queues, M_IXGBE);
667 sc->tx_queues = NULL;
668 }
669 if (rx_que != NULL) {
670 free(sc->rx_queues, M_IXGBE);
671 sc->rx_queues = NULL;
672 }
673 } /* ixgbe_if_queues_free */
674
675 /************************************************************************
676 * ixgbe_initialize_rss_mapping
677 ************************************************************************/
678 static void
ixgbe_initialize_rss_mapping(struct ixgbe_softc * sc)679 ixgbe_initialize_rss_mapping(struct ixgbe_softc *sc)
680 {
681 struct ixgbe_hw *hw = &sc->hw;
682 bool per_pool_rss;
683 u32 reta = 0, mrqc, rss_fields, rss_key[10];
684 int i, index_mult, j, queue_id, reta_queues, table_size;
685 u32 rss_hash_config;
686 #ifdef PCI_IOV
687 u32 pfmrqc;
688 #endif
689
690 rss_getkey((uint8_t *)rss_key);
691
692 /* Set multiplier for RETA setup and table size based on MAC */
693 index_mult = 0x1;
694 per_pool_rss = false;
695 table_size = 128;
696 switch (sc->hw.mac.type) {
697 case ixgbe_mac_82598EB:
698 index_mult = 0x11;
699 break;
700 case ixgbe_mac_X550:
701 case ixgbe_mac_X550EM_x:
702 case ixgbe_mac_X550EM_a:
703 case ixgbe_mac_E610:
704 table_size = 512;
705 #ifdef PCI_IOV
706 if (sc->iov_mode != IXGBE_NO_VM) {
707 per_pool_rss = true;
708 table_size = 64;
709 }
710 #endif
711 break;
712 default:
713 break;
714 }
715
716 /*
717 * The global RETA is shared by the PF and VFs on 82599 and X540.
718 * X550-family devices instead use per-pool tables in multiple-RSS
719 * mode; initialize only the PF pool here because each VF owns and
720 * programs its own key and redirection table.
721 * On the shared tables, program all four queue indices while SR-IOV
722 * is active so a VF can use its full queue grant even when the PF uses
723 * fewer queues. PSRTYPE.RQPL limits the subset selected in each pool.
724 */
725 reta_queues = sc->num_rx_queues;
726 #ifdef PCI_IOV
727 if (sc->iov_mode != IXGBE_NO_VM && !per_pool_rss)
728 reta_queues = MAX(reta_queues, 4);
729 #endif
730
731 /* Set up the redirection table */
732 for (i = 0, j = 0; i < table_size; i++, j++) {
733 if (j == reta_queues)
734 j = 0;
735
736 if (sc->feat_en & IXGBE_FEATURE_RSS) {
737 /*
738 * Fetch the RSS bucket id for the given indirection
739 * entry. Cap it at the number of queue indices that must
740 * be represented in the shared table.
741 */
742 queue_id = rss_get_indirection_to_bucket(i);
743 queue_id = queue_id % reta_queues;
744 } else
745 queue_id = (j * index_mult);
746
747 /*
748 * The low 8 bits are for hash value (n+0);
749 * The next 8 bits are for hash value (n+1), etc.
750 */
751 reta = reta >> 8;
752 reta = reta | (((uint32_t)queue_id) << 24);
753 if ((i & 3) == 3) {
754 if (per_pool_rss) {
755 #ifdef PCI_IOV
756 IXGBE_WRITE_REG(hw,
757 IXGBE_PFVFRETA(i >> 2, sc->pool), reta);
758 #endif
759 } else if (i < 128)
760 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
761 else
762 IXGBE_WRITE_REG(hw,
763 IXGBE_ERETA((i >> 2) - 32), reta);
764 reta = 0;
765 }
766 }
767
768 /* Now fill our hash function seeds */
769 for (i = 0; i < 10; i++) {
770 if (per_pool_rss) {
771 #ifdef PCI_IOV
772 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, sc->pool),
773 rss_key[i]);
774 #endif
775 } else
776 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), rss_key[i]);
777 }
778
779 /* Perform hash on these packet types */
780 if (sc->feat_en & IXGBE_FEATURE_RSS)
781 rss_hash_config = rss_gethashconfig();
782 else {
783 /*
784 * Disable UDP - IP fragments aren't currently being handled
785 * and so we end up with a mix of 2-tuple and 4-tuple
786 * traffic.
787 */
788 rss_hash_config = RSS_HASHTYPE_RSS_IPV4 |
789 RSS_HASHTYPE_RSS_TCP_IPV4 |
790 RSS_HASHTYPE_RSS_IPV6 |
791 RSS_HASHTYPE_RSS_TCP_IPV6 |
792 RSS_HASHTYPE_RSS_IPV6_EX |
793 RSS_HASHTYPE_RSS_TCP_IPV6_EX;
794 }
795
796 mrqc = ixgbe_get_mrqc(sc->iov_mode);
797 rss_fields = 0;
798 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
799 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV4;
800 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
801 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
802 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6)
803 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6;
804 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6)
805 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
806 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX)
807 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
808 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6_EX)
809 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
810 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4)
811 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
812 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6)
813 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
814 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6_EX)
815 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
816 if (hw->mac.type == ixgbe_mac_E610) {
817 /* E610 folds IPv6 extension headers into the base selectors. */
818 if (rss_fields & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
819 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6;
820 if (rss_fields & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
821 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
822 if (rss_fields & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
823 rss_fields |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
824 rss_fields &= ~(IXGBE_MRQC_RSS_FIELD_IPV6_EX |
825 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP |
826 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP);
827 }
828
829 if (per_pool_rss) {
830 #ifdef PCI_IOV
831 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
832 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
833
834 pfmrqc = IXGBE_MRQC_RSSEN | rss_fields;
835 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(sc->pool), pfmrqc);
836 #endif
837 } else {
838 mrqc |= rss_fields;
839 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
840 }
841 } /* ixgbe_initialize_rss_mapping */
842
843 /************************************************************************
844 * ixgbe_initialize_receive_units - Setup receive registers and features.
845 ************************************************************************/
846 #define BSIZEPKT_ROUNDUP ((1<<IXGBE_SRRCTL_BSIZEPKT_SHIFT)-1)
847
848 static void
ixgbe_initialize_receive_units(if_ctx_t ctx)849 ixgbe_initialize_receive_units(if_ctx_t ctx)
850 {
851 struct ixgbe_softc *sc = iflib_get_softc(ctx);
852 if_softc_ctx_t scctx = sc->shared;
853 struct ixgbe_hw *hw = &sc->hw;
854 if_t ifp = iflib_get_ifp(ctx);
855 struct ix_rx_queue *que;
856 int i, j;
857 u32 bufsz, fctrl, srrctl, rxcsum;
858 u32 hlreg;
859
860 /*
861 * Make sure receives are disabled while
862 * setting up the descriptor ring
863 */
864 ixgbe_disable_rx(hw);
865
866 /* Enable broadcasts */
867 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
868 fctrl |= IXGBE_FCTRL_BAM;
869 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
870 fctrl |= IXGBE_FCTRL_DPF;
871 fctrl |= IXGBE_FCTRL_PMCF;
872 }
873 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
874
875 /* Set for Jumbo Frames? */
876 hlreg = IXGBE_READ_REG(hw, IXGBE_HLREG0);
877 if (if_getmtu(ifp) > ETHERMTU)
878 hlreg |= IXGBE_HLREG0_JUMBOEN;
879 else
880 hlreg &= ~IXGBE_HLREG0_JUMBOEN;
881 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg);
882
883 bufsz = (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
884 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
885
886 /* Setup the Base and Length of the Rx Descriptor Ring */
887 for (i = 0, que = sc->rx_queues; i < sc->num_rx_queues; i++, que++) {
888 struct rx_ring *rxr = &que->rxr;
889 u64 rdba = rxr->rx_paddr;
890
891 j = rxr->me;
892
893 /* Setup the Base and Length of the Rx Descriptor Ring */
894 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j),
895 (rdba & 0x00000000ffffffffULL));
896 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
897 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j),
898 scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc));
899
900 /* Set up the SRRCTL register */
901 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(j));
902 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
903 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
904 srrctl |= bufsz;
905 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
906
907 /*
908 * Set DROP_EN iff we have no flow control and >1 queue.
909 * Note that srrctl was cleared shortly before during reset,
910 * so we do not need to clear the bit, but do it just in case
911 * this code is moved elsewhere.
912 */
913 if (sc->num_rx_queues > 1 &&
914 sc->hw.fc.requested_mode == ixgbe_fc_none) {
915 srrctl |= IXGBE_SRRCTL_DROP_EN;
916 } else {
917 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
918 }
919
920 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(j), srrctl);
921
922 /* Setup the HW Rx Head and Tail Descriptor Pointers */
923 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
924 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
925
926 /* Set the driver rx tail address */
927 rxr->tail = IXGBE_RDT(rxr->me);
928 }
929
930 if (sc->hw.mac.type != ixgbe_mac_82598EB) {
931 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
932 IXGBE_PSRTYPE_UDPHDR |
933 IXGBE_PSRTYPE_IPV4HDR |
934 IXGBE_PSRTYPE_IPV6HDR;
935
936 /*
937 * In VMDq+RSS mode PSRTYPE is per pool, and RQPL controls
938 * how many receive queues RSS may select within that pool.
939 * The PF occupies the last pool rather than pool zero.
940 */
941 #ifdef PCI_IOV
942 if (sc->iov_mode != IXGBE_NO_VM) {
943 if (sc->num_rx_queues > 3)
944 psrtype |= 2u << IXGBE_PSRTYPE_RQPL_SHIFT;
945 else if (sc->num_rx_queues > 1)
946 psrtype |= 1u << IXGBE_PSRTYPE_RQPL_SHIFT;
947 }
948 #endif
949 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(sc->pool), psrtype);
950 }
951
952 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
953
954 ixgbe_initialize_rss_mapping(sc);
955
956 if (sc->feat_en & IXGBE_FEATURE_RSS) {
957 /* RSS and RX IPP Checksum are mutually exclusive */
958 rxcsum |= IXGBE_RXCSUM_PCSD;
959 }
960
961 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
962 rxcsum |= IXGBE_RXCSUM_PCSD;
963
964 /* This is useful for calculating UDP/IP fragment checksums */
965 if (!(rxcsum & IXGBE_RXCSUM_PCSD))
966 rxcsum |= IXGBE_RXCSUM_IPPCSE;
967
968 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
969
970 } /* ixgbe_initialize_receive_units */
971
972 /************************************************************************
973 * ixgbe_initialize_transmit_units - Enable transmit units.
974 ************************************************************************/
975 static void
ixgbe_initialize_transmit_units(if_ctx_t ctx)976 ixgbe_initialize_transmit_units(if_ctx_t ctx)
977 {
978 struct ixgbe_softc *sc = iflib_get_softc(ctx);
979 struct ixgbe_hw *hw = &sc->hw;
980 if_softc_ctx_t scctx = sc->shared;
981 struct ix_tx_queue *que;
982 int i;
983
984 /* Setup the Base and Length of the Tx Descriptor Ring */
985 for (i = 0, que = sc->tx_queues; i < sc->num_tx_queues;
986 i++, que++) {
987 struct tx_ring *txr = &que->txr;
988 u64 tdba = txr->tx_paddr;
989 u32 txctrl = 0;
990 int j = txr->me;
991
992 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
993 (tdba & 0x00000000ffffffffULL));
994 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
995 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j),
996 scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc));
997
998 /* Setup the HW Tx Head and Tail descriptor pointers */
999 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1000 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1001
1002 /* Cache the tail address */
1003 txr->tail = IXGBE_TDT(txr->me);
1004
1005 txr->tx_rs_cidx = txr->tx_rs_pidx;
1006 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1007 for (int k = 0; k < scctx->isc_ntxd[0]; k++)
1008 txr->tx_rsq[k] = QIDX_INVALID;
1009
1010 /* Disable Head Writeback */
1011 /*
1012 * Note: for X550 series devices, these registers are actually
1013 * prefixed with TPH_ isntead of DCA_, but the addresses and
1014 * fields remain the same.
1015 */
1016 switch (hw->mac.type) {
1017 case ixgbe_mac_82598EB:
1018 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1019 break;
1020 default:
1021 txctrl =
1022 IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1023 break;
1024 }
1025 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
1026 switch (hw->mac.type) {
1027 case ixgbe_mac_82598EB:
1028 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1029 break;
1030 default:
1031 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j),
1032 txctrl);
1033 break;
1034 }
1035
1036 }
1037
1038 if (hw->mac.type != ixgbe_mac_82598EB) {
1039 u32 dmatxctl, rttdcs;
1040
1041 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1042 dmatxctl |= IXGBE_DMATXCTL_TE;
1043 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
1044 /* Disable arbiter to set MTQC */
1045 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1046 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1047 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1048 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
1049 ixgbe_get_mtqc(sc->iov_mode));
1050 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
1051 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1052 }
1053
1054 } /* ixgbe_initialize_transmit_units */
1055
1056 static int
ixgbe_check_fw_api_version(struct ixgbe_softc * sc)1057 ixgbe_check_fw_api_version(struct ixgbe_softc *sc)
1058 {
1059 struct ixgbe_hw *hw = &sc->hw;
1060 if (hw->api_maj_ver > IXGBE_FW_API_VER_MAJOR) {
1061 device_printf(sc->dev,
1062 "The driver for the device stopped because the NVM "
1063 "image is newer than expected. You must install the "
1064 "most recent version of the network driver.\n");
1065 return (EOPNOTSUPP);
1066 } else if (hw->api_maj_ver == IXGBE_FW_API_VER_MAJOR &&
1067 hw->api_min_ver > (IXGBE_FW_API_VER_MINOR + 2)) {
1068 device_printf(sc->dev,
1069 "The driver for the device detected a newer version of "
1070 "the NVM image than expected. Please install the most "
1071 "recent version of the network driver.\n");
1072 } else if (hw->api_maj_ver < IXGBE_FW_API_VER_MAJOR ||
1073 hw->api_min_ver < IXGBE_FW_API_VER_MINOR - 2) {
1074 device_printf(sc->dev,
1075 "The driver for the device detected an older version "
1076 "of the NVM image than expected. "
1077 "Please update the NVM image.\n");
1078 }
1079 return (0);
1080 }
1081
1082 /************************************************************************
1083 * ixgbe_register
1084 ************************************************************************/
1085 static void *
ixgbe_register(device_t dev)1086 ixgbe_register(device_t dev)
1087 {
1088 return (&ixgbe_sctx_init);
1089 } /* ixgbe_register */
1090
1091 /************************************************************************
1092 * ixgbe_if_attach_pre - Device initialization routine, part 1
1093 *
1094 * Called when the driver is being loaded.
1095 * Identifies the type of hardware, initializes the hardware,
1096 * and initializes iflib structures.
1097 *
1098 * return 0 on success, positive on failure
1099 ************************************************************************/
1100 static int
ixgbe_if_attach_pre(if_ctx_t ctx)1101 ixgbe_if_attach_pre(if_ctx_t ctx)
1102 {
1103 struct ixgbe_softc *sc;
1104 device_t dev;
1105 if_softc_ctx_t scctx;
1106 struct ixgbe_hw *hw;
1107 int error = 0;
1108 u32 ctrl_ext;
1109 size_t i;
1110
1111 INIT_DEBUGOUT("ixgbe_attach: begin");
1112
1113 /* Allocate, clear, and link in our adapter structure */
1114 dev = iflib_get_dev(ctx);
1115 sc = iflib_get_softc(ctx);
1116 sc->hw.back = sc;
1117 sc->ctx = ctx;
1118 sc->dev = dev;
1119 scctx = sc->shared = iflib_get_softc_ctx(ctx);
1120 sc->media = iflib_get_media(ctx);
1121 hw = &sc->hw;
1122
1123 /* Determine hardware revision */
1124 hw->vendor_id = pci_get_vendor(dev);
1125 hw->device_id = pci_get_device(dev);
1126 hw->revision_id = pci_get_revid(dev);
1127 hw->subsystem_vendor_id = pci_get_subvendor(dev);
1128 hw->subsystem_device_id = pci_get_subdevice(dev);
1129
1130 /* Do base PCI setup - map BAR0 */
1131 if (ixgbe_allocate_pci_resources(ctx)) {
1132 device_printf(dev, "Allocation of PCI resources failed\n");
1133 return (ENXIO);
1134 }
1135
1136 /* let hardware know driver is loaded */
1137 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1138 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1139 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1140
1141 /*
1142 * Initialize the shared code
1143 */
1144 if (ixgbe_init_shared_code(hw) != 0) {
1145 device_printf(dev, "Unable to initialize the shared code\n");
1146 error = ENXIO;
1147 goto err_pci;
1148 }
1149
1150 if (hw->mac.type == ixgbe_mac_E610)
1151 ixgbe_init_aci(hw);
1152
1153 sc->do_debug_dump = false;
1154
1155 if (hw->mac.ops.fw_recovery_mode &&
1156 hw->mac.ops.fw_recovery_mode(hw)) {
1157 device_printf(dev,
1158 "Firmware recovery mode detected. Limiting "
1159 "functionality.\nRefer to the Intel(R) Ethernet Adapters "
1160 "and Devices User Guide for details on firmware recovery "
1161 "mode.");
1162 error = ENOSYS;
1163 goto err_pci;
1164 }
1165
1166 /* 82598 Does not support SR-IOV, initialize everything else */
1167 if (hw->mac.type >= ixgbe_mac_82599_vf) {
1168 for (i = 0; i < sc->num_vfs; i++)
1169 hw->mbx.ops[i].init_params(hw);
1170 }
1171
1172 hw->allow_unsupported_sfp = allow_unsupported_sfp;
1173
1174 if (hw->mac.type != ixgbe_mac_82598EB)
1175 hw->phy.smart_speed = ixgbe_smart_speed;
1176
1177 ixgbe_init_device_features(sc);
1178
1179 /* Verify adapter fan is still functional (if applicable) */
1180 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) {
1181 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1182 ixgbe_check_fan_failure(sc, esdp, false);
1183 }
1184
1185 /* Ensure SW/FW semaphore is free */
1186 ixgbe_init_swfw_semaphore(hw);
1187
1188 /* Enable EEE power saving */
1189 if (sc->feat_en & IXGBE_FEATURE_EEE)
1190 hw->mac.ops.setup_eee(hw, true);
1191
1192 /* Set an initial default flow control value */
1193 hw->fc.requested_mode = ixgbe_flow_control;
1194
1195 hw->phy.reset_if_overtemp = true;
1196 error = ixgbe_reset_hw(hw);
1197 hw->phy.reset_if_overtemp = false;
1198 if (error == IXGBE_ERR_SFP_NOT_PRESENT) {
1199 /*
1200 * No optics in this port, set up
1201 * so the timer routine will probe
1202 * for later insertion.
1203 */
1204 sc->sfp_probe = true;
1205 error = 0;
1206 } else if (error == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1207 device_printf(dev, "Unsupported SFP+ module detected!\n");
1208 error = EIO;
1209 goto err_pci;
1210 } else if (error) {
1211 device_printf(dev, "Hardware initialization failed\n");
1212 error = EIO;
1213 goto err_pci;
1214 }
1215
1216 /* Make sure we have a good EEPROM before we read from it */
1217 if (ixgbe_validate_eeprom_checksum(&sc->hw, NULL) < 0) {
1218 device_printf(dev, "The EEPROM Checksum Is Not Valid\n");
1219 error = EIO;
1220 goto err_pci;
1221 }
1222
1223 error = ixgbe_start_hw(hw);
1224 switch (error) {
1225 case IXGBE_ERR_EEPROM_VERSION:
1226 device_printf(dev,
1227 "This device is a pre-production adapter/LOM. Please be"
1228 " aware there may be issues associated with your"
1229 " hardware.\nIf you are experiencing problems please"
1230 " contact your Intel or hardware representative who"
1231 " provided you with this hardware.\n");
1232 break;
1233 case IXGBE_ERR_SFP_NOT_SUPPORTED:
1234 device_printf(dev, "Unsupported SFP+ Module\n");
1235 error = EIO;
1236 goto err_pci;
1237 case IXGBE_ERR_SFP_NOT_PRESENT:
1238 device_printf(dev, "No SFP+ Module found\n");
1239 /* falls thru */
1240 default:
1241 break;
1242 }
1243
1244 /* Check the FW API version and enable FW logging support for E610 */
1245 if (hw->mac.type == ixgbe_mac_E610) {
1246 if (ixgbe_check_fw_api_version(sc)) {
1247 error = EIO;
1248 goto err_pci;
1249 }
1250 ixgbe_fwlog_set_support_ena(hw);
1251 }
1252
1253 /* Most of the iflib initialization... */
1254
1255 iflib_set_mac(ctx, hw->mac.addr);
1256 switch (sc->hw.mac.type) {
1257 case ixgbe_mac_X550:
1258 case ixgbe_mac_X550EM_x:
1259 case ixgbe_mac_X550EM_a:
1260 scctx->isc_rss_table_size = 512;
1261 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 64;
1262 break;
1263 default:
1264 scctx->isc_rss_table_size = 128;
1265 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 16;
1266 }
1267
1268 /* Allow legacy interrupts */
1269 ixgbe_txrx.ift_legacy_intr = ixgbe_intr;
1270
1271 scctx->isc_txqsizes[0] =
1272 roundup2(scctx->isc_ntxd[0] * sizeof(union ixgbe_adv_tx_desc) +
1273 sizeof(u32), DBA_ALIGN),
1274 scctx->isc_rxqsizes[0] =
1275 roundup2(scctx->isc_nrxd[0] * sizeof(union ixgbe_adv_rx_desc),
1276 DBA_ALIGN);
1277
1278 /* XXX */
1279 scctx->isc_tx_csum_flags = CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TSO |
1280 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_TSO;
1281 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
1282 scctx->isc_tx_nsegments = IXGBE_82598_SCATTER;
1283 } else {
1284 scctx->isc_tx_csum_flags |= CSUM_SCTP |CSUM_IP6_SCTP;
1285 scctx->isc_tx_nsegments = IXGBE_82599_SCATTER;
1286 }
1287
1288 scctx->isc_msix_bar = pci_msix_table_bar(dev);
1289
1290 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments;
1291 scctx->isc_tx_tso_size_max = IXGBE_TSO_SIZE;
1292 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
1293
1294 scctx->isc_txrx = &ixgbe_txrx;
1295
1296 scctx->isc_capabilities = scctx->isc_capenable = IXGBE_CAPS;
1297 ixgbe_configure_wakeup(ctx);
1298
1299 return (0);
1300
1301 err_pci:
1302 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT);
1303 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD;
1304 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext);
1305 ixgbe_free_pci_resources(ctx);
1306
1307 if (hw->mac.type == ixgbe_mac_E610)
1308 ixgbe_shutdown_aci(hw);
1309
1310 return (error);
1311 } /* ixgbe_if_attach_pre */
1312
1313 /*********************************************************************
1314 * ixgbe_if_attach_post - Device initialization routine, part 2
1315 *
1316 * Called during driver load, but after interrupts and
1317 * resources have been allocated and configured.
1318 * Sets up some data structures not relevant to iflib.
1319 *
1320 * return 0 on success, positive on failure
1321 *********************************************************************/
1322 static int
ixgbe_if_attach_post(if_ctx_t ctx)1323 ixgbe_if_attach_post(if_ctx_t ctx)
1324 {
1325 device_t dev;
1326 struct ixgbe_softc *sc;
1327 struct ixgbe_hw *hw;
1328 int error = 0;
1329
1330 dev = iflib_get_dev(ctx);
1331 sc = iflib_get_softc(ctx);
1332 hw = &sc->hw;
1333 ixgbe_init_iov_recovery(sc);
1334
1335 if (sc->intr_type == IFLIB_INTR_LEGACY &&
1336 (sc->feat_cap & IXGBE_FEATURE_LEGACY_IRQ) == 0) {
1337 device_printf(dev, "Device does not support legacy interrupts");
1338 error = ENXIO;
1339 goto err;
1340 }
1341
1342 /* Allocate multicast array memory. */
1343 sc->mta = malloc(sizeof(*sc->mta) * MAX_NUM_MULTICAST_ADDRESSES,
1344 M_IXGBE, M_NOWAIT);
1345 if (sc->mta == NULL) {
1346 device_printf(dev,
1347 "Can not allocate multicast setup array\n");
1348 error = ENOMEM;
1349 goto err;
1350 }
1351
1352 /* hw.ix defaults init */
1353 ixgbe_set_advertise(sc, ixgbe_advertise_speed);
1354
1355 /* Enable the optics for 82599 SFP+ fiber */
1356 ixgbe_enable_tx_laser(hw);
1357
1358 /* Enable power to the phy. */
1359 ixgbe_set_phy_power(hw, true);
1360
1361 ixgbe_initialize_iov(sc);
1362
1363 error = ixgbe_setup_interface(ctx);
1364 if (error) {
1365 device_printf(dev, "Interface setup failed: %d\n", error);
1366 goto err;
1367 }
1368
1369 ixgbe_if_update_admin_status(ctx);
1370
1371 /* Initialize statistics */
1372 ixgbe_update_stats_counters(sc);
1373 ixgbe_add_hw_stats(sc);
1374
1375 /* Check PCIE slot type/speed/width */
1376 ixgbe_get_slot_info(sc);
1377
1378 /*
1379 * Do time init and sysctl init here, but
1380 * only on the first port of a bypass sc.
1381 */
1382 ixgbe_bypass_init(sc);
1383
1384 /* Display NVM and Option ROM versions */
1385 ixgbe_print_fw_version(ctx);
1386
1387 /* Set an initial dmac value */
1388 sc->dmac = 0;
1389 /* Set initial advertised speeds (if applicable) */
1390 sc->advertise = ixgbe_get_default_advertise(sc);
1391
1392 if (sc->feat_cap & IXGBE_FEATURE_SRIOV)
1393 ixgbe_define_iov_schemas(sc, &error);
1394
1395 /* Add sysctls */
1396 ixgbe_add_device_sysctls(ctx);
1397
1398 /* Add MDIO bus if required / supported */
1399 ixgbe_mdio_attach(sc);
1400
1401 /* Init recovery mode timer and state variable */
1402 if (sc->feat_en & IXGBE_FEATURE_RECOVERY_MODE) {
1403 sc->recovery_mode = 0;
1404
1405 /* Set up the timer callout */
1406 callout_init(&sc->fw_mode_timer, true);
1407 sc->fw_mode_timer_initialized = true;
1408
1409 /* Start the task */
1410 callout_reset(&sc->fw_mode_timer, hz, ixgbe_fw_mode_timer, sc);
1411 }
1412
1413 return (0);
1414 err:
1415 return (error);
1416 } /* ixgbe_if_attach_post */
1417
1418 /************************************************************************
1419 * ixgbe_configure_wakeup
1420 *
1421 * Advertise the wake modes supported by this board and port. The NVM
1422 * APME setting selects the initial magic-packet policy.
1423 ************************************************************************/
1424 static void
ixgbe_configure_wakeup(if_ctx_t ctx)1425 ixgbe_configure_wakeup(if_ctx_t ctx)
1426 {
1427 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1428 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
1429 struct ixgbe_hw *hw = &sc->hw;
1430 device_t dev = iflib_get_dev(ctx);
1431 u16 dev_caps = 0;
1432 u16 subdevice_id;
1433 u16 wol_cap;
1434 bool apme, supported;
1435
1436 supported = false;
1437 subdevice_id = hw->subsystem_device_id;
1438 if (hw->mac.ops.set_lan_id != NULL)
1439 hw->mac.ops.set_lan_id(hw);
1440
1441 /* X540 and newer advertise per-port WoL support in the NVM. */
1442 if (hw->mac.type >= ixgbe_mac_X540) {
1443 if (ixgbe_get_device_caps(hw, &dev_caps) == IXGBE_SUCCESS) {
1444 wol_cap = dev_caps & IXGBE_DEVICE_CAPS_WOL_MASK;
1445 if (wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1 ||
1446 (wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0 &&
1447 hw->bus.func == 0))
1448 supported = true;
1449 }
1450 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1451 /* 82599 WoL support is board and, in some cases, port specific. */
1452 switch (hw->device_id) {
1453 case IXGBE_DEV_ID_82599_SFP:
1454 switch (subdevice_id) {
1455 case IXGBE_SUBDEV_ID_82599_560FLR:
1456 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
1457 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
1458 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
1459 supported = hw->bus.func == 0;
1460 break;
1461 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
1462 case IXGBE_SUBDEV_ID_82599_SFP:
1463 case IXGBE_SUBDEV_ID_82599_RNDC:
1464 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
1465 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
1466 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
1467 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
1468 supported = true;
1469 break;
1470 default:
1471 break;
1472 }
1473 break;
1474 case IXGBE_DEV_ID_82599EN_SFP:
1475 supported =
1476 subdevice_id == IXGBE_SUBDEV_ID_82599EN_SFP_OCP1;
1477 break;
1478 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
1479 supported =
1480 subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ;
1481 break;
1482 case IXGBE_DEV_ID_82599_KX4:
1483 supported = true;
1484 break;
1485 default:
1486 break;
1487 }
1488 }
1489 if (!pci_has_pme(dev, PCI_POWERSTATE_D3_HOT))
1490 supported = false;
1491 apme = supported &&
1492 (IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw)) & IXGBE_GRC_APME) != 0;
1493
1494 scctx->isc_capabilities &= ~IFCAP_WOL;
1495 scctx->isc_capenable &= ~IFCAP_WOL;
1496 if (supported) {
1497 scctx->isc_capabilities |= IFCAP_WOL;
1498 if (apme)
1499 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1500 }
1501
1502 /* hw->wol_enabled describes the policy active in hardware, not support. */
1503 hw->wol_enabled = false;
1504 sc->wol_filters = 0;
1505 } /* ixgbe_configure_wakeup */
1506
1507 /************************************************************************
1508 * ixgbe_setup_interface
1509 *
1510 * Setup networking device structure and register an interface.
1511 ************************************************************************/
1512 static int
ixgbe_setup_interface(if_ctx_t ctx)1513 ixgbe_setup_interface(if_ctx_t ctx)
1514 {
1515 if_t ifp = iflib_get_ifp(ctx);
1516 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1517
1518 INIT_DEBUGOUT("ixgbe_setup_interface: begin");
1519
1520 if_setbaudrate(ifp, IF_Gbps(10));
1521
1522 sc->max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN;
1523
1524 sc->phy_layer = ixgbe_get_supported_physical_layer(&sc->hw);
1525
1526 ixgbe_add_media_types(ctx);
1527
1528 /* Autoselect media by default */
1529 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1530
1531 return (0);
1532 } /* ixgbe_setup_interface */
1533
1534 /************************************************************************
1535 * ixgbe_if_get_counter
1536 ************************************************************************/
1537 static uint64_t
ixgbe_if_get_counter(if_ctx_t ctx,ift_counter cnt)1538 ixgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
1539 {
1540 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1541 if_t ifp = iflib_get_ifp(ctx);
1542
1543 switch (cnt) {
1544 case IFCOUNTER_IPACKETS:
1545 return (sc->ipackets);
1546 case IFCOUNTER_OPACKETS:
1547 return (sc->opackets);
1548 case IFCOUNTER_IBYTES:
1549 return (sc->ibytes);
1550 case IFCOUNTER_OBYTES:
1551 return (sc->obytes);
1552 case IFCOUNTER_IMCASTS:
1553 return (sc->imcasts);
1554 case IFCOUNTER_OMCASTS:
1555 return (sc->omcasts);
1556 case IFCOUNTER_COLLISIONS:
1557 return (0);
1558 case IFCOUNTER_IQDROPS:
1559 return (sc->iqdrops);
1560 case IFCOUNTER_IERRORS:
1561 return (sc->ierrors);
1562 default:
1563 return (if_get_counter_default(ifp, cnt));
1564 }
1565 } /* ixgbe_if_get_counter */
1566
1567 /************************************************************************
1568 * ixgbe_if_i2c_req
1569 ************************************************************************/
1570 static int
ixgbe_if_i2c_req(if_ctx_t ctx,struct ifi2creq * req)1571 ixgbe_if_i2c_req(if_ctx_t ctx, struct ifi2creq *req)
1572 {
1573 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1574 struct ixgbe_hw *hw = &sc->hw;
1575 int i;
1576
1577 if (hw->phy.ops.read_i2c_byte == NULL)
1578 return (ENXIO);
1579 for (i = 0; i < req->len; i++)
1580 hw->phy.ops.read_i2c_byte(hw, req->offset + i,
1581 req->dev_addr, &req->data[i]);
1582 return (0);
1583 } /* ixgbe_if_i2c_req */
1584
1585 /* ixgbe_if_needs_restart - Tell iflib when the driver needs to be
1586 * reinitialized
1587 * @ctx: iflib context
1588 * @event: event code to check
1589 *
1590 * Defaults to returning false for unknown events.
1591 *
1592 * @returns true if iflib needs to reinit the interface
1593 */
1594 static bool
ixgbe_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)1595 ixgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1596 {
1597 switch (event) {
1598 case IFLIB_RESTART_VLAN_CONFIG:
1599 default:
1600 return (false);
1601 }
1602 }
1603
1604 /************************************************************************
1605 * ixgbe_if_priv_ioctl - Ioctl handler for driver
1606 *
1607 * Handler for custom driver specific ioctls
1608 *
1609 * return 0 on success, positive on failure
1610 ************************************************************************/
1611 static int
ixgbe_if_priv_ioctl(if_ctx_t ctx,u_long command,caddr_t data)1612 ixgbe_if_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data)
1613 {
1614 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1615 struct ifdrv *ifd;
1616 device_t dev = sc->dev;
1617
1618 /* Make sure the command type is valid */
1619 switch (command) {
1620 case SIOCSDRVSPEC:
1621 case SIOCGDRVSPEC:
1622 /* Accepted commands */
1623 break;
1624 case SIOCGPRIVATE_0:
1625 /*
1626 * Although we do not support this ioctl command, it's expected
1627 * that iflib will forward it to the IFDI_PRIV_IOCTL handler.
1628 * Do not print a message in this case.
1629 */
1630 return (ENOTSUP);
1631 default:
1632 /*
1633 * If we get a different command for this function, it's
1634 * definitely unexpected, so log a message indicating what
1635 * command we got for debugging purposes.
1636 */
1637 device_printf(dev,
1638 "%s: unexpected ioctl command %08lx\n",
1639 __func__, command);
1640 return (EINVAL);
1641 }
1642
1643 ifd = (struct ifdrv *)data;
1644
1645 switch (ifd->ifd_cmd) {
1646 case IXGBE_NVM_ACCESS:
1647 IOCTL_DEBUGOUT("ioctl: NVM ACCESS");
1648 return (ixgbe_nvm_access_ioctl(sc, ifd));
1649 case IXGBE_DEBUG_DUMP:
1650 IOCTL_DEBUGOUT("ioctl: DEBUG DUMP");
1651 return (ixgbe_debug_dump_ioctl(sc, ifd));
1652 default:
1653 IOCTL_DEBUGOUT1(
1654 "ioctl: UNKNOWN SIOC(S|G)DRVSPEC (0x%X) command\n",
1655 (int)ifd->ifd_cmd);
1656 return (EINVAL);
1657 }
1658
1659 return (0);
1660 }
1661
1662 /************************************************************************
1663 * ixgbe_nvm_access_ioctl
1664 *
1665 * Handles an NVM access ioctl request
1666 ************************************************************************/
1667 static int
ixgbe_nvm_access_ioctl(struct ixgbe_softc * sc,struct ifdrv * ifd)1668 ixgbe_nvm_access_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd)
1669 {
1670 struct ixgbe_nvm_access_data *data;
1671 struct ixgbe_nvm_access_cmd *cmd;
1672 struct ixgbe_hw *hw = &sc->hw;
1673 size_t ifd_len = ifd->ifd_len;
1674 size_t malloc_len;
1675 device_t dev = sc->dev;
1676 s32 status;
1677 u8 *nvm_buffer;
1678 int error = 0;
1679
1680 /*
1681 * ifioctl forwards SIOCxDRVSPEC to iflib without conducting
1682 * a privilege check. Subsequently, iflib passes the ioctl to the driver
1683 * without verifying privileges. To prevent non-privileged threads from
1684 * accessing this interface, perform a privilege check at this point.
1685 */
1686 error = priv_check(curthread, PRIV_DRIVER);
1687 if (error)
1688 return (error);
1689
1690 if (ifd_len < sizeof(*cmd)) {
1691 device_printf(dev,
1692 "%s: ifdrv length is too small. Got %zu, "
1693 "but expected %zu\n",
1694 __func__, ifd_len, sizeof(*cmd));
1695 return (EINVAL);
1696 }
1697
1698 if (ifd->ifd_data == NULL) {
1699 device_printf(dev, "%s: No ifd data buffer.\n",
1700 __func__);
1701 return (EINVAL);
1702 }
1703
1704 malloc_len = max(ifd_len, sizeof(*data) + sizeof(*cmd));
1705
1706 nvm_buffer = (u8 *)malloc(malloc_len, M_IXGBE, M_ZERO | M_NOWAIT);
1707 if (!nvm_buffer)
1708 return (ENOMEM);
1709
1710 /* Copy the NVM access command and data in from user space */
1711 error = copyin(ifd->ifd_data, nvm_buffer, ifd_len);
1712 if (error) {
1713 device_printf(dev, "%s: Failed to copy data in, error: %d\n",
1714 __func__, error);
1715 goto cleanup_free_nvm_buffer;
1716 }
1717
1718 /*
1719 * The NVM command structure is immediately followed by data which
1720 * varies in size based on the command.
1721 */
1722 cmd = (struct ixgbe_nvm_access_cmd *)nvm_buffer;
1723 data = (struct ixgbe_nvm_access_data *)
1724 (nvm_buffer + sizeof(struct ixgbe_nvm_access_cmd));
1725
1726 /* Handle the NVM access request */
1727 status = ixgbe_handle_nvm_access(hw, cmd, data);
1728 if (status) {
1729 device_printf(dev, "%s: NVM access request failed, error %d\n",
1730 __func__, status);
1731 }
1732
1733 /* Copy the possibly modified contents of the handled request out */
1734 error = copyout(nvm_buffer, ifd->ifd_data, ifd_len);
1735 if (error) {
1736 device_printf(dev, "%s: Copying response back to "
1737 "user space failed, error %d\n",
1738 __func__, error);
1739 goto cleanup_free_nvm_buffer;
1740 }
1741
1742 /* Convert private status to an error code for proper ioctl response */
1743 switch (status) {
1744 case IXGBE_SUCCESS:
1745 error = 0;
1746 break;
1747 case IXGBE_ERR_OUT_OF_RANGE:
1748 error = ENOTTY;
1749 break;
1750 case IXGBE_ERR_PARAM:
1751 default:
1752 error = EINVAL;
1753 break;
1754 }
1755
1756 cleanup_free_nvm_buffer:
1757 free(nvm_buffer, M_IXGBE);
1758 return (error);
1759 }
1760
1761 /************************************************************************
1762 * ixgbe_debug_dump_ioctl
1763 *
1764 * Makes debug dump of internal FW/HW data.
1765 ************************************************************************/
1766 static int
ixgbe_debug_dump_ioctl(struct ixgbe_softc * sc,struct ifdrv * ifd)1767 ixgbe_debug_dump_ioctl(struct ixgbe_softc *sc, struct ifdrv *ifd)
1768 {
1769 struct ixgbe_debug_dump_cmd *dd_cmd;
1770 struct ixgbe_hw *hw = &sc->hw;
1771 size_t ifd_len = ifd->ifd_len;
1772 device_t dev = sc->dev;
1773 s32 error = 0;
1774
1775 if (!(sc->feat_en & IXGBE_FEATURE_DBG_DUMP))
1776 return (ENODEV);
1777
1778 /* Data returned from ACI command */
1779 u16 ret_buf_size = 0;
1780 u16 ret_next_cluster = 0;
1781 u16 ret_next_table = 0;
1782 u32 ret_next_index = 0;
1783
1784 /*
1785 * ifioctl forwards SIOCxDRVSPEC to iflib without conducting
1786 * a privilege check. Subsequently, iflib passes the ioctl to the driver
1787 * without verifying privileges. To prevent non-privileged threads from
1788 * accessing this interface, perform a privilege check at this point.
1789 */
1790 error = priv_check(curthread, PRIV_DRIVER);
1791 if (error)
1792 return (error);
1793
1794 if (ifd_len < sizeof(*dd_cmd)) {
1795 device_printf(dev,
1796 "%s: ifdrv length is too small. Got %zu, "
1797 "but expected %zu\n",
1798 __func__, ifd_len, sizeof(*dd_cmd));
1799 return (EINVAL);
1800 }
1801
1802 if (ifd->ifd_data == NULL) {
1803 device_printf(dev, "%s: No ifd data buffer.\n",
1804 __func__);
1805 return (EINVAL);
1806 }
1807
1808 dd_cmd = (struct ixgbe_debug_dump_cmd *)malloc(ifd_len, M_IXGBE,
1809 M_NOWAIT | M_ZERO);
1810 if (!dd_cmd) {
1811 error = -ENOMEM;
1812 goto out;
1813 }
1814 /* copy data from userspace */
1815 error = copyin(ifd->ifd_data, dd_cmd, ifd_len);
1816 if (error) {
1817 device_printf(dev, "%s: Failed to copy data in, error: %d\n",
1818 __func__, error);
1819 goto out;
1820 }
1821
1822 /* ACI command requires buf_size arg to be grater than 0 */
1823 if (dd_cmd->data_size == 0) {
1824 device_printf(dev, "%s: data_size must be greater than 0\n",
1825 __func__);
1826 error = EINVAL;
1827 goto out;
1828 }
1829
1830 /* Zero the data buffer memory space */
1831 memset(dd_cmd->data, 0, ifd_len - sizeof(*dd_cmd));
1832
1833 error = ixgbe_aci_get_internal_data(hw, dd_cmd->cluster_id,
1834 dd_cmd->table_id, dd_cmd->offset, dd_cmd->data, dd_cmd->data_size,
1835 &ret_buf_size, &ret_next_cluster, &ret_next_table, &ret_next_index);
1836 if (error) {
1837 device_printf(dev,
1838 "%s: Failed to get internal FW/HW data, error: %d\n",
1839 __func__, error);
1840 goto out;
1841 }
1842
1843 dd_cmd->cluster_id = ret_next_cluster;
1844 dd_cmd->table_id = ret_next_table;
1845 dd_cmd->offset = ret_next_index;
1846 dd_cmd->data_size = ret_buf_size;
1847
1848 error = copyout(dd_cmd, ifd->ifd_data, ifd->ifd_len);
1849 if (error) {
1850 device_printf(dev,
1851 "%s: Failed to copy data out, error: %d\n",
1852 __func__, error);
1853 }
1854
1855 out:
1856 free(dd_cmd, M_IXGBE);
1857
1858 return (error);
1859 }
1860
1861 /************************************************************************
1862 * ixgbe_add_media_types
1863 ************************************************************************/
1864 static void
ixgbe_add_media_types(if_ctx_t ctx)1865 ixgbe_add_media_types(if_ctx_t ctx)
1866 {
1867 struct ixgbe_softc *sc = iflib_get_softc(ctx);
1868 struct ixgbe_hw *hw = &sc->hw;
1869 device_t dev = iflib_get_dev(ctx);
1870 u64 layer;
1871
1872 layer = sc->phy_layer = ixgbe_get_supported_physical_layer(hw);
1873
1874 /* Media types with matching FreeBSD media defines */
1875 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_T)
1876 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1877 if (layer & IXGBE_PHYSICAL_LAYER_5000BASE_T)
1878 ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL);
1879 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_T)
1880 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL);
1881 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_T)
1882 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1883 if (layer & IXGBE_PHYSICAL_LAYER_100BASE_TX)
1884 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1885 if (layer & IXGBE_PHYSICAL_LAYER_10BASE_T)
1886 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1887
1888 if (hw->mac.type == ixgbe_mac_X550) {
1889 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL);
1890 ifmedia_add(sc->media, IFM_ETHER | IFM_5000_T, 0, NULL);
1891 }
1892
1893 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU ||
1894 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA) {
1895 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_TWINAX, 0,
1896 NULL);
1897 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1898 }
1899
1900 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR) {
1901 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_LR, 0, NULL);
1902 if (hw->phy.multispeed_fiber)
1903 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0,
1904 NULL);
1905 }
1906 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_BX) {
1907 device_printf(dev, "Media supported: 10Gbase-BX\n");
1908 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_BX, 0, NULL);
1909 }
1910 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR) {
1911 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL);
1912 if (hw->phy.multispeed_fiber)
1913 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0,
1914 NULL);
1915 } else if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX)
1916 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1917 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4)
1918 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL);
1919
1920 #ifdef IFM_ETH_XTYPE
1921 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR)
1922 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1923 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4)
1924 ifmedia_add( sc->media, IFM_ETHER | IFM_10G_KX4, 0, NULL);
1925 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX)
1926 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1927 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX)
1928 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_KX, 0, NULL);
1929 #else
1930 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR) {
1931 device_printf(dev, "Media supported: 10GbaseKR\n");
1932 device_printf(dev, "10GbaseKR mapped to 10GbaseSR\n");
1933 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SR, 0, NULL);
1934 }
1935 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4) {
1936 device_printf(dev, "Media supported: 10GbaseKX4\n");
1937 device_printf(dev, "10GbaseKX4 mapped to 10GbaseCX4\n");
1938 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_CX4, 0, NULL);
1939 }
1940 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX) {
1941 device_printf(dev, "Media supported: 1000baseKX\n");
1942 device_printf(dev, "1000baseKX mapped to 1000baseCX\n");
1943 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1944 }
1945 if (layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX) {
1946 device_printf(dev, "Media supported: 2500baseKX\n");
1947 device_printf(dev, "2500baseKX mapped to 2500baseSX\n");
1948 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_SX, 0, NULL);
1949 }
1950 #endif
1951 if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_BX) {
1952 device_printf(dev, "Media supported: 1000baseBX\n");
1953 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_BX, 0, NULL);
1954 }
1955
1956 if (hw->device_id == IXGBE_DEV_ID_82598AT) {
1957 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX,
1958 0, NULL);
1959 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1960 }
1961
1962 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1963 } /* ixgbe_add_media_types */
1964
1965 /************************************************************************
1966 * ixgbe_is_sfp
1967 ************************************************************************/
1968 static inline bool
ixgbe_is_sfp(struct ixgbe_hw * hw)1969 ixgbe_is_sfp(struct ixgbe_hw *hw)
1970 {
1971 switch (hw->mac.type) {
1972 case ixgbe_mac_82598EB:
1973 if (hw->phy.type == ixgbe_phy_nl)
1974 return (true);
1975 return (false);
1976 case ixgbe_mac_82599EB:
1977 switch (hw->mac.ops.get_media_type(hw)) {
1978 case ixgbe_media_type_fiber:
1979 case ixgbe_media_type_fiber_qsfp:
1980 return (true);
1981 default:
1982 return (false);
1983 }
1984 case ixgbe_mac_X550EM_x:
1985 case ixgbe_mac_X550EM_a:
1986 case ixgbe_mac_E610:
1987 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1988 return (true);
1989 return (false);
1990 default:
1991 return (false);
1992 }
1993 } /* ixgbe_is_sfp */
1994
1995 /************************************************************************
1996 * ixgbe_config_link
1997 ************************************************************************/
1998 static void
ixgbe_config_link(if_ctx_t ctx)1999 ixgbe_config_link(if_ctx_t ctx)
2000 {
2001 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2002 struct ixgbe_hw *hw = &sc->hw;
2003 u32 autoneg, err = 0;
2004 bool sfp, negotiate;
2005
2006 sfp = ixgbe_is_sfp(hw);
2007
2008 if (sfp) {
2009 /* ixgbe_if_stop() disables it on every 82599 SFP port. */
2010 ixgbe_enable_tx_laser(hw);
2011 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MOD);
2012 iflib_admin_intr_deferred(ctx);
2013 } else {
2014 if (hw->mac.ops.check_link)
2015 err = ixgbe_check_link(hw, &sc->link_speed,
2016 &sc->link_up, false);
2017 if (err)
2018 return;
2019 autoneg = hw->phy.autoneg_advertised;
2020 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
2021 err = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2022 &negotiate);
2023 if (err)
2024 return;
2025
2026 if (hw->mac.type == ixgbe_mac_X550 &&
2027 hw->phy.autoneg_advertised == 0) {
2028 /*
2029 * 2.5G and 5G autonegotiation speeds on X550
2030 * are disabled by default due to reported
2031 * interoperability issues with some switches.
2032 *
2033 * The second condition checks if any operations
2034 * involving setting autonegotiation speeds have
2035 * been performed prior to this ixgbe_config_link()
2036 * call.
2037 *
2038 * If hw->phy.autoneg_advertised does not
2039 * equal 0, this means that the user might have
2040 * set autonegotiation speeds via the sysctl
2041 * before bringing the interface up. In this
2042 * case, we should not disable 2.5G and 5G
2043 * since that speeds might be selected by the
2044 * user.
2045 *
2046 * Otherwise (i.e. if hw->phy.autoneg_advertised
2047 * is set to 0), it is the first time we set
2048 * autonegotiation preferences and the default
2049 * set of speeds should exclude 2.5G and 5G.
2050 */
2051 autoneg &= ~(IXGBE_LINK_SPEED_2_5GB_FULL |
2052 IXGBE_LINK_SPEED_5GB_FULL);
2053 }
2054
2055 if (hw->mac.type == ixgbe_mac_E610) {
2056 hw->phy.ops.init(hw);
2057 err = ixgbe_enable_lse(sc);
2058 if (err)
2059 device_printf(sc->dev,
2060 "Failed to enable Link Status Event, "
2061 "error: %d", err);
2062 }
2063
2064 if (hw->mac.ops.setup_link)
2065 err = hw->mac.ops.setup_link(hw, autoneg,
2066 sc->link_up);
2067 }
2068 } /* ixgbe_config_link */
2069
2070 /************************************************************************
2071 * ixgbe_update_stats_counters - Update board statistics counters.
2072 ************************************************************************/
2073 static void
ixgbe_update_stats_counters(struct ixgbe_softc * sc)2074 ixgbe_update_stats_counters(struct ixgbe_softc *sc)
2075 {
2076 struct ixgbe_hw *hw = &sc->hw;
2077 struct ixgbe_hw_stats *stats = &sc->stats.pf;
2078 u32 missed_rx = 0, mpc, bprc, lxon, lxoff;
2079 u32 lxoffrxc;
2080 u64 total_missed_rx = 0, total;
2081
2082 stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2083 stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2084 stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2085 stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2086 for (int i = 0; i < nitems(stats->mpc); i++) {
2087 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2088 missed_rx += mpc;
2089 stats->mpc[i] += mpc;
2090 total_missed_rx += stats->mpc[i];
2091 }
2092 stats->mpctotal = total_missed_rx;
2093
2094 for (int i = 0; i < 16; i++) {
2095 stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2096 stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2097 stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2098 }
2099 stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2100 stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2101 stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2102
2103 /* Hardware workaround, gprc counts missed packets */
2104 stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2105 stats->gprc -= missed_rx;
2106
2107 if (hw->mac.type != ixgbe_mac_82598EB) {
2108 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL) +
2109 ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2110 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL) +
2111 ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2112 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL) +
2113 ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2114 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2115 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2116 stats->lxoffrxc += lxoffrxc;
2117 } else {
2118 stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2119 lxoffrxc = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2120 stats->lxoffrxc += lxoffrxc;
2121 /* 82598 only has a counter in the high register */
2122 stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2123 stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2124 stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2125 }
2126
2127 /*
2128 * For watchdog management we need to know if we have been paused
2129 * during the last interval, so capture that here.
2130 */
2131 if (lxoffrxc)
2132 sc->shared->isc_pause_frames = 1;
2133
2134 /*
2135 * Workaround: mprc hardware is incorrectly counting
2136 * broadcasts, so for now we subtract those.
2137 */
2138 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2139 stats->bprc += bprc;
2140 stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2141 if (hw->mac.type == ixgbe_mac_82598EB)
2142 stats->mprc -= bprc;
2143
2144 stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2145 stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2146 stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2147 stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2148 stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2149 stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2150
2151 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2152 stats->lxontxc += lxon;
2153 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2154 stats->lxofftxc += lxoff;
2155 total = (u64)lxon + lxoff;
2156
2157 stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2158 stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2159 stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2160 stats->gptc -= total;
2161 stats->mptc -= total;
2162 stats->ptc64 -= total;
2163 stats->gotc -= total * ETHER_MIN_LEN;
2164
2165 stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2166 stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2167 stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2168 stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2169 stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2170 stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2171 stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2172 stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2173 stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2174 stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2175 stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2176 stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2177 stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2178 stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2179 stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2180 stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2181 stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2182 stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2183 /* Only read FCOE on 82599 */
2184 if (hw->mac.type != ixgbe_mac_82598EB) {
2185 stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2186 stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2187 stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2188 stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2189 stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2190 }
2191
2192 /* TLPIC and RLPIC are clear-on-read. */
2193 if (sc->feat_cap & IXGBE_FEATURE_EEE) {
2194 stats->tlpic += IXGBE_READ_REG(hw, IXGBE_TLPIC);
2195 stats->rlpic += IXGBE_READ_REG(hw, IXGBE_RLPIC);
2196 }
2197
2198 /* Fill out the OS statistics structure */
2199 IXGBE_SET_IPACKETS(sc, stats->gprc);
2200 IXGBE_SET_OPACKETS(sc, stats->gptc);
2201 IXGBE_SET_IBYTES(sc, stats->gorc);
2202 IXGBE_SET_OBYTES(sc, stats->gotc);
2203 IXGBE_SET_IMCASTS(sc, stats->mprc);
2204 IXGBE_SET_OMCASTS(sc, stats->mptc);
2205 IXGBE_SET_COLLISIONS(sc, 0);
2206 IXGBE_SET_IQDROPS(sc, total_missed_rx);
2207
2208 /*
2209 * Aggregate following types of errors as RX errors:
2210 * - CRC error count,
2211 * - illegal byte error count,
2212 * - missed packets count,
2213 * - length error count,
2214 * - undersized packets count,
2215 * - fragmented packets count,
2216 * - oversized packets count,
2217 * - jabber count.
2218 */
2219 IXGBE_SET_IERRORS(sc, stats->crcerrs + stats->illerrc +
2220 stats->mpctotal + stats->rlec + stats->ruc + stats->rfc +
2221 stats->roc + stats->rjc);
2222 } /* ixgbe_update_stats_counters */
2223
2224 /************************************************************************
2225 * ixgbe_add_hw_stats
2226 *
2227 * Add sysctl variables, one per statistic, to the system.
2228 ************************************************************************/
2229 static void
ixgbe_add_hw_stats(struct ixgbe_softc * sc)2230 ixgbe_add_hw_stats(struct ixgbe_softc *sc)
2231 {
2232 device_t dev = iflib_get_dev(sc->ctx);
2233 struct ix_rx_queue *rx_que;
2234 struct ix_tx_queue *tx_que;
2235 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
2236 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
2237 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
2238 struct ixgbe_hw_stats *stats = &sc->stats.pf;
2239 struct sysctl_oid *stat_node, *queue_node;
2240 struct sysctl_oid_list *stat_list, *queue_list;
2241 int i;
2242
2243 #define QUEUE_NAME_LEN 32
2244 char namebuf[QUEUE_NAME_LEN];
2245
2246 /* Driver Statistics */
2247 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
2248 CTLFLAG_RD, &sc->dropped_pkts, "Driver dropped packets");
2249 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
2250 CTLFLAG_RD, &sc->link_irq, "Link MSI-X IRQ Handled");
2251
2252 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues;
2253 i++, tx_que++) {
2254 struct tx_ring *txr = &tx_que->txr;
2255 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i);
2256 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
2257 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
2258 queue_list = SYSCTL_CHILDREN(queue_node);
2259
2260 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
2261 CTLTYPE_UINT | CTLFLAG_RD, txr, 0,
2262 ixgbe_sysctl_tdh_handler, "IU",
2263 "Transmit Descriptor Head");
2264 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
2265 CTLTYPE_UINT | CTLFLAG_RD, txr, 0,
2266 ixgbe_sysctl_tdt_handler, "IU",
2267 "Transmit Descriptor Tail");
2268 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx",
2269 CTLFLAG_RD, &txr->tso_tx, "TSO");
2270 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets",
2271 CTLFLAG_RD, &txr->total_packets,
2272 "Queue Packets Transmitted");
2273 }
2274
2275 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues;
2276 i++, rx_que++) {
2277 struct rx_ring *rxr = &rx_que->rxr;
2278 snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i);
2279 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
2280 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
2281 queue_list = SYSCTL_CHILDREN(queue_node);
2282
2283 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
2284 CTLTYPE_UINT | CTLFLAG_RW,
2285 &sc->rx_queues[i], 0,
2286 ixgbe_sysctl_interrupt_rate_handler, "IU",
2287 "Interrupt Rate");
2288 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs",
2289 CTLFLAG_RD, &(sc->rx_queues[i].irqs),
2290 "irqs on this queue");
2291 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
2292 CTLTYPE_UINT | CTLFLAG_RD, rxr, 0,
2293 ixgbe_sysctl_rdh_handler, "IU",
2294 "Receive Descriptor Head");
2295 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
2296 CTLTYPE_UINT | CTLFLAG_RD, rxr, 0,
2297 ixgbe_sysctl_rdt_handler, "IU",
2298 "Receive Descriptor Tail");
2299 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets",
2300 CTLFLAG_RD, &rxr->rx_packets, "Queue Packets Received");
2301 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes",
2302 CTLFLAG_RD, &rxr->rx_bytes, "Queue Bytes Received");
2303 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_copies",
2304 CTLFLAG_RD, &rxr->rx_copies, "Copied RX Frames");
2305 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_discarded",
2306 CTLFLAG_RD, &rxr->rx_discarded, "Discarded RX packets");
2307 }
2308
2309 /* MAC stats get their own sub node */
2310 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
2311 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MAC Statistics");
2312 stat_list = SYSCTL_CHILDREN(stat_node);
2313
2314 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_errs",
2315 CTLFLAG_RD, &sc->ierrors, IXGBE_SYSCTL_DESC_RX_ERRS);
2316 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
2317 CTLFLAG_RD, &stats->crcerrs, "CRC Errors");
2318 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "ill_errs",
2319 CTLFLAG_RD, &stats->illerrc, "Illegal Byte Errors");
2320 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "byte_errs",
2321 CTLFLAG_RD, &stats->errbc, "Byte Errors");
2322 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "short_discards",
2323 CTLFLAG_RD, &stats->mspdc, "MAC Short Packets Discarded");
2324 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "local_faults",
2325 CTLFLAG_RD, &stats->mlfc, "MAC Local Faults");
2326 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "remote_faults",
2327 CTLFLAG_RD, &stats->mrfc, "MAC Remote Faults");
2328 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rec_len_errs",
2329 CTLFLAG_RD, &stats->rlec, "Receive Length Errors");
2330 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_missed_packets",
2331 CTLFLAG_RD, &stats->mpctotal, "RX Missed Packet Count");
2332
2333 /* Flow Control stats */
2334 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
2335 CTLFLAG_RD, &stats->lxontxc, "Link XON Transmitted");
2336 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
2337 CTLFLAG_RD, &stats->lxonrxc, "Link XON Received");
2338 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
2339 CTLFLAG_RD, &stats->lxofftxc, "Link XOFF Transmitted");
2340 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
2341 CTLFLAG_RD, &stats->lxoffrxc, "Link XOFF Received");
2342
2343 /* Packet Reception Stats */
2344 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_octets_rcvd",
2345 CTLFLAG_RD, &stats->tor, "Total Octets Received");
2346 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_rcvd",
2347 CTLFLAG_RD, &stats->gorc, "Good Octets Received");
2348 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_rcvd",
2349 CTLFLAG_RD, &stats->tpr, "Total Packets Received");
2350 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_rcvd",
2351 CTLFLAG_RD, &stats->gprc, "Good Packets Received");
2352 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_rcvd",
2353 CTLFLAG_RD, &stats->mprc, "Multicast Packets Received");
2354 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_rcvd",
2355 CTLFLAG_RD, &stats->bprc, "Broadcast Packets Received");
2356 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
2357 CTLFLAG_RD, &stats->prc64, "64 byte frames received ");
2358 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
2359 CTLFLAG_RD, &stats->prc127, "65-127 byte frames received");
2360 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
2361 CTLFLAG_RD, &stats->prc255, "128-255 byte frames received");
2362 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
2363 CTLFLAG_RD, &stats->prc511, "256-511 byte frames received");
2364 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
2365 CTLFLAG_RD, &stats->prc1023, "512-1023 byte frames received");
2366 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
2367 CTLFLAG_RD, &stats->prc1522, "1023-1522 byte frames received");
2368 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersized",
2369 CTLFLAG_RD, &stats->ruc, "Receive Undersized");
2370 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
2371 CTLFLAG_RD, &stats->rfc, "Fragmented Packets Received ");
2372 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversized",
2373 CTLFLAG_RD, &stats->roc, "Oversized Packets Received");
2374 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabberd",
2375 CTLFLAG_RD, &stats->rjc, "Received Jabber");
2376 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_rcvd",
2377 CTLFLAG_RD, &stats->mngprc, "Management Packets Received");
2378 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_drpd",
2379 CTLFLAG_RD, &stats->mngpdc, "Management Packets Dropped");
2380 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "checksum_errs",
2381 CTLFLAG_RD, &stats->xec, "Checksum Errors");
2382
2383 /* Packet Transmission Stats */
2384 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
2385 CTLFLAG_RD, &stats->gotc, "Good Octets Transmitted");
2386 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
2387 CTLFLAG_RD, &stats->tpt, "Total Packets Transmitted");
2388 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
2389 CTLFLAG_RD, &stats->gptc, "Good Packets Transmitted");
2390 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
2391 CTLFLAG_RD, &stats->bptc, "Broadcast Packets Transmitted");
2392 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
2393 CTLFLAG_RD, &stats->mptc, "Multicast Packets Transmitted");
2394 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "management_pkts_txd",
2395 CTLFLAG_RD, &stats->mngptc, "Management Packets Transmitted");
2396 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
2397 CTLFLAG_RD, &stats->ptc64, "64 byte frames transmitted ");
2398 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
2399 CTLFLAG_RD, &stats->ptc127, "65-127 byte frames transmitted");
2400 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
2401 CTLFLAG_RD, &stats->ptc255, "128-255 byte frames transmitted");
2402 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
2403 CTLFLAG_RD, &stats->ptc511, "256-511 byte frames transmitted");
2404 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
2405 CTLFLAG_RD, &stats->ptc1023, "512-1023 byte frames transmitted");
2406 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
2407 CTLFLAG_RD, &stats->ptc1522, "1024-1522 byte frames transmitted");
2408 } /* ixgbe_add_hw_stats */
2409
2410 /************************************************************************
2411 * ixgbe_sysctl_tdh_handler - Transmit Descriptor Head handler function
2412 *
2413 * Retrieves the TDH value from the hardware
2414 ************************************************************************/
2415 static int
ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS)2416 ixgbe_sysctl_tdh_handler(SYSCTL_HANDLER_ARGS)
2417 {
2418 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1);
2419 int error;
2420 unsigned int val;
2421
2422 if (!txr)
2423 return (0);
2424
2425
2426 if (atomic_load_acq_int(&txr->sc->recovery_mode))
2427 return (EPERM);
2428
2429 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDH(txr->me));
2430 error = sysctl_handle_int(oidp, &val, 0, req);
2431 if (error || !req->newptr)
2432 return error;
2433
2434 return (0);
2435 } /* ixgbe_sysctl_tdh_handler */
2436
2437 /************************************************************************
2438 * ixgbe_sysctl_tdt_handler - Transmit Descriptor Tail handler function
2439 *
2440 * Retrieves the TDT value from the hardware
2441 ************************************************************************/
2442 static int
ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS)2443 ixgbe_sysctl_tdt_handler(SYSCTL_HANDLER_ARGS)
2444 {
2445 struct tx_ring *txr = ((struct tx_ring *)oidp->oid_arg1);
2446 int error;
2447 unsigned int val;
2448
2449 if (!txr)
2450 return (0);
2451
2452 if (atomic_load_acq_int(&txr->sc->recovery_mode))
2453 return (EPERM);
2454
2455 val = IXGBE_READ_REG(&txr->sc->hw, IXGBE_TDT(txr->me));
2456 error = sysctl_handle_int(oidp, &val, 0, req);
2457 if (error || !req->newptr)
2458 return error;
2459
2460 return (0);
2461 } /* ixgbe_sysctl_tdt_handler */
2462
2463 /************************************************************************
2464 * ixgbe_sysctl_rdh_handler - Receive Descriptor Head handler function
2465 *
2466 * Retrieves the RDH value from the hardware
2467 ************************************************************************/
2468 static int
ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS)2469 ixgbe_sysctl_rdh_handler(SYSCTL_HANDLER_ARGS)
2470 {
2471 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1);
2472 int error;
2473 unsigned int val;
2474
2475 if (!rxr)
2476 return (0);
2477
2478 if (atomic_load_acq_int(&rxr->sc->recovery_mode))
2479 return (EPERM);
2480
2481 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDH(rxr->me));
2482 error = sysctl_handle_int(oidp, &val, 0, req);
2483 if (error || !req->newptr)
2484 return error;
2485
2486 return (0);
2487 } /* ixgbe_sysctl_rdh_handler */
2488
2489 /************************************************************************
2490 * ixgbe_sysctl_rdt_handler - Receive Descriptor Tail handler function
2491 *
2492 * Retrieves the RDT value from the hardware
2493 ************************************************************************/
2494 static int
ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS)2495 ixgbe_sysctl_rdt_handler(SYSCTL_HANDLER_ARGS)
2496 {
2497 struct rx_ring *rxr = ((struct rx_ring *)oidp->oid_arg1);
2498 int error;
2499 unsigned int val;
2500
2501 if (!rxr)
2502 return (0);
2503
2504 if (atomic_load_acq_int(&rxr->sc->recovery_mode))
2505 return (EPERM);
2506
2507 val = IXGBE_READ_REG(&rxr->sc->hw, IXGBE_RDT(rxr->me));
2508 error = sysctl_handle_int(oidp, &val, 0, req);
2509 if (error || !req->newptr)
2510 return error;
2511
2512 return (0);
2513 } /* ixgbe_sysctl_rdt_handler */
2514
2515 /************************************************************************
2516 * ixgbe_if_vlan_register
2517 *
2518 * Run via vlan config EVENT, it enables us to use the
2519 * HW Filter table since we can get the vlan id. This
2520 * just creates the entry in the soft version of the
2521 * VFTA, init will repopulate the real table.
2522 ************************************************************************/
2523 static void
ixgbe_if_vlan_register(if_ctx_t ctx,u16 vtag)2524 ixgbe_if_vlan_register(if_ctx_t ctx, u16 vtag)
2525 {
2526 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2527 bool present;
2528 u16 index;
2529 u32 mask;
2530
2531 index = (vtag >> 5) & 0x7F;
2532 mask = 1U << (vtag & 0x1F);
2533 present = (sc->shadow_vfta[index] & mask) != 0;
2534 sc->shadow_vfta[index] |= mask;
2535 if (!present)
2536 ++sc->num_vlans;
2537 #ifdef PCI_IOV
2538 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) != 0 &&
2539 sc->iov_vfta_valid && !sc->iov_vlan_promisc)
2540 (void)ixgbe_set_vfta(&sc->hw, vtag, sc->pool, true, true);
2541 #endif
2542 ixgbe_setup_vlan_hw_support(ctx);
2543 } /* ixgbe_if_vlan_register */
2544
2545 /************************************************************************
2546 * ixgbe_if_vlan_unregister
2547 *
2548 * Run via vlan unconfig EVENT, remove our entry in the soft vfta.
2549 ************************************************************************/
2550 static void
ixgbe_if_vlan_unregister(if_ctx_t ctx,u16 vtag)2551 ixgbe_if_vlan_unregister(if_ctx_t ctx, u16 vtag)
2552 {
2553 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2554 bool present;
2555 u16 index;
2556 u32 mask;
2557
2558 index = (vtag >> 5) & 0x7F;
2559 mask = 1U << (vtag & 0x1F);
2560 present = (sc->shadow_vfta[index] & mask) != 0;
2561 sc->shadow_vfta[index] &= ~mask;
2562 if (present)
2563 --sc->num_vlans;
2564 #ifdef PCI_IOV
2565 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) != 0 &&
2566 sc->iov_vfta_valid && !sc->iov_vlan_promisc)
2567 (void)ixgbe_set_vfta(&sc->hw, vtag, sc->pool, false, true);
2568 #endif
2569 ixgbe_setup_vlan_hw_support(ctx);
2570 } /* ixgbe_if_vlan_unregister */
2571
2572 #ifdef PCI_IOV
2573 static bool
ixgbe_iov_pf_owns_vlan(const struct ixgbe_softc * sc,u16 vlan)2574 ixgbe_iov_pf_owns_vlan(const struct ixgbe_softc *sc, u16 vlan)
2575 {
2576
2577 return ((sc->shadow_vfta[vlan >> 5] &
2578 (1U << (vlan & 0x1f))) != 0);
2579 }
2580
2581 /*
2582 * start_hw clears both VFTA and VLVF. Reconstruct the shared tables from
2583 * PF and VF desired state after every reset or filtering-mode transition.
2584 * Allocate VF entries first so PF-only VLANs cannot exhaust VLVF.
2585 */
2586 static void
ixgbe_iov_vlan_rebuild(struct ixgbe_softc * sc,bool promisc)2587 ixgbe_iov_vlan_rebuild(struct ixgbe_softc *sc, bool promisc)
2588 {
2589 struct ixgbe_hw *hw;
2590 struct ixgbe_vf *vf;
2591 u32 vfta[IXGBE_VFTA_SIZE];
2592 u32 bits, vlan, vlvf;
2593 int bit, failures, i, word;
2594
2595 hw = &sc->hw;
2596 bcopy(sc->shadow_vfta, vfta, sizeof(vfta));
2597 (void)ixgbe_clear_vfta(hw);
2598 failures = 0;
2599 for (i = 0; i < sc->num_vfs; i++) {
2600 vf = &sc->vfs[i];
2601 if ((vf->flags & IXGBE_VF_ACTIVE) == 0)
2602 continue;
2603 if (vf->default_vlan == 0 &&
2604 ixgbe_set_vfta(hw, 0, vf->pool, true, false) !=
2605 IXGBE_SUCCESS)
2606 failures++;
2607 for (word = 0; word < IXGBE_VFTA_SIZE; word++) {
2608 bits = vf->vlans[word];
2609 while (bits != 0) {
2610 bit = ffs(bits) - 1;
2611 vlan = word * 32 + bit;
2612 if (ixgbe_set_vfta(hw, vlan, vf->pool, true,
2613 false) == IXGBE_SUCCESS)
2614 vfta[word] |= 1U << bit;
2615 else
2616 failures++;
2617 bits &= ~(1U << bit);
2618 }
2619 }
2620 }
2621 if (ixgbe_set_vfta(hw, 0, sc->pool, true, false) != IXGBE_SUCCESS)
2622 failures++;
2623
2624 /* Add the PF to shared entries, or every entry in promiscuous mode. */
2625 for (i = 1; i < IXGBE_VLVF_ENTRIES; i++) {
2626 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
2627 if ((vlvf & IXGBE_VLVF_VIEN) == 0)
2628 continue;
2629 vlan = vlvf & IXGBE_VLVF_VLANID_MASK;
2630 if (promisc || ixgbe_iov_pf_owns_vlan(sc, vlan))
2631 (void)ixgbe_set_vfta(hw, vlan, sc->pool, true, true);
2632 vfta[vlan >> 5] |= 1U << (vlan & 0x1f);
2633 }
2634 if (promisc)
2635 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2636 vfta[i] = UINT32_MAX;
2637 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2638 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), vfta[i]);
2639 if (failures != 0)
2640 device_printf(sc->dev,
2641 "VLAN pool restore failed for %d memberships\n", failures);
2642 }
2643
2644 static void
ixgbe_iov_vlan_sync(struct ixgbe_softc * sc,bool promisc)2645 ixgbe_iov_vlan_sync(struct ixgbe_softc *sc, bool promisc)
2646 {
2647
2648 if (sc->iov_vfta_valid && sc->iov_vlan_promisc == promisc)
2649 return;
2650 ixgbe_iov_vlan_rebuild(sc, promisc);
2651 sc->iov_vlan_promisc = promisc;
2652 sc->iov_vfta_valid = true;
2653 }
2654 #endif
2655
2656 /************************************************************************
2657 * ixgbe_setup_vlan_hw_support
2658 ************************************************************************/
2659 void
ixgbe_setup_vlan_hw_support(if_ctx_t ctx)2660 ixgbe_setup_vlan_hw_support(if_ctx_t ctx)
2661 {
2662 if_t ifp = iflib_get_ifp(ctx);
2663 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2664 struct ixgbe_hw *hw = &sc->hw;
2665 struct rx_ring *rxr;
2666 bool strip;
2667 int i;
2668 u32 ctrl;
2669
2670 strip = sc->num_vlans != 0 &&
2671 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0;
2672 for (i = 0; i < sc->num_rx_queues; i++) {
2673 rxr = &sc->rx_queues[i].rxr;
2674 /* On 82599 and newer VLAN stripping is per receive queue. */
2675 if (hw->mac.type != ixgbe_mac_82598EB) {
2676 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me));
2677 if (strip)
2678 ctrl |= IXGBE_RXDCTL_VME;
2679 else
2680 ctrl &= ~IXGBE_RXDCTL_VME;
2681 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), ctrl);
2682 }
2683 rxr->vtag_strip = strip;
2684 }
2685
2686 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2687 if (hw->mac.type == ixgbe_mac_82598EB) {
2688 if (strip)
2689 ctrl |= IXGBE_VLNCTRL_VME;
2690 else
2691 ctrl &= ~IXGBE_VLNCTRL_VME;
2692 }
2693
2694 /* Always admit priority-tagged frames. */
2695 sc->shadow_vfta[0] |= 1U;
2696
2697 #ifdef PCI_IOV
2698 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) != 0) {
2699 /*
2700 * VFE must remain enabled to enforce per-pool VLAN ownership.
2701 */
2702 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2703 ctrl |= IXGBE_VLNCTRL_VFE;
2704 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2705 ixgbe_iov_vlan_sync(sc,
2706 (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0);
2707 return;
2708 }
2709 #endif
2710
2711 if (!strip ||
2712 (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) {
2713 ctrl |= IXGBE_VLNCTRL_CFIEN;
2714 ctrl &= ~IXGBE_VLNCTRL_VFE;
2715 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2716 return;
2717 }
2718
2719 /* A soft reset clears VFTA, so restore the PF's desired bitmap. */
2720 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2721 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), sc->shadow_vfta[i]);
2722 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2723 ctrl |= IXGBE_VLNCTRL_VFE;
2724 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2725 } /* ixgbe_setup_vlan_hw_support */
2726
2727 /************************************************************************
2728 * ixgbe_get_slot_info
2729 *
2730 * Get the width and transaction speed of
2731 * the slot this adapter is plugged into.
2732 ************************************************************************/
2733 static void
ixgbe_get_slot_info(struct ixgbe_softc * sc)2734 ixgbe_get_slot_info(struct ixgbe_softc *sc)
2735 {
2736 device_t dev = iflib_get_dev(sc->ctx);
2737 struct ixgbe_hw *hw = &sc->hw;
2738 int bus_info_valid = true;
2739 u32 offset;
2740 u16 link;
2741
2742 /* Some devices are behind an internal bridge */
2743 switch (hw->device_id) {
2744 case IXGBE_DEV_ID_82599_SFP_SF_QP:
2745 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
2746 goto get_parent_info;
2747 default:
2748 break;
2749 }
2750
2751 ixgbe_get_bus_info(hw);
2752
2753 /*
2754 * Some devices don't use PCI-E, but there is no need
2755 * to display "Unknown" for bus speed and width.
2756 */
2757 switch (hw->mac.type) {
2758 case ixgbe_mac_X550EM_x:
2759 case ixgbe_mac_X550EM_a:
2760 return;
2761 default:
2762 goto display;
2763 }
2764
2765 get_parent_info:
2766 /*
2767 * For the Quad port adapter we need to parse back
2768 * up the PCI tree to find the speed of the expansion
2769 * slot into which this adapter is plugged. A bit more work.
2770 */
2771 dev = device_get_parent(device_get_parent(dev));
2772 #ifdef IXGBE_DEBUG
2773 device_printf(dev, "parent pcib = %x,%x,%x\n", pci_get_bus(dev),
2774 pci_get_slot(dev), pci_get_function(dev));
2775 #endif
2776 dev = device_get_parent(device_get_parent(dev));
2777 #ifdef IXGBE_DEBUG
2778 device_printf(dev, "slot pcib = %x,%x,%x\n", pci_get_bus(dev),
2779 pci_get_slot(dev), pci_get_function(dev));
2780 #endif
2781 /* Now get the PCI Express Capabilities offset */
2782 if (pci_find_cap(dev, PCIY_EXPRESS, &offset)) {
2783 /*
2784 * Hmm...can't get PCI-Express capabilities.
2785 * Falling back to default method.
2786 */
2787 bus_info_valid = false;
2788 ixgbe_get_bus_info(hw);
2789 goto display;
2790 }
2791 /* ...and read the Link Status Register */
2792 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2);
2793 ixgbe_set_pci_config_data_generic(hw, link);
2794
2795 display:
2796 device_printf(dev, "PCI Express Bus: Speed %s Width %s\n",
2797 ((hw->bus.speed == ixgbe_bus_speed_16000) ? "16.0GT/s" :
2798 (hw->bus.speed == ixgbe_bus_speed_8000) ? "8.0GT/s" :
2799 (hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0GT/s" :
2800 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5GT/s" :
2801 "Unknown"),
2802 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "x8" :
2803 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "x4" :
2804 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "x1" :
2805 "Unknown"));
2806
2807 if (bus_info_valid) {
2808 if ((hw->device_id != IXGBE_DEV_ID_82599_SFP_SF_QP) &&
2809 ((hw->bus.width <= ixgbe_bus_width_pcie_x4) &&
2810 (hw->bus.speed == ixgbe_bus_speed_2500))) {
2811 device_printf(dev,
2812 "PCI-Express bandwidth available for this card"
2813 " is not sufficient for optimal performance.\n");
2814 device_printf(dev,
2815 "For optimal performance a x8 PCIE, or x4 PCIE"
2816 " Gen2 slot is required.\n");
2817 }
2818 if ((hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP) &&
2819 ((hw->bus.width <= ixgbe_bus_width_pcie_x8) &&
2820 (hw->bus.speed < ixgbe_bus_speed_8000))) {
2821 device_printf(dev,
2822 "PCI-Express bandwidth available for this card"
2823 " is not sufficient for optimal performance.\n");
2824 device_printf(dev,
2825 "For optimal performance a x8 PCIE Gen3 slot is"
2826 " required.\n");
2827 }
2828 } else
2829 device_printf(dev,
2830 "Unable to determine slot speed/width. The speed/width"
2831 " reported are that of the internal switch.\n");
2832
2833 return;
2834 } /* ixgbe_get_slot_info */
2835
2836 /************************************************************************
2837 * ixgbe_if_msix_intr_assign
2838 *
2839 * Setup MSI-X Interrupt resources and handlers
2840 ************************************************************************/
2841 static int
ixgbe_if_msix_intr_assign(if_ctx_t ctx,int msix)2842 ixgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
2843 {
2844 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2845 struct ix_rx_queue *rx_que = sc->rx_queues;
2846 struct ix_tx_queue *tx_que;
2847 int error, rid, vector = 0;
2848 char buf[16];
2849
2850 /* Admin Que is vector 0*/
2851 rid = vector + 1;
2852 for (int i = 0; i < sc->num_rx_queues; i++, vector++, rx_que++) {
2853 rid = vector + 1;
2854
2855 snprintf(buf, sizeof(buf), "rxq%d", i);
2856 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid,
2857 IFLIB_INTR_RXTX, ixgbe_msix_que, rx_que, rx_que->rxr.me,
2858 buf);
2859
2860 if (error) {
2861 device_printf(iflib_get_dev(ctx),
2862 "Failed to allocate que int %d err: %d",
2863 i,error);
2864 sc->num_rx_queues = i + 1;
2865 goto fail;
2866 }
2867
2868 rx_que->msix = vector;
2869 }
2870 for (int i = 0; i < sc->num_tx_queues; i++) {
2871 snprintf(buf, sizeof(buf), "txq%d", i);
2872 tx_que = &sc->tx_queues[i];
2873 tx_que->msix = i % sc->num_rx_queues;
2874 iflib_softirq_alloc_generic(ctx,
2875 &sc->rx_queues[tx_que->msix].que_irq,
2876 IFLIB_INTR_TX, tx_que, tx_que->txr.me, buf);
2877 }
2878 rid = vector + 1;
2879 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid,
2880 IFLIB_INTR_ADMIN, ixgbe_msix_link, sc, 0, "aq");
2881 if (error) {
2882 device_printf(iflib_get_dev(ctx),
2883 "Failed to register admin handler");
2884 return (error);
2885 }
2886
2887 sc->vector = vector;
2888
2889 return (0);
2890 fail:
2891 iflib_irq_free(ctx, &sc->irq);
2892 rx_que = sc->rx_queues;
2893 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++)
2894 iflib_irq_free(ctx, &rx_que->que_irq);
2895
2896 return (error);
2897 } /* ixgbe_if_msix_intr_assign */
2898
2899 static inline void
ixgbe_perform_aim(struct ixgbe_softc * sc,struct ix_rx_queue * que)2900 ixgbe_perform_aim(struct ixgbe_softc *sc, struct ix_rx_queue *que)
2901 {
2902 uint32_t newitr = 0;
2903 struct rx_ring *rxr = &que->rxr;
2904 /* FIXME struct tx_ring *txr = ... ->txr; */
2905
2906 /*
2907 * Do Adaptive Interrupt Moderation:
2908 * - Write out last calculated setting
2909 * - Calculate based on average size over
2910 * the last interval.
2911 */
2912 if (que->eitr_setting) {
2913 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(que->msix),
2914 que->eitr_setting);
2915 }
2916
2917 que->eitr_setting = 0;
2918 /* Idle, do nothing */
2919 if (rxr->bytes == 0) {
2920 /* FIXME && txr->bytes == 0 */
2921 return;
2922 }
2923
2924 if ((rxr->bytes) && (rxr->packets))
2925 newitr = rxr->bytes / rxr->packets;
2926 /* FIXME for transmit accounting
2927 * if ((txr->bytes) && (txr->packets))
2928 * newitr = txr->bytes/txr->packets;
2929 * if ((rxr->bytes) && (rxr->packets))
2930 * newitr = max(newitr, (rxr->bytes / rxr->packets));
2931 */
2932
2933 newitr += 24; /* account for hardware frame, crc */
2934 /* set an upper boundary */
2935 newitr = min(newitr, 3000);
2936
2937 /* Be nice to the mid range */
2938 if ((newitr > 300) && (newitr < 1200)) {
2939 newitr = (newitr / 3);
2940 } else {
2941 newitr = (newitr / 2);
2942 }
2943
2944 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
2945 newitr |= newitr << 16;
2946 } else {
2947 newitr |= IXGBE_EITR_CNT_WDIS;
2948 }
2949
2950 /* save for next interrupt */
2951 que->eitr_setting = newitr;
2952
2953 /* Reset state */
2954 /* FIXME txr->bytes = 0; */
2955 /* FIXME txr->packets = 0; */
2956 rxr->bytes = 0;
2957 rxr->packets = 0;
2958
2959 return;
2960 }
2961
2962 /*********************************************************************
2963 * ixgbe_msix_que - MSI-X Queue Interrupt Service routine
2964 **********************************************************************/
2965 static int
ixgbe_msix_que(void * arg)2966 ixgbe_msix_que(void *arg)
2967 {
2968 struct ix_rx_queue *que = arg;
2969 struct ixgbe_softc *sc = que->sc;
2970
2971 /* Protect against spurious interrupts */
2972 if (!iflib_is_running(sc->ctx))
2973 return (FILTER_HANDLED);
2974
2975 ixgbe_disable_queue(sc, que->msix);
2976 ++que->irqs;
2977
2978 /* Check for AIM */
2979 if (sc->enable_aim) {
2980 ixgbe_perform_aim(sc, que);
2981 }
2982
2983 return (FILTER_SCHEDULE_THREAD);
2984 } /* ixgbe_msix_que */
2985
2986 /************************************************************************
2987 * ixgbe_media_status - Media Ioctl callback
2988 *
2989 * Called whenever the user queries the status of
2990 * the interface using ifconfig.
2991 ************************************************************************/
2992 static void
ixgbe_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)2993 ixgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2994 {
2995 struct ixgbe_softc *sc = iflib_get_softc(ctx);
2996 struct ixgbe_hw *hw = &sc->hw;
2997 int layer;
2998
2999 INIT_DEBUGOUT("ixgbe_if_media_status: begin");
3000
3001 ifmr->ifm_status = IFM_AVALID;
3002 ifmr->ifm_active = IFM_ETHER;
3003
3004 if (!sc->link_active)
3005 return;
3006
3007 ifmr->ifm_status |= IFM_ACTIVE;
3008 layer = sc->phy_layer;
3009
3010 if (layer & IXGBE_PHYSICAL_LAYERS_BASE_T_ALL)
3011 switch (sc->link_speed) {
3012 case IXGBE_LINK_SPEED_10GB_FULL:
3013 ifmr->ifm_active |= IFM_10G_T | IFM_FDX;
3014 break;
3015 case IXGBE_LINK_SPEED_5GB_FULL:
3016 ifmr->ifm_active |= IFM_5000_T | IFM_FDX;
3017 break;
3018 case IXGBE_LINK_SPEED_2_5GB_FULL:
3019 ifmr->ifm_active |= IFM_2500_T | IFM_FDX;
3020 break;
3021 case IXGBE_LINK_SPEED_1GB_FULL:
3022 ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
3023 break;
3024 case IXGBE_LINK_SPEED_100_FULL:
3025 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
3026 break;
3027 case IXGBE_LINK_SPEED_10_FULL:
3028 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
3029 break;
3030 }
3031 if (layer & IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU ||
3032 layer & IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA)
3033 switch (sc->link_speed) {
3034 case IXGBE_LINK_SPEED_10GB_FULL:
3035 ifmr->ifm_active |= IFM_10G_TWINAX | IFM_FDX;
3036 break;
3037 case IXGBE_LINK_SPEED_1GB_FULL:
3038 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX;
3039 break;
3040 }
3041 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LR)
3042 switch (sc->link_speed) {
3043 case IXGBE_LINK_SPEED_10GB_FULL:
3044 ifmr->ifm_active |= IFM_10G_LR | IFM_FDX;
3045 break;
3046 case IXGBE_LINK_SPEED_1GB_FULL:
3047 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX;
3048 break;
3049 }
3050 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_BX &&
3051 sc->link_speed == IXGBE_LINK_SPEED_10GB_FULL)
3052 ifmr->ifm_active |= IFM_10G_BX | IFM_FDX;
3053 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_LRM)
3054 switch (sc->link_speed) {
3055 case IXGBE_LINK_SPEED_10GB_FULL:
3056 ifmr->ifm_active |= IFM_10G_LRM | IFM_FDX;
3057 break;
3058 case IXGBE_LINK_SPEED_1GB_FULL:
3059 ifmr->ifm_active |= IFM_1000_LX | IFM_FDX;
3060 break;
3061 }
3062 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_SR ||
3063 layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX)
3064 switch (sc->link_speed) {
3065 case IXGBE_LINK_SPEED_10GB_FULL:
3066 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX;
3067 break;
3068 case IXGBE_LINK_SPEED_1GB_FULL:
3069 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
3070 break;
3071 }
3072 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_CX4)
3073 switch (sc->link_speed) {
3074 case IXGBE_LINK_SPEED_10GB_FULL:
3075 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX;
3076 break;
3077 }
3078 /*
3079 * XXX: These need to use the proper media types once
3080 * they're added.
3081 */
3082 #ifndef IFM_ETH_XTYPE
3083 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR)
3084 switch (sc->link_speed) {
3085 case IXGBE_LINK_SPEED_10GB_FULL:
3086 ifmr->ifm_active |= IFM_10G_SR | IFM_FDX;
3087 break;
3088 case IXGBE_LINK_SPEED_2_5GB_FULL:
3089 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
3090 break;
3091 case IXGBE_LINK_SPEED_1GB_FULL:
3092 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX;
3093 break;
3094 }
3095 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 ||
3096 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX ||
3097 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX)
3098 switch (sc->link_speed) {
3099 case IXGBE_LINK_SPEED_10GB_FULL:
3100 ifmr->ifm_active |= IFM_10G_CX4 | IFM_FDX;
3101 break;
3102 case IXGBE_LINK_SPEED_2_5GB_FULL:
3103 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
3104 break;
3105 case IXGBE_LINK_SPEED_1GB_FULL:
3106 ifmr->ifm_active |= IFM_1000_CX | IFM_FDX;
3107 break;
3108 }
3109 #else
3110 if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KR)
3111 switch (sc->link_speed) {
3112 case IXGBE_LINK_SPEED_10GB_FULL:
3113 ifmr->ifm_active |= IFM_10G_KR | IFM_FDX;
3114 break;
3115 case IXGBE_LINK_SPEED_2_5GB_FULL:
3116 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX;
3117 break;
3118 case IXGBE_LINK_SPEED_1GB_FULL:
3119 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX;
3120 break;
3121 }
3122 else if (layer & IXGBE_PHYSICAL_LAYER_10GBASE_KX4 ||
3123 layer & IXGBE_PHYSICAL_LAYER_2500BASE_KX ||
3124 layer & IXGBE_PHYSICAL_LAYER_1000BASE_KX)
3125 switch (sc->link_speed) {
3126 case IXGBE_LINK_SPEED_10GB_FULL:
3127 ifmr->ifm_active |= IFM_10G_KX4 | IFM_FDX;
3128 break;
3129 case IXGBE_LINK_SPEED_2_5GB_FULL:
3130 ifmr->ifm_active |= IFM_2500_KX | IFM_FDX;
3131 break;
3132 case IXGBE_LINK_SPEED_1GB_FULL:
3133 ifmr->ifm_active |= IFM_1000_KX | IFM_FDX;
3134 break;
3135 }
3136 #endif
3137
3138 /* If nothing is recognized... */
3139 if (IFM_SUBTYPE(ifmr->ifm_active) == 0)
3140 ifmr->ifm_active |= IFM_UNKNOWN;
3141
3142 /* Display current flow control setting used on link */
3143 if (hw->fc.current_mode == ixgbe_fc_rx_pause ||
3144 hw->fc.current_mode == ixgbe_fc_full)
3145 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
3146 if (hw->fc.current_mode == ixgbe_fc_tx_pause ||
3147 hw->fc.current_mode == ixgbe_fc_full)
3148 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
3149 } /* ixgbe_media_status */
3150
3151 /************************************************************************
3152 * ixgbe_media_change - Media Ioctl callback
3153 *
3154 * Called when the user changes speed/duplex using
3155 * media/mediopt option with ifconfig.
3156 ************************************************************************/
3157 static int
ixgbe_if_media_change(if_ctx_t ctx)3158 ixgbe_if_media_change(if_ctx_t ctx)
3159 {
3160 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3161 struct ifmedia *ifm = iflib_get_media(ctx);
3162 struct ixgbe_hw *hw = &sc->hw;
3163 ixgbe_link_speed speed = 0;
3164
3165 INIT_DEBUGOUT("ixgbe_if_media_change: begin");
3166
3167 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3168 return (EINVAL);
3169
3170 if (hw->phy.media_type == ixgbe_media_type_backplane)
3171 return (EPERM);
3172
3173 /*
3174 * We don't actually need to check against the supported
3175 * media types of the adapter; ifmedia will take care of
3176 * that for us.
3177 */
3178 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3179 case IFM_AUTO:
3180 case IFM_10G_T:
3181 speed |= IXGBE_LINK_SPEED_100_FULL;
3182 speed |= IXGBE_LINK_SPEED_1GB_FULL;
3183 speed |= IXGBE_LINK_SPEED_10GB_FULL;
3184 break;
3185 case IFM_10G_BX:
3186 speed |= IXGBE_LINK_SPEED_10GB_FULL;
3187 break;
3188 case IFM_10G_LRM:
3189 case IFM_10G_LR:
3190 #ifndef IFM_ETH_XTYPE
3191 case IFM_10G_SR: /* KR, too */
3192 case IFM_10G_CX4: /* KX4 */
3193 #else
3194 case IFM_10G_KR:
3195 case IFM_10G_KX4:
3196 #endif
3197 speed |= IXGBE_LINK_SPEED_1GB_FULL;
3198 speed |= IXGBE_LINK_SPEED_10GB_FULL;
3199 break;
3200 #ifndef IFM_ETH_XTYPE
3201 case IFM_1000_CX: /* KX */
3202 #else
3203 case IFM_1000_KX:
3204 #endif
3205 case IFM_1000_LX:
3206 case IFM_1000_SX:
3207 case IFM_1000_BX:
3208 speed |= IXGBE_LINK_SPEED_1GB_FULL;
3209 break;
3210 case IFM_1000_T:
3211 speed |= IXGBE_LINK_SPEED_100_FULL;
3212 speed |= IXGBE_LINK_SPEED_1GB_FULL;
3213 break;
3214 case IFM_10G_TWINAX:
3215 speed |= IXGBE_LINK_SPEED_10GB_FULL;
3216 break;
3217 case IFM_5000_T:
3218 speed |= IXGBE_LINK_SPEED_5GB_FULL;
3219 break;
3220 case IFM_2500_T:
3221 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
3222 break;
3223 case IFM_100_TX:
3224 speed |= IXGBE_LINK_SPEED_100_FULL;
3225 break;
3226 case IFM_10_T:
3227 speed |= IXGBE_LINK_SPEED_10_FULL;
3228 break;
3229 default:
3230 goto invalid;
3231 }
3232
3233 hw->mac.autotry_restart = true;
3234 hw->mac.ops.setup_link(hw, speed, true);
3235 sc->advertise =
3236 ((speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) |
3237 ((speed & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) |
3238 ((speed & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) |
3239 ((speed & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) |
3240 ((speed & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) |
3241 ((speed & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0);
3242
3243 return (0);
3244
3245 invalid:
3246 device_printf(iflib_get_dev(ctx), "Invalid media type!\n");
3247
3248 return (EINVAL);
3249 } /* ixgbe_if_media_change */
3250
3251 /************************************************************************
3252 * ixgbe_set_promisc
3253 ************************************************************************/
3254 static int
ixgbe_if_promisc_set(if_ctx_t ctx,int flags)3255 ixgbe_if_promisc_set(if_ctx_t ctx, int flags)
3256 {
3257 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3258 if_t ifp = iflib_get_ifp(ctx);
3259 u32 rctl;
3260 int mcnt = 0;
3261
3262 rctl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL);
3263 rctl &= (~IXGBE_FCTRL_UPE);
3264 if (if_getflags(ifp) & IFF_ALLMULTI)
3265 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
3266 else {
3267 mcnt = min(if_llmaddr_count(ifp),
3268 MAX_NUM_MULTICAST_ADDRESSES);
3269 }
3270 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
3271 rctl &= (~IXGBE_FCTRL_MPE);
3272 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl);
3273
3274 if (if_getflags(ifp) & IFF_PROMISC) {
3275 rctl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3276 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl);
3277 } else if (if_getflags(ifp) & IFF_ALLMULTI) {
3278 rctl |= IXGBE_FCTRL_MPE;
3279 rctl &= ~IXGBE_FCTRL_UPE;
3280 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, rctl);
3281 }
3282 return (0);
3283 } /* ixgbe_if_promisc_set */
3284
3285 /************************************************************************
3286 * ixgbe_handle_ecc - Defer recovery from an ECC interrupt
3287 ************************************************************************/
3288 static bool
ixgbe_handle_ecc(struct ixgbe_softc * sc,u32 eicr)3289 ixgbe_handle_ecc(struct ixgbe_softc *sc, u32 eicr)
3290 {
3291 struct ixgbe_hw *hw = &sc->hw;
3292
3293 if ((eicr & IXGBE_EICR_ECC) == 0)
3294 return (false);
3295
3296 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_ECC);
3297 if (!atomic_cmpset_int(&sc->ecc_reset_pending, 0, 1))
3298 return (false);
3299
3300 device_printf(sc->dev, "Received ECC Err, initiating reset\n");
3301 return (true);
3302 }
3303
3304 /************************************************************************
3305 * ixgbe_msix_link - Link status change ISR (MSI/MSI-X)
3306 ************************************************************************/
3307 static int
ixgbe_msix_link(void * arg)3308 ixgbe_msix_link(void *arg)
3309 {
3310 struct ixgbe_softc *sc = arg;
3311 struct ixgbe_hw *hw = &sc->hw;
3312 u32 eicr, eicr_mask;
3313 s32 retval;
3314
3315 ++sc->link_irq;
3316
3317 /* Pause other interrupts */
3318 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER);
3319
3320 /* First get the cause */
3321 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3322 /* Be sure the queue bits are not cleared */
3323 eicr &= ~IXGBE_EICR_RTX_QUEUE;
3324 /* Clear interrupt with write */
3325 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3326
3327 /* Link status change */
3328 if (eicr & IXGBE_EICR_LSC) {
3329 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
3330 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_LSC);
3331 }
3332
3333 if (eicr & IXGBE_EICR_FW_EVENT) {
3334 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_FW_EVENT);
3335 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_FWEVENT);
3336 }
3337
3338 if (sc->hw.mac.type != ixgbe_mac_82598EB) {
3339 if ((sc->feat_en & IXGBE_FEATURE_FDIR) &&
3340 (eicr & IXGBE_EICR_FLOW_DIR)) {
3341 /* This is probably overkill :) */
3342 if (atomic_cmpset_int(&sc->fdir_reinit, 0, 1)) {
3343 /* Disable the interrupt */
3344 IXGBE_WRITE_REG(hw, IXGBE_EIMC,
3345 IXGBE_EICR_FLOW_DIR);
3346 atomic_set_32(&sc->task_requests,
3347 IXGBE_REQUEST_TASK_FDIR);
3348 }
3349 }
3350 if (ixgbe_handle_ecc(sc, eicr))
3351 atomic_set_32(&sc->task_requests,
3352 IXGBE_REQUEST_TASK_RESET);
3353
3354 /* Check for over temp condition */
3355 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR) {
3356 switch (sc->hw.mac.type) {
3357 case ixgbe_mac_X550EM_a:
3358 if (!(eicr & IXGBE_EICR_GPI_SDP0_X550EM_a))
3359 break;
3360 IXGBE_WRITE_REG(hw, IXGBE_EIMC,
3361 IXGBE_EICR_GPI_SDP0_X550EM_a);
3362 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3363 IXGBE_EICR_GPI_SDP0_X550EM_a);
3364 retval = hw->phy.ops.check_overtemp(hw);
3365 if (retval != IXGBE_ERR_OVERTEMP)
3366 break;
3367 device_printf(iflib_get_dev(sc->ctx),
3368 "\nCRITICAL: OVER TEMP!!"
3369 " PHY IS SHUT DOWN!!\n");
3370 device_printf(iflib_get_dev(sc->ctx),
3371 "System shutdown required!\n");
3372 break;
3373 default:
3374 if (!(eicr & IXGBE_EICR_TS))
3375 break;
3376 retval = hw->phy.ops.check_overtemp(hw);
3377 if (retval != IXGBE_ERR_OVERTEMP)
3378 break;
3379 device_printf(iflib_get_dev(sc->ctx),
3380 "\nCRITICAL: OVER TEMP!!"
3381 " PHY IS SHUT DOWN!!\n");
3382 device_printf(iflib_get_dev(sc->ctx),
3383 "System shutdown required!\n");
3384 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3385 IXGBE_EICR_TS);
3386 break;
3387 }
3388 }
3389
3390 /* Check for VF message */
3391 if ((sc->feat_en & IXGBE_FEATURE_SRIOV) &&
3392 (eicr & IXGBE_EICR_MAILBOX)) {
3393 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MBX);
3394 }
3395 }
3396
3397 /*
3398 * On E610, the firmware handles PHY configuration, so
3399 * there is no need to perform any SFP-specific tasks.
3400 */
3401 if (hw->mac.type != ixgbe_mac_E610 && ixgbe_is_sfp(hw)) {
3402 /* Pluggable optics-related interrupt */
3403 if (hw->mac.type >= ixgbe_mac_X540)
3404 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
3405 else
3406 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw);
3407
3408 if (eicr & eicr_mask) {
3409 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
3410 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MOD);
3411 }
3412
3413 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3414 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) {
3415 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3416 IXGBE_EICR_GPI_SDP1_BY_MAC(hw));
3417 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MSF);
3418 }
3419 }
3420
3421 /* Check for fan failure */
3422 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL) {
3423 ixgbe_check_fan_failure(sc, eicr, true);
3424 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3425 IXGBE_EICR_GPI_SDP1_BY_MAC(hw));
3426 }
3427
3428 /* External PHY interrupt */
3429 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) &&
3430 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3431 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0_X540);
3432 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_PHY);
3433 }
3434
3435 return (atomic_load_acq_32(&sc->task_requests) != 0) ?
3436 FILTER_SCHEDULE_THREAD : FILTER_HANDLED;
3437 } /* ixgbe_msix_link */
3438
3439 /************************************************************************
3440 * ixgbe_sysctl_interrupt_rate_handler
3441 ************************************************************************/
3442 static int
ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)3443 ixgbe_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)
3444 {
3445 struct ix_rx_queue *que = ((struct ix_rx_queue *)oidp->oid_arg1);
3446 int error;
3447 unsigned int reg, usec, rate;
3448
3449 if (atomic_load_acq_int(&que->sc->recovery_mode))
3450 return (EPERM);
3451
3452 reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_EITR(que->msix));
3453 usec = ((reg & 0x0FF8) >> 3);
3454 if (usec > 0)
3455 rate = 500000 / usec;
3456 else
3457 rate = 0;
3458 error = sysctl_handle_int(oidp, &rate, 0, req);
3459 if (error || !req->newptr)
3460 return error;
3461 reg &= ~0xfff; /* default, no limitation */
3462 ixgbe_max_interrupt_rate = 0;
3463 if (rate > 0 && rate < 500000) {
3464 if (rate < 1000)
3465 rate = 1000;
3466 ixgbe_max_interrupt_rate = rate;
3467 reg |= ((4000000/rate) & 0xff8);
3468 }
3469 IXGBE_WRITE_REG(&que->sc->hw, IXGBE_EITR(que->msix), reg);
3470
3471 return (0);
3472 } /* ixgbe_sysctl_interrupt_rate_handler */
3473
3474 /************************************************************************
3475 * ixgbe_debug_dump_print_cluster
3476 ************************************************************************/
3477 static u8
ixgbe_debug_dump_print_cluster(struct ixgbe_softc * sc,struct sbuf * sbuf,u8 cluster_id)3478 ixgbe_debug_dump_print_cluster(struct ixgbe_softc *sc, struct sbuf *sbuf,
3479 u8 cluster_id)
3480 {
3481 u16 data_buf_size = IXGBE_ACI_MAX_BUFFER_SIZE;
3482 device_t dev = sc->dev;
3483 struct ixgbe_hw *hw = &sc->hw;
3484 const u8 reserved_buf[8] = {};
3485 int max_aci_calls = 1000;
3486 int error, counter = 0;
3487 u8 *data_buf;
3488
3489 /* Input parameters / loop variables */
3490 u16 table_id = 0;
3491 u32 offset = 0;
3492
3493 /* Data returned from ACI command */
3494 u16 ret_buf_size = 0;
3495 u16 ret_next_cluster = 0;
3496 u16 ret_next_table = 0;
3497 u32 ret_next_index = 0;
3498
3499 data_buf = (u8 *)malloc(data_buf_size, M_IXGBE, M_NOWAIT | M_ZERO);
3500 if (!data_buf)
3501 return (0);
3502
3503 DEBUGOUT2("%s: dumping cluster id (relative) %d\n",
3504 __func__, cluster_id);
3505
3506 do {
3507 DEBUGOUT3("table_id 0x%04x offset 0x%08x buf_size %d\n",
3508 table_id, offset, data_buf_size);
3509
3510 error = ixgbe_aci_get_internal_data(hw, cluster_id, table_id,
3511 offset, data_buf, data_buf_size, &ret_buf_size,
3512 &ret_next_cluster, &ret_next_table, &ret_next_index);
3513 if (error) {
3514 device_printf(dev,
3515 "%s: Failed to get internal FW/HW data, error: %d, "
3516 "last aci status: %d\n",
3517 __func__, error, hw->aci.last_status);
3518 break;
3519 }
3520
3521 DEBUGOUT3("ret_table_id 0x%04x ret_offset 0x%08x "
3522 "ret_buf_size %d\n",
3523 ret_next_table, ret_next_index, ret_buf_size);
3524
3525 /* Print cluster id */
3526 u32 print_cluster_id = (u32)cluster_id;
3527 sbuf_bcat(sbuf, &print_cluster_id, sizeof(print_cluster_id));
3528 /* Print table id */
3529 u32 print_table_id = (u32)table_id;
3530 sbuf_bcat(sbuf, &print_table_id, sizeof(print_table_id));
3531 /* Print table length */
3532 u32 print_table_length = (u32)ret_buf_size;
3533 sbuf_bcat(sbuf, &print_table_length,
3534 sizeof(print_table_length));
3535 /* Print current offset */
3536 u32 print_curr_offset = offset;
3537 sbuf_bcat(sbuf, &print_curr_offset, sizeof(print_curr_offset));
3538 /* Print reserved bytes */
3539 sbuf_bcat(sbuf, reserved_buf, sizeof(reserved_buf));
3540 /* Print data */
3541 sbuf_bcat(sbuf, data_buf, ret_buf_size);
3542
3543 /* Prepare for the next loop spin */
3544 memset(data_buf, 0, data_buf_size);
3545
3546 bool last_index = (ret_next_index == 0xffffffff);
3547 bool last_table = ((ret_next_table == 0xff ||
3548 ret_next_table == 0xffff) &&
3549 last_index);
3550
3551 if (last_table) {
3552 /* End of the cluster */
3553 DEBUGOUT1("End of the cluster ID %d\n", cluster_id);
3554 break;
3555 } else if (last_index) {
3556 /* End of the table */
3557 table_id = ret_next_table;
3558 offset = 0;
3559 } else {
3560 /* More data left in the table */
3561 offset = ret_next_index;
3562 }
3563 } while (++counter < max_aci_calls);
3564
3565 if (counter >= max_aci_calls)
3566 device_printf(dev, "Exceeded nr of ACI calls for cluster %d\n",
3567 cluster_id);
3568
3569 free(data_buf, M_IXGBE);
3570
3571 return (++cluster_id);
3572 } /* ixgbe_print_debug_dump_cluster */
3573
3574 /************************************************************************
3575 * ixgbe_sysctl_debug_dump_set_clusters
3576 *
3577 * Sets the cluster to dump from FW when Debug Dump requested.
3578 ************************************************************************/
3579 static int
ixgbe_sysctl_debug_dump_set_clusters(SYSCTL_HANDLER_ARGS)3580 ixgbe_sysctl_debug_dump_set_clusters(SYSCTL_HANDLER_ARGS)
3581 {
3582 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
3583 u32 clusters = sc->debug_dump_cluster_mask;
3584 device_t dev = sc->dev;
3585 int error;
3586
3587 error = sysctl_handle_32(oidp, &clusters, 0, req);
3588 if ((error) || !req->newptr)
3589 return (error);
3590
3591 if (clusters & ~(IXGBE_DBG_DUMP_VALID_CLUSTERS_MASK)) {
3592 device_printf(dev,
3593 "%s: Unrecognized parameter: %u\n",
3594 __func__, clusters);
3595 sc->debug_dump_cluster_mask =
3596 IXGBE_ACI_DBG_DUMP_CLUSTER_ID_INVALID;
3597 return (EINVAL);
3598 }
3599
3600 sc->debug_dump_cluster_mask = clusters;
3601
3602 return (0);
3603 } /* ixgbe_sysctl_debug_dump_set_clusters */
3604
3605 /************************************************************************
3606 * ixgbe_sysctl_dump_debug_dump
3607 ************************************************************************/
3608 static int
ixgbe_sysctl_dump_debug_dump(SYSCTL_HANDLER_ARGS)3609 ixgbe_sysctl_dump_debug_dump(SYSCTL_HANDLER_ARGS)
3610 {
3611 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
3612 device_t dev = sc->dev;
3613 struct sbuf *sbuf;
3614 int error = 0;
3615
3616 UNREFERENCED_PARAMETER(arg2);
3617
3618 if (!sc->do_debug_dump) {
3619 if (req->oldptr == NULL && req->newptr == NULL) {
3620 error = SYSCTL_OUT(req, 0, 0);
3621 return (error);
3622 }
3623
3624 char input_buf[2] = "";
3625 error = sysctl_handle_string(oidp, input_buf,
3626 sizeof(input_buf), req);
3627 if ((error) || (req->newptr == NULL))
3628 return (error);
3629
3630 if (input_buf[0] == '1') {
3631 if (sc->debug_dump_cluster_mask ==
3632 IXGBE_ACI_DBG_DUMP_CLUSTER_ID_INVALID) {
3633 device_printf(dev,
3634 "Debug Dump failed because an invalid "
3635 "cluster was specified.\n");
3636 return (EINVAL);
3637 }
3638
3639 sc->do_debug_dump = true;
3640 return (0);
3641 }
3642
3643 return (EINVAL);
3644 }
3645
3646 /* Caller just wants the upper bound for size */
3647 if (req->oldptr == NULL && req->newptr == NULL) {
3648 size_t est_output_len = IXGBE_DBG_DUMP_BASE_SIZE;
3649 if (sc->debug_dump_cluster_mask & 0x2)
3650 est_output_len += IXGBE_DBG_DUMP_BASE_SIZE;
3651 error = SYSCTL_OUT(req, 0, est_output_len);
3652 return (error);
3653 }
3654
3655 sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
3656 sbuf_clear_flags(sbuf, SBUF_INCLUDENUL);
3657
3658 DEBUGOUT("FW Debug Dump running...\n");
3659
3660 if (sc->debug_dump_cluster_mask) {
3661 for (u8 id = 0; id <= IXGBE_ACI_DBG_DUMP_CLUSTER_ID_MAX; id++) {
3662 if (sc->debug_dump_cluster_mask & BIT(id)) {
3663 DEBUGOUT1("Dumping cluster ID %u...\n", id);
3664 ixgbe_debug_dump_print_cluster(sc, sbuf, id);
3665 }
3666 }
3667 } else {
3668 u8 next_cluster_id = 0;
3669 do {
3670 DEBUGOUT1("Dumping cluster ID %u...\n",
3671 next_cluster_id);
3672 next_cluster_id = ixgbe_debug_dump_print_cluster(sc,
3673 sbuf, next_cluster_id);
3674 } while (next_cluster_id != 0 &&
3675 next_cluster_id <= IXGBE_ACI_DBG_DUMP_CLUSTER_ID_MAX);
3676 }
3677
3678 sbuf_finish(sbuf);
3679 sbuf_delete(sbuf);
3680
3681 sc->do_debug_dump = false;
3682
3683 return (error);
3684 } /* ixgbe_sysctl_dump_debug_dump */
3685
3686 /************************************************************************
3687 * ixgbe_add_debug_dump_sysctls
3688 ************************************************************************/
3689 static void
ixgbe_add_debug_dump_sysctls(struct ixgbe_softc * sc)3690 ixgbe_add_debug_dump_sysctls(struct ixgbe_softc *sc)
3691 {
3692 struct sysctl_oid_list *debug_list, *dump_list;
3693 struct sysctl_oid *dump_node;
3694 struct sysctl_ctx_list *ctx;
3695 device_t dev = sc->dev;
3696
3697 ctx = device_get_sysctl_ctx(dev);
3698 debug_list = SYSCTL_CHILDREN(sc->debug_sysctls);
3699
3700 dump_node = SYSCTL_ADD_NODE(ctx, debug_list, OID_AUTO, "dump",
3701 CTLFLAG_RD, NULL, "Internal FW/HW Dump");
3702 dump_list = SYSCTL_CHILDREN(dump_node);
3703
3704 SYSCTL_ADD_PROC(ctx, dump_list, OID_AUTO, "clusters",
3705 CTLTYPE_U32 | CTLFLAG_RW, sc, 0,
3706 ixgbe_sysctl_debug_dump_set_clusters, "SU",
3707 IXGBE_SYSCTL_DESC_DEBUG_DUMP_SET_CLUSTER);
3708
3709 SYSCTL_ADD_PROC(ctx, dump_list, OID_AUTO, "dump",
3710 CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
3711 ixgbe_sysctl_dump_debug_dump, "",
3712 IXGBE_SYSCTL_DESC_DUMP_DEBUG_DUMP);
3713 } /* ixgbe_add_debug_dump_sysctls */
3714
3715 static void
ixgbe_add_debug_sysctls(struct ixgbe_softc * sc)3716 ixgbe_add_debug_sysctls(struct ixgbe_softc *sc)
3717 {
3718 struct sysctl_oid_list *ctx_list;
3719 struct sysctl_ctx_list *ctx;
3720 device_t dev = sc->dev;
3721
3722 ctx = device_get_sysctl_ctx(dev);
3723 ctx_list = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
3724
3725 sc->debug_sysctls = SYSCTL_ADD_NODE(ctx, ctx_list, OID_AUTO, "debug",
3726 CTLFLAG_RD, NULL, "Debug Sysctls");
3727
3728 if (sc->feat_en & IXGBE_FEATURE_DBG_DUMP)
3729 ixgbe_add_debug_dump_sysctls(sc);
3730
3731 if (sc->feat_en & IXGBE_FEATURE_FW_LOGGING)
3732 ixgbe_add_fw_logging_tunables(sc, sc->debug_sysctls);
3733 } /* ixgbe_add_debug_sysctls */
3734
3735 /************************************************************************
3736 * ixgbe_add_device_sysctls
3737 ************************************************************************/
3738 static void
ixgbe_add_device_sysctls(if_ctx_t ctx)3739 ixgbe_add_device_sysctls(if_ctx_t ctx)
3740 {
3741 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3742 device_t dev = iflib_get_dev(ctx);
3743 struct ixgbe_hw *hw = &sc->hw;
3744 struct sysctl_oid_list *child;
3745 struct sysctl_ctx_list *ctx_list;
3746
3747 ctx_list = device_get_sysctl_ctx(dev);
3748 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
3749
3750 /* Sysctls for all devices */
3751 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc",
3752 CTLTYPE_INT | CTLFLAG_RW,
3753 sc, 0, ixgbe_sysctl_flowcntl, "I",
3754 IXGBE_SYSCTL_DESC_SET_FC);
3755
3756 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "advertise_speed",
3757 CTLTYPE_INT | CTLFLAG_RW,
3758 sc, 0, ixgbe_sysctl_advertise, "I",
3759 IXGBE_SYSCTL_DESC_ADV_SPEED);
3760 if (hw->mac.type == ixgbe_mac_82599EB ||
3761 hw->mac.type == ixgbe_mac_X540) {
3762 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO,
3763 "iov_dma_abort_events", CTLFLAG_RD,
3764 &sc->iov_dma_abort_events, 0,
3765 "VF invalid-DMA events");
3766 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO,
3767 "iov_dma_abort_flr_failures", CTLFLAG_RD,
3768 &sc->iov_dma_abort_flr_failures, 0,
3769 "Failed VF reset attempts after invalid-DMA events");
3770 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO,
3771 "iov_dma_abort_quarantines", CTLFLAG_RD,
3772 &sc->iov_dma_abort_quarantines, 0,
3773 "VFs quarantined after repeated invalid-DMA events");
3774 SYSCTL_ADD_U64(ctx_list, child, OID_AUTO,
3775 "iov_quarantined_vfs", CTLFLAG_RD,
3776 &sc->iov_quarantined_vfs, 0,
3777 "Bitmap of quarantined VF pools");
3778 }
3779
3780 sc->enable_aim = ixgbe_enable_aim;
3781 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", CTLFLAG_RW,
3782 &sc->enable_aim, 0, "Interrupt Moderation");
3783
3784 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version",
3785 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
3786 ixgbe_sysctl_print_fw_version, "A", "Prints FW/NVM Versions");
3787
3788 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
3789 "tso_tcp_flags_mask_first_segment",
3790 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
3791 sc, 0, ixgbe_sysctl_tso_tcp_flags_mask, "IU",
3792 "TSO TCP flags mask for first segment");
3793
3794 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
3795 "tso_tcp_flags_mask_middle_segment",
3796 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
3797 sc, 1, ixgbe_sysctl_tso_tcp_flags_mask, "IU",
3798 "TSO TCP flags mask for middle segment");
3799
3800 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
3801 "tso_tcp_flags_mask_last_segment",
3802 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
3803 sc, 2, ixgbe_sysctl_tso_tcp_flags_mask, "IU",
3804 "TSO TCP flags mask for last segment");
3805
3806 #ifdef IXGBE_DEBUG
3807 /* testing sysctls (for all devices) */
3808 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "power_state",
3809 CTLTYPE_INT | CTLFLAG_RW,
3810 sc, 0, ixgbe_sysctl_power_state,
3811 "I", "PCI Power State");
3812
3813 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "print_rss_config",
3814 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
3815 ixgbe_sysctl_print_rss_config, "A", "Prints RSS Configuration");
3816 #endif
3817 /* for X550 series devices */
3818 if (hw->mac.type >= ixgbe_mac_X550)
3819 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac",
3820 CTLTYPE_U16 | CTLFLAG_RW,
3821 sc, 0, ixgbe_sysctl_dmac,
3822 "I", "DMA Coalesce");
3823
3824 /* for X552/X557-AT devices */
3825 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
3826 struct sysctl_oid *phy_node;
3827 struct sysctl_oid_list *phy_list;
3828
3829 phy_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "phy",
3830 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3831 "External PHY sysctls");
3832 phy_list = SYSCTL_CHILDREN(phy_node);
3833
3834 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO, "temp",
3835 CTLTYPE_U16 | CTLFLAG_RD,
3836 sc, 0, ixgbe_sysctl_phy_temp,
3837 "I", "Current External PHY Temperature (Celsius)");
3838
3839 SYSCTL_ADD_PROC(ctx_list, phy_list, OID_AUTO,
3840 "overtemp_occurred",
3841 CTLTYPE_U16 | CTLFLAG_RD, sc, 0,
3842 ixgbe_sysctl_phy_overtemp_occurred, "I",
3843 "External PHY High Temperature Event Occurred");
3844 }
3845
3846 if (sc->feat_cap & IXGBE_FEATURE_EEE) {
3847 struct sysctl_oid *eee_node;
3848 struct sysctl_oid_list *eee_list;
3849
3850 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_state",
3851 CTLTYPE_INT | CTLFLAG_RW, sc, 0,
3852 ixgbe_sysctl_eee_state, "I", "EEE Power Save State");
3853
3854 eee_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "eee",
3855 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3856 "Energy Efficient Ethernet statistics");
3857 eee_list = SYSCTL_CHILDREN(eee_node);
3858 SYSCTL_ADD_UQUAD(ctx_list, eee_list, OID_AUTO, "tx_lpi_count",
3859 CTLFLAG_RD, &sc->stats.pf.tlpic, "TX LPI event count");
3860 SYSCTL_ADD_UQUAD(ctx_list, eee_list, OID_AUTO, "rx_lpi_count",
3861 CTLFLAG_RD, &sc->stats.pf.rlpic, "RX LPI event count");
3862 }
3863
3864 ixgbe_add_debug_sysctls(sc);
3865 } /* ixgbe_add_device_sysctls */
3866
3867 /************************************************************************
3868 * ixgbe_allocate_pci_resources
3869 ************************************************************************/
3870 static int
ixgbe_allocate_pci_resources(if_ctx_t ctx)3871 ixgbe_allocate_pci_resources(if_ctx_t ctx)
3872 {
3873 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3874 device_t dev = iflib_get_dev(ctx);
3875 int rid;
3876
3877 rid = PCIR_BAR(0);
3878 sc->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3879 RF_ACTIVE);
3880
3881 if (!(sc->pci_mem)) {
3882 device_printf(dev,
3883 "Unable to allocate bus resource: memory\n");
3884 return (ENXIO);
3885 }
3886
3887 /* Save bus_space values for READ/WRITE_REG macros */
3888 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->pci_mem);
3889 sc->osdep.mem_bus_space_handle =
3890 rman_get_bushandle(sc->pci_mem);
3891 /* Set hw values for shared code */
3892 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
3893
3894 return (0);
3895 } /* ixgbe_allocate_pci_resources */
3896
3897 /************************************************************************
3898 * ixgbe_detach - Device removal routine
3899 *
3900 * Called when the driver is being removed.
3901 * Stops the adapter and deallocates all the resources
3902 * that were allocated for driver operation.
3903 *
3904 * return 0 on success, positive on failure
3905 ************************************************************************/
3906 static int
ixgbe_if_detach(if_ctx_t ctx)3907 ixgbe_if_detach(if_ctx_t ctx)
3908 {
3909 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3910 u32 ctrl_ext;
3911
3912 INIT_DEBUGOUT("ixgbe_detach: begin");
3913
3914 sc->iov_recovery_stop = true;
3915 ixgbe_fw_mode_timer_pause(sc);
3916
3917 ixgbe_setup_low_power_mode(ctx);
3918
3919 /* let hardware know driver is unloading */
3920 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT);
3921 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD;
3922 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext);
3923
3924 if (sc->hw.mac.type == ixgbe_mac_E610) {
3925 ixgbe_disable_lse(sc);
3926 ixgbe_shutdown_aci(&sc->hw);
3927 }
3928
3929 ixgbe_free_pci_resources(ctx);
3930
3931 free(sc->mta, M_IXGBE);
3932
3933 return (0);
3934 } /* ixgbe_if_detach */
3935
3936 static void
ixgbe_prepare_wakeup(if_ctx_t ctx,bool arm_wake)3937 ixgbe_prepare_wakeup(if_ctx_t ctx, bool arm_wake)
3938 {
3939 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3940 struct ixgbe_hw *hw = &sc->hw;
3941 if_t ifp = iflib_get_ifp(ctx);
3942 int enabled;
3943 u32 wufc;
3944
3945 enabled = arm_wake ?
3946 if_getcapenable(ifp) & if_getcapabilities(ifp) & IFCAP_WOL : 0;
3947 wufc = 0;
3948 if ((enabled & IFCAP_WOL_MAGIC) != 0)
3949 wufc |= IXGBE_WUFC_MAG;
3950 if ((enabled & IFCAP_WOL_UCAST) != 0)
3951 wufc |= IXGBE_WUFC_EX;
3952 if ((enabled & IFCAP_WOL_MCAST) != 0)
3953 wufc |= IXGBE_WUFC_MC;
3954 sc->wol_filters = wufc;
3955 hw->wol_enabled = wufc != 0;
3956
3957 /* X550EM 10GBASE-T requires PHY reset suppression during the stop. */
3958 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T &&
3959 hw->phy.ops.enter_lplu != NULL)
3960 hw->phy.reset_disable = true;
3961 }
3962
3963 static u_int
ixgbe_wakeup_mta_apply(void * arg,struct sockaddr_dl * sdl,u_int idx __unused)3964 ixgbe_wakeup_mta_apply(void *arg, struct sockaddr_dl *sdl, u_int idx __unused)
3965 {
3966 struct ixgbe_hw *hw = arg;
3967
3968 ixgbe_set_mta(hw, LLADDR(sdl));
3969 return (1);
3970 }
3971
3972 /* Restore multicast hashes needed by directed and multicast-magic wake. */
3973 static void
ixgbe_configure_wakeup_mta(if_ctx_t ctx)3974 ixgbe_configure_wakeup_mta(if_ctx_t ctx)
3975 {
3976 struct ixgbe_softc *sc = iflib_get_softc(ctx);
3977 struct ixgbe_hw *hw = &sc->hw;
3978 u_int i, mcnt;
3979
3980 bzero(hw->mac.mta_shadow, sizeof(hw->mac.mta_shadow));
3981 hw->addr_ctrl.mta_in_use = 0;
3982 mcnt = if_foreach_llmaddr(iflib_get_ifp(ctx),
3983 ixgbe_wakeup_mta_apply, hw);
3984 hw->addr_ctrl.num_mc_addrs = mcnt;
3985 for (i = 0; i < hw->mac.mcft_size; i++)
3986 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
3987 hw->mac.mta_shadow[i]);
3988 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3989 (hw->addr_ctrl.mta_in_use != 0 ? IXGBE_MCSTCTRL_MFE : 0) |
3990 hw->mac.mc_filter_type);
3991 }
3992
3993 /************************************************************************
3994 * ixgbe_if_power_prepare - Establish policy required before a terminal stop
3995 *
3996 * Snapshot the requested wake filters before iflib stops the interface.
3997 * X550EM 10GBASE-T must also suppress its PHY reset during that stop.
3998 ************************************************************************/
3999 static int
ixgbe_if_power_prepare(if_ctx_t ctx,enum iflib_power_event event)4000 ixgbe_if_power_prepare(if_ctx_t ctx, enum iflib_power_event event)
4001 {
4002 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4003
4004 ixgbe_fw_mode_timer_pause(sc);
4005 ixgbe_prepare_wakeup(ctx, event != IFLIB_POWER_DETACH);
4006 return (0);
4007 }
4008
4009 /************************************************************************
4010 * ixgbe_setup_low_power_mode - LPLU/WoL preparation
4011 *
4012 * Prepare the adapter/port for LPLU and/or WoL after a terminal stop
4013 ************************************************************************/
4014 static int
ixgbe_setup_low_power_mode(if_ctx_t ctx)4015 ixgbe_setup_low_power_mode(if_ctx_t ctx)
4016 {
4017 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4018 struct ixgbe_hw *hw = &sc->hw;
4019 device_t dev = iflib_get_dev(ctx);
4020 u32 fctrl, grc, wufc;
4021 s32 error = 0;
4022
4023 wufc = sc->wol_filters;
4024
4025 /* Limit power management flow to X550EM baseT */
4026 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T &&
4027 hw->phy.ops.enter_lplu) {
4028 /* X550EM baseT adapters need a special LPLU flow. */
4029 error = hw->phy.ops.enter_lplu(hw);
4030 if (error)
4031 device_printf(dev, "Error entering LPLU: %d\n",
4032 error);
4033 hw->phy.reset_disable = false;
4034 error = 0;
4035 }
4036
4037 /* Disable the 82599 link only when actually entering D3. */
4038 if (hw->mac.type == ixgbe_mac_82599EB)
4039 ixgbe_stop_mac_link_on_d3_82599(hw);
4040
4041 /*
4042 * Make ifconfig's ACPI policy authoritative. All supported families,
4043 * including E610, implement the standard filters in WUFC; leaving the
4044 * NVM-selected APM path enabled would permit an unrequested magic wake.
4045 */
4046 if (hw->mac.type != ixgbe_mac_82598EB) {
4047 grc = IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw));
4048 IXGBE_WRITE_REG(hw, IXGBE_GRC_BY_MAC(hw),
4049 grc & ~IXGBE_GRC_APME);
4050 }
4051 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4052 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4053 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff);
4054 pci_clear_pme(dev);
4055 if (wufc != 0) {
4056 bcopy(if_getlladdr(iflib_get_ifp(ctx)), hw->mac.addr,
4057 IXGBE_ETH_LENGTH_OF_ADDRESS);
4058 error = ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool,
4059 IXGBE_RAH_AV);
4060 if (error != IXGBE_SUCCESS) {
4061 device_printf(dev,
4062 "Could not restore unicast wake address: %d\n", error);
4063 sc->wol_filters = 0;
4064 hw->wol_enabled = false;
4065 goto no_wake;
4066 }
4067
4068 /* 82599 SFP+ ports need the laser for an optical wake packet. */
4069 ixgbe_enable_tx_laser(hw);
4070
4071 /* Rebuild address filtering erased by the terminal reset. */
4072 ixgbe_configure_wakeup_mta(ctx);
4073 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4074 fctrl |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_MPE;
4075 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4076
4077 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4078 IXGBE_WRITE_REG(hw, IXGBE_WUC,
4079 IXGBE_WUC_WKEN | IXGBE_WUC_PME_EN);
4080 pci_enable_pme(dev);
4081 return (0);
4082 }
4083
4084 no_wake:
4085 ixgbe_set_phy_power(hw, false);
4086 return (error == IXGBE_SUCCESS ? 0 : EIO);
4087 } /* ixgbe_setup_low_power_mode */
4088
4089 /************************************************************************
4090 * ixgbe_shutdown - Shutdown entry point
4091 ************************************************************************/
4092 static int
ixgbe_if_shutdown(if_ctx_t ctx)4093 ixgbe_if_shutdown(if_ctx_t ctx)
4094 {
4095 int error = 0;
4096
4097 INIT_DEBUGOUT("ixgbe_shutdown: begin");
4098
4099 error = ixgbe_setup_low_power_mode(ctx);
4100 if (error != 0)
4101 device_printf(iflib_get_dev(ctx),
4102 "Wake configuration failed during shutdown: %d\n", error);
4103 return (0);
4104 } /* ixgbe_if_shutdown */
4105
4106 /************************************************************************
4107 * ixgbe_suspend
4108 *
4109 * From D0 to D3
4110 ************************************************************************/
4111 static int
ixgbe_if_suspend(if_ctx_t ctx)4112 ixgbe_if_suspend(if_ctx_t ctx)
4113 {
4114 int error = 0;
4115
4116 INIT_DEBUGOUT("ixgbe_suspend: begin");
4117
4118 error = ixgbe_setup_low_power_mode(ctx);
4119
4120 return (error);
4121 } /* ixgbe_if_suspend */
4122
4123 /************************************************************************
4124 * ixgbe_resume
4125 *
4126 * From D3 to D0
4127 ************************************************************************/
4128 static int
ixgbe_if_resume(if_ctx_t ctx)4129 ixgbe_if_resume(if_ctx_t ctx)
4130 {
4131 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4132 device_t dev = iflib_get_dev(ctx);
4133 struct ixgbe_hw *hw = &sc->hw;
4134 u32 wus;
4135
4136 INIT_DEBUGOUT("ixgbe_resume: begin");
4137
4138 /* Read & clear WUS register */
4139 wus = IXGBE_READ_REG(hw, IXGBE_WUS);
4140 if (wus)
4141 device_printf(dev, "Woken up by (WUS): %#010x\n",
4142 wus);
4143 /* Remove every device wake source before clearing PCI PME. */
4144 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4145 if (hw->mac.type != ixgbe_mac_82598EB)
4146 IXGBE_WRITE_REG(hw, IXGBE_GRC_BY_MAC(hw),
4147 IXGBE_READ_REG(hw, IXGBE_GRC_BY_MAC(hw)) &
4148 ~IXGBE_GRC_APME);
4149 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4150 IXGBE_WRITE_REG(hw, IXGBE_WUS, 0xffffffff);
4151 pci_clear_pme(dev);
4152 hw->wol_enabled = false;
4153 sc->wol_filters = 0;
4154 ixgbe_fw_mode_timer_resume(sc);
4155
4156 return (0);
4157 } /* ixgbe_if_resume */
4158
4159 /************************************************************************
4160 * ixgbe_if_mtu_set - Ioctl mtu entry point
4161 *
4162 * Return 0 on success, EINVAL on failure
4163 ************************************************************************/
4164 static int
ixgbe_if_mtu_set(if_ctx_t ctx,uint32_t mtu)4165 ixgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
4166 {
4167 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4168 int error = 0;
4169
4170 IOCTL_DEBUGOUT("ioctl: SIOCIFMTU (Set Interface MTU)");
4171
4172 if (mtu > IXGBE_MAX_MTU) {
4173 error = EINVAL;
4174 } else {
4175 sc->max_frame_size = mtu + IXGBE_MTU_HDR;
4176 }
4177
4178 return error;
4179 } /* ixgbe_if_mtu_set */
4180
4181 /************************************************************************
4182 * ixgbe_if_crcstrip_set
4183 ************************************************************************/
4184 static void
ixgbe_if_crcstrip_set(if_ctx_t ctx,int onoff,int crcstrip)4185 ixgbe_if_crcstrip_set(if_ctx_t ctx, int onoff, int crcstrip)
4186 {
4187 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4188 struct ixgbe_hw *hw = &sc->hw;
4189 /* crc stripping is set in two places:
4190 * IXGBE_HLREG0 (modified on init_locked and hw reset)
4191 * IXGBE_RDRXCTL (set by the original driver in
4192 * ixgbe_setup_hw_rsc() called in init_locked.
4193 * We disable the setting when netmap is compiled in).
4194 * We update the values here, but also in ixgbe.c because
4195 * init_locked sometimes is called outside our control.
4196 */
4197 uint32_t hl, rxc;
4198
4199 hl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4200 rxc = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4201 #ifdef NETMAP
4202 if (netmap_verbose)
4203 D("%s read HLREG 0x%x rxc 0x%x",
4204 onoff ? "enter" : "exit", hl, rxc);
4205 #endif
4206 /* hw requirements ... */
4207 rxc &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4208 rxc |= IXGBE_RDRXCTL_RSCACKC;
4209 if (onoff && !crcstrip) {
4210 /* keep the crc. Fast rx */
4211 hl &= ~IXGBE_HLREG0_RXCRCSTRP;
4212 rxc &= ~IXGBE_RDRXCTL_CRCSTRIP;
4213 } else {
4214 /* reset default mode */
4215 hl |= IXGBE_HLREG0_RXCRCSTRP;
4216 rxc |= IXGBE_RDRXCTL_CRCSTRIP;
4217 }
4218 #ifdef NETMAP
4219 if (netmap_verbose)
4220 D("%s write HLREG 0x%x rxc 0x%x",
4221 onoff ? "enter" : "exit", hl, rxc);
4222 #endif
4223 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hl);
4224 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rxc);
4225 } /* ixgbe_if_crcstrip_set */
4226
4227 /*********************************************************************
4228 * ixgbe_if_init - Init entry point
4229 *
4230 * Used in two ways: It is used by the stack as an init
4231 * entry point in network interface structure. It is also
4232 * used by the driver as a hw/sw initialization routine to
4233 * get to a consistent state.
4234 *
4235 * Return 0 on success, positive on failure
4236 **********************************************************************/
4237 void
ixgbe_if_init(if_ctx_t ctx)4238 ixgbe_if_init(if_ctx_t ctx)
4239 {
4240 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4241 if_t ifp = iflib_get_ifp(ctx);
4242 device_t dev = iflib_get_dev(ctx);
4243 struct ixgbe_hw *hw = &sc->hw;
4244 struct ix_rx_queue *rx_que;
4245 struct ix_tx_queue *tx_que;
4246 u32 txdctl, mhadd;
4247 u32 rxdctl, rxctrl;
4248 u32 ctrl_ext;
4249
4250 int i, j, err;
4251 s32 status;
4252
4253 INIT_DEBUGOUT("ixgbe_if_init: begin");
4254 if (atomic_load_acq_int(&sc->recovery_mode)) {
4255 iflib_init_failed(ctx);
4256 return;
4257 }
4258 /* Leave an overheated adapter stopped until an operator retries. */
4259 if (sc->overtemp_shutdown_pending) {
4260 sc->overtemp_shutdown_pending = false;
4261 iflib_init_failed(ctx);
4262 return;
4263 }
4264
4265 /* Preserve the largest frame requested by the PF or an active VF. */
4266 sc->max_frame_size = if_getmtu(ifp) + IXGBE_MTU_HDR;
4267 ixgbe_recalculate_max_frame(sc);
4268
4269 /* Queue indices may change with IOV mode */
4270 ixgbe_align_all_queue_indices(sc);
4271
4272 /* reprogram the RAR[0] in case user changed it. */
4273 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, IXGBE_RAH_AV);
4274
4275 /* Get the latest mac address, User can use a LAA */
4276 bcopy(if_getlladdr(ifp), hw->mac.addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
4277 ixgbe_set_rar(hw, 0, hw->mac.addr, sc->pool, 1);
4278 hw->addr_ctrl.rar_used_count = 1;
4279
4280 status = ixgbe_init_hw(hw);
4281 if (status != IXGBE_SUCCESS) {
4282 device_printf(dev, "Hardware initialization failed: %d\n",
4283 status);
4284 iflib_init_failed(ctx);
4285 return;
4286 }
4287 sc->iov_mta_valid = false;
4288 sc->iov_vfta_valid = false;
4289
4290 ixgbe_initialize_iov(sc);
4291
4292 ixgbe_initialize_transmit_units(ctx);
4293
4294 /* Setup Multicast table */
4295 ixgbe_if_multi_set(ctx);
4296
4297 /* Determine the correct mbuf pool, based on frame size */
4298 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
4299
4300 /* Configure RX settings */
4301 ixgbe_initialize_receive_units(ctx);
4302
4303 /*
4304 * Initialize the deferred administrative request mask.
4305 */
4306 atomic_store_rel_32(&sc->task_requests, 0);
4307
4308 /* Enable SDP & MSI-X interrupts based on adapter */
4309 ixgbe_config_gpie(sc);
4310
4311 /* Set MTU size */
4312 if (sc->max_frame_size > ETHER_MAX_LEN) {
4313 /* aka IXGBE_MAXFRS on 82599 and newer */
4314 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4315 mhadd &= ~IXGBE_MHADD_MFS_MASK;
4316 mhadd |= sc->max_frame_size << IXGBE_MHADD_MFS_SHIFT;
4317 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4318 }
4319
4320 /* Now enable all the queues */
4321 for (i = 0, tx_que = sc->tx_queues; i < sc->num_tx_queues;
4322 i++, tx_que++) {
4323 struct tx_ring *txr = &tx_que->txr;
4324
4325 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txr->me));
4326 txdctl &= ~IXGBE_TXDCTL_THRESH_MASK;
4327 txdctl |= IXGBE_TXDCTL_ENABLE | IXGBE_TXDCTL_THRESH_DEFAULT;
4328 /*
4329 * When the internal queue falls below PTHRESH (32),
4330 * start prefetching as long as there are at least
4331 * HTHRESH (1) buffers ready. Leave WTHRESH at zero
4332 * so that writeback follows iflib's sparse RS bits.
4333 * Prefetching enables tx line rate even with 1 queue.
4334 */
4335 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txr->me), txdctl);
4336 }
4337
4338 for (i = 0, rx_que = sc->rx_queues; i < sc->num_rx_queues;
4339 i++, rx_que++) {
4340 struct rx_ring *rxr = &rx_que->rxr;
4341
4342 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me));
4343 if (hw->mac.type == ixgbe_mac_82598EB) {
4344 /*
4345 * PTHRESH = 21
4346 * HTHRESH = 4
4347 * WTHRESH = 8
4348 */
4349 rxdctl &= ~0x3FFFFF;
4350 rxdctl |= 0x080420;
4351 }
4352 rxdctl |= IXGBE_RXDCTL_ENABLE;
4353 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxr->me), rxdctl);
4354 for (j = 0; j < 10; j++) {
4355 if (IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxr->me)) &
4356 IXGBE_RXDCTL_ENABLE)
4357 break;
4358 else
4359 msec_delay(1);
4360 }
4361 wmb();
4362 }
4363
4364 /* Enable Receive engine */
4365 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4366 if (hw->mac.type == ixgbe_mac_82598EB)
4367 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4368 rxctrl |= IXGBE_RXCTRL_RXEN;
4369 ixgbe_enable_rx_dma(hw, rxctrl);
4370
4371 /* Set up MSI/MSI-X routing */
4372 if (ixgbe_enable_msix) {
4373 ixgbe_configure_ivars(sc);
4374 /* Set up auto-mask */
4375 if (hw->mac.type == ixgbe_mac_82598EB)
4376 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4377 else {
4378 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4379 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4380 }
4381 } else { /* Simple settings for Legacy/MSI */
4382 ixgbe_set_ivar(sc, 0, 0, 0);
4383 ixgbe_set_ivar(sc, 0, 0, 1);
4384 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4385 }
4386
4387 ixgbe_init_fdir(sc);
4388
4389 /*
4390 * Check on any SFP devices that
4391 * need to be kick-started
4392 */
4393 if (hw->phy.type == ixgbe_phy_none) {
4394 err = hw->phy.ops.identify(hw);
4395 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4396 device_printf(dev,
4397 "Unsupported SFP+ module type was detected.\n");
4398 return;
4399 }
4400 }
4401
4402 /* Set moderation on the Link interrupt */
4403 IXGBE_WRITE_REG(hw, IXGBE_EITR(sc->vector), IXGBE_LINK_ITR);
4404
4405 /* Enable power to the phy. */
4406 ixgbe_set_phy_power(hw, true);
4407
4408 /* Config/Enable Link */
4409 ixgbe_config_link(ctx);
4410
4411 /* Hardware Packet Buffer & Flow Control setup */
4412 ixgbe_config_delay_values(sc);
4413
4414 /* Initialize the FC settings */
4415 ixgbe_start_hw(hw);
4416
4417 /* Set up VLAN support and filter */
4418 ixgbe_setup_vlan_hw_support(ctx);
4419
4420 /* Setup DMA Coalescing */
4421 ixgbe_config_dmac(sc);
4422
4423 if (sc->feat_en & IXGBE_FEATURE_SRIOV) {
4424 ixgbe_enable_mdd(hw);
4425 ixgbe_activate_vfs(sc);
4426 }
4427
4428 /* And now turn on interrupts */
4429 ixgbe_if_enable_intr(ctx);
4430
4431 /* Enable the use of the MBX by the VF's */
4432 if (sc->feat_en & IXGBE_FEATURE_SRIOV) {
4433 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4434 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4435 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4436 }
4437
4438 } /* ixgbe_init_locked */
4439
4440 /************************************************************************
4441 * ixgbe_set_ivar
4442 *
4443 * Setup the correct IVAR register for a particular MSI-X interrupt
4444 * (yes this is all very magic and confusing :)
4445 * - entry is the register array entry
4446 * - vector is the MSI-X vector for this queue
4447 * - type is RX/TX/MISC
4448 ************************************************************************/
4449 static void
ixgbe_set_ivar(struct ixgbe_softc * sc,u8 entry,u8 vector,s8 type)4450 ixgbe_set_ivar(struct ixgbe_softc *sc, u8 entry, u8 vector, s8 type)
4451 {
4452 struct ixgbe_hw *hw = &sc->hw;
4453 u32 ivar, index;
4454
4455 vector |= IXGBE_IVAR_ALLOC_VAL;
4456
4457 switch (hw->mac.type) {
4458 case ixgbe_mac_82598EB:
4459 if (type == -1)
4460 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4461 else
4462 entry += (type * 64);
4463 index = (entry >> 2) & 0x1F;
4464 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4465 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4466 ivar |= (vector << (8 * (entry & 0x3)));
4467 IXGBE_WRITE_REG(&sc->hw, IXGBE_IVAR(index), ivar);
4468 break;
4469 case ixgbe_mac_82599EB:
4470 case ixgbe_mac_X540:
4471 case ixgbe_mac_X550:
4472 case ixgbe_mac_X550EM_x:
4473 case ixgbe_mac_X550EM_a:
4474 case ixgbe_mac_E610:
4475 if (type == -1) { /* MISC IVAR */
4476 index = (entry & 1) * 8;
4477 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4478 ivar &= ~(0xFF << index);
4479 ivar |= (vector << index);
4480 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4481 } else { /* RX/TX IVARS */
4482 index = (16 * (entry & 1)) + (8 * type);
4483 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4484 ivar &= ~(0xFF << index);
4485 ivar |= (vector << index);
4486 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4487 }
4488 default:
4489 break;
4490 }
4491 } /* ixgbe_set_ivar */
4492
4493 /************************************************************************
4494 * ixgbe_configure_ivars
4495 ************************************************************************/
4496 static void
ixgbe_configure_ivars(struct ixgbe_softc * sc)4497 ixgbe_configure_ivars(struct ixgbe_softc *sc)
4498 {
4499 struct ix_rx_queue *rx_que = sc->rx_queues;
4500 struct ix_tx_queue *tx_que = sc->tx_queues;
4501 u32 newitr;
4502
4503 if (ixgbe_max_interrupt_rate > 0)
4504 newitr = (4000000 / ixgbe_max_interrupt_rate) & 0x0FF8;
4505 else {
4506 /*
4507 * Disable DMA coalescing if interrupt moderation is
4508 * disabled.
4509 */
4510 sc->dmac = 0;
4511 newitr = 0;
4512 }
4513
4514 for (int i = 0; i < sc->num_rx_queues; i++, rx_que++) {
4515 struct rx_ring *rxr = &rx_que->rxr;
4516
4517 /* First the RX queue entry */
4518 ixgbe_set_ivar(sc, rxr->me, rx_que->msix, 0);
4519
4520 /* Set an Initial EITR value */
4521 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(rx_que->msix), newitr);
4522 }
4523 for (int i = 0; i < sc->num_tx_queues; i++, tx_que++) {
4524 struct tx_ring *txr = &tx_que->txr;
4525
4526 /* ... and the TX */
4527 ixgbe_set_ivar(sc, txr->me, tx_que->msix, 1);
4528 }
4529 /* For the Link interrupt */
4530 ixgbe_set_ivar(sc, 1, sc->vector, -1);
4531 } /* ixgbe_configure_ivars */
4532
4533 /************************************************************************
4534 * ixgbe_config_gpie
4535 ************************************************************************/
4536 static void
ixgbe_config_gpie(struct ixgbe_softc * sc)4537 ixgbe_config_gpie(struct ixgbe_softc *sc)
4538 {
4539 struct ixgbe_hw *hw = &sc->hw;
4540 u32 gpie;
4541
4542 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4543
4544 if (sc->intr_type == IFLIB_INTR_MSIX) {
4545 /* Enable Enhanced MSI-X mode */
4546 gpie |= IXGBE_GPIE_MSIX_MODE |
4547 IXGBE_GPIE_EIAME |
4548 IXGBE_GPIE_PBA_SUPPORT |
4549 IXGBE_GPIE_OCD;
4550 }
4551
4552 /* Fan Failure Interrupt */
4553 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL)
4554 gpie |= IXGBE_SDP1_GPIEN;
4555
4556 /* Thermal Sensor Interrupt */
4557 if (sc->feat_en & IXGBE_FEATURE_TEMP_SENSOR)
4558 gpie |= IXGBE_SDP0_GPIEN_X540;
4559
4560 /* Link detection */
4561 switch (hw->mac.type) {
4562 case ixgbe_mac_82599EB:
4563 gpie |= IXGBE_SDP1_GPIEN | IXGBE_SDP2_GPIEN;
4564 break;
4565 case ixgbe_mac_X550EM_x:
4566 case ixgbe_mac_X550EM_a:
4567 gpie |= IXGBE_SDP0_GPIEN_X540;
4568 break;
4569 default:
4570 break;
4571 }
4572
4573 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4574
4575 } /* ixgbe_config_gpie */
4576
4577 /************************************************************************
4578 * ixgbe_config_delay_values
4579 *
4580 * Requires sc->max_frame_size to be set.
4581 ************************************************************************/
4582 static void
ixgbe_config_delay_values(struct ixgbe_softc * sc)4583 ixgbe_config_delay_values(struct ixgbe_softc *sc)
4584 {
4585 struct ixgbe_hw *hw = &sc->hw;
4586 u32 rxpb, frame, size, tmp;
4587
4588 frame = sc->max_frame_size;
4589
4590 /* Calculate High Water */
4591 switch (hw->mac.type) {
4592 case ixgbe_mac_X540:
4593 case ixgbe_mac_X550:
4594 case ixgbe_mac_X550EM_x:
4595 case ixgbe_mac_X550EM_a:
4596 tmp = IXGBE_DV_X540(frame, frame);
4597 break;
4598 default:
4599 tmp = IXGBE_DV(frame, frame);
4600 break;
4601 }
4602 size = IXGBE_BT2KB(tmp);
4603 rxpb = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) >> 10;
4604 hw->fc.high_water[0] = rxpb - size;
4605
4606 /* Now calculate Low Water */
4607 switch (hw->mac.type) {
4608 case ixgbe_mac_X540:
4609 case ixgbe_mac_X550:
4610 case ixgbe_mac_X550EM_x:
4611 case ixgbe_mac_X550EM_a:
4612 tmp = IXGBE_LOW_DV_X540(frame);
4613 break;
4614 default:
4615 tmp = IXGBE_LOW_DV(frame);
4616 break;
4617 }
4618 hw->fc.low_water[0] = IXGBE_BT2KB(tmp);
4619
4620 hw->fc.pause_time = IXGBE_FC_PAUSE;
4621 hw->fc.send_xon = true;
4622 } /* ixgbe_config_delay_values */
4623
4624 /************************************************************************
4625 * ixgbe_set_multi - Multicast Update
4626 *
4627 * Called whenever multicast address list is updated.
4628 ************************************************************************/
4629 static u_int
ixgbe_mc_filter_apply(void * arg,struct sockaddr_dl * sdl,u_int idx)4630 ixgbe_mc_filter_apply(void *arg, struct sockaddr_dl *sdl, u_int idx)
4631 {
4632 struct ixgbe_softc *sc = arg;
4633 struct ixgbe_mc_addr *mta = sc->mta;
4634
4635 if (idx == MAX_NUM_MULTICAST_ADDRESSES)
4636 return (0);
4637 bcopy(LLADDR(sdl), mta[idx].addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
4638 mta[idx].vmdq = sc->pool;
4639
4640 return (1);
4641 } /* ixgbe_mc_filter_apply */
4642
4643 #ifdef PCI_IOV
4644 /*
4645 * The MTA is shared by the PF and every VF. Rebuild it from all owners
4646 * because an individual bit cannot be cleared safely when hashes collide.
4647 */
4648 u_int
ixgbe_iov_rebuild_mta(struct ixgbe_softc * sc)4649 ixgbe_iov_rebuild_mta(struct ixgbe_softc *sc)
4650 {
4651 struct ixgbe_hw *hw;
4652 struct ixgbe_mc_addr *mta;
4653 struct ixgbe_vf *vf;
4654 u32 old_mta[IXGBE_MAX_MTA];
4655 u32 hash;
4656 u_int i, mcnt;
4657 int vf_index;
4658
4659 hw = &sc->hw;
4660 mta = sc->mta;
4661 bzero(mta, sizeof(*mta) * MAX_NUM_MULTICAST_ADDRESSES);
4662 mcnt = if_foreach_llmaddr(iflib_get_ifp(sc->ctx),
4663 ixgbe_mc_filter_apply, sc);
4664
4665 bcopy(hw->mac.mta_shadow, old_mta, sizeof(old_mta));
4666 bzero(hw->mac.mta_shadow, sizeof(hw->mac.mta_shadow));
4667 hw->addr_ctrl.num_mc_addrs = mcnt;
4668 hw->addr_ctrl.mta_in_use = 0;
4669
4670 for (i = 0; i < mcnt; i++)
4671 ixgbe_set_mta(hw, mta[i].addr);
4672
4673 for (vf_index = 0; vf_index < sc->num_vfs; vf_index++) {
4674 vf = &sc->vfs[vf_index];
4675 if (!(vf->flags & IXGBE_VF_ACTIVE))
4676 continue;
4677
4678 for (i = 0; i < vf->num_mc_hashes; i++) {
4679 hash = vf->mc_hash[i] & 0xfff;
4680 hw->mac.mta_shadow[(hash >> 5) &
4681 (hw->mac.mcft_size - 1)] |=
4682 1U << (hash & 0x1f);
4683 hw->addr_ctrl.mta_in_use++;
4684 }
4685 }
4686
4687 for (i = 0; i < hw->mac.mcft_size; i++) {
4688 if (sc->iov_mta_valid &&
4689 old_mta[i] == hw->mac.mta_shadow[i])
4690 continue;
4691 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
4692 hw->mac.mta_shadow[i]);
4693 }
4694 sc->iov_mta_valid = true;
4695
4696 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4697 (hw->addr_ctrl.mta_in_use != 0 ? IXGBE_MCSTCTRL_MFE : 0) |
4698 hw->mac.mc_filter_type);
4699
4700 return (mcnt);
4701 }
4702 #endif
4703
4704 static void
ixgbe_if_multi_set(if_ctx_t ctx)4705 ixgbe_if_multi_set(if_ctx_t ctx)
4706 {
4707 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4708 struct ixgbe_mc_addr *mta;
4709 if_t ifp = iflib_get_ifp(ctx);
4710 u8 *update_ptr;
4711 u32 fctrl;
4712 u_int mcnt;
4713
4714 IOCTL_DEBUGOUT("ixgbe_if_multi_set: begin");
4715
4716 #ifdef PCI_IOV
4717 if (sc->feat_en & IXGBE_FEATURE_SRIOV) {
4718 mcnt = ixgbe_iov_rebuild_mta(sc);
4719 } else
4720 #endif
4721 {
4722 mta = sc->mta;
4723 bzero(mta, sizeof(*mta) * MAX_NUM_MULTICAST_ADDRESSES);
4724
4725 mcnt = if_foreach_llmaddr(iflib_get_ifp(ctx),
4726 ixgbe_mc_filter_apply, sc);
4727
4728 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) {
4729 update_ptr = (u8 *)mta;
4730 ixgbe_update_mc_addr_list(&sc->hw, update_ptr, mcnt,
4731 ixgbe_mc_array_itr, true);
4732 }
4733 }
4734
4735 fctrl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL);
4736
4737 if (if_getflags(ifp) & IFF_PROMISC)
4738 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4739 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
4740 if_getflags(ifp) & IFF_ALLMULTI) {
4741 fctrl |= IXGBE_FCTRL_MPE;
4742 fctrl &= ~IXGBE_FCTRL_UPE;
4743 } else
4744 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4745
4746 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, fctrl);
4747 } /* ixgbe_if_multi_set */
4748
4749 /************************************************************************
4750 * ixgbe_mc_array_itr
4751 *
4752 * An iterator function needed by the multicast shared code.
4753 * It feeds the shared code routine the addresses in the
4754 * array of ixgbe_set_multi() one by one.
4755 ************************************************************************/
4756 static u8 *
ixgbe_mc_array_itr(struct ixgbe_hw * hw,u8 ** update_ptr,u32 * vmdq)4757 ixgbe_mc_array_itr(struct ixgbe_hw *hw, u8 **update_ptr, u32 *vmdq)
4758 {
4759 struct ixgbe_mc_addr *mta;
4760
4761 mta = (struct ixgbe_mc_addr *)*update_ptr;
4762 *vmdq = mta->vmdq;
4763
4764 *update_ptr = (u8*)(mta + 1);
4765
4766 return (mta->addr);
4767 } /* ixgbe_mc_array_itr */
4768
4769 /************************************************************************
4770 * ixgbe_local_timer - Timer routine
4771 *
4772 * Checks for link status, updates statistics,
4773 * and runs the watchdog check.
4774 ************************************************************************/
4775 static void
ixgbe_if_timer(if_ctx_t ctx,uint16_t qid)4776 ixgbe_if_timer(if_ctx_t ctx, uint16_t qid)
4777 {
4778 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4779
4780 if (qid != 0)
4781 return;
4782
4783 /* Check for pluggable optics */
4784 if (sc->sfp_probe)
4785 if (!ixgbe_sfp_probe(ctx))
4786 return; /* Nothing to do */
4787
4788 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up, 0);
4789
4790 /* Fire off the adminq task */
4791 iflib_admin_intr_deferred(ctx);
4792
4793 } /* ixgbe_if_timer */
4794
4795 /************************************************************************
4796 * ixgbe_fw_mode_timer - FW mode timer routine
4797 ************************************************************************/
4798 static void
ixgbe_fw_mode_timer(void * arg)4799 ixgbe_fw_mode_timer(void *arg)
4800 {
4801 struct ixgbe_softc *sc = arg;
4802 struct ixgbe_hw *hw = &sc->hw;
4803
4804 if (atomic_load_acq_int(&sc->fw_mode_timer_paused) != 0)
4805 return;
4806
4807 if (ixgbe_fw_recovery_mode(hw)) {
4808 if (atomic_cmpset_acq_int(&sc->recovery_mode, 0, 1)) {
4809 /* Firmware error detected, entering recovery mode */
4810 device_printf(sc->dev,
4811 "Firmware recovery mode detected. Limiting"
4812 " functionality. Refer to the Intel(R) Ethernet"
4813 " Adapters and Devices User Guide for details on"
4814 " firmware recovery mode.\n");
4815
4816 /* Stop and publish the failure from the iflib taskqueue. */
4817 iflib_request_reset_if_up(sc->ctx);
4818 iflib_admin_intr_deferred(sc->ctx);
4819 }
4820 } else if (atomic_cmpset_acq_int(&sc->recovery_mode, 1, 0)) {
4821 /* Reinitialize an interface which was up when recovery began. */
4822 iflib_request_reset_if_up(sc->ctx);
4823 iflib_admin_intr_deferred(sc->ctx);
4824 }
4825
4826 if (atomic_load_acq_int(&sc->fw_mode_timer_paused) == 0)
4827 callout_reset(&sc->fw_mode_timer, hz,
4828 ixgbe_fw_mode_timer, sc);
4829 } /* ixgbe_fw_mode_timer */
4830
4831 static void
ixgbe_fw_mode_timer_pause(struct ixgbe_softc * sc)4832 ixgbe_fw_mode_timer_pause(struct ixgbe_softc *sc)
4833 {
4834
4835 if (!sc->fw_mode_timer_initialized ||
4836 atomic_swap_int(&sc->fw_mode_timer_paused, 1) != 0)
4837 return;
4838 callout_drain(&sc->fw_mode_timer);
4839 }
4840
4841 static void
ixgbe_fw_mode_timer_resume(struct ixgbe_softc * sc)4842 ixgbe_fw_mode_timer_resume(struct ixgbe_softc *sc)
4843 {
4844
4845 if (!sc->fw_mode_timer_initialized ||
4846 atomic_swap_int(&sc->fw_mode_timer_paused, 0) == 0)
4847 return;
4848 callout_reset(&sc->fw_mode_timer, hz, ixgbe_fw_mode_timer, sc);
4849 }
4850
4851 /************************************************************************
4852 * ixgbe_sfp_probe
4853 *
4854 * Determine if a port had optics inserted.
4855 ************************************************************************/
4856 static bool
ixgbe_sfp_probe(if_ctx_t ctx)4857 ixgbe_sfp_probe(if_ctx_t ctx)
4858 {
4859 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4860 struct ixgbe_hw *hw = &sc->hw;
4861 device_t dev = iflib_get_dev(ctx);
4862 bool result = false;
4863
4864 if ((hw->phy.type == ixgbe_phy_nl) &&
4865 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4866 s32 ret = hw->phy.ops.identify_sfp(hw);
4867 if (ret)
4868 goto out;
4869 ret = hw->phy.ops.reset(hw);
4870 sc->sfp_probe = false;
4871 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4872 device_printf(dev,
4873 "Unsupported SFP+ module detected!");
4874 device_printf(dev,
4875 "Reload driver with supported module.\n");
4876 goto out;
4877 } else
4878 device_printf(dev, "SFP+ module detected!\n");
4879 /* We now have supported optics */
4880 result = true;
4881 }
4882 out:
4883
4884 return (result);
4885 } /* ixgbe_sfp_probe */
4886
4887 /************************************************************************
4888 * ixgbe_handle_mod - Tasklet for SFP module interrupts
4889 ************************************************************************/
4890 static bool
ixgbe_handle_mod(void * context)4891 ixgbe_handle_mod(void *context)
4892 {
4893 if_ctx_t ctx = context;
4894 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4895 struct ixgbe_hw *hw = &sc->hw;
4896 device_t dev = iflib_get_dev(ctx);
4897 u32 err, cage_full = 0;
4898
4899 if (sc->hw.need_crosstalk_fix) {
4900 switch (hw->mac.type) {
4901 case ixgbe_mac_82599EB:
4902 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4903 IXGBE_ESDP_SDP2;
4904 break;
4905 case ixgbe_mac_X550EM_x:
4906 case ixgbe_mac_X550EM_a:
4907 cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4908 IXGBE_ESDP_SDP0;
4909 break;
4910 default:
4911 break;
4912 }
4913
4914 if (!cage_full)
4915 goto handle_mod_out;
4916 }
4917
4918 err = hw->phy.ops.identify_sfp(hw);
4919 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4920 device_printf(dev,
4921 "Unsupported SFP+ module type was detected.\n");
4922 goto handle_mod_out;
4923 }
4924
4925 if (hw->mac.type == ixgbe_mac_82598EB)
4926 err = hw->phy.ops.reset(hw);
4927 else
4928 err = hw->mac.ops.setup_sfp(hw);
4929
4930 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4931 device_printf(dev,
4932 "Setup failure - unsupported SFP+ module type.\n");
4933 goto handle_mod_out;
4934 }
4935 return (true);
4936
4937 handle_mod_out:
4938 return (false);
4939 } /* ixgbe_handle_mod */
4940
4941
4942 /************************************************************************
4943 * ixgbe_handle_msf - Tasklet for MSF (multispeed fiber) interrupts
4944 ************************************************************************/
4945 static void
ixgbe_handle_msf(void * context)4946 ixgbe_handle_msf(void *context)
4947 {
4948 if_ctx_t ctx = context;
4949 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4950 struct ixgbe_hw *hw = &sc->hw;
4951 u32 autoneg;
4952 bool negotiate;
4953
4954 /* get_supported_phy_layer will call hw->phy.ops.identify_sfp() */
4955 sc->phy_layer = ixgbe_get_supported_physical_layer(hw);
4956
4957 autoneg = hw->phy.autoneg_advertised;
4958 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4959 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiate);
4960 if (hw->mac.ops.setup_link)
4961 hw->mac.ops.setup_link(hw, autoneg, true);
4962
4963 /* Adjust media types shown in ifconfig */
4964 ifmedia_removeall(sc->media);
4965 ixgbe_add_media_types(sc->ctx);
4966 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
4967 } /* ixgbe_handle_msf */
4968
4969 /************************************************************************
4970 * ixgbe_handle_phy - Tasklet for external PHY interrupts
4971 ************************************************************************/
4972 static void
ixgbe_handle_phy(void * context)4973 ixgbe_handle_phy(void *context)
4974 {
4975 if_ctx_t ctx = context;
4976 struct ixgbe_softc *sc = iflib_get_softc(ctx);
4977 struct ixgbe_hw *hw = &sc->hw;
4978 int error;
4979
4980 error = hw->phy.ops.handle_lasi(hw);
4981 if (error == IXGBE_ERR_OVERTEMP)
4982 device_printf(sc->dev,
4983 "CRITICAL: EXTERNAL PHY OVER TEMP!!"
4984 " PHY will downshift to lower power state!\n");
4985 else if (error)
4986 device_printf(sc->dev,
4987 "Error handling LASI interrupt: %d\n", error);
4988 } /* ixgbe_handle_phy */
4989
4990 /************************************************************************
4991 * ixgbe_enable_lse - enable link status events
4992 *
4993 * Sets mask and enables link status events
4994 ************************************************************************/
ixgbe_enable_lse(struct ixgbe_softc * sc)4995 s32 ixgbe_enable_lse(struct ixgbe_softc *sc)
4996 {
4997 s32 error;
4998
4999 u16 mask = ~((u16)(IXGBE_ACI_LINK_EVENT_UPDOWN |
5000 IXGBE_ACI_LINK_EVENT_MEDIA_NA |
5001 IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL |
5002 IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL));
5003
5004 error = ixgbe_configure_lse(&sc->hw, TRUE, mask);
5005 if (error)
5006 return (error);
5007
5008 sc->lse_mask = mask;
5009 return (IXGBE_SUCCESS);
5010 } /* ixgbe_enable_lse */
5011
5012 /************************************************************************
5013 * ixgbe_disable_lse - disable link status events
5014 ************************************************************************/
ixgbe_disable_lse(struct ixgbe_softc * sc)5015 s32 ixgbe_disable_lse(struct ixgbe_softc *sc)
5016 {
5017 s32 error;
5018
5019 error = ixgbe_configure_lse(&sc->hw, false, sc->lse_mask);
5020 if (error)
5021 return (error);
5022
5023 sc->lse_mask = 0;
5024 return (IXGBE_SUCCESS);
5025 } /* ixgbe_disable_lse */
5026
5027 /************************************************************************
5028 * ixgbe_handle_fw_event - Tasklet for MSI-X Link Status Event interrupts
5029 ************************************************************************/
5030 static u32
ixgbe_handle_fw_event(void * context)5031 ixgbe_handle_fw_event(void *context)
5032 {
5033 if_ctx_t ctx = context;
5034 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5035 struct ixgbe_hw *hw = &sc->hw;
5036 struct ixgbe_aci_event event;
5037 bool pending = false;
5038 s32 error;
5039 u32 requests = 0;
5040
5041 event.buf_len = IXGBE_ACI_MAX_BUFFER_SIZE;
5042 event.msg_buf = malloc(event.buf_len, M_IXGBE, M_ZERO | M_NOWAIT);
5043 if (!event.msg_buf) {
5044 device_printf(sc->dev, "Can not allocate buffer for "
5045 "event message\n");
5046 return (0);
5047 }
5048
5049 do {
5050 error = ixgbe_aci_get_event(hw, &event, &pending);
5051 if (error) {
5052 device_printf(sc->dev, "Error getting event from "
5053 "FW:%d\n", error);
5054 break;
5055 }
5056
5057 switch (le16toh(event.desc.opcode)) {
5058 case ixgbe_aci_opc_get_link_status:
5059 requests |= IXGBE_REQUEST_TASK_LSC;
5060 break;
5061
5062 case ixgbe_aci_opc_fw_logs_event:
5063 ixgbe_fwlog_event_dump(&sc->hw, &event.desc, event.msg_buf);
5064 break;
5065
5066 case ixgbe_aci_opc_temp_tca_event:
5067 if (!sc->overtemp_shutdown_pending) {
5068 sc->overtemp_shutdown_pending = true;
5069 requests |= IXGBE_REQUEST_TASK_RESET;
5070 device_printf(sc->dev,
5071 "CRITICAL: OVER TEMP!! PHY IS SHUT DOWN!!\n");
5072 device_printf(sc->dev,
5073 "System shutdown required!\n");
5074 }
5075 break;
5076
5077 default:
5078 device_printf(sc->dev,
5079 "Unknown FW event captured, opcode=0x%04X\n",
5080 le16toh(event.desc.opcode));
5081 break;
5082 }
5083 } while (pending);
5084
5085 free(event.msg_buf, M_IXGBE);
5086 return (requests);
5087 } /* ixgbe_handle_fw_event */
5088
5089 /************************************************************************
5090 * ixgbe_if_stop - Stop the hardware
5091 *
5092 * Disables all traffic on the adapter by issuing a
5093 * global reset on the MAC and deallocates TX/RX buffers.
5094 ************************************************************************/
5095 static void
ixgbe_if_stop(if_ctx_t ctx)5096 ixgbe_if_stop(if_ctx_t ctx)
5097 {
5098 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5099 struct ixgbe_hw *hw = &sc->hw;
5100
5101 INIT_DEBUGOUT("ixgbe_if_stop: begin\n");
5102
5103 ixgbe_led_restore(sc);
5104 if (sc->feat_en & IXGBE_FEATURE_SRIOV) {
5105 ixgbe_disable_mdd(hw);
5106 ixgbe_quiesce_vfs(sc);
5107 }
5108 ixgbe_reset_hw(hw);
5109 atomic_store_rel_int(&sc->ecc_reset_pending, 0);
5110 hw->adapter_stopped = false;
5111 ixgbe_stop_adapter(hw);
5112 /* Turn off the laser - noop with no optics */
5113 ixgbe_disable_tx_laser(hw);
5114
5115 /* Update the stack */
5116 sc->link_up = false;
5117 if (sc->link_active) {
5118 if (bootverbose)
5119 device_printf(sc->dev, "Link is Down\n");
5120 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
5121 sc->link_active = false;
5122 }
5123
5124 /* reprogram the RAR[0] in case user changed it. */
5125 ixgbe_set_rar(&sc->hw, 0, sc->hw.mac.addr, 0, IXGBE_RAH_AV);
5126
5127 return;
5128 } /* ixgbe_if_stop */
5129
5130 /*
5131 * Identify the physical port while retaining the NVM-selected LED mode.
5132 * E610 exposes identification through firmware rather than LEDCTL.
5133 */
5134 static void
ixgbe_if_led_func(if_ctx_t ctx,int onoff)5135 ixgbe_if_led_func(if_ctx_t ctx, int onoff)
5136 {
5137 struct ixgbe_softc *sc;
5138 struct ixgbe_hw *hw;
5139
5140 sc = iflib_get_softc(ctx);
5141 hw = &sc->hw;
5142 if (!onoff) {
5143 ixgbe_led_restore(sc);
5144 return;
5145 }
5146 if (sc->led_active)
5147 return;
5148
5149 if (hw->mac.type == ixgbe_mac_E610) {
5150 if (ixgbe_aci_set_port_id_led(hw, false) == IXGBE_SUCCESS)
5151 sc->led_active = true;
5152 return;
5153 }
5154
5155 sc->ledctl_default = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
5156 if (ixgbe_led_on(hw, hw->mac.led_link_act) == IXGBE_SUCCESS)
5157 sc->led_active = true;
5158 }
5159
5160 static void
ixgbe_led_restore(struct ixgbe_softc * sc)5161 ixgbe_led_restore(struct ixgbe_softc *sc)
5162 {
5163 struct ixgbe_hw *hw;
5164
5165 if (!sc->led_active)
5166 return;
5167
5168 hw = &sc->hw;
5169 if (hw->mac.type == ixgbe_mac_E610) {
5170 (void)ixgbe_aci_set_port_id_led(hw, true);
5171 } else {
5172 /* Clear any PHY manual override before restoring LEDCTL. */
5173 (void)ixgbe_led_off(hw, hw->mac.led_link_act);
5174 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, sc->ledctl_default);
5175 IXGBE_WRITE_FLUSH(hw);
5176 }
5177 sc->led_active = false;
5178 }
5179
5180 /************************************************************************
5181 * ixgbe_link_speed_to_str - Convert link speed to string
5182 *
5183 * Helper function to convert link speed constants to human-readable
5184 * string representations in conventional Gbps or Mbps.
5185 ************************************************************************/
5186 static const char *
ixgbe_link_speed_to_str(u32 link_speed)5187 ixgbe_link_speed_to_str(u32 link_speed)
5188 {
5189 switch (link_speed) {
5190 case IXGBE_LINK_SPEED_10GB_FULL:
5191 return "10 Gbps";
5192 case IXGBE_LINK_SPEED_5GB_FULL:
5193 return "5 Gbps";
5194 case IXGBE_LINK_SPEED_2_5GB_FULL:
5195 return "2.5 Gbps";
5196 case IXGBE_LINK_SPEED_1GB_FULL:
5197 return "1 Gbps";
5198 case IXGBE_LINK_SPEED_100_FULL:
5199 return "100 Mbps";
5200 case IXGBE_LINK_SPEED_10_FULL:
5201 return "10 Mbps";
5202 default:
5203 return "Unknown";
5204 }
5205 } /* ixgbe_link_speed_to_str */
5206
5207 /************************************************************************
5208 * ixgbe_update_link_status - Update OS on link state
5209 *
5210 * Process deferred administrative requests and update the OS link state.
5211 ************************************************************************/
5212 static void
ixgbe_if_update_admin_status(if_ctx_t ctx)5213 ixgbe_if_update_admin_status(if_ctx_t ctx)
5214 {
5215 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5216 device_t dev = iflib_get_dev(ctx);
5217 u32 requests;
5218 u_int pass;
5219 bool check_link = false;
5220
5221 /*
5222 * The interrupt filter and other producers can run concurrently with
5223 * this task. Claim each batch atomically so a request posted while the
5224 * task is running remains pending for this or the next invocation.
5225 *
5226 * MOD and firmware events can produce dependent requests. Fold those
5227 * into the claimed batch so link state is sampled after any link setup.
5228 */
5229 if (iflib_is_running(ctx) &&
5230 (sc->iov_mbx_cleanup_pending || ixgbe_mbx_pending(sc)))
5231 atomic_set_32(&sc->task_requests, IXGBE_REQUEST_TASK_MBX);
5232 for (pass = 0; pass < IXGBE_ADMIN_TASK_BUDGET; pass++) {
5233 requests = atomic_readandclear_32(&sc->task_requests);
5234 if (requests == 0)
5235 break;
5236 if (requests & IXGBE_REQUEST_TASK_FWEVENT)
5237 requests |= ixgbe_handle_fw_event(ctx);
5238 if (requests & IXGBE_REQUEST_TASK_MOD) {
5239 if (ixgbe_handle_mod(ctx))
5240 requests |= IXGBE_REQUEST_TASK_MSF;
5241 else
5242 requests &= ~IXGBE_REQUEST_TASK_MSF;
5243 }
5244 if (requests & IXGBE_REQUEST_TASK_MSF)
5245 ixgbe_handle_msf(ctx);
5246 /* A reset request can re-enable VF traffic; skip it while stopped. */
5247 if ((requests & IXGBE_REQUEST_TASK_MBX) != 0 &&
5248 iflib_is_running(ctx))
5249 ixgbe_handle_mbx(ctx);
5250 if (requests & IXGBE_REQUEST_TASK_FDIR)
5251 ixgbe_reinit_fdir(ctx);
5252 if (requests & IXGBE_REQUEST_TASK_PHY)
5253 ixgbe_handle_phy(ctx);
5254 if (requests & IXGBE_REQUEST_TASK_LSC)
5255 check_link = true;
5256 if (requests & IXGBE_REQUEST_TASK_RESET) {
5257 /* Re-enter the admin task so it observes IFC_DO_RESET. */
5258 iflib_request_reset(ctx);
5259 iflib_admin_intr_deferred(ctx);
5260 }
5261 }
5262
5263 /* Do not let a continuous producer monopolize the admin taskqueue. */
5264 if (atomic_load_acq_32(&sc->task_requests) != 0)
5265 iflib_admin_intr_deferred(ctx);
5266
5267 if (check_link)
5268 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up,
5269 false);
5270
5271 if (sc->link_up) {
5272 if (sc->link_active == false) {
5273 if (bootverbose)
5274 device_printf(dev,
5275 "Link is up %s Full Duplex\n",
5276 ixgbe_link_speed_to_str(sc->link_speed));
5277 sc->link_active = true;
5278
5279 /* If link speed is <= 1Gbps and EEE is enabled,
5280 * log info.
5281 */
5282 if (sc->hw.mac.type == ixgbe_mac_E610 &&
5283 (sc->feat_en & IXGBE_FEATURE_EEE) &&
5284 sc->link_speed <= IXGBE_LINK_SPEED_1GB_FULL) {
5285 device_printf(sc->dev,
5286 "Energy Efficient Ethernet (EEE) feature "
5287 "is not supported on link speeds equal to "
5288 "or below 1Gbps. EEE is supported on "
5289 "speeds above 1Gbps.\n");
5290 }
5291
5292 /* Update any Flow Control changes */
5293 ixgbe_fc_enable(&sc->hw);
5294 /* Update DMA coalescing config */
5295 ixgbe_config_dmac(sc);
5296 iflib_link_state_change(ctx, LINK_STATE_UP,
5297 ixgbe_link_speed_to_baudrate(sc->link_speed));
5298
5299 if (sc->feat_en & IXGBE_FEATURE_SRIOV)
5300 ixgbe_ping_all_vfs(sc);
5301 }
5302 } else { /* Link down */
5303 if (sc->link_active == true) {
5304 if (bootverbose)
5305 device_printf(dev, "Link is Down\n");
5306 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
5307 sc->link_active = false;
5308 if (sc->feat_en & IXGBE_FEATURE_SRIOV)
5309 ixgbe_ping_all_vfs(sc);
5310 }
5311 }
5312
5313 ixgbe_schedule_iov_recovery(sc);
5314
5315 ixgbe_update_stats_counters(sc);
5316 } /* ixgbe_if_update_admin_status */
5317
5318 /************************************************************************
5319 * ixgbe_config_dmac - Configure DMA Coalescing
5320 ************************************************************************/
5321 static void
ixgbe_config_dmac(struct ixgbe_softc * sc)5322 ixgbe_config_dmac(struct ixgbe_softc *sc)
5323 {
5324 struct ixgbe_hw *hw = &sc->hw;
5325 struct ixgbe_dmac_config *dcfg = &hw->mac.dmac_config;
5326
5327 if (hw->mac.type < ixgbe_mac_X550 || !hw->mac.ops.dmac_config)
5328 return;
5329
5330 if (dcfg->watchdog_timer ^ sc->dmac ||
5331 dcfg->link_speed ^ sc->link_speed) {
5332 dcfg->watchdog_timer = sc->dmac;
5333 dcfg->fcoe_en = false;
5334 dcfg->link_speed = sc->link_speed;
5335 dcfg->num_tcs = 1;
5336
5337 INIT_DEBUGOUT2("dmac settings: watchdog %d, link speed %d\n",
5338 dcfg->watchdog_timer, dcfg->link_speed);
5339
5340 hw->mac.ops.dmac_config(hw);
5341 }
5342 } /* ixgbe_config_dmac */
5343
5344 /************************************************************************
5345 * ixgbe_if_enable_intr
5346 ************************************************************************/
5347 void
ixgbe_if_enable_intr(if_ctx_t ctx)5348 ixgbe_if_enable_intr(if_ctx_t ctx)
5349 {
5350 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5351 struct ixgbe_hw *hw = &sc->hw;
5352 struct ix_rx_queue *que = sc->rx_queues;
5353 u32 mask, fwsm;
5354
5355 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
5356
5357 switch (sc->hw.mac.type) {
5358 case ixgbe_mac_82599EB:
5359 mask |= IXGBE_EIMS_ECC;
5360 /* Temperature sensor on some scs */
5361 mask |= IXGBE_EIMS_GPI_SDP0;
5362 /* SFP+ (RX_LOS_N & MOD_ABS_N) */
5363 mask |= IXGBE_EIMS_GPI_SDP1;
5364 mask |= IXGBE_EIMS_GPI_SDP2;
5365 break;
5366 case ixgbe_mac_X540:
5367 /* Detect if Thermal Sensor is enabled */
5368 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5369 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5370 mask |= IXGBE_EIMS_TS;
5371 mask |= IXGBE_EIMS_ECC;
5372 break;
5373 case ixgbe_mac_X550:
5374 /* MAC thermal sensor is automatically enabled */
5375 mask |= IXGBE_EIMS_TS;
5376 mask |= IXGBE_EIMS_ECC;
5377 break;
5378 case ixgbe_mac_X550EM_x:
5379 case ixgbe_mac_X550EM_a:
5380 /* Some devices use SDP0 for important information */
5381 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
5382 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
5383 hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N ||
5384 hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T)
5385 mask |= IXGBE_EIMS_GPI_SDP0_BY_MAC(hw);
5386 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
5387 mask |= IXGBE_EICR_GPI_SDP0_X540;
5388 mask |= IXGBE_EIMS_ECC;
5389 break;
5390 case ixgbe_mac_E610:
5391 mask |= IXGBE_EIMS_FW_EVENT;
5392 break;
5393 default:
5394 break;
5395 }
5396
5397 /* Enable Fan Failure detection */
5398 if (sc->feat_en & IXGBE_FEATURE_FAN_FAIL)
5399 mask |= IXGBE_EIMS_GPI_SDP1;
5400 /* Enable SR-IOV */
5401 if (sc->feat_en & IXGBE_FEATURE_SRIOV)
5402 mask |= IXGBE_EIMS_MAILBOX;
5403 /* Enable Flow Director */
5404 if (sc->feat_en & IXGBE_FEATURE_FDIR)
5405 mask |= IXGBE_EIMS_FLOW_DIR;
5406 if (atomic_load_acq_int(&sc->ecc_reset_pending))
5407 mask &= ~IXGBE_EIMS_ECC;
5408
5409 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
5410
5411 /* With MSI-X we use auto clear */
5412 if (sc->intr_type == IFLIB_INTR_MSIX) {
5413 mask = IXGBE_EIMS_ENABLE_MASK;
5414 /* Don't autoclear Link */
5415 mask &= ~IXGBE_EIMS_OTHER;
5416 mask &= ~IXGBE_EIMS_LSC;
5417 mask &= ~IXGBE_EIMS_FW_EVENT;
5418 if (sc->feat_cap & IXGBE_FEATURE_SRIOV)
5419 mask &= ~IXGBE_EIMS_MAILBOX;
5420 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5421 }
5422
5423 /*
5424 * Now enable all queues, this is done separately to
5425 * allow for handling the extended (beyond 32) MSI-X
5426 * vectors that can be used by 82599
5427 */
5428 for (int i = 0; i < sc->num_rx_queues; i++, que++)
5429 ixgbe_enable_queue(sc, que->msix);
5430
5431 IXGBE_WRITE_FLUSH(hw);
5432
5433 } /* ixgbe_if_enable_intr */
5434
5435 /************************************************************************
5436 * ixgbe_if_disable_intr
5437 ************************************************************************/
5438 static void
ixgbe_if_disable_intr(if_ctx_t ctx)5439 ixgbe_if_disable_intr(if_ctx_t ctx)
5440 {
5441 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5442
5443 if (sc->intr_type == IFLIB_INTR_MSIX)
5444 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAC, 0);
5445 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
5446 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, ~0);
5447 } else {
5448 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, 0xFFFF0000);
5449 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(0), ~0);
5450 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(1), ~0);
5451 }
5452 IXGBE_WRITE_FLUSH(&sc->hw);
5453
5454 } /* ixgbe_if_disable_intr */
5455
5456 /************************************************************************
5457 * ixgbe_link_intr_enable
5458 ************************************************************************/
5459 static void
ixgbe_link_intr_enable(if_ctx_t ctx)5460 ixgbe_link_intr_enable(if_ctx_t ctx)
5461 {
5462 struct ixgbe_hw *hw =
5463 &((struct ixgbe_softc *)iflib_get_softc(ctx))->hw;
5464
5465 /* Re-enable other interrupts */
5466 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
5467 } /* ixgbe_link_intr_enable */
5468
5469 /************************************************************************
5470 * ixgbe_if_rx_queue_intr_enable
5471 ************************************************************************/
5472 static int
ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t rxqid)5473 ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
5474 {
5475 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5476 struct ix_rx_queue *que = &sc->rx_queues[rxqid];
5477
5478 ixgbe_enable_queue(sc, que->msix);
5479
5480 return (0);
5481 } /* ixgbe_if_rx_queue_intr_enable */
5482
5483 /************************************************************************
5484 * ixgbe_enable_queue
5485 ************************************************************************/
5486 static void
ixgbe_enable_queue(struct ixgbe_softc * sc,u32 vector)5487 ixgbe_enable_queue(struct ixgbe_softc *sc, u32 vector)
5488 {
5489 struct ixgbe_hw *hw = &sc->hw;
5490 u64 queue = 1ULL << vector;
5491 u32 mask;
5492
5493 if (hw->mac.type == ixgbe_mac_82598EB) {
5494 mask = (IXGBE_EIMS_RTX_QUEUE & queue);
5495 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
5496 } else {
5497 mask = (queue & 0xFFFFFFFF);
5498 if (mask)
5499 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5500 mask = (queue >> 32);
5501 if (mask)
5502 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5503 }
5504 } /* ixgbe_enable_queue */
5505
5506 /************************************************************************
5507 * ixgbe_disable_queue
5508 ************************************************************************/
5509 static void
ixgbe_disable_queue(struct ixgbe_softc * sc,u32 vector)5510 ixgbe_disable_queue(struct ixgbe_softc *sc, u32 vector)
5511 {
5512 struct ixgbe_hw *hw = &sc->hw;
5513 u64 queue = 1ULL << vector;
5514 u32 mask;
5515
5516 if (hw->mac.type == ixgbe_mac_82598EB) {
5517 mask = (IXGBE_EIMS_RTX_QUEUE & queue);
5518 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
5519 } else {
5520 mask = (queue & 0xFFFFFFFF);
5521 if (mask)
5522 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
5523 mask = (queue >> 32);
5524 if (mask)
5525 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
5526 }
5527 } /* ixgbe_disable_queue */
5528
5529 /************************************************************************
5530 * ixgbe_intr - Legacy Interrupt Service Routine
5531 ************************************************************************/
5532 int
ixgbe_intr(void * arg)5533 ixgbe_intr(void *arg)
5534 {
5535 struct ixgbe_softc *sc = arg;
5536 struct ix_rx_queue *que = sc->rx_queues;
5537 struct ixgbe_hw *hw = &sc->hw;
5538 if_ctx_t ctx = sc->ctx;
5539 u32 eicr, eicr_mask, requests;
5540
5541 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
5542 requests = 0;
5543
5544 ++que->irqs;
5545 if (eicr == 0) {
5546 ixgbe_if_enable_intr(ctx);
5547 return (FILTER_HANDLED);
5548 }
5549
5550 /* Check for fan failure */
5551 if ((sc->feat_en & IXGBE_FEATURE_FAN_FAIL) &&
5552 (eicr & IXGBE_EICR_GPI_SDP1)) {
5553 device_printf(sc->dev,
5554 "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n");
5555 IXGBE_WRITE_REG(hw, IXGBE_EIMS,
5556 IXGBE_EICR_GPI_SDP1_BY_MAC(hw));
5557 }
5558
5559 /* Link status change */
5560 if (eicr & IXGBE_EICR_LSC) {
5561 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
5562 requests |= IXGBE_REQUEST_TASK_LSC;
5563 }
5564
5565 if (ixgbe_is_sfp(hw)) {
5566 /* Pluggable optics-related interrupt */
5567 if (hw->mac.type >= ixgbe_mac_X540)
5568 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
5569 else
5570 eicr_mask = IXGBE_EICR_GPI_SDP2_BY_MAC(hw);
5571
5572 if (eicr & eicr_mask) {
5573 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
5574 requests |= IXGBE_REQUEST_TASK_MOD;
5575 }
5576
5577 if ((hw->mac.type == ixgbe_mac_82599EB) &&
5578 (eicr & IXGBE_EICR_GPI_SDP1_BY_MAC(hw))) {
5579 IXGBE_WRITE_REG(hw, IXGBE_EICR,
5580 IXGBE_EICR_GPI_SDP1_BY_MAC(hw));
5581 requests |= IXGBE_REQUEST_TASK_MSF;
5582 }
5583 }
5584
5585 /* External PHY interrupt */
5586 if ((hw->phy.type == ixgbe_phy_x550em_ext_t) &&
5587 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
5588 requests |= IXGBE_REQUEST_TASK_PHY;
5589 }
5590 if (hw->mac.type != ixgbe_mac_82598EB &&
5591 ixgbe_handle_ecc(sc, eicr))
5592 requests |= IXGBE_REQUEST_TASK_RESET;
5593 if (requests != 0) {
5594 atomic_set_32(&sc->task_requests, requests);
5595 iflib_admin_intr_deferred(ctx);
5596 }
5597
5598 return (FILTER_SCHEDULE_THREAD);
5599 } /* ixgbe_intr */
5600
5601 /************************************************************************
5602 * ixgbe_free_pci_resources
5603 ************************************************************************/
5604 static void
ixgbe_free_pci_resources(if_ctx_t ctx)5605 ixgbe_free_pci_resources(if_ctx_t ctx)
5606 {
5607 struct ixgbe_softc *sc = iflib_get_softc(ctx);
5608 struct ix_rx_queue *que = sc->rx_queues;
5609 device_t dev = iflib_get_dev(ctx);
5610
5611 /* Release all MSI-X queue resources */
5612 if (sc->intr_type == IFLIB_INTR_MSIX)
5613 iflib_irq_free(ctx, &sc->irq);
5614
5615 if (que != NULL) {
5616 for (int i = 0; i < sc->num_rx_queues; i++, que++) {
5617 iflib_irq_free(ctx, &que->que_irq);
5618 }
5619 }
5620
5621 if (sc->pci_mem != NULL)
5622 bus_release_resource(dev, SYS_RES_MEMORY,
5623 rman_get_rid(sc->pci_mem), sc->pci_mem);
5624 } /* ixgbe_free_pci_resources */
5625
5626 /************************************************************************
5627 * ixgbe_sysctl_flowcntl
5628 *
5629 * SYSCTL wrapper around setting Flow Control
5630 ************************************************************************/
5631 static int
ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS)5632 ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS)
5633 {
5634 struct ixgbe_softc *sc;
5635 struct sx *ctx_lock;
5636 int error, fc;
5637
5638 sc = (struct ixgbe_softc *)arg1;
5639 fc = sc->hw.fc.requested_mode;
5640
5641 error = sysctl_handle_int(oidp, &fc, 0, req);
5642 if ((error) || (req->newptr == NULL))
5643 return (error);
5644
5645 /* Serialize the live register update with the administrative task. */
5646 ctx_lock = iflib_ctx_lock_get(sc->ctx);
5647 sx_xlock(ctx_lock);
5648 if (fc == sc->hw.fc.requested_mode)
5649 error = 0;
5650 else
5651 error = ixgbe_set_flowcntl(sc, fc);
5652 sx_xunlock(ctx_lock);
5653 return (error);
5654 } /* ixgbe_sysctl_flowcntl */
5655
5656 /************************************************************************
5657 * ixgbe_set_flowcntl - Set flow control
5658 *
5659 * Flow control values:
5660 * 0 - off
5661 * 1 - rx pause
5662 * 2 - tx pause
5663 * 3 - full
5664 ************************************************************************/
5665 static int
ixgbe_set_flowcntl(struct ixgbe_softc * sc,int fc)5666 ixgbe_set_flowcntl(struct ixgbe_softc *sc, int fc)
5667 {
5668 bool enable_drop, mdd_active;
5669
5670 switch (fc) {
5671 case ixgbe_fc_rx_pause:
5672 case ixgbe_fc_tx_pause:
5673 case ixgbe_fc_full:
5674 enable_drop = false;
5675 break;
5676 case ixgbe_fc_none:
5677 enable_drop = true;
5678 break;
5679 default:
5680 return (EINVAL);
5681 }
5682
5683 sc->hw.fc.requested_mode = fc;
5684 /* Don't autoneg if forcing a value. */
5685 sc->hw.fc.disable_fc_autoneg = true;
5686 /* Init replays the policy; closed admission does not prove DMA stopped. */
5687 if (!iflib_is_running(sc->ctx))
5688 return (0);
5689
5690 /* Updating SRRCTL on a live queue is itself an MDD violation. */
5691 mdd_active = sc->num_rx_queues > 1 &&
5692 (sc->feat_en & IXGBE_FEATURE_SRIOV) != 0;
5693 if (mdd_active)
5694 ixgbe_disable_mdd(&sc->hw);
5695 if (sc->num_rx_queues > 1) {
5696 if (enable_drop)
5697 ixgbe_enable_rx_drop(sc);
5698 else
5699 ixgbe_disable_rx_drop(sc);
5700 }
5701 if (mdd_active) {
5702 ixgbe_enable_mdd(&sc->hw);
5703 /* Service an event whose interrupt edge was lost while masked. */
5704 if (ixgbe_mbx_pending(sc)) {
5705 atomic_set_32(&sc->task_requests,
5706 IXGBE_REQUEST_TASK_MBX);
5707 iflib_admin_intr_deferred(sc->ctx);
5708 }
5709 }
5710
5711 ixgbe_fc_enable(&sc->hw);
5712
5713 return (0);
5714 } /* ixgbe_set_flowcntl */
5715
5716 /************************************************************************
5717 * ixgbe_enable_rx_drop
5718 *
5719 * Enable the hardware to drop packets when the buffer is
5720 * full. This is useful with multiqueue, so that no single
5721 * queue being full stalls the entire RX engine. We only
5722 * enable this when Multiqueue is enabled AND Flow Control
5723 * is disabled.
5724 ************************************************************************/
5725 static void
ixgbe_enable_rx_drop(struct ixgbe_softc * sc)5726 ixgbe_enable_rx_drop(struct ixgbe_softc *sc)
5727 {
5728 struct ixgbe_hw *hw = &sc->hw;
5729 struct rx_ring *rxr;
5730 u32 srrctl;
5731
5732 for (int i = 0; i < sc->num_rx_queues; i++) {
5733 rxr = &sc->rx_queues[i].rxr;
5734 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me));
5735 srrctl |= IXGBE_SRRCTL_DROP_EN;
5736 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl);
5737 }
5738
5739 } /* ixgbe_enable_rx_drop */
5740
5741 /************************************************************************
5742 * ixgbe_disable_rx_drop
5743 ************************************************************************/
5744 static void
ixgbe_disable_rx_drop(struct ixgbe_softc * sc)5745 ixgbe_disable_rx_drop(struct ixgbe_softc *sc)
5746 {
5747 struct ixgbe_hw *hw = &sc->hw;
5748 struct rx_ring *rxr;
5749 u32 srrctl;
5750
5751 for (int i = 0; i < sc->num_rx_queues; i++) {
5752 rxr = &sc->rx_queues[i].rxr;
5753 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxr->me));
5754 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
5755 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxr->me), srrctl);
5756 }
5757
5758 } /* ixgbe_disable_rx_drop */
5759
5760 /************************************************************************
5761 * ixgbe_sysctl_advertise
5762 *
5763 * SYSCTL wrapper around setting advertised speed
5764 ************************************************************************/
5765 static int
ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS)5766 ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS)
5767 {
5768 struct ixgbe_softc *sc;
5769 int error, advertise;
5770
5771 sc = (struct ixgbe_softc *)arg1;
5772 if (atomic_load_acq_int(&sc->recovery_mode))
5773 return (EPERM);
5774
5775 advertise = sc->advertise;
5776
5777 error = sysctl_handle_int(oidp, &advertise, 0, req);
5778 if ((error) || (req->newptr == NULL))
5779 return (error);
5780
5781 return ixgbe_set_advertise(sc, advertise);
5782 } /* ixgbe_sysctl_advertise */
5783
5784 /************************************************************************
5785 * ixgbe_set_advertise - Control advertised link speed
5786 *
5787 * Flags:
5788 * 0x1 - advertise 100 Mb
5789 * 0x2 - advertise 1G
5790 * 0x4 - advertise 10G
5791 * 0x8 - advertise 10 Mb (yes, Mb)
5792 * 0x10 - advertise 2.5G (disabled by default)
5793 * 0x20 - advertise 5G (disabled by default)
5794 *
5795 ************************************************************************/
5796 static int
ixgbe_set_advertise(struct ixgbe_softc * sc,int advertise)5797 ixgbe_set_advertise(struct ixgbe_softc *sc, int advertise)
5798 {
5799 device_t dev = iflib_get_dev(sc->ctx);
5800 struct ixgbe_hw *hw;
5801 ixgbe_link_speed speed = 0;
5802 ixgbe_link_speed link_caps = 0;
5803 s32 err = IXGBE_NOT_IMPLEMENTED;
5804 bool negotiate = false;
5805
5806 /* Checks to validate new value */
5807 if (sc->advertise == advertise) /* no change */
5808 return (0);
5809
5810 hw = &sc->hw;
5811
5812 /* No speed changes for backplane media */
5813 if (hw->phy.media_type == ixgbe_media_type_backplane)
5814 return (ENODEV);
5815
5816 if (!((hw->phy.media_type == ixgbe_media_type_copper) ||
5817 (hw->phy.multispeed_fiber))) {
5818 device_printf(dev,
5819 "Advertised speed can only be set on copper or multispeed"
5820 " fiber media types.\n");
5821 return (EINVAL);
5822 }
5823
5824 if (advertise < 0x1 || advertise > 0x3F) {
5825 device_printf(dev,
5826 "Invalid advertised speed; valid modes are 0x1 through"
5827 " 0x3F\n");
5828 return (EINVAL);
5829 }
5830
5831 if (hw->mac.ops.get_link_capabilities) {
5832 err = hw->mac.ops.get_link_capabilities(hw, &link_caps,
5833 &negotiate);
5834 if (err != IXGBE_SUCCESS) {
5835 device_printf(dev,
5836 "Unable to determine supported advertise speeds"
5837 "\n");
5838 return (ENODEV);
5839 }
5840 }
5841
5842 /* Set new value and report new advertised mode */
5843 if (advertise & 0x1) {
5844 if (!(link_caps & IXGBE_LINK_SPEED_100_FULL)) {
5845 device_printf(dev,
5846 "Interface does not support 100Mb advertised"
5847 " speed\n");
5848 return (EINVAL);
5849 }
5850 speed |= IXGBE_LINK_SPEED_100_FULL;
5851 }
5852 if (advertise & 0x2) {
5853 if (!(link_caps & IXGBE_LINK_SPEED_1GB_FULL)) {
5854 device_printf(dev,
5855 "Interface does not support 1Gb advertised speed"
5856 "\n");
5857 return (EINVAL);
5858 }
5859 speed |= IXGBE_LINK_SPEED_1GB_FULL;
5860 }
5861 if (advertise & 0x4) {
5862 if (!(link_caps & IXGBE_LINK_SPEED_10GB_FULL)) {
5863 device_printf(dev,
5864 "Interface does not support 10Gb advertised speed"
5865 "\n");
5866 return (EINVAL);
5867 }
5868 speed |= IXGBE_LINK_SPEED_10GB_FULL;
5869 }
5870 if (advertise & 0x8) {
5871 if (!(link_caps & IXGBE_LINK_SPEED_10_FULL)) {
5872 device_printf(dev,
5873 "Interface does not support 10Mb advertised speed"
5874 "\n");
5875 return (EINVAL);
5876 }
5877 speed |= IXGBE_LINK_SPEED_10_FULL;
5878 }
5879 if (advertise & 0x10) {
5880 if (!(link_caps & IXGBE_LINK_SPEED_2_5GB_FULL)) {
5881 device_printf(dev,
5882 "Interface does not support 2.5G advertised speed"
5883 "\n");
5884 return (EINVAL);
5885 }
5886 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
5887 }
5888 if (advertise & 0x20) {
5889 if (!(link_caps & IXGBE_LINK_SPEED_5GB_FULL)) {
5890 device_printf(dev,
5891 "Interface does not support 5G advertised speed"
5892 "\n");
5893 return (EINVAL);
5894 }
5895 speed |= IXGBE_LINK_SPEED_5GB_FULL;
5896 }
5897
5898 hw->mac.autotry_restart = true;
5899 hw->mac.ops.setup_link(hw, speed, true);
5900 sc->advertise = advertise;
5901
5902 return (0);
5903 } /* ixgbe_set_advertise */
5904
5905 /************************************************************************
5906 * ixgbe_get_default_advertise - Get default advertised speed settings
5907 *
5908 * Formatted for sysctl usage.
5909 * Flags:
5910 * 0x1 - advertise 100 Mb
5911 * 0x2 - advertise 1G
5912 * 0x4 - advertise 10G
5913 * 0x8 - advertise 10 Mb (yes, Mb)
5914 * 0x10 - advertise 2.5G (disabled by default)
5915 * 0x20 - advertise 5G (disabled by default)
5916 ************************************************************************/
5917 static int
ixgbe_get_default_advertise(struct ixgbe_softc * sc)5918 ixgbe_get_default_advertise(struct ixgbe_softc *sc)
5919 {
5920 struct ixgbe_hw *hw = &sc->hw;
5921 int speed;
5922 ixgbe_link_speed link_caps = 0;
5923 s32 err;
5924 bool negotiate = false;
5925
5926 /*
5927 * Advertised speed means nothing unless it's copper or
5928 * multi-speed fiber
5929 */
5930 if (!(hw->phy.media_type == ixgbe_media_type_copper) &&
5931 !(hw->phy.multispeed_fiber))
5932 return (0);
5933
5934 err = hw->mac.ops.get_link_capabilities(hw, &link_caps, &negotiate);
5935 if (err != IXGBE_SUCCESS)
5936 return (0);
5937
5938 if (hw->mac.type == ixgbe_mac_X550) {
5939 /*
5940 * 2.5G and 5G autonegotiation speeds on X550
5941 * are disabled by default due to reported
5942 * interoperability issues with some switches.
5943 */
5944 link_caps &= ~(IXGBE_LINK_SPEED_2_5GB_FULL |
5945 IXGBE_LINK_SPEED_5GB_FULL);
5946 }
5947
5948 speed =
5949 ((link_caps & IXGBE_LINK_SPEED_10GB_FULL) ? 0x4 : 0) |
5950 ((link_caps & IXGBE_LINK_SPEED_5GB_FULL) ? 0x20 : 0) |
5951 ((link_caps & IXGBE_LINK_SPEED_2_5GB_FULL) ? 0x10 : 0) |
5952 ((link_caps & IXGBE_LINK_SPEED_1GB_FULL) ? 0x2 : 0) |
5953 ((link_caps & IXGBE_LINK_SPEED_100_FULL) ? 0x1 : 0) |
5954 ((link_caps & IXGBE_LINK_SPEED_10_FULL) ? 0x8 : 0);
5955
5956 return speed;
5957 } /* ixgbe_get_default_advertise */
5958
5959 /************************************************************************
5960 * ixgbe_sysctl_dmac - Manage DMA Coalescing
5961 *
5962 * Control values:
5963 * 0/1 - off / on (use default value of 1000)
5964 *
5965 * Legal timer values are:
5966 * 50,100,250,500,1000,2000,5000,10000
5967 *
5968 * Turning off interrupt moderation will also turn this off.
5969 ************************************************************************/
5970 static int
ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS)5971 ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS)
5972 {
5973 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
5974 struct sx *ctx_lock = iflib_ctx_lock_get(sc->ctx);
5975 int error;
5976 u16 newval;
5977
5978 sx_xlock(ctx_lock);
5979 newval = sc->dmac;
5980 sx_xunlock(ctx_lock);
5981 error = sysctl_handle_16(oidp, &newval, 0, req);
5982 if ((error) || (req->newptr == NULL))
5983 return (error);
5984
5985 switch (newval) {
5986 case 0:
5987 /* Disabled */
5988 break;
5989 case 1:
5990 /* Enable and use default */
5991 newval = 1000;
5992 break;
5993 case 50:
5994 case 100:
5995 case 250:
5996 case 500:
5997 case 1000:
5998 case 2000:
5999 case 5000:
6000 case 10000:
6001 /* Legal values - allow */
6002 break;
6003 default:
6004 /* Do nothing, illegal value */
6005 return (EINVAL);
6006 }
6007
6008 sx_xlock(ctx_lock);
6009 if (iflib_in_detach(sc->ctx)) {
6010 error = ENXIO;
6011 } else if (sc->dmac != newval) {
6012 sc->dmac = newval;
6013 /* Apply through init only if still administratively up. */
6014 iflib_request_reset_if_up(sc->ctx);
6015 iflib_admin_intr_deferred(sc->ctx);
6016 }
6017 sx_xunlock(ctx_lock);
6018
6019 return (error);
6020 } /* ixgbe_sysctl_dmac */
6021
6022 #ifdef IXGBE_DEBUG
6023 /************************************************************************
6024 * ixgbe_sysctl_power_state
6025 *
6026 * Sysctl to test power states
6027 * Values:
6028 * 0 - set device to D0
6029 * 3 - set device to D3
6030 * (none) - get current device power state
6031 ************************************************************************/
6032 static int
ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS)6033 ixgbe_sysctl_power_state(SYSCTL_HANDLER_ARGS)
6034 {
6035 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6036 device_t dev = sc->dev;
6037 int curr_ps, new_ps, error = 0;
6038
6039 curr_ps = new_ps = pci_get_powerstate(dev);
6040
6041 error = sysctl_handle_int(oidp, &new_ps, 0, req);
6042 if ((error) || (req->newptr == NULL))
6043 return (error);
6044
6045 if (new_ps == curr_ps)
6046 return (0);
6047
6048 if (new_ps == 3 && curr_ps == 0)
6049 error = DEVICE_SUSPEND(dev);
6050 else if (new_ps == 0 && curr_ps == 3)
6051 error = DEVICE_RESUME(dev);
6052 else
6053 return (EINVAL);
6054
6055 device_printf(dev, "New state: %d\n", pci_get_powerstate(dev));
6056
6057 return (error);
6058 } /* ixgbe_sysctl_power_state */
6059 #endif
6060
6061 #ifdef IXGBE_DEBUG
6062 /************************************************************************
6063 * ixgbe_sysctl_print_rss_config
6064 ************************************************************************/
6065 static int
ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS)6066 ixgbe_sysctl_print_rss_config(SYSCTL_HANDLER_ARGS)
6067 {
6068 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6069 struct ixgbe_hw *hw = &sc->hw;
6070 device_t dev = sc->dev;
6071 struct sbuf *buf;
6072 int error = 0, reta_size;
6073 u32 reg;
6074
6075 if (atomic_load_acq_int(&sc->recovery_mode))
6076 return (EPERM);
6077
6078 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6079 if (!buf) {
6080 device_printf(dev, "Could not allocate sbuf for output.\n");
6081 return (ENOMEM);
6082 }
6083
6084 // TODO: use sbufs to make a string to print out
6085 /* Set multiplier for RETA setup and table size based on MAC */
6086 switch (sc->hw.mac.type) {
6087 case ixgbe_mac_X550:
6088 case ixgbe_mac_X550EM_x:
6089 case ixgbe_mac_X550EM_a:
6090 reta_size = 128;
6091 break;
6092 default:
6093 reta_size = 32;
6094 break;
6095 }
6096
6097 /* Print out the redirection table */
6098 sbuf_cat(buf, "\n");
6099 for (int i = 0; i < reta_size; i++) {
6100 if (i < 32) {
6101 reg = IXGBE_READ_REG(hw, IXGBE_RETA(i));
6102 sbuf_printf(buf, "RETA(%2d): 0x%08x\n", i, reg);
6103 } else {
6104 reg = IXGBE_READ_REG(hw, IXGBE_ERETA(i - 32));
6105 sbuf_printf(buf, "ERETA(%2d): 0x%08x\n", i - 32, reg);
6106 }
6107 }
6108
6109 // TODO: print more config
6110
6111 error = sbuf_finish(buf);
6112 if (error)
6113 device_printf(dev, "Error finishing sbuf: %d\n", error);
6114
6115 sbuf_delete(buf);
6116
6117 return (0);
6118 } /* ixgbe_sysctl_print_rss_config */
6119 #endif /* IXGBE_DEBUG */
6120
6121 /************************************************************************
6122 * ixgbe_sysctl_phy_temp - Retrieve temperature of PHY
6123 *
6124 * For X552/X557-AT devices using an external PHY
6125 ************************************************************************/
6126 static int
ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS)6127 ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS)
6128 {
6129 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6130 struct ixgbe_hw *hw = &sc->hw;
6131 u16 reg;
6132
6133 if (atomic_load_acq_int(&sc->recovery_mode))
6134 return (EPERM);
6135
6136 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) {
6137 device_printf(iflib_get_dev(sc->ctx),
6138 "Device has no supported external thermal sensor.\n");
6139 return (ENODEV);
6140 }
6141
6142 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_CURRENT_TEMP,
6143 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) {
6144 device_printf(iflib_get_dev(sc->ctx),
6145 "Error reading from PHY's current temperature register"
6146 "\n");
6147 return (EAGAIN);
6148 }
6149
6150 /* Shift temp for output */
6151 reg = reg >> 8;
6152
6153 return (sysctl_handle_16(oidp, NULL, reg, req));
6154 } /* ixgbe_sysctl_phy_temp */
6155
6156 /************************************************************************
6157 * ixgbe_sysctl_phy_overtemp_occurred
6158 *
6159 * Reports (directly from the PHY) whether the current PHY
6160 * temperature is over the overtemp threshold.
6161 ************************************************************************/
6162 static int
ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS)6163 ixgbe_sysctl_phy_overtemp_occurred(SYSCTL_HANDLER_ARGS)
6164 {
6165 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6166 struct ixgbe_hw *hw = &sc->hw;
6167 u16 reg;
6168
6169 if (atomic_load_acq_int(&sc->recovery_mode))
6170 return (EPERM);
6171
6172 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_10G_T) {
6173 device_printf(iflib_get_dev(sc->ctx),
6174 "Device has no supported external thermal sensor.\n");
6175 return (ENODEV);
6176 }
6177
6178 if (hw->phy.ops.read_reg(hw, IXGBE_PHY_OVERTEMP_STATUS,
6179 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, ®)) {
6180 device_printf(iflib_get_dev(sc->ctx),
6181 "Error reading from PHY's temperature status register\n");
6182 return (EAGAIN);
6183 }
6184
6185 /* Get occurrence bit */
6186 reg = !!(reg & 0x4000);
6187
6188 return (sysctl_handle_16(oidp, 0, reg, req));
6189 } /* ixgbe_sysctl_phy_overtemp_occurred */
6190
6191 /************************************************************************
6192 * ixgbe_sysctl_eee_state
6193 *
6194 * Sysctl to set EEE power saving feature
6195 * Values:
6196 * 0 - disable EEE
6197 * 1 - enable EEE
6198 * (none) - get current device EEE state
6199 ************************************************************************/
6200 static int
ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS)6201 ixgbe_sysctl_eee_state(SYSCTL_HANDLER_ARGS)
6202 {
6203 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6204 device_t dev = sc->dev;
6205 if_t ifp = iflib_get_ifp(sc->ctx);
6206 int curr_eee, new_eee, error = 0;
6207 s32 retval;
6208
6209 if (atomic_load_acq_int(&sc->recovery_mode))
6210 return (EPERM);
6211
6212 curr_eee = new_eee = !!(sc->feat_en & IXGBE_FEATURE_EEE);
6213
6214 error = sysctl_handle_int(oidp, &new_eee, 0, req);
6215 if ((error) || (req->newptr == NULL))
6216 return (error);
6217
6218 /* Nothing to do */
6219 if (new_eee == curr_eee)
6220 return (0);
6221
6222 /* Not supported */
6223 if (!(sc->feat_cap & IXGBE_FEATURE_EEE))
6224 return (EINVAL);
6225
6226 /* Bounds checking */
6227 if ((new_eee < 0) || (new_eee > 1))
6228 return (EINVAL);
6229
6230 /* If link speed is <= 1Gbps and EEE is being enabled, log info */
6231 if (sc->hw.mac.type == ixgbe_mac_E610 &&
6232 new_eee &&
6233 sc->link_speed <= IXGBE_LINK_SPEED_1GB_FULL) {
6234 device_printf(dev,
6235 "Energy Efficient Ethernet (EEE) feature is not "
6236 "supported on link speeds equal to or below 1Gbps. "
6237 "EEE is supported on speeds above 1Gbps.\n");
6238 return (EINVAL);
6239 }
6240
6241 retval = ixgbe_setup_eee(&sc->hw, new_eee);
6242 if (retval) {
6243 device_printf(dev, "Error in EEE setup: 0x%08X\n", retval);
6244 return (EINVAL);
6245 }
6246
6247 /* Restart auto-neg */
6248 if_init(ifp, ifp);
6249
6250 device_printf(dev, "New EEE state: %d\n", new_eee);
6251
6252 /* Cache new value */
6253 if (new_eee)
6254 sc->feat_en |= IXGBE_FEATURE_EEE;
6255 else
6256 sc->feat_en &= ~IXGBE_FEATURE_EEE;
6257
6258 return (error);
6259 } /* ixgbe_sysctl_eee_state */
6260
6261 static int
ixgbe_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)6262 ixgbe_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)
6263 {
6264 struct ixgbe_softc *sc;
6265 u32 reg, val, shift;
6266 int error, mask;
6267
6268 sc = oidp->oid_arg1;
6269 switch (oidp->oid_arg2) {
6270 case 0:
6271 reg = IXGBE_DTXTCPFLGL;
6272 shift = 0;
6273 break;
6274 case 1:
6275 reg = IXGBE_DTXTCPFLGL;
6276 shift = 16;
6277 break;
6278 case 2:
6279 reg = IXGBE_DTXTCPFLGH;
6280 shift = 0;
6281 break;
6282 default:
6283 return (EINVAL);
6284 break;
6285 }
6286 val = IXGBE_READ_REG(&sc->hw, reg);
6287 mask = (val >> shift) & 0xfff;
6288 error = sysctl_handle_int(oidp, &mask, 0, req);
6289 if (error != 0 || req->newptr == NULL)
6290 return (error);
6291 if (mask < 0 || mask > 0xfff)
6292 return (EINVAL);
6293 val = (val & ~(0xfff << shift)) | (mask << shift);
6294 IXGBE_WRITE_REG(&sc->hw, reg, val);
6295 return (0);
6296 }
6297
6298 /************************************************************************
6299 * ixgbe_init_device_features
6300 ************************************************************************/
6301 static void
ixgbe_init_device_features(struct ixgbe_softc * sc)6302 ixgbe_init_device_features(struct ixgbe_softc *sc)
6303 {
6304 s32 error;
6305
6306 sc->feat_cap = IXGBE_FEATURE_NETMAP |
6307 IXGBE_FEATURE_RSS |
6308 IXGBE_FEATURE_MSI |
6309 IXGBE_FEATURE_MSIX |
6310 IXGBE_FEATURE_LEGACY_IRQ;
6311
6312 /* Set capabilities first... */
6313 switch (sc->hw.mac.type) {
6314 case ixgbe_mac_82598EB:
6315 if (sc->hw.device_id == IXGBE_DEV_ID_82598AT)
6316 sc->feat_cap |= IXGBE_FEATURE_FAN_FAIL;
6317 break;
6318 case ixgbe_mac_X540:
6319 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6320 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6321 if ((sc->hw.device_id == IXGBE_DEV_ID_X540_BYPASS) &&
6322 (sc->hw.bus.func == 0))
6323 sc->feat_cap |= IXGBE_FEATURE_BYPASS;
6324 break;
6325 case ixgbe_mac_X550:
6326 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE;
6327 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR;
6328 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6329 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6330 break;
6331 case ixgbe_mac_X550EM_x:
6332 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE;
6333 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6334 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6335 if (sc->hw.device_id == IXGBE_DEV_ID_X550EM_X_KR)
6336 sc->feat_cap |= IXGBE_FEATURE_EEE;
6337 break;
6338 case ixgbe_mac_X550EM_a:
6339 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE;
6340 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6341 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6342 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ;
6343 if ((sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
6344 (sc->hw.device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
6345 sc->feat_cap |= IXGBE_FEATURE_TEMP_SENSOR;
6346 sc->feat_cap |= IXGBE_FEATURE_EEE;
6347 }
6348 break;
6349 case ixgbe_mac_82599EB:
6350 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6351 sc->feat_cap |= IXGBE_FEATURE_FDIR;
6352 if ((sc->hw.device_id == IXGBE_DEV_ID_82599_BYPASS) &&
6353 (sc->hw.bus.func == 0))
6354 sc->feat_cap |= IXGBE_FEATURE_BYPASS;
6355 if (sc->hw.device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP)
6356 sc->feat_cap &= ~IXGBE_FEATURE_LEGACY_IRQ;
6357 break;
6358 case ixgbe_mac_E610:
6359 sc->feat_cap |= IXGBE_FEATURE_RECOVERY_MODE;
6360 sc->feat_cap |= IXGBE_FEATURE_SRIOV;
6361 sc->feat_cap |= IXGBE_FEATURE_DBG_DUMP;
6362 sc->feat_cap |= IXGBE_FEATURE_FW_LOGGING;
6363 error = ixgbe_get_caps(&sc->hw);
6364 if (error == 0 && sc->hw.func_caps.common_cap.eee_support != 0)
6365 sc->feat_cap |= IXGBE_FEATURE_EEE;
6366 break;
6367 default:
6368 break;
6369 }
6370
6371 /* Enabled by default... */
6372 /* Fan failure detection */
6373 if (sc->feat_cap & IXGBE_FEATURE_FAN_FAIL)
6374 sc->feat_en |= IXGBE_FEATURE_FAN_FAIL;
6375 /* Netmap */
6376 if (sc->feat_cap & IXGBE_FEATURE_NETMAP)
6377 sc->feat_en |= IXGBE_FEATURE_NETMAP;
6378 /* EEE */
6379 if (sc->feat_cap & IXGBE_FEATURE_EEE)
6380 sc->feat_en |= IXGBE_FEATURE_EEE;
6381 /* Thermal Sensor */
6382 if (sc->feat_cap & IXGBE_FEATURE_TEMP_SENSOR)
6383 sc->feat_en |= IXGBE_FEATURE_TEMP_SENSOR;
6384 /* Recovery mode */
6385 if (sc->feat_cap & IXGBE_FEATURE_RECOVERY_MODE)
6386 sc->feat_en |= IXGBE_FEATURE_RECOVERY_MODE;
6387 /* FW Debug Dump */
6388 if (sc->feat_cap & IXGBE_FEATURE_DBG_DUMP)
6389 sc->feat_en |= IXGBE_FEATURE_DBG_DUMP;
6390 /* FW Logging */
6391 if (sc->feat_cap & IXGBE_FEATURE_FW_LOGGING)
6392 sc->feat_en |= IXGBE_FEATURE_FW_LOGGING;
6393
6394 /* Enabled via global sysctl... */
6395 /* Flow Director */
6396 if (ixgbe_enable_fdir) {
6397 if (sc->feat_cap & IXGBE_FEATURE_FDIR)
6398 sc->feat_en |= IXGBE_FEATURE_FDIR;
6399 else
6400 device_printf(sc->dev,
6401 "Device does not support Flow Director."
6402 " Leaving disabled.");
6403 }
6404 /*
6405 * Message Signal Interrupts - Extended (MSI-X)
6406 * Normal MSI is only enabled if MSI-X calls fail.
6407 */
6408 if (!ixgbe_enable_msix)
6409 sc->feat_cap &= ~IXGBE_FEATURE_MSIX;
6410 /* Receive-Side Scaling (RSS) */
6411 if ((sc->feat_cap & IXGBE_FEATURE_RSS) && ixgbe_enable_rss)
6412 sc->feat_en |= IXGBE_FEATURE_RSS;
6413
6414 /* Disable features with unmet dependencies... */
6415 /* No MSI-X */
6416 if (!(sc->feat_cap & IXGBE_FEATURE_MSIX)) {
6417 sc->feat_cap &= ~IXGBE_FEATURE_RSS;
6418 sc->feat_cap &= ~IXGBE_FEATURE_SRIOV;
6419 sc->feat_en &= ~IXGBE_FEATURE_RSS;
6420 sc->feat_en &= ~IXGBE_FEATURE_SRIOV;
6421 }
6422 } /* ixgbe_init_device_features */
6423
6424 /************************************************************************
6425 * ixgbe_check_fan_failure
6426 ************************************************************************/
6427 static void
ixgbe_check_fan_failure(struct ixgbe_softc * sc,u32 reg,bool in_interrupt)6428 ixgbe_check_fan_failure(struct ixgbe_softc *sc, u32 reg, bool in_interrupt)
6429 {
6430 u32 mask;
6431
6432 mask = (in_interrupt) ? IXGBE_EICR_GPI_SDP1_BY_MAC(&sc->hw) :
6433 IXGBE_ESDP_SDP1;
6434
6435 if (reg & mask)
6436 device_printf(sc->dev,
6437 "\nCRITICAL: FAN FAILURE!! REPLACE IMMEDIATELY!!\n");
6438 } /* ixgbe_check_fan_failure */
6439
6440 /************************************************************************
6441 * ixgbe_sbuf_fw_version
6442 ************************************************************************/
6443 static void
ixgbe_sbuf_fw_version(struct ixgbe_hw * hw,struct sbuf * buf)6444 ixgbe_sbuf_fw_version(struct ixgbe_hw *hw, struct sbuf *buf)
6445 {
6446 struct ixgbe_nvm_version nvm_ver = {0};
6447 const char *space = "";
6448
6449 ixgbe_get_nvm_version(hw, &nvm_ver); /* NVM version */
6450 ixgbe_get_oem_prod_version(hw, &nvm_ver); /* OEM's NVM version */
6451 ixgbe_get_etk_id(hw, &nvm_ver); /* eTrack a build ID in Intel's SCM */
6452 ixgbe_get_orom_version(hw, &nvm_ver); /* Option ROM */
6453
6454 /* FW version */
6455 if ((nvm_ver.phy_fw_maj == 0x0 &&
6456 nvm_ver.phy_fw_min == 0x0 &&
6457 nvm_ver.phy_fw_id == 0x0) ||
6458 (nvm_ver.phy_fw_maj == 0xF &&
6459 nvm_ver.phy_fw_min == 0xFF &&
6460 nvm_ver.phy_fw_id == 0xF)) {
6461 /* If major, minor and id numbers are set to 0,
6462 * reading FW version is unsupported. If major number
6463 * is set to 0xF, minor is set to 0xFF and id is set
6464 * to 0xF, this means that number read is invalid. */
6465 } else
6466 sbuf_printf(buf, "fw %d.%d.%d ",
6467 nvm_ver.phy_fw_maj, nvm_ver.phy_fw_min,
6468 nvm_ver.phy_fw_id);
6469
6470 /* NVM version */
6471 if ((nvm_ver.nvm_major == 0x0 &&
6472 nvm_ver.nvm_minor == 0x0 &&
6473 nvm_ver.nvm_id == 0x0) ||
6474 (nvm_ver.nvm_major == 0xF &&
6475 nvm_ver.nvm_minor == 0xFF &&
6476 nvm_ver.nvm_id == 0xF)) {
6477 /* If major, minor and id numbers are set to 0,
6478 * reading NVM version is unsupported. If major number
6479 * is set to 0xF, minor is set to 0xFF and id is set
6480 * to 0xF, this means that number read is invalid. */
6481 } else
6482 sbuf_printf(buf, "nvm %x.%02x.%x ",
6483 nvm_ver.nvm_major, nvm_ver.nvm_minor, nvm_ver.nvm_id);
6484
6485 if (nvm_ver.oem_valid) {
6486 sbuf_printf(buf, "NVM OEM V%d.%d R%d", nvm_ver.oem_major,
6487 nvm_ver.oem_minor, nvm_ver.oem_release);
6488 space = " ";
6489 }
6490
6491 if (nvm_ver.or_valid) {
6492 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d",
6493 space, nvm_ver.or_major, nvm_ver.or_build,
6494 nvm_ver.or_patch);
6495 space = " ";
6496 }
6497
6498 if (nvm_ver.etk_id != ((NVM_VER_INVALID << NVM_ETK_SHIFT) |
6499 NVM_VER_INVALID | 0xFFFFFFFF)) {
6500 sbuf_printf(buf, "%seTrack 0x%08x", space, nvm_ver.etk_id);
6501 }
6502 } /* ixgbe_sbuf_fw_version */
6503
6504 /************************************************************************
6505 * ixgbe_print_fw_version
6506 ************************************************************************/
6507 static void
ixgbe_print_fw_version(if_ctx_t ctx)6508 ixgbe_print_fw_version(if_ctx_t ctx)
6509 {
6510 struct ixgbe_softc *sc = iflib_get_softc(ctx);
6511 struct ixgbe_hw *hw = &sc->hw;
6512 device_t dev = sc->dev;
6513 struct sbuf *buf;
6514 int error = 0;
6515
6516 buf = sbuf_new_auto();
6517 if (!buf) {
6518 device_printf(dev, "Could not allocate sbuf for output.\n");
6519 return;
6520 }
6521
6522 ixgbe_sbuf_fw_version(hw, buf);
6523
6524 error = sbuf_finish(buf);
6525 if (error)
6526 device_printf(dev, "Error finishing sbuf: %d\n", error);
6527 else if (sbuf_len(buf))
6528 device_printf(dev, "%s\n", sbuf_data(buf));
6529
6530 sbuf_delete(buf);
6531 } /* ixgbe_print_fw_version */
6532
6533 /************************************************************************
6534 * ixgbe_sysctl_print_fw_version
6535 ************************************************************************/
6536 static int
ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)6537 ixgbe_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)
6538 {
6539 struct ixgbe_softc *sc = (struct ixgbe_softc *)arg1;
6540 struct ixgbe_hw *hw = &sc->hw;
6541 device_t dev = sc->dev;
6542 struct sbuf *buf;
6543 int error = 0;
6544
6545 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
6546 if (!buf) {
6547 device_printf(dev, "Could not allocate sbuf for output.\n");
6548 return (ENOMEM);
6549 }
6550
6551 ixgbe_sbuf_fw_version(hw, buf);
6552
6553 error = sbuf_finish(buf);
6554 if (error)
6555 device_printf(dev, "Error finishing sbuf: %d\n", error);
6556
6557 sbuf_delete(buf);
6558
6559 return (0);
6560 } /* ixgbe_sysctl_print_fw_version */
6561