1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2017, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
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10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
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17 3. Neither the name of the Intel Corporation nor the names of its
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19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34 /*$FreeBSD$*/
35
36
37 #include "ixgbe_type.h"
38 #include "ixgbe_dcb.h"
39 #include "ixgbe_dcb_82598.h"
40
41 /**
42 * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
43 * @hw: pointer to hardware structure
44 * @stats: pointer to statistics structure
45 * @tc_count: Number of elements in bwg_array.
46 *
47 * This function returns the status data for each of the Traffic Classes in use.
48 */
ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw * hw,struct ixgbe_hw_stats * stats,u8 tc_count)49 s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
50 struct ixgbe_hw_stats *stats,
51 u8 tc_count)
52 {
53 int tc;
54
55 DEBUGFUNC("dcb_get_tc_stats");
56
57 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
58 return IXGBE_ERR_PARAM;
59
60 /* Statistics pertaining to each traffic class */
61 for (tc = 0; tc < tc_count; tc++) {
62 /* Transmitted Packets */
63 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
64 /* Transmitted Bytes */
65 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
66 /* Received Packets */
67 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
68 /* Received Bytes */
69 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
70
71 #if 0
72 /* Can we get rid of these?? Consequently, getting rid
73 * of the tc_stats structure.
74 */
75 tc_stats_array[up]->in_overflow_discards = 0;
76 tc_stats_array[up]->out_overflow_discards = 0;
77 #endif
78 }
79
80 return IXGBE_SUCCESS;
81 }
82
83 /**
84 * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
85 * @hw: pointer to hardware structure
86 * @stats: pointer to statistics structure
87 * @tc_count: Number of elements in bwg_array.
88 *
89 * This function returns the CBFC status data for each of the Traffic Classes.
90 */
ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw * hw,struct ixgbe_hw_stats * stats,u8 tc_count)91 s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
92 struct ixgbe_hw_stats *stats,
93 u8 tc_count)
94 {
95 int tc;
96
97 DEBUGFUNC("dcb_get_pfc_stats");
98
99 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
100 return IXGBE_ERR_PARAM;
101
102 for (tc = 0; tc < tc_count; tc++) {
103 /* Priority XOFF Transmitted */
104 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
105 /* Priority XOFF Received */
106 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
107 }
108
109 return IXGBE_SUCCESS;
110 }
111
112 /**
113 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
114 * @hw: pointer to hardware structure
115 * @refill: refill credits index by traffic class
116 * @max: max credits index by traffic class
117 * @tsa: transmission selection algorithm indexed by traffic class
118 *
119 * Configure Rx Data Arbiter and credits for each traffic class.
120 */
ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * tsa)121 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
122 u16 *max, u8 *tsa)
123 {
124 u32 reg = 0;
125 u32 credit_refill = 0;
126 u32 credit_max = 0;
127 u8 i = 0;
128
129 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
130 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
131
132 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
133 /* Enable Arbiter */
134 reg &= ~IXGBE_RMCS_ARBDIS;
135 /* Enable Receive Recycle within the BWG */
136 reg |= IXGBE_RMCS_RRM;
137 /* Enable Deficit Fixed Priority arbitration*/
138 reg |= IXGBE_RMCS_DFP;
139
140 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
141
142 /* Configure traffic class credits and priority */
143 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
144 credit_refill = refill[i];
145 credit_max = max[i];
146
147 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
148
149 if (tsa[i] == ixgbe_dcb_tsa_strict)
150 reg |= IXGBE_RT2CR_LSP;
151
152 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
153 }
154
155 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
156 reg |= IXGBE_RDRXCTL_RDMTS_1_2;
157 reg |= IXGBE_RDRXCTL_MPBEN;
158 reg |= IXGBE_RDRXCTL_MCEN;
159 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
160
161 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
162 /* Make sure there is enough descriptors before arbitration */
163 reg &= ~IXGBE_RXCTRL_DMBYPS;
164 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
165
166 return IXGBE_SUCCESS;
167 }
168
169 /**
170 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
171 * @hw: pointer to hardware structure
172 * @refill: refill credits index by traffic class
173 * @max: max credits index by traffic class
174 * @bwg_id: bandwidth grouping indexed by traffic class
175 * @tsa: transmission selection algorithm indexed by traffic class
176 *
177 * Configure Tx Descriptor Arbiter and credits for each traffic class.
178 */
ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa)179 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
180 u16 *refill, u16 *max, u8 *bwg_id,
181 u8 *tsa)
182 {
183 u32 reg, max_credits;
184 u8 i;
185
186 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
187
188 /* Enable arbiter */
189 reg &= ~IXGBE_DPMCS_ARBDIS;
190 reg |= IXGBE_DPMCS_TSOEF;
191
192 /* Configure Max TSO packet size 34KB including payload and headers */
193 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
194
195 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
196
197 /* Configure traffic class credits and priority */
198 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
199 max_credits = max[i];
200 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
201 reg |= refill[i];
202 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
203
204 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
205 reg |= IXGBE_TDTQ2TCCR_GSP;
206
207 if (tsa[i] == ixgbe_dcb_tsa_strict)
208 reg |= IXGBE_TDTQ2TCCR_LSP;
209
210 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
211 }
212
213 return IXGBE_SUCCESS;
214 }
215
216 /**
217 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
218 * @hw: pointer to hardware structure
219 * @refill: refill credits index by traffic class
220 * @max: max credits index by traffic class
221 * @bwg_id: bandwidth grouping indexed by traffic class
222 * @tsa: transmission selection algorithm indexed by traffic class
223 *
224 * Configure Tx Data Arbiter and credits for each traffic class.
225 */
ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa)226 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
227 u16 *refill, u16 *max, u8 *bwg_id,
228 u8 *tsa)
229 {
230 u32 reg;
231 u8 i;
232
233 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
234 /* Enable Data Plane Arbiter */
235 reg &= ~IXGBE_PDPMCS_ARBDIS;
236 /* Enable DFP and Transmit Recycle Mode */
237 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
238
239 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
240
241 /* Configure traffic class credits and priority */
242 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
243 reg = refill[i];
244 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
245 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
246
247 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
248 reg |= IXGBE_TDPT2TCCR_GSP;
249
250 if (tsa[i] == ixgbe_dcb_tsa_strict)
251 reg |= IXGBE_TDPT2TCCR_LSP;
252
253 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
254 }
255
256 /* Enable Tx packet buffer division */
257 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
258 reg |= IXGBE_DTXCTL_ENDBUBD;
259 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
260
261 return IXGBE_SUCCESS;
262 }
263
264 /**
265 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
266 * @hw: pointer to hardware structure
267 * @pfc_en: enabled pfc bitmask
268 *
269 * Configure Priority Flow Control for each traffic class.
270 */
ixgbe_dcb_config_pfc_82598(struct ixgbe_hw * hw,u8 pfc_en)271 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
272 {
273 u32 fcrtl, reg;
274 u8 i;
275
276 /* Enable Transmit Priority Flow Control */
277 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
278 reg &= ~IXGBE_RMCS_TFCE_802_3X;
279 reg |= IXGBE_RMCS_TFCE_PRIORITY;
280 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
281
282 /* Enable Receive Priority Flow Control */
283 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
284 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
285
286 if (pfc_en)
287 reg |= IXGBE_FCTRL_RPFCE;
288
289 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
290
291 /* Configure PFC Tx thresholds per TC */
292 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
293 if (!(pfc_en & (1 << i))) {
294 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
295 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
296 continue;
297 }
298
299 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
300 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
301 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
302 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
303 }
304
305 /* Configure pause time */
306 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
307 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
308 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
309
310 /* Configure flow control refresh threshold value */
311 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
312
313 return IXGBE_SUCCESS;
314 }
315
316 /**
317 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
318 * @hw: pointer to hardware structure
319 *
320 * Configure queue statistics registers, all queues belonging to same traffic
321 * class uses a single set of queue statistics counters.
322 */
ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw * hw)323 s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
324 {
325 u32 reg = 0;
326 u8 i = 0;
327 u8 j = 0;
328
329 /* Receive Queues stats setting - 8 queues per statistics reg */
330 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
331 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
332 reg |= ((0x1010101) * j);
333 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
334 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
335 reg |= ((0x1010101) * j);
336 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
337 }
338 /* Transmit Queues stats setting - 4 queues per statistics reg*/
339 for (i = 0; i < 8; i++) {
340 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
341 reg |= ((0x1010101) * i);
342 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
343 }
344
345 return IXGBE_SUCCESS;
346 }
347
348 /**
349 * ixgbe_dcb_hw_config_82598 - Config and enable DCB
350 * @hw: pointer to hardware structure
351 * @link_speed: unused
352 * @refill: refill credits index by traffic class
353 * @max: max credits index by traffic class
354 * @bwg_id: bandwidth grouping indexed by traffic class
355 * @tsa: transmission selection algorithm indexed by traffic class
356 *
357 * Configure dcb settings and enable dcb mode.
358 */
ixgbe_dcb_hw_config_82598(struct ixgbe_hw * hw,int link_speed,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa)359 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed,
360 u16 *refill, u16 *max, u8 *bwg_id,
361 u8 *tsa)
362 {
363 UNREFERENCED_1PARAMETER(link_speed);
364
365 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
366 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
367 tsa);
368 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
369 tsa);
370 ixgbe_dcb_config_tc_stats_82598(hw);
371
372
373 return IXGBE_SUCCESS;
374 }
375