1 /* $OpenBSD: if_iwm.c,v 1.167 2017/04/04 00:40:52 claudio Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90 /*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105 #include <sys/cdefs.h> 106 #include "opt_wlan.h" 107 #include "opt_iwm.h" 108 109 #include <sys/param.h> 110 #include <sys/bus.h> 111 #include <sys/conf.h> 112 #include <sys/endian.h> 113 #include <sys/firmware.h> 114 #include <sys/kernel.h> 115 #include <sys/malloc.h> 116 #include <sys/mbuf.h> 117 #include <sys/mutex.h> 118 #include <sys/module.h> 119 #include <sys/proc.h> 120 #include <sys/rman.h> 121 #include <sys/socket.h> 122 #include <sys/sockio.h> 123 #include <sys/sysctl.h> 124 #include <sys/linker.h> 125 126 #include <machine/bus.h> 127 #include <machine/endian.h> 128 #include <machine/resource.h> 129 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/pcireg.h> 132 133 #include <net/bpf.h> 134 135 #include <net/if.h> 136 #include <net/if_var.h> 137 #include <net/if_arp.h> 138 #include <net/if_dl.h> 139 #include <net/if_media.h> 140 #include <net/if_types.h> 141 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/if_ether.h> 145 #include <netinet/ip.h> 146 147 #include <net80211/ieee80211_var.h> 148 #include <net80211/ieee80211_regdomain.h> 149 #include <net80211/ieee80211_ratectl.h> 150 #include <net80211/ieee80211_radiotap.h> 151 152 #include <dev/iwm/if_iwmreg.h> 153 #include <dev/iwm/if_iwmvar.h> 154 #include <dev/iwm/if_iwm_config.h> 155 #include <dev/iwm/if_iwm_debug.h> 156 #include <dev/iwm/if_iwm_notif_wait.h> 157 #include <dev/iwm/if_iwm_util.h> 158 #include <dev/iwm/if_iwm_binding.h> 159 #include <dev/iwm/if_iwm_phy_db.h> 160 #include <dev/iwm/if_iwm_mac_ctxt.h> 161 #include <dev/iwm/if_iwm_phy_ctxt.h> 162 #include <dev/iwm/if_iwm_time_event.h> 163 #include <dev/iwm/if_iwm_power.h> 164 #include <dev/iwm/if_iwm_scan.h> 165 #include <dev/iwm/if_iwm_sf.h> 166 #include <dev/iwm/if_iwm_sta.h> 167 168 #include <dev/iwm/if_iwm_pcie_trans.h> 169 #include <dev/iwm/if_iwm_led.h> 170 #include <dev/iwm/if_iwm_fw.h> 171 172 /* From DragonflyBSD */ 173 #define mtodoff(m, t, off) ((t)((m)->m_data + (off))) 174 175 const uint8_t iwm_nvm_channels[] = { 176 /* 2.4 GHz */ 177 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 178 /* 5 GHz */ 179 36, 40, 44, 48, 52, 56, 60, 64, 180 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 181 149, 153, 157, 161, 165 182 }; 183 _Static_assert(nitems(iwm_nvm_channels) <= IWM_NUM_CHANNELS, 184 "IWM_NUM_CHANNELS is too small"); 185 186 const uint8_t iwm_nvm_channels_8000[] = { 187 /* 2.4 GHz */ 188 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 189 /* 5 GHz */ 190 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 191 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 192 149, 153, 157, 161, 165, 169, 173, 177, 181 193 }; 194 _Static_assert(nitems(iwm_nvm_channels_8000) <= IWM_NUM_CHANNELS_8000, 195 "IWM_NUM_CHANNELS_8000 is too small"); 196 197 #define IWM_NUM_2GHZ_CHANNELS 14 198 #define IWM_N_HW_ADDR_MASK 0xF 199 200 const struct iwm_rate { 201 uint16_t rate; 202 uint8_t plcp; 203 uint8_t ht_plcp; 204 } iwm_rates[] = { 205 /* Legacy */ /* HT */ 206 { 2, IWM_RATE_1M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 207 { 4, IWM_RATE_2M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 208 { 11, IWM_RATE_5M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 209 { 22, IWM_RATE_11M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 210 { 12, IWM_RATE_6M_PLCP, IWM_RATE_HT_SISO_MCS_0_PLCP }, 211 { 18, IWM_RATE_9M_PLCP, IWM_RATE_HT_SISO_MCS_INV_PLCP }, 212 { 24, IWM_RATE_12M_PLCP, IWM_RATE_HT_SISO_MCS_1_PLCP }, 213 { 26, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_8_PLCP }, 214 { 36, IWM_RATE_18M_PLCP, IWM_RATE_HT_SISO_MCS_2_PLCP }, 215 { 48, IWM_RATE_24M_PLCP, IWM_RATE_HT_SISO_MCS_3_PLCP }, 216 { 52, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_9_PLCP }, 217 { 72, IWM_RATE_36M_PLCP, IWM_RATE_HT_SISO_MCS_4_PLCP }, 218 { 78, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_10_PLCP }, 219 { 96, IWM_RATE_48M_PLCP, IWM_RATE_HT_SISO_MCS_5_PLCP }, 220 { 104, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_11_PLCP }, 221 { 108, IWM_RATE_54M_PLCP, IWM_RATE_HT_SISO_MCS_6_PLCP }, 222 { 128, IWM_RATE_INVM_PLCP, IWM_RATE_HT_SISO_MCS_7_PLCP }, 223 { 156, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_12_PLCP }, 224 { 208, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_13_PLCP }, 225 { 234, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_14_PLCP }, 226 { 260, IWM_RATE_INVM_PLCP, IWM_RATE_HT_MIMO2_MCS_15_PLCP }, 227 }; 228 #define IWM_RIDX_CCK 0 229 #define IWM_RIDX_OFDM 4 230 #define IWM_RIDX_MAX (nitems(iwm_rates)-1) 231 #define IWM_RIDX_IS_CCK(_i_) ((_i_) < IWM_RIDX_OFDM) 232 #define IWM_RIDX_IS_OFDM(_i_) ((_i_) >= IWM_RIDX_OFDM) 233 #define IWM_RVAL_IS_OFDM(_i_) ((_i_) >= 12 && (_i_) != 22) 234 235 /* Convert an MCS index into an iwm_rates[] index. */ 236 const int iwm_mcs2ridx[] = { 237 IWM_RATE_MCS_0_INDEX, 238 IWM_RATE_MCS_1_INDEX, 239 IWM_RATE_MCS_2_INDEX, 240 IWM_RATE_MCS_3_INDEX, 241 IWM_RATE_MCS_4_INDEX, 242 IWM_RATE_MCS_5_INDEX, 243 IWM_RATE_MCS_6_INDEX, 244 IWM_RATE_MCS_7_INDEX, 245 IWM_RATE_MCS_8_INDEX, 246 IWM_RATE_MCS_9_INDEX, 247 IWM_RATE_MCS_10_INDEX, 248 IWM_RATE_MCS_11_INDEX, 249 IWM_RATE_MCS_12_INDEX, 250 IWM_RATE_MCS_13_INDEX, 251 IWM_RATE_MCS_14_INDEX, 252 IWM_RATE_MCS_15_INDEX, 253 }; 254 255 struct iwm_nvm_section { 256 uint16_t length; 257 uint8_t *data; 258 }; 259 260 #define IWM_UCODE_ALIVE_TIMEOUT hz 261 #define IWM_UCODE_CALIB_TIMEOUT (2*hz) 262 263 struct iwm_alive_data { 264 int valid; 265 uint32_t scd_base_addr; 266 }; 267 268 static int iwm_store_cscheme(struct iwm_softc *, const uint8_t *, size_t); 269 static int iwm_firmware_store_section(struct iwm_softc *, 270 enum iwm_ucode_type, 271 const uint8_t *, size_t); 272 static int iwm_set_default_calib(struct iwm_softc *, const void *); 273 static void iwm_fw_info_free(struct iwm_fw_info *); 274 static int iwm_read_firmware(struct iwm_softc *); 275 static int iwm_alloc_fwmem(struct iwm_softc *); 276 static int iwm_alloc_sched(struct iwm_softc *); 277 static int iwm_alloc_kw(struct iwm_softc *); 278 static int iwm_alloc_ict(struct iwm_softc *); 279 static int iwm_alloc_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 280 static void iwm_reset_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 281 static void iwm_free_rx_ring(struct iwm_softc *, struct iwm_rx_ring *); 282 static int iwm_alloc_tx_ring(struct iwm_softc *, struct iwm_tx_ring *, 283 int); 284 static void iwm_reset_tx_ring(struct iwm_softc *, struct iwm_tx_ring *); 285 static void iwm_free_tx_ring(struct iwm_softc *, struct iwm_tx_ring *); 286 static void iwm_enable_interrupts(struct iwm_softc *); 287 static void iwm_restore_interrupts(struct iwm_softc *); 288 static void iwm_disable_interrupts(struct iwm_softc *); 289 static void iwm_ict_reset(struct iwm_softc *); 290 static int iwm_allow_mcast(struct ieee80211vap *, struct iwm_softc *); 291 static void iwm_stop_device(struct iwm_softc *); 292 static void iwm_nic_config(struct iwm_softc *); 293 static int iwm_nic_rx_init(struct iwm_softc *); 294 static int iwm_nic_tx_init(struct iwm_softc *); 295 static int iwm_nic_init(struct iwm_softc *); 296 static int iwm_trans_pcie_fw_alive(struct iwm_softc *, uint32_t); 297 static int iwm_nvm_read_chunk(struct iwm_softc *, uint16_t, uint16_t, 298 uint16_t, uint8_t *, uint16_t *); 299 static int iwm_nvm_read_section(struct iwm_softc *, uint16_t, uint8_t *, 300 uint16_t *, uint32_t); 301 static uint32_t iwm_eeprom_channel_flags(uint16_t); 302 static void iwm_add_channel_band(struct iwm_softc *, 303 struct ieee80211_channel[], int, int *, int, size_t, 304 const uint8_t[]); 305 static void iwm_init_channel_map(struct ieee80211com *, int, int *, 306 struct ieee80211_channel[]); 307 static struct iwm_nvm_data * 308 iwm_parse_nvm_data(struct iwm_softc *, const uint16_t *, 309 const uint16_t *, const uint16_t *, 310 const uint16_t *, const uint16_t *, 311 const uint16_t *); 312 static void iwm_free_nvm_data(struct iwm_nvm_data *); 313 static void iwm_set_hw_address_family_8000(struct iwm_softc *, 314 struct iwm_nvm_data *, 315 const uint16_t *, 316 const uint16_t *); 317 static int iwm_get_sku(const struct iwm_softc *, const uint16_t *, 318 const uint16_t *); 319 static int iwm_get_nvm_version(const struct iwm_softc *, const uint16_t *); 320 static int iwm_get_radio_cfg(const struct iwm_softc *, const uint16_t *, 321 const uint16_t *); 322 static int iwm_get_n_hw_addrs(const struct iwm_softc *, 323 const uint16_t *); 324 static void iwm_set_radio_cfg(const struct iwm_softc *, 325 struct iwm_nvm_data *, uint32_t); 326 static struct iwm_nvm_data * 327 iwm_parse_nvm_sections(struct iwm_softc *, struct iwm_nvm_section *); 328 static int iwm_nvm_init(struct iwm_softc *); 329 static int iwm_pcie_load_section(struct iwm_softc *, uint8_t, 330 const struct iwm_fw_desc *); 331 static int iwm_pcie_load_firmware_chunk(struct iwm_softc *, uint32_t, 332 bus_addr_t, uint32_t); 333 static int iwm_pcie_load_cpu_sections_8000(struct iwm_softc *sc, 334 const struct iwm_fw_img *, 335 int, int *); 336 static int iwm_pcie_load_cpu_sections(struct iwm_softc *, 337 const struct iwm_fw_img *, 338 int, int *); 339 static int iwm_pcie_load_given_ucode_8000(struct iwm_softc *, 340 const struct iwm_fw_img *); 341 static int iwm_pcie_load_given_ucode(struct iwm_softc *, 342 const struct iwm_fw_img *); 343 static int iwm_start_fw(struct iwm_softc *, const struct iwm_fw_img *); 344 static int iwm_send_tx_ant_cfg(struct iwm_softc *, uint8_t); 345 static int iwm_send_phy_cfg_cmd(struct iwm_softc *); 346 static int iwm_load_ucode_wait_alive(struct iwm_softc *, 347 enum iwm_ucode_type); 348 static int iwm_run_init_ucode(struct iwm_softc *, int); 349 static int iwm_config_ltr(struct iwm_softc *sc); 350 static int iwm_rx_addbuf(struct iwm_softc *, int, int); 351 static void iwm_rx_rx_phy_cmd(struct iwm_softc *, 352 struct iwm_rx_packet *); 353 static int iwm_get_noise(struct iwm_softc *, 354 const struct iwm_statistics_rx_non_phy *); 355 static void iwm_handle_rx_statistics(struct iwm_softc *, 356 struct iwm_rx_packet *); 357 static bool iwm_rx_mpdu(struct iwm_softc *, struct mbuf *, 358 uint32_t, bool); 359 static int iwm_rx_tx_cmd_single(struct iwm_softc *, 360 struct iwm_rx_packet *, 361 struct iwm_node *); 362 static void iwm_rx_tx_cmd(struct iwm_softc *, struct iwm_rx_packet *); 363 static void iwm_cmd_done(struct iwm_softc *, struct iwm_rx_packet *); 364 #if 0 365 static void iwm_update_sched(struct iwm_softc *, int, int, uint8_t, 366 uint16_t); 367 #endif 368 static const struct iwm_rate * 369 iwm_tx_fill_cmd(struct iwm_softc *, struct iwm_node *, 370 struct mbuf *, struct iwm_tx_cmd *); 371 static int iwm_tx(struct iwm_softc *, struct mbuf *, 372 struct ieee80211_node *, int); 373 static int iwm_raw_xmit(struct ieee80211_node *, struct mbuf *, 374 const struct ieee80211_bpf_params *); 375 static int iwm_update_quotas(struct iwm_softc *, struct iwm_vap *); 376 static int iwm_auth(struct ieee80211vap *, struct iwm_softc *); 377 static struct ieee80211_node * 378 iwm_node_alloc(struct ieee80211vap *, 379 const uint8_t[IEEE80211_ADDR_LEN]); 380 static uint8_t iwm_rate_from_ucode_rate(uint32_t); 381 static int iwm_rate2ridx(struct iwm_softc *, uint8_t); 382 static void iwm_setrates(struct iwm_softc *, struct iwm_node *, int); 383 static int iwm_newstate(struct ieee80211vap *, enum ieee80211_state, int); 384 static void iwm_endscan_cb(void *, int); 385 static int iwm_send_bt_init_conf(struct iwm_softc *); 386 static boolean_t iwm_is_lar_supported(struct iwm_softc *); 387 static boolean_t iwm_is_wifi_mcc_supported(struct iwm_softc *); 388 static int iwm_send_update_mcc_cmd(struct iwm_softc *, const char *); 389 static void iwm_tt_tx_backoff(struct iwm_softc *, uint32_t); 390 static int iwm_init_hw(struct iwm_softc *); 391 static void iwm_init(struct iwm_softc *); 392 static void iwm_start(struct iwm_softc *); 393 static void iwm_stop(struct iwm_softc *); 394 static void iwm_watchdog(void *); 395 static void iwm_parent(struct ieee80211com *); 396 #ifdef IWM_DEBUG 397 static const char * 398 iwm_desc_lookup(uint32_t); 399 static void iwm_nic_error(struct iwm_softc *); 400 static void iwm_nic_umac_error(struct iwm_softc *); 401 #endif 402 static void iwm_handle_rxb(struct iwm_softc *, struct mbuf *); 403 static void iwm_notif_intr(struct iwm_softc *); 404 static void iwm_intr(void *); 405 static void iwm_intr_msix(void *); 406 static int iwm_attach(device_t); 407 static int iwm_is_valid_ether_addr(uint8_t *); 408 static void iwm_preinit(void *); 409 static int iwm_detach_local(struct iwm_softc *sc, int); 410 static void iwm_init_task(void *); 411 static void iwm_radiotap_attach(struct iwm_softc *); 412 static struct ieee80211vap * 413 iwm_vap_create(struct ieee80211com *, 414 const char [IFNAMSIZ], int, 415 enum ieee80211_opmode, int, 416 const uint8_t [IEEE80211_ADDR_LEN], 417 const uint8_t [IEEE80211_ADDR_LEN]); 418 static void iwm_vap_delete(struct ieee80211vap *); 419 static void iwm_xmit_queue_drain(struct iwm_softc *); 420 static void iwm_scan_start(struct ieee80211com *); 421 static void iwm_scan_end(struct ieee80211com *); 422 static void iwm_update_mcast(struct ieee80211com *); 423 static void iwm_set_channel(struct ieee80211com *); 424 static void iwm_scan_curchan(struct ieee80211_scan_state *, unsigned long); 425 static void iwm_scan_mindwell(struct ieee80211_scan_state *); 426 static int iwm_detach(device_t); 427 428 static int iwm_lar_disable = 0; 429 TUNABLE_INT("hw.iwm.lar.disable", &iwm_lar_disable); 430 431 /* 432 * Firmware parser. 433 */ 434 435 static int 436 iwm_store_cscheme(struct iwm_softc *sc, const uint8_t *data, size_t dlen) 437 { 438 const struct iwm_fw_cscheme_list *l = (const void *)data; 439 440 if (dlen < sizeof(*l) || 441 dlen < sizeof(l->size) + l->size * sizeof(*l->cs)) 442 return EINVAL; 443 444 /* we don't actually store anything for now, always use s/w crypto */ 445 446 return 0; 447 } 448 449 static int 450 iwm_firmware_store_section(struct iwm_softc *sc, 451 enum iwm_ucode_type type, const uint8_t *data, size_t dlen) 452 { 453 struct iwm_fw_img *fws; 454 struct iwm_fw_desc *fwone; 455 456 if (type >= IWM_UCODE_TYPE_MAX) 457 return EINVAL; 458 if (dlen < sizeof(uint32_t)) 459 return EINVAL; 460 461 fws = &sc->sc_fw.img[type]; 462 if (fws->fw_count >= IWM_UCODE_SECTION_MAX) 463 return EINVAL; 464 465 fwone = &fws->sec[fws->fw_count]; 466 467 /* first 32bit are device load offset */ 468 memcpy(&fwone->offset, data, sizeof(uint32_t)); 469 470 /* rest is data */ 471 fwone->data = data + sizeof(uint32_t); 472 fwone->len = dlen - sizeof(uint32_t); 473 474 fws->fw_count++; 475 476 return 0; 477 } 478 479 #define IWM_DEFAULT_SCAN_CHANNELS 40 480 481 /* iwlwifi: iwl-drv.c */ 482 struct iwm_tlv_calib_data { 483 uint32_t ucode_type; 484 struct iwm_tlv_calib_ctrl calib; 485 } __packed; 486 487 static int 488 iwm_set_default_calib(struct iwm_softc *sc, const void *data) 489 { 490 const struct iwm_tlv_calib_data *def_calib = data; 491 uint32_t ucode_type = le32toh(def_calib->ucode_type); 492 493 if (ucode_type >= IWM_UCODE_TYPE_MAX) { 494 device_printf(sc->sc_dev, 495 "Wrong ucode_type %u for default " 496 "calibration.\n", ucode_type); 497 return EINVAL; 498 } 499 500 sc->sc_default_calib[ucode_type].flow_trigger = 501 def_calib->calib.flow_trigger; 502 sc->sc_default_calib[ucode_type].event_trigger = 503 def_calib->calib.event_trigger; 504 505 return 0; 506 } 507 508 static int 509 iwm_set_ucode_api_flags(struct iwm_softc *sc, const uint8_t *data, 510 struct iwm_ucode_capabilities *capa) 511 { 512 const struct iwm_ucode_api *ucode_api = (const void *)data; 513 uint32_t api_index = le32toh(ucode_api->api_index); 514 uint32_t api_flags = le32toh(ucode_api->api_flags); 515 int i; 516 517 if (api_index >= howmany(IWM_NUM_UCODE_TLV_API, 32)) { 518 device_printf(sc->sc_dev, 519 "api flags index %d larger than supported by driver\n", 520 api_index); 521 /* don't return an error so we can load FW that has more bits */ 522 return 0; 523 } 524 525 for (i = 0; i < 32; i++) { 526 if (api_flags & (1U << i)) 527 setbit(capa->enabled_api, i + 32 * api_index); 528 } 529 530 return 0; 531 } 532 533 static int 534 iwm_set_ucode_capabilities(struct iwm_softc *sc, const uint8_t *data, 535 struct iwm_ucode_capabilities *capa) 536 { 537 const struct iwm_ucode_capa *ucode_capa = (const void *)data; 538 uint32_t api_index = le32toh(ucode_capa->api_index); 539 uint32_t api_flags = le32toh(ucode_capa->api_capa); 540 int i; 541 542 if (api_index >= howmany(IWM_NUM_UCODE_TLV_CAPA, 32)) { 543 device_printf(sc->sc_dev, 544 "capa flags index %d larger than supported by driver\n", 545 api_index); 546 /* don't return an error so we can load FW that has more bits */ 547 return 0; 548 } 549 550 for (i = 0; i < 32; i++) { 551 if (api_flags & (1U << i)) 552 setbit(capa->enabled_capa, i + 32 * api_index); 553 } 554 555 return 0; 556 } 557 558 static void 559 iwm_fw_info_free(struct iwm_fw_info *fw) 560 { 561 firmware_put(fw->fw_fp, FIRMWARE_UNLOAD); 562 fw->fw_fp = NULL; 563 memset(fw->img, 0, sizeof(fw->img)); 564 } 565 566 static uint8_t 567 iwm_lookup_cmd_ver(struct iwm_softc *sc, uint8_t grp, uint8_t cmd) 568 { 569 const struct iwm_fw_cmd_version *entry; 570 int i; 571 572 for (i = 0; i < sc->n_cmd_versions; i++) { 573 entry = &sc->cmd_versions[i]; 574 if (entry->group == grp && entry->cmd == cmd) 575 return entry->cmd_ver; 576 } 577 578 return IWM_FW_CMD_VER_UNKNOWN; 579 } 580 581 static int 582 iwm_read_firmware(struct iwm_softc *sc) 583 { 584 struct iwm_fw_info *fw = &sc->sc_fw; 585 const struct iwm_tlv_ucode_header *uhdr; 586 const struct iwm_ucode_tlv *tlv; 587 struct iwm_ucode_capabilities *capa = &sc->sc_fw.ucode_capa; 588 enum iwm_ucode_tlv_type tlv_type; 589 const struct firmware *fwp; 590 const uint8_t *data; 591 uint32_t tlv_len; 592 uint32_t usniffer_img; 593 const uint8_t *tlv_data; 594 uint32_t paging_mem_size; 595 int num_of_cpus; 596 int error = 0; 597 size_t len; 598 599 /* 600 * Load firmware into driver memory. 601 * fw_fp will be set. 602 */ 603 fwp = firmware_get(sc->cfg->fw_name); 604 if (fwp == NULL) { 605 device_printf(sc->sc_dev, 606 "could not read firmware %s (error %d)\n", 607 sc->cfg->fw_name, error); 608 goto out; 609 } 610 fw->fw_fp = fwp; 611 612 /* (Re-)Initialize default values. */ 613 capa->flags = 0; 614 capa->max_probe_length = IWM_DEFAULT_MAX_PROBE_LENGTH; 615 capa->n_scan_channels = IWM_DEFAULT_SCAN_CHANNELS; 616 memset(capa->enabled_capa, 0, sizeof(capa->enabled_capa)); 617 memset(capa->enabled_api, 0, sizeof(capa->enabled_api)); 618 memset(sc->sc_fw_mcc, 0, sizeof(sc->sc_fw_mcc)); 619 620 /* 621 * Parse firmware contents 622 */ 623 624 uhdr = (const void *)fw->fw_fp->data; 625 if (*(const uint32_t *)fw->fw_fp->data != 0 626 || le32toh(uhdr->magic) != IWM_TLV_UCODE_MAGIC) { 627 device_printf(sc->sc_dev, "invalid firmware %s\n", 628 sc->cfg->fw_name); 629 error = EINVAL; 630 goto out; 631 } 632 633 snprintf(sc->sc_fwver, sizeof(sc->sc_fwver), "%u.%u (API ver %u)", 634 IWM_UCODE_MAJOR(le32toh(uhdr->ver)), 635 IWM_UCODE_MINOR(le32toh(uhdr->ver)), 636 IWM_UCODE_API(le32toh(uhdr->ver))); 637 data = uhdr->data; 638 len = fw->fw_fp->datasize - sizeof(*uhdr); 639 640 while (len >= sizeof(*tlv)) { 641 len -= sizeof(*tlv); 642 tlv = (const void *)data; 643 644 tlv_len = le32toh(tlv->length); 645 tlv_type = le32toh(tlv->type); 646 tlv_data = tlv->data; 647 648 if (len < tlv_len) { 649 device_printf(sc->sc_dev, 650 "firmware too short: %zu bytes\n", 651 len); 652 error = EINVAL; 653 goto parse_out; 654 } 655 len -= roundup2(tlv_len, 4); 656 data += sizeof(*tlv) + roundup2(tlv_len, 4); 657 658 switch ((int)tlv_type) { 659 case IWM_UCODE_TLV_PROBE_MAX_LEN: 660 if (tlv_len != sizeof(uint32_t)) { 661 device_printf(sc->sc_dev, 662 "%s: PROBE_MAX_LEN (%u) != sizeof(uint32_t)\n", 663 __func__, tlv_len); 664 error = EINVAL; 665 goto parse_out; 666 } 667 capa->max_probe_length = 668 le32_to_cpup((const uint32_t *)tlv_data); 669 /* limit it to something sensible */ 670 if (capa->max_probe_length > 671 IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE) { 672 IWM_DPRINTF(sc, IWM_DEBUG_FIRMWARE_TLV, 673 "%s: IWM_UCODE_TLV_PROBE_MAX_LEN " 674 "ridiculous\n", __func__); 675 error = EINVAL; 676 goto parse_out; 677 } 678 break; 679 case IWM_UCODE_TLV_PAN: 680 if (tlv_len) { 681 device_printf(sc->sc_dev, 682 "%s: IWM_UCODE_TLV_PAN: tlv_len (%u) > 0\n", 683 __func__, tlv_len); 684 error = EINVAL; 685 goto parse_out; 686 } 687 capa->flags |= IWM_UCODE_TLV_FLAGS_PAN; 688 break; 689 case IWM_UCODE_TLV_FLAGS: 690 if (tlv_len < sizeof(uint32_t)) { 691 device_printf(sc->sc_dev, 692 "%s: IWM_UCODE_TLV_FLAGS: tlv_len (%u) < sizeof(uint32_t)\n", 693 __func__, tlv_len); 694 error = EINVAL; 695 goto parse_out; 696 } 697 if (tlv_len % sizeof(uint32_t)) { 698 device_printf(sc->sc_dev, 699 "%s: IWM_UCODE_TLV_FLAGS: tlv_len (%u) %% sizeof(uint32_t)\n", 700 __func__, tlv_len); 701 error = EINVAL; 702 goto parse_out; 703 } 704 /* 705 * Apparently there can be many flags, but Linux driver 706 * parses only the first one, and so do we. 707 * 708 * XXX: why does this override IWM_UCODE_TLV_PAN? 709 * Intentional or a bug? Observations from 710 * current firmware file: 711 * 1) TLV_PAN is parsed first 712 * 2) TLV_FLAGS contains TLV_FLAGS_PAN 713 * ==> this resets TLV_PAN to itself... hnnnk 714 */ 715 capa->flags = le32_to_cpup((const uint32_t *)tlv_data); 716 break; 717 case IWM_UCODE_TLV_CSCHEME: 718 if ((error = iwm_store_cscheme(sc, 719 tlv_data, tlv_len)) != 0) { 720 device_printf(sc->sc_dev, 721 "%s: iwm_store_cscheme(): returned %d\n", 722 __func__, error); 723 goto parse_out; 724 } 725 break; 726 case IWM_UCODE_TLV_NUM_OF_CPU: 727 if (tlv_len != sizeof(uint32_t)) { 728 device_printf(sc->sc_dev, 729 "%s: IWM_UCODE_TLV_NUM_OF_CPU: tlv_len (%u) != sizeof(uint32_t)\n", 730 __func__, tlv_len); 731 error = EINVAL; 732 goto parse_out; 733 } 734 num_of_cpus = le32_to_cpup((const uint32_t *)tlv_data); 735 if (num_of_cpus == 2) { 736 fw->img[IWM_UCODE_REGULAR].is_dual_cpus = 737 TRUE; 738 fw->img[IWM_UCODE_INIT].is_dual_cpus = 739 TRUE; 740 fw->img[IWM_UCODE_WOWLAN].is_dual_cpus = 741 TRUE; 742 } else if ((num_of_cpus > 2) || (num_of_cpus < 1)) { 743 device_printf(sc->sc_dev, 744 "%s: Driver supports only 1 or 2 CPUs\n", 745 __func__); 746 error = EINVAL; 747 goto parse_out; 748 } 749 break; 750 case IWM_UCODE_TLV_SEC_RT: 751 if ((error = iwm_firmware_store_section(sc, 752 IWM_UCODE_REGULAR, tlv_data, tlv_len)) != 0) { 753 device_printf(sc->sc_dev, 754 "%s: IWM_UCODE_REGULAR: iwm_firmware_store_section() failed; %d\n", 755 __func__, error); 756 goto parse_out; 757 } 758 break; 759 case IWM_UCODE_TLV_SEC_INIT: 760 if ((error = iwm_firmware_store_section(sc, 761 IWM_UCODE_INIT, tlv_data, tlv_len)) != 0) { 762 device_printf(sc->sc_dev, 763 "%s: IWM_UCODE_INIT: iwm_firmware_store_section() failed; %d\n", 764 __func__, error); 765 goto parse_out; 766 } 767 break; 768 case IWM_UCODE_TLV_SEC_WOWLAN: 769 if ((error = iwm_firmware_store_section(sc, 770 IWM_UCODE_WOWLAN, tlv_data, tlv_len)) != 0) { 771 device_printf(sc->sc_dev, 772 "%s: IWM_UCODE_WOWLAN: iwm_firmware_store_section() failed; %d\n", 773 __func__, error); 774 goto parse_out; 775 } 776 break; 777 case IWM_UCODE_TLV_DEF_CALIB: 778 if (tlv_len != sizeof(struct iwm_tlv_calib_data)) { 779 device_printf(sc->sc_dev, 780 "%s: IWM_UCODE_TLV_DEV_CALIB: tlv_len (%u) < sizeof(iwm_tlv_calib_data) (%zu)\n", 781 __func__, tlv_len, 782 sizeof(struct iwm_tlv_calib_data)); 783 error = EINVAL; 784 goto parse_out; 785 } 786 if ((error = iwm_set_default_calib(sc, tlv_data)) != 0) { 787 device_printf(sc->sc_dev, 788 "%s: iwm_set_default_calib() failed: %d\n", 789 __func__, error); 790 goto parse_out; 791 } 792 break; 793 case IWM_UCODE_TLV_PHY_SKU: 794 if (tlv_len != sizeof(uint32_t)) { 795 error = EINVAL; 796 device_printf(sc->sc_dev, 797 "%s: IWM_UCODE_TLV_PHY_SKU: tlv_len (%u) < sizeof(uint32_t)\n", 798 __func__, tlv_len); 799 goto parse_out; 800 } 801 sc->sc_fw.phy_config = 802 le32_to_cpup((const uint32_t *)tlv_data); 803 sc->sc_fw.valid_tx_ant = (sc->sc_fw.phy_config & 804 IWM_FW_PHY_CFG_TX_CHAIN) >> 805 IWM_FW_PHY_CFG_TX_CHAIN_POS; 806 sc->sc_fw.valid_rx_ant = (sc->sc_fw.phy_config & 807 IWM_FW_PHY_CFG_RX_CHAIN) >> 808 IWM_FW_PHY_CFG_RX_CHAIN_POS; 809 break; 810 811 case IWM_UCODE_TLV_API_CHANGES_SET: { 812 if (tlv_len != sizeof(struct iwm_ucode_api)) { 813 error = EINVAL; 814 goto parse_out; 815 } 816 if (iwm_set_ucode_api_flags(sc, tlv_data, capa)) { 817 error = EINVAL; 818 goto parse_out; 819 } 820 break; 821 } 822 823 case IWM_UCODE_TLV_ENABLED_CAPABILITIES: { 824 if (tlv_len != sizeof(struct iwm_ucode_capa)) { 825 error = EINVAL; 826 goto parse_out; 827 } 828 if (iwm_set_ucode_capabilities(sc, tlv_data, capa)) { 829 error = EINVAL; 830 goto parse_out; 831 } 832 break; 833 } 834 835 case IWM_UCODE_TLV_CMD_VERSIONS: 836 if (tlv_len % sizeof(struct iwm_fw_cmd_version)) { 837 tlv_len /= sizeof(struct iwm_fw_cmd_version); 838 tlv_len *= sizeof(struct iwm_fw_cmd_version); 839 } 840 if (sc->n_cmd_versions != 0) { 841 error = EINVAL; 842 goto parse_out; 843 } 844 if (tlv_len > sizeof(sc->cmd_versions)) { 845 error = EINVAL; 846 goto parse_out; 847 } 848 memcpy(&sc->cmd_versions[0], tlv_data, tlv_len); 849 sc->n_cmd_versions = tlv_len / sizeof(struct iwm_fw_cmd_version); 850 break; 851 852 case IWM_UCODE_TLV_SDIO_ADMA_ADDR: 853 case IWM_UCODE_TLV_FW_GSCAN_CAPA: 854 /* ignore, not used by current driver */ 855 break; 856 857 case IWM_UCODE_TLV_SEC_RT_USNIFFER: 858 if ((error = iwm_firmware_store_section(sc, 859 IWM_UCODE_REGULAR_USNIFFER, tlv_data, 860 tlv_len)) != 0) 861 goto parse_out; 862 break; 863 864 case IWM_UCODE_TLV_PAGING: 865 if (tlv_len != sizeof(uint32_t)) { 866 error = EINVAL; 867 goto parse_out; 868 } 869 paging_mem_size = le32_to_cpup((const uint32_t *)tlv_data); 870 871 IWM_DPRINTF(sc, IWM_DEBUG_FIRMWARE_TLV, 872 "%s: Paging: paging enabled (size = %u bytes)\n", 873 __func__, paging_mem_size); 874 if (paging_mem_size > IWM_MAX_PAGING_IMAGE_SIZE) { 875 device_printf(sc->sc_dev, 876 "%s: Paging: driver supports up to %u bytes for paging image\n", 877 __func__, IWM_MAX_PAGING_IMAGE_SIZE); 878 error = EINVAL; 879 goto out; 880 } 881 if (paging_mem_size & (IWM_FW_PAGING_SIZE - 1)) { 882 device_printf(sc->sc_dev, 883 "%s: Paging: image isn't multiple %u\n", 884 __func__, IWM_FW_PAGING_SIZE); 885 error = EINVAL; 886 goto out; 887 } 888 889 sc->sc_fw.img[IWM_UCODE_REGULAR].paging_mem_size = 890 paging_mem_size; 891 usniffer_img = IWM_UCODE_REGULAR_USNIFFER; 892 sc->sc_fw.img[usniffer_img].paging_mem_size = 893 paging_mem_size; 894 break; 895 896 case IWM_UCODE_TLV_N_SCAN_CHANNELS: 897 if (tlv_len != sizeof(uint32_t)) { 898 error = EINVAL; 899 goto parse_out; 900 } 901 capa->n_scan_channels = 902 le32_to_cpup((const uint32_t *)tlv_data); 903 break; 904 905 case IWM_UCODE_TLV_FW_VERSION: 906 if (tlv_len != sizeof(uint32_t) * 3) { 907 error = EINVAL; 908 goto parse_out; 909 } 910 snprintf(sc->sc_fwver, sizeof(sc->sc_fwver), 911 "%u.%u.%u", 912 le32toh(((const uint32_t *)tlv_data)[0]), 913 le32toh(((const uint32_t *)tlv_data)[1]), 914 le32toh(((const uint32_t *)tlv_data)[2])); 915 break; 916 917 case IWM_UCODE_TLV_FW_MEM_SEG: 918 break; 919 920 default: 921 device_printf(sc->sc_dev, 922 "%s: unknown firmware section %d, abort\n", 923 __func__, tlv_type); 924 error = EINVAL; 925 goto parse_out; 926 } 927 } 928 929 KASSERT(error == 0, ("unhandled error")); 930 931 parse_out: 932 if (error) { 933 device_printf(sc->sc_dev, "firmware parse error %d, " 934 "section type %d\n", error, tlv_type); 935 } 936 937 out: 938 if (error) { 939 if (fw->fw_fp != NULL) 940 iwm_fw_info_free(fw); 941 } 942 943 return error; 944 } 945 946 /* 947 * DMA resource routines 948 */ 949 950 /* fwmem is used to load firmware onto the card */ 951 static int 952 iwm_alloc_fwmem(struct iwm_softc *sc) 953 { 954 /* Must be aligned on a 16-byte boundary. */ 955 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, 956 IWM_FH_MEM_TB_MAX_LENGTH, 16); 957 } 958 959 /* tx scheduler rings. not used? */ 960 static int 961 iwm_alloc_sched(struct iwm_softc *sc) 962 { 963 /* TX scheduler rings must be aligned on a 1KB boundary. */ 964 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 965 nitems(sc->txq) * sizeof(struct iwm_agn_scd_bc_tbl), 1024); 966 } 967 968 /* keep-warm page is used internally by the card. see iwl-fh.h for more info */ 969 static int 970 iwm_alloc_kw(struct iwm_softc *sc) 971 { 972 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, 4096, 4096); 973 } 974 975 /* interrupt cause table */ 976 static int 977 iwm_alloc_ict(struct iwm_softc *sc) 978 { 979 return iwm_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 980 IWM_ICT_SIZE, 1<<IWM_ICT_PADDR_SHIFT); 981 } 982 983 static int 984 iwm_alloc_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 985 { 986 bus_size_t size; 987 size_t descsz; 988 int count, i, error; 989 990 ring->cur = 0; 991 if (sc->cfg->mqrx_supported) { 992 count = IWM_RX_MQ_RING_COUNT; 993 descsz = sizeof(uint64_t); 994 } else { 995 count = IWM_RX_LEGACY_RING_COUNT; 996 descsz = sizeof(uint32_t); 997 } 998 999 /* Allocate RX descriptors (256-byte aligned). */ 1000 size = count * descsz; 1001 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->free_desc_dma, size, 1002 256); 1003 if (error != 0) { 1004 device_printf(sc->sc_dev, 1005 "could not allocate RX ring DMA memory\n"); 1006 goto fail; 1007 } 1008 ring->desc = ring->free_desc_dma.vaddr; 1009 1010 /* Allocate RX status area (16-byte aligned). */ 1011 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1012 sizeof(*ring->stat), 16); 1013 if (error != 0) { 1014 device_printf(sc->sc_dev, 1015 "could not allocate RX status DMA memory\n"); 1016 goto fail; 1017 } 1018 ring->stat = ring->stat_dma.vaddr; 1019 1020 if (sc->cfg->mqrx_supported) { 1021 size = count * sizeof(uint32_t); 1022 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->used_desc_dma, 1023 size, 256); 1024 if (error != 0) { 1025 device_printf(sc->sc_dev, 1026 "could not allocate RX ring DMA memory\n"); 1027 goto fail; 1028 } 1029 } 1030 1031 /* Create RX buffer DMA tag. */ 1032 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1033 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1034 IWM_RBUF_SIZE, 1, IWM_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat); 1035 if (error != 0) { 1036 device_printf(sc->sc_dev, 1037 "%s: could not create RX buf DMA tag, error %d\n", 1038 __func__, error); 1039 goto fail; 1040 } 1041 1042 /* Allocate spare bus_dmamap_t for iwm_rx_addbuf() */ 1043 error = bus_dmamap_create(ring->data_dmat, 0, &ring->spare_map); 1044 if (error != 0) { 1045 device_printf(sc->sc_dev, 1046 "%s: could not create RX buf DMA map, error %d\n", 1047 __func__, error); 1048 goto fail; 1049 } 1050 1051 /* 1052 * Allocate and map RX buffers. 1053 */ 1054 for (i = 0; i < count; i++) { 1055 struct iwm_rx_data *data = &ring->data[i]; 1056 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1057 if (error != 0) { 1058 device_printf(sc->sc_dev, 1059 "%s: could not create RX buf DMA map, error %d\n", 1060 __func__, error); 1061 goto fail; 1062 } 1063 data->m = NULL; 1064 1065 if ((error = iwm_rx_addbuf(sc, IWM_RBUF_SIZE, i)) != 0) { 1066 goto fail; 1067 } 1068 } 1069 return 0; 1070 1071 fail: iwm_free_rx_ring(sc, ring); 1072 return error; 1073 } 1074 1075 static void 1076 iwm_reset_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 1077 { 1078 /* Reset the ring state */ 1079 ring->cur = 0; 1080 1081 /* 1082 * The hw rx ring index in shared memory must also be cleared, 1083 * otherwise the discrepancy can cause reprocessing chaos. 1084 */ 1085 if (sc->rxq.stat) 1086 memset(sc->rxq.stat, 0, sizeof(*sc->rxq.stat)); 1087 } 1088 1089 static void 1090 iwm_free_rx_ring(struct iwm_softc *sc, struct iwm_rx_ring *ring) 1091 { 1092 int count, i; 1093 1094 iwm_dma_contig_free(&ring->free_desc_dma); 1095 iwm_dma_contig_free(&ring->stat_dma); 1096 iwm_dma_contig_free(&ring->used_desc_dma); 1097 1098 count = sc->cfg->mqrx_supported ? IWM_RX_MQ_RING_COUNT : 1099 IWM_RX_LEGACY_RING_COUNT; 1100 1101 for (i = 0; i < count; i++) { 1102 struct iwm_rx_data *data = &ring->data[i]; 1103 1104 if (data->m != NULL) { 1105 bus_dmamap_sync(ring->data_dmat, data->map, 1106 BUS_DMASYNC_POSTREAD); 1107 bus_dmamap_unload(ring->data_dmat, data->map); 1108 m_freem(data->m); 1109 data->m = NULL; 1110 } 1111 if (data->map != NULL) { 1112 bus_dmamap_destroy(ring->data_dmat, data->map); 1113 data->map = NULL; 1114 } 1115 } 1116 if (ring->spare_map != NULL) { 1117 bus_dmamap_destroy(ring->data_dmat, ring->spare_map); 1118 ring->spare_map = NULL; 1119 } 1120 if (ring->data_dmat != NULL) { 1121 bus_dma_tag_destroy(ring->data_dmat); 1122 ring->data_dmat = NULL; 1123 } 1124 } 1125 1126 static int 1127 iwm_alloc_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring, int qid) 1128 { 1129 bus_addr_t paddr; 1130 bus_size_t size; 1131 size_t maxsize; 1132 int nsegments; 1133 int i, error; 1134 1135 ring->qid = qid; 1136 ring->queued = 0; 1137 ring->cur = 0; 1138 1139 /* Allocate TX descriptors (256-byte aligned). */ 1140 size = IWM_TX_RING_COUNT * sizeof (struct iwm_tfd); 1141 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, size, 256); 1142 if (error != 0) { 1143 device_printf(sc->sc_dev, 1144 "could not allocate TX ring DMA memory\n"); 1145 goto fail; 1146 } 1147 ring->desc = ring->desc_dma.vaddr; 1148 1149 /* 1150 * There is no need to allocate DMA buffers for unused rings. 1151 * 7k/8k/9k hardware supports up to 31 Tx rings which is more 1152 * than we currently need. 1153 * 1154 * In DQA mode we use 1 command queue + 4 DQA mgmt/data queues. 1155 * The command is queue 0 (sc->txq[0]), and 4 mgmt/data frame queues 1156 * are sc->tqx[IWM_DQA_MIN_MGMT_QUEUE + ac], i.e. sc->txq[5:8], 1157 * in order to provide one queue per EDCA category. 1158 * Tx aggregation requires additional queues, one queue per TID for 1159 * which aggregation is enabled. We map TID 0-7 to sc->txq[10:17]. 1160 * 1161 * In non-DQA mode, we use rings 0 through 9 (0-3 are EDCA, 9 is cmd), 1162 * and Tx aggregation is not supported. 1163 * 1164 * Unfortunately, we cannot tell if DQA will be used until the 1165 * firmware gets loaded later, so just allocate sufficient rings 1166 * in order to satisfy both cases. 1167 */ 1168 if (qid > IWM_LAST_AGG_TX_QUEUE) 1169 return 0; 1170 1171 size = IWM_TX_RING_COUNT * sizeof(struct iwm_device_cmd); 1172 error = iwm_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, size, 4); 1173 if (error != 0) { 1174 device_printf(sc->sc_dev, 1175 "could not allocate TX cmd DMA memory\n"); 1176 goto fail; 1177 } 1178 ring->cmd = ring->cmd_dma.vaddr; 1179 1180 /* 1181 * FW commands may require more mapped space than packets. The 1182 * DQA command queue is ring 0 and we can't tell at allocation 1183 * time which command queue id will be used, so give both the 1184 * command-sized DMA tag. 1185 */ 1186 if (qid == IWM_CMD_QUEUE || qid == IWM_DQA_CMD_QUEUE) { 1187 maxsize = IWM_RBUF_SIZE; 1188 nsegments = 1; 1189 } else { 1190 maxsize = MCLBYTES; 1191 nsegments = IWM_MAX_SCATTER - 2; 1192 } 1193 1194 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1195 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1196 nsegments, maxsize, 0, NULL, NULL, &ring->data_dmat); 1197 if (error != 0) { 1198 device_printf(sc->sc_dev, "could not create TX buf DMA tag\n"); 1199 goto fail; 1200 } 1201 1202 paddr = ring->cmd_dma.paddr; 1203 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1204 struct iwm_tx_data *data = &ring->data[i]; 1205 1206 data->cmd_paddr = paddr; 1207 data->scratch_paddr = paddr + sizeof(struct iwm_cmd_header) 1208 + offsetof(struct iwm_tx_cmd, scratch); 1209 paddr += sizeof(struct iwm_device_cmd); 1210 1211 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1212 if (error != 0) { 1213 device_printf(sc->sc_dev, 1214 "could not create TX buf DMA map\n"); 1215 goto fail; 1216 } 1217 } 1218 KASSERT(paddr == ring->cmd_dma.paddr + size, 1219 ("invalid physical address")); 1220 return 0; 1221 1222 fail: iwm_free_tx_ring(sc, ring); 1223 return error; 1224 } 1225 1226 static void 1227 iwm_reset_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring) 1228 { 1229 int i; 1230 1231 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1232 struct iwm_tx_data *data = &ring->data[i]; 1233 1234 if (data->m != NULL) { 1235 bus_dmamap_sync(ring->data_dmat, data->map, 1236 BUS_DMASYNC_POSTWRITE); 1237 bus_dmamap_unload(ring->data_dmat, data->map); 1238 m_freem(data->m); 1239 data->m = NULL; 1240 } 1241 } 1242 /* Clear TX descriptors. */ 1243 memset(ring->desc, 0, ring->desc_dma.size); 1244 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1245 BUS_DMASYNC_PREWRITE); 1246 sc->qfullmsk &= ~(1 << ring->qid); 1247 sc->qenablemsk &= ~(1 << ring->qid); 1248 ring->queued = 0; 1249 ring->cur = 0; 1250 1251 if (ring->qid == sc->cmdqid && sc->cmd_hold_nic_awake) 1252 iwm_pcie_clear_cmd_in_flight(sc); 1253 } 1254 1255 static void 1256 iwm_free_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring) 1257 { 1258 int i; 1259 1260 iwm_dma_contig_free(&ring->desc_dma); 1261 iwm_dma_contig_free(&ring->cmd_dma); 1262 1263 for (i = 0; i < IWM_TX_RING_COUNT; i++) { 1264 struct iwm_tx_data *data = &ring->data[i]; 1265 1266 if (data->m != NULL) { 1267 bus_dmamap_sync(ring->data_dmat, data->map, 1268 BUS_DMASYNC_POSTWRITE); 1269 bus_dmamap_unload(ring->data_dmat, data->map); 1270 m_freem(data->m); 1271 data->m = NULL; 1272 } 1273 if (data->map != NULL) { 1274 bus_dmamap_destroy(ring->data_dmat, data->map); 1275 data->map = NULL; 1276 } 1277 } 1278 if (ring->data_dmat != NULL) { 1279 bus_dma_tag_destroy(ring->data_dmat); 1280 ring->data_dmat = NULL; 1281 } 1282 } 1283 1284 /* 1285 * High-level hardware frobbing routines 1286 */ 1287 1288 static void 1289 iwm_enable_interrupts(struct iwm_softc *sc) 1290 { 1291 if (!sc->sc_msix) { 1292 sc->sc_intmask = IWM_CSR_INI_SET_MASK; 1293 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 1294 } else { 1295 /* 1296 * fh/hw_mask keeps all the unmasked causes. 1297 * Unlike msi, in msix cause is enabled when it is unset. 1298 */ 1299 sc->sc_hw_mask = sc->sc_hw_init_mask; 1300 sc->sc_fh_mask = sc->sc_fh_init_mask; 1301 IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD, 1302 ~sc->sc_fh_mask); 1303 IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD, 1304 ~sc->sc_hw_mask); 1305 } 1306 } 1307 1308 static void 1309 iwm_restore_interrupts(struct iwm_softc *sc) 1310 { 1311 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 1312 } 1313 1314 static void 1315 iwm_disable_interrupts(struct iwm_softc *sc) 1316 { 1317 if (!sc->sc_msix) { 1318 /* disable interrupts */ 1319 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0); 1320 1321 /* acknowledge all interrupts */ 1322 IWM_WRITE(sc, IWM_CSR_INT, ~0); 1323 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, ~0); 1324 } else { 1325 IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD, 1326 sc->sc_fh_init_mask); 1327 IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD, 1328 sc->sc_hw_init_mask); 1329 } 1330 } 1331 1332 static void 1333 iwm_ict_reset(struct iwm_softc *sc) 1334 { 1335 iwm_disable_interrupts(sc); 1336 1337 /* Reset ICT table. */ 1338 memset(sc->ict_dma.vaddr, 0, IWM_ICT_SIZE); 1339 sc->ict_cur = 0; 1340 1341 /* Set physical address of ICT table (4KB aligned). */ 1342 IWM_WRITE(sc, IWM_CSR_DRAM_INT_TBL_REG, 1343 IWM_CSR_DRAM_INT_TBL_ENABLE 1344 | IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER 1345 | IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK 1346 | sc->ict_dma.paddr >> IWM_ICT_PADDR_SHIFT); 1347 1348 /* Switch to ICT interrupt mode in driver. */ 1349 sc->sc_flags |= IWM_FLAG_USE_ICT; 1350 1351 /* Re-enable interrupts. */ 1352 IWM_WRITE(sc, IWM_CSR_INT, ~0); 1353 iwm_enable_interrupts(sc); 1354 } 1355 1356 /* iwlwifi pcie/trans.c */ 1357 1358 /* 1359 * Since this .. hard-resets things, it's time to actually 1360 * mark the first vap (if any) as having no mac context. 1361 * It's annoying, but since the driver is potentially being 1362 * stop/start'ed whilst active (thanks openbsd port!) we 1363 * have to correctly track this. 1364 */ 1365 static void 1366 iwm_stop_device(struct iwm_softc *sc) 1367 { 1368 struct ieee80211com *ic = &sc->sc_ic; 1369 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1370 int chnl, qid; 1371 uint32_t mask = 0; 1372 1373 /* tell the device to stop sending interrupts */ 1374 iwm_disable_interrupts(sc); 1375 1376 /* 1377 * FreeBSD-local: mark the first vap as not-uploaded, 1378 * so the next transition through auth/assoc 1379 * will correctly populate the MAC context. 1380 */ 1381 if (vap) { 1382 struct iwm_vap *iv = IWM_VAP(vap); 1383 iv->phy_ctxt = NULL; 1384 iv->is_uploaded = 0; 1385 } 1386 sc->sc_firmware_state = 0; 1387 sc->sc_flags &= ~IWM_FLAG_TE_ACTIVE; 1388 1389 /* device going down, Stop using ICT table */ 1390 sc->sc_flags &= ~IWM_FLAG_USE_ICT; 1391 1392 /* stop tx and rx. tx and rx bits, as usual, are from if_iwn */ 1393 1394 if (iwm_nic_lock(sc)) { 1395 iwm_write_prph(sc, IWM_SCD_TXFACT, 0); 1396 1397 /* Stop each Tx DMA channel */ 1398 for (chnl = 0; chnl < IWM_FH_TCSR_CHNL_NUM; chnl++) { 1399 IWM_WRITE(sc, 1400 IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl), 0); 1401 mask |= IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(chnl); 1402 } 1403 1404 /* Wait for DMA channels to be idle */ 1405 if (!iwm_poll_bit(sc, IWM_FH_TSSR_TX_STATUS_REG, mask, mask, 1406 5000)) { 1407 device_printf(sc->sc_dev, 1408 "Failing on timeout while stopping DMA channel: [0x%08x]\n", 1409 IWM_READ(sc, IWM_FH_TSSR_TX_STATUS_REG)); 1410 } 1411 iwm_nic_unlock(sc); 1412 } 1413 iwm_pcie_rx_stop(sc); 1414 1415 /* Stop RX ring. */ 1416 iwm_reset_rx_ring(sc, &sc->rxq); 1417 1418 /* Reset all TX rings. */ 1419 for (qid = 0; qid < nitems(sc->txq); qid++) 1420 iwm_reset_tx_ring(sc, &sc->txq[qid]); 1421 1422 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 1423 /* Power-down device's busmaster DMA clocks */ 1424 if (iwm_nic_lock(sc)) { 1425 iwm_write_prph(sc, IWM_APMG_CLK_DIS_REG, 1426 IWM_APMG_CLK_VAL_DMA_CLK_RQT); 1427 iwm_nic_unlock(sc); 1428 } 1429 DELAY(5); 1430 } 1431 1432 /* Make sure (redundant) we've released our request to stay awake */ 1433 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 1434 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1435 1436 /* Stop the device, and put it in low power state */ 1437 iwm_apm_stop(sc); 1438 1439 /* stop and reset the on-board processor */ 1440 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET); 1441 DELAY(5000); 1442 1443 /* 1444 * Upon stop, the IVAR table gets erased, so msi-x won't 1445 * work. This causes a bug in RF-KILL flows, since the interrupt 1446 * that enables radio won't fire on the correct irq, and the 1447 * driver won't be able to handle the interrupt. 1448 * Configure the IVAR table again after reset. 1449 */ 1450 iwm_conf_msix_hw(sc, 1); 1451 1452 /* 1453 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1454 * Clear the interrupt again. 1455 */ 1456 iwm_disable_interrupts(sc); 1457 1458 /* 1459 * Even if we stop the HW, we still want the RF kill 1460 * interrupt 1461 */ 1462 iwm_enable_rfkill_int(sc); 1463 iwm_check_rfkill(sc); 1464 1465 iwm_prepare_card_hw(sc); 1466 } 1467 1468 /* iwlwifi: mvm/ops.c */ 1469 static void 1470 iwm_nic_config(struct iwm_softc *sc) 1471 { 1472 uint8_t radio_cfg_type, radio_cfg_step, radio_cfg_dash; 1473 uint32_t mask, val, reg_val = 0; 1474 uint32_t phy_config = iwm_get_phy_config(sc); 1475 1476 radio_cfg_type = (phy_config & IWM_FW_PHY_CFG_RADIO_TYPE) >> 1477 IWM_FW_PHY_CFG_RADIO_TYPE_POS; 1478 radio_cfg_step = (phy_config & IWM_FW_PHY_CFG_RADIO_STEP) >> 1479 IWM_FW_PHY_CFG_RADIO_STEP_POS; 1480 radio_cfg_dash = (phy_config & IWM_FW_PHY_CFG_RADIO_DASH) >> 1481 IWM_FW_PHY_CFG_RADIO_DASH_POS; 1482 1483 /* SKU control */ 1484 reg_val |= IWM_CSR_HW_REV_STEP(sc->sc_hw_rev) << 1485 IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP; 1486 reg_val |= IWM_CSR_HW_REV_DASH(sc->sc_hw_rev) << 1487 IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH; 1488 1489 /* radio configuration */ 1490 reg_val |= radio_cfg_type << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE; 1491 reg_val |= radio_cfg_step << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP; 1492 reg_val |= radio_cfg_dash << IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH; 1493 1494 mask = IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH | 1495 IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP | 1496 IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP | 1497 IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH | 1498 IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE | 1499 IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 1500 IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI; 1501 1502 val = IWM_READ(sc, IWM_CSR_HW_IF_CONFIG_REG); 1503 val &= ~mask; 1504 val |= reg_val; 1505 IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG, val); 1506 1507 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1508 "Radio type=0x%x-0x%x-0x%x\n", radio_cfg_type, 1509 radio_cfg_step, radio_cfg_dash); 1510 1511 /* 1512 * W/A : NIC is stuck in a reset state after Early PCIe power off 1513 * (PCIe power is lost before PERST# is asserted), causing ME FW 1514 * to lose ownership and not being able to obtain it back. 1515 */ 1516 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 1517 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 1518 IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 1519 ~IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 1520 } 1521 } 1522 1523 static int 1524 iwm_nic_rx_mq_init(struct iwm_softc *sc) 1525 { 1526 int enabled; 1527 1528 if (!iwm_nic_lock(sc)) 1529 return EBUSY; 1530 1531 /* Stop RX DMA. */ 1532 iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG, 0); 1533 /* Disable RX used and free queue operation. */ 1534 iwm_write_prph(sc, IWM_RFH_RXF_RXQ_ACTIVE, 0); 1535 1536 iwm_write_prph64(sc, IWM_RFH_Q0_FRBDCB_BA_LSB, 1537 sc->rxq.free_desc_dma.paddr); 1538 iwm_write_prph64(sc, IWM_RFH_Q0_URBDCB_BA_LSB, 1539 sc->rxq.used_desc_dma.paddr); 1540 iwm_write_prph64(sc, IWM_RFH_Q0_URBD_STTS_WPTR_LSB, 1541 sc->rxq.stat_dma.paddr); 1542 iwm_write_prph(sc, IWM_RFH_Q0_FRBDCB_WIDX, 0); 1543 iwm_write_prph(sc, IWM_RFH_Q0_FRBDCB_RIDX, 0); 1544 iwm_write_prph(sc, IWM_RFH_Q0_URBDCB_WIDX, 0); 1545 1546 /* We configure only queue 0 for now. */ 1547 enabled = ((1 << 0) << 16) | (1 << 0); 1548 1549 /* Enable RX DMA, 4KB buffer size. */ 1550 iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG, 1551 IWM_RFH_DMA_EN_ENABLE_VAL | 1552 IWM_RFH_RXF_DMA_RB_SIZE_4K | 1553 IWM_RFH_RXF_DMA_MIN_RB_4_8 | 1554 IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK | 1555 IWM_RFH_RXF_DMA_RBDCB_SIZE_512); 1556 1557 /* Enable RX DMA snooping. */ 1558 iwm_write_prph(sc, IWM_RFH_GEN_CFG, 1559 IWM_RFH_GEN_CFG_RFH_DMA_SNOOP | 1560 IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP | 1561 (sc->cfg->integrated ? IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 : 1562 IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128)); 1563 1564 /* Enable the configured queue(s). */ 1565 iwm_write_prph(sc, IWM_RFH_RXF_RXQ_ACTIVE, enabled); 1566 1567 iwm_nic_unlock(sc); 1568 1569 IWM_WRITE_1(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_TIMEOUT_DEF); 1570 1571 IWM_WRITE(sc, IWM_RFH_Q0_FRBDCB_WIDX_TRG, 8); 1572 1573 return (0); 1574 } 1575 1576 static int 1577 iwm_nic_rx_legacy_init(struct iwm_softc *sc) 1578 { 1579 1580 /* Stop Rx DMA */ 1581 iwm_pcie_rx_stop(sc); 1582 1583 if (!iwm_nic_lock(sc)) 1584 return EBUSY; 1585 1586 /* reset and flush pointers */ 1587 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0); 1588 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0); 1589 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RDPTR, 0); 1590 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 1591 1592 /* Set physical address of RX ring (256-byte aligned). */ 1593 IWM_WRITE(sc, 1594 IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG, 1595 sc->rxq.free_desc_dma.paddr >> 8); 1596 1597 /* Set physical address of RX status (16-byte aligned). */ 1598 IWM_WRITE(sc, 1599 IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG, sc->rxq.stat_dma.paddr >> 4); 1600 1601 /* Enable Rx DMA 1602 * XXX 5000 HW isn't supported by the iwm(4) driver. 1603 * IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 1604 * the credit mechanism in 5000 HW RX FIFO 1605 * Direct rx interrupts to hosts 1606 * Rx buffer size 4 or 8k or 12k 1607 * RB timeout 0x10 1608 * 256 RBDs 1609 */ 1610 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 1611 IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 1612 IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | /* HW bug */ 1613 IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 1614 IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K | 1615 (IWM_RX_RB_TIMEOUT << IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 1616 IWM_RX_QUEUE_SIZE_LOG << IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS); 1617 1618 IWM_WRITE_1(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_TIMEOUT_DEF); 1619 1620 /* W/A for interrupt coalescing bug in 7260 and 3160 */ 1621 if (sc->cfg->host_interrupt_operation_mode) 1622 IWM_SETBITS(sc, IWM_CSR_INT_COALESCING, IWM_HOST_INT_OPER_MODE); 1623 1624 iwm_nic_unlock(sc); 1625 1626 IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, 8); 1627 1628 return 0; 1629 } 1630 1631 static int 1632 iwm_nic_rx_init(struct iwm_softc *sc) 1633 { 1634 if (sc->cfg->mqrx_supported) 1635 return iwm_nic_rx_mq_init(sc); 1636 else 1637 return iwm_nic_rx_legacy_init(sc); 1638 } 1639 1640 static int 1641 iwm_nic_tx_init(struct iwm_softc *sc) 1642 { 1643 int qid; 1644 1645 if (!iwm_nic_lock(sc)) 1646 return EBUSY; 1647 1648 /* Deactivate TX scheduler. */ 1649 iwm_write_prph(sc, IWM_SCD_TXFACT, 0); 1650 1651 /* Set physical address of "keep warm" page (16-byte aligned). */ 1652 IWM_WRITE(sc, IWM_FH_KW_MEM_ADDR_REG, sc->kw_dma.paddr >> 4); 1653 1654 /* Initialize TX rings. */ 1655 for (qid = 0; qid < nitems(sc->txq); qid++) { 1656 struct iwm_tx_ring *txq = &sc->txq[qid]; 1657 1658 /* Set physical address of TX ring (256-byte aligned). */ 1659 IWM_WRITE(sc, IWM_FH_MEM_CBBC_QUEUE(qid), 1660 txq->desc_dma.paddr >> 8); 1661 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 1662 "%s: loading ring %d descriptors (%p) at %lx\n", 1663 __func__, 1664 qid, txq->desc, 1665 (unsigned long) (txq->desc_dma.paddr >> 8)); 1666 } 1667 1668 iwm_set_bits_prph(sc, IWM_SCD_GP_CTRL, 1669 IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE | 1670 IWM_SCD_GP_CTRL_ENABLE_31_QUEUES); 1671 1672 iwm_nic_unlock(sc); 1673 1674 return 0; 1675 } 1676 1677 static int 1678 iwm_nic_init(struct iwm_softc *sc) 1679 { 1680 int error; 1681 1682 iwm_apm_init(sc); 1683 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) 1684 iwm_set_pwr(sc); 1685 1686 iwm_nic_config(sc); 1687 1688 if ((error = iwm_nic_rx_init(sc)) != 0) 1689 return error; 1690 1691 /* 1692 * Ditto for TX, from iwn 1693 */ 1694 if ((error = iwm_nic_tx_init(sc)) != 0) 1695 return error; 1696 1697 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 1698 "%s: shadow registers enabled\n", __func__); 1699 IWM_SETBITS(sc, IWM_CSR_MAC_SHADOW_REG_CTRL, 0x800fffff); 1700 1701 return 0; 1702 } 1703 1704 int 1705 iwm_enable_ac_txq(struct iwm_softc *sc, int qid, int fifo) 1706 { 1707 int err; 1708 1709 if (!sc->cmd_hold_nic_awake) { 1710 device_printf(sc->sc_dev, "%s: NIC not awake\n", __func__); 1711 return (ENXIO); 1712 } 1713 1714 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | 0); 1715 1716 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1717 (0 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) 1718 | (1 << IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 1719 1720 err = iwm_clear_bits_prph(sc, IWM_SCD_AGGR_SEL, (1 << qid)); 1721 if (err) { 1722 return err; 1723 } 1724 1725 iwm_write_prph(sc, IWM_SCD_QUEUE_RDPTR(qid), 0); 1726 1727 iwm_write_mem32(sc, 1728 sc->scd_base_addr + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid), 0); 1729 1730 /* Set scheduler window size and frame limit. */ 1731 iwm_write_mem32(sc, 1732 sc->scd_base_addr + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid) + 1733 sizeof(uint32_t), 1734 ((IWM_FRAME_LIMIT << IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1735 IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1736 ((IWM_FRAME_LIMIT 1737 << IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1738 IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1739 1740 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1741 (1 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1742 (fifo << IWM_SCD_QUEUE_STTS_REG_POS_TXF) | 1743 (1 << IWM_SCD_QUEUE_STTS_REG_POS_WSL) | 1744 IWM_SCD_QUEUE_STTS_REG_MSK); 1745 1746 if (qid == sc->cmdqid) 1747 iwm_write_prph(sc, IWM_SCD_EN_CTRL, 1748 iwm_read_prph(sc, IWM_SCD_EN_CTRL) | (1 << qid)); 1749 1750 return 0; 1751 } 1752 1753 int 1754 iwm_enable_txq(struct iwm_softc *sc, int sta_id, int qid, int fifo) 1755 { 1756 int qmsk; 1757 1758 qmsk = 1 << qid; 1759 1760 if (!iwm_nic_lock(sc)) { 1761 device_printf(sc->sc_dev, "%s: cannot enable txq %d\n", 1762 __func__, qid); 1763 return EBUSY; 1764 } 1765 1766 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | 0); 1767 1768 if (qid == sc->cmdqid) { 1769 #if 0 1770 /* Disable the scheduler. */ 1771 iwm_write_prph(sc, IWM_SCD_EN_CTRL, 0); 1772 #endif 1773 1774 /* Stop the TX queue prior to configuration. */ 1775 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1776 (0 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1777 (1 << IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 1778 1779 iwm_nic_unlock(sc); 1780 1781 /* Disable aggregations for this queue. */ 1782 iwm_clear_bits_prph(sc, IWM_SCD_AGGR_SEL, qmsk); 1783 1784 if (!iwm_nic_lock(sc)) { 1785 device_printf(sc->sc_dev, 1786 "%s: cannot enable txq %d\n", __func__, qid); 1787 return EBUSY; 1788 } 1789 iwm_write_prph(sc, IWM_SCD_QUEUE_RDPTR(qid), 0); 1790 iwm_nic_unlock(sc); 1791 1792 iwm_write_mem32(sc, 1793 sc->scd_base_addr + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid), 0); 1794 /* Set scheduler window size and frame limit. */ 1795 iwm_write_mem32(sc, 1796 sc->scd_base_addr + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid) + 1797 sizeof(uint32_t), 1798 ((IWM_FRAME_LIMIT << IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1799 IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1800 ((IWM_FRAME_LIMIT << IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1801 IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1802 1803 if (!iwm_nic_lock(sc)) { 1804 device_printf(sc->sc_dev, 1805 "%s: cannot enable txq %d\n", __func__, qid); 1806 return EBUSY; 1807 } 1808 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid), 1809 (1 << IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1810 (fifo << IWM_SCD_QUEUE_STTS_REG_POS_TXF) | 1811 (1 << IWM_SCD_QUEUE_STTS_REG_POS_WSL) | 1812 IWM_SCD_QUEUE_STTS_REG_MSK); 1813 1814 /* Enable the scheduler for this queue. */ 1815 iwm_write_prph(sc, IWM_SCD_EN_CTRL, 1816 iwm_read_prph(sc, IWM_SCD_EN_CTRL) | qmsk); 1817 } else { 1818 struct iwm_scd_txq_cfg_cmd cmd; 1819 int error; 1820 1821 iwm_nic_unlock(sc); 1822 1823 memset(&cmd, 0, sizeof(cmd)); 1824 cmd.scd_queue = qid; 1825 cmd.enable = 1; 1826 cmd.sta_id = sta_id; 1827 cmd.tx_fifo = fifo; 1828 cmd.aggregate = 0; 1829 cmd.window = IWM_FRAME_LIMIT; 1830 1831 error = iwm_send_cmd_pdu(sc, IWM_SCD_QUEUE_CFG, IWM_CMD_SYNC, 1832 sizeof(cmd), &cmd); 1833 if (error) { 1834 device_printf(sc->sc_dev, 1835 "cannot enable txq %d\n", qid); 1836 return error; 1837 } 1838 1839 if (!iwm_nic_lock(sc)) 1840 return EBUSY; 1841 } 1842 1843 iwm_nic_unlock(sc); 1844 1845 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, "%s: enabled txq %d FIFO %d\n", 1846 __func__, qid, fifo); 1847 1848 sc->qenablemsk |= (1 << qid); 1849 return 0; 1850 } 1851 1852 static int 1853 iwm_trans_pcie_fw_alive(struct iwm_softc *sc, uint32_t scd_base_addr) 1854 { 1855 int error, chnl; 1856 1857 int clear_dwords = (IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND - 1858 IWM_SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(uint32_t); 1859 1860 if (!iwm_nic_lock(sc)) 1861 return EBUSY; 1862 1863 iwm_ict_reset(sc); 1864 1865 sc->scd_base_addr = iwm_read_prph(sc, IWM_SCD_SRAM_BASE_ADDR); 1866 if (scd_base_addr != 0 && 1867 scd_base_addr != sc->scd_base_addr) { 1868 device_printf(sc->sc_dev, 1869 "%s: sched addr mismatch: alive: 0x%x prph: 0x%x\n", 1870 __func__, sc->scd_base_addr, scd_base_addr); 1871 } 1872 1873 iwm_nic_unlock(sc); 1874 1875 /* reset context data, TX status and translation data */ 1876 error = iwm_write_mem(sc, 1877 sc->scd_base_addr + IWM_SCD_CONTEXT_MEM_LOWER_BOUND, 1878 NULL, clear_dwords); 1879 if (error) 1880 return EBUSY; 1881 1882 if (!iwm_nic_lock(sc)) 1883 return EBUSY; 1884 1885 /* Set physical address of TX scheduler rings (1KB aligned). */ 1886 iwm_write_prph(sc, IWM_SCD_DRAM_BASE_ADDR, sc->sched_dma.paddr >> 10); 1887 1888 iwm_write_prph(sc, IWM_SCD_CHAINEXT_EN, 0); 1889 1890 iwm_nic_unlock(sc); 1891 1892 /* enable command channel */ 1893 error = iwm_enable_ac_txq(sc, sc->cmdqid, IWM_TX_FIFO_CMD); 1894 if (error) 1895 return error; 1896 1897 if (!iwm_nic_lock(sc)) 1898 return EBUSY; 1899 1900 iwm_write_prph(sc, IWM_SCD_TXFACT, 0xff); 1901 1902 /* Enable DMA channels. */ 1903 for (chnl = 0; chnl < IWM_FH_TCSR_CHNL_NUM; chnl++) { 1904 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl), 1905 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1906 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 1907 } 1908 1909 IWM_SETBITS(sc, IWM_FH_TX_CHICKEN_BITS_REG, 1910 IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 1911 1912 iwm_nic_unlock(sc); 1913 1914 /* Enable L1-Active */ 1915 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 1916 iwm_clear_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 1917 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 1918 } 1919 1920 return error; 1921 } 1922 1923 /* 1924 * NVM read access and content parsing. We do not support 1925 * external NVM or writing NVM. 1926 * iwlwifi/mvm/nvm.c 1927 */ 1928 1929 /* Default NVM size to read */ 1930 #define IWM_NVM_DEFAULT_CHUNK_SIZE (2*1024) 1931 1932 #define IWM_NVM_WRITE_OPCODE 1 1933 #define IWM_NVM_READ_OPCODE 0 1934 1935 /* load nvm chunk response */ 1936 enum { 1937 IWM_READ_NVM_CHUNK_SUCCEED = 0, 1938 IWM_READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1 1939 }; 1940 1941 static int 1942 iwm_nvm_read_chunk(struct iwm_softc *sc, uint16_t section, 1943 uint16_t offset, uint16_t length, uint8_t *data, uint16_t *len) 1944 { 1945 struct iwm_nvm_access_cmd nvm_access_cmd = { 1946 .offset = htole16(offset), 1947 .length = htole16(length), 1948 .type = htole16(section), 1949 .op_code = IWM_NVM_READ_OPCODE, 1950 }; 1951 struct iwm_nvm_access_resp *nvm_resp; 1952 struct iwm_rx_packet *pkt; 1953 struct iwm_host_cmd cmd = { 1954 .id = IWM_NVM_ACCESS_CMD, 1955 .flags = IWM_CMD_WANT_SKB | IWM_CMD_SEND_IN_RFKILL, 1956 .data = { &nvm_access_cmd, }, 1957 }; 1958 int ret, bytes_read, offset_read; 1959 uint8_t *resp_data; 1960 1961 cmd.len[0] = sizeof(struct iwm_nvm_access_cmd); 1962 1963 ret = iwm_send_cmd(sc, &cmd); 1964 if (ret) { 1965 device_printf(sc->sc_dev, 1966 "Could not send NVM_ACCESS command (error=%d)\n", ret); 1967 return ret; 1968 } 1969 1970 pkt = cmd.resp_pkt; 1971 1972 /* Extract NVM response */ 1973 nvm_resp = (void *)pkt->data; 1974 ret = le16toh(nvm_resp->status); 1975 bytes_read = le16toh(nvm_resp->length); 1976 offset_read = le16toh(nvm_resp->offset); 1977 resp_data = nvm_resp->data; 1978 if (ret) { 1979 if ((offset != 0) && 1980 (ret == IWM_READ_NVM_CHUNK_NOT_VALID_ADDRESS)) { 1981 /* 1982 * meaning of NOT_VALID_ADDRESS: 1983 * driver try to read chunk from address that is 1984 * multiple of 2K and got an error since addr is empty. 1985 * meaning of (offset != 0): driver already 1986 * read valid data from another chunk so this case 1987 * is not an error. 1988 */ 1989 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 1990 "NVM access command failed on offset 0x%x since that section size is multiple 2K\n", 1991 offset); 1992 *len = 0; 1993 ret = 0; 1994 } else { 1995 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 1996 "NVM access command failed with status %d\n", ret); 1997 ret = EIO; 1998 } 1999 goto exit; 2000 } 2001 2002 if (offset_read != offset) { 2003 device_printf(sc->sc_dev, 2004 "NVM ACCESS response with invalid offset %d\n", 2005 offset_read); 2006 ret = EINVAL; 2007 goto exit; 2008 } 2009 2010 if (bytes_read > length) { 2011 device_printf(sc->sc_dev, 2012 "NVM ACCESS response with too much data " 2013 "(%d bytes requested, %d bytes received)\n", 2014 length, bytes_read); 2015 ret = EINVAL; 2016 goto exit; 2017 } 2018 2019 /* Write data to NVM */ 2020 memcpy(data + offset, resp_data, bytes_read); 2021 *len = bytes_read; 2022 2023 exit: 2024 iwm_free_resp(sc, &cmd); 2025 return ret; 2026 } 2027 2028 /* 2029 * Reads an NVM section completely. 2030 * NICs prior to 7000 family don't have a real NVM, but just read 2031 * section 0 which is the EEPROM. Because the EEPROM reading is unlimited 2032 * by uCode, we need to manually check in this case that we don't 2033 * overflow and try to read more than the EEPROM size. 2034 * For 7000 family NICs, we supply the maximal size we can read, and 2035 * the uCode fills the response with as much data as we can, 2036 * without overflowing, so no check is needed. 2037 */ 2038 static int 2039 iwm_nvm_read_section(struct iwm_softc *sc, 2040 uint16_t section, uint8_t *data, uint16_t *len, uint32_t size_read) 2041 { 2042 uint16_t seglen, length, offset = 0; 2043 int ret; 2044 2045 /* Set nvm section read length */ 2046 length = IWM_NVM_DEFAULT_CHUNK_SIZE; 2047 2048 seglen = length; 2049 2050 /* Read the NVM until exhausted (reading less than requested) */ 2051 while (seglen == length) { 2052 /* Check no memory assumptions fail and cause an overflow */ 2053 if ((size_read + offset + length) > 2054 sc->cfg->eeprom_size) { 2055 device_printf(sc->sc_dev, 2056 "EEPROM size is too small for NVM\n"); 2057 return ENOBUFS; 2058 } 2059 2060 ret = iwm_nvm_read_chunk(sc, section, offset, length, data, &seglen); 2061 if (ret) { 2062 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 2063 "Cannot read NVM from section %d offset %d, length %d\n", 2064 section, offset, length); 2065 return ret; 2066 } 2067 offset += seglen; 2068 } 2069 2070 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 2071 "NVM section %d read completed\n", section); 2072 *len = offset; 2073 return 0; 2074 } 2075 2076 /* 2077 * BEGIN IWM_NVM_PARSE 2078 */ 2079 2080 /* iwlwifi/iwl-nvm-parse.c */ 2081 2082 /* 2083 * Translate EEPROM flags to net80211. 2084 */ 2085 static uint32_t 2086 iwm_eeprom_channel_flags(uint16_t ch_flags) 2087 { 2088 uint32_t nflags; 2089 2090 nflags = 0; 2091 if ((ch_flags & IWM_NVM_CHANNEL_ACTIVE) == 0) 2092 nflags |= IEEE80211_CHAN_PASSIVE; 2093 if ((ch_flags & IWM_NVM_CHANNEL_IBSS) == 0) 2094 nflags |= IEEE80211_CHAN_NOADHOC; 2095 if (ch_flags & IWM_NVM_CHANNEL_RADAR) { 2096 nflags |= IEEE80211_CHAN_DFS; 2097 /* Just in case. */ 2098 nflags |= IEEE80211_CHAN_NOADHOC; 2099 } 2100 2101 return (nflags); 2102 } 2103 2104 static void 2105 iwm_add_channel_band(struct iwm_softc *sc, struct ieee80211_channel chans[], 2106 int maxchans, int *nchans, int ch_idx, size_t ch_num, 2107 const uint8_t bands[]) 2108 { 2109 const uint16_t * const nvm_ch_flags = sc->nvm_data->nvm_ch_flags; 2110 uint32_t nflags; 2111 uint16_t ch_flags; 2112 uint8_t ieee; 2113 int error; 2114 2115 for (; ch_idx < ch_num; ch_idx++) { 2116 ch_flags = le16_to_cpup(nvm_ch_flags + ch_idx); 2117 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) 2118 ieee = iwm_nvm_channels[ch_idx]; 2119 else 2120 ieee = iwm_nvm_channels_8000[ch_idx]; 2121 2122 if (!(ch_flags & IWM_NVM_CHANNEL_VALID)) { 2123 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM, 2124 "Ch. %d Flags %x [%sGHz] - No traffic\n", 2125 ieee, ch_flags, 2126 (ch_idx >= IWM_NUM_2GHZ_CHANNELS) ? 2127 "5.2" : "2.4"); 2128 continue; 2129 } 2130 2131 nflags = iwm_eeprom_channel_flags(ch_flags); 2132 error = ieee80211_add_channel(chans, maxchans, nchans, 2133 ieee, 0, 0, nflags, bands); 2134 if (error != 0) 2135 break; 2136 2137 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM, 2138 "Ch. %d Flags %x [%sGHz] - Added\n", 2139 ieee, ch_flags, 2140 (ch_idx >= IWM_NUM_2GHZ_CHANNELS) ? 2141 "5.2" : "2.4"); 2142 } 2143 } 2144 2145 /* TODO: HT20 */ 2146 /* TODO: HT40 */ 2147 /* TODO: VHT20 */ 2148 /* TODO: VHT40, VHT80 */ 2149 2150 static void 2151 iwm_init_channel_map(struct ieee80211com *ic, int maxchans, int *nchans, 2152 struct ieee80211_channel chans[]) 2153 { 2154 struct iwm_softc *sc = ic->ic_softc; 2155 struct iwm_nvm_data *data = sc->nvm_data; 2156 uint8_t bands[IEEE80211_MODE_BYTES]; 2157 size_t ch_num; 2158 2159 memset(bands, 0, sizeof(bands)); 2160 /* 1-13: 11b/g channels. */ 2161 setbit(bands, IEEE80211_MODE_11B); 2162 setbit(bands, IEEE80211_MODE_11G); 2163 iwm_add_channel_band(sc, chans, maxchans, nchans, 0, 2164 IWM_NUM_2GHZ_CHANNELS - 1, bands); 2165 2166 /* 14: 11b channel only. */ 2167 clrbit(bands, IEEE80211_MODE_11G); 2168 iwm_add_channel_band(sc, chans, maxchans, nchans, 2169 IWM_NUM_2GHZ_CHANNELS - 1, IWM_NUM_2GHZ_CHANNELS, bands); 2170 2171 if (data->sku_cap_band_52GHz_enable) { 2172 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) 2173 ch_num = nitems(iwm_nvm_channels); 2174 else 2175 ch_num = nitems(iwm_nvm_channels_8000); 2176 memset(bands, 0, sizeof(bands)); 2177 setbit(bands, IEEE80211_MODE_11A); 2178 iwm_add_channel_band(sc, chans, maxchans, nchans, 2179 IWM_NUM_2GHZ_CHANNELS, ch_num, bands); 2180 } 2181 } 2182 2183 static int 2184 iwm_mimo_enabled(struct iwm_softc *sc) 2185 { 2186 return (!sc->nvm_data->sku_cap_mimo_disable); 2187 } 2188 2189 static void 2190 iwm_setup_ht_rates(struct iwm_softc *sc) 2191 { 2192 /* XXX TODO MCS0..7 */ 2193 2194 if (!iwm_mimo_enabled(sc)) 2195 return; 2196 2197 /* XXX TODO: MCS8..15 if >1 antenna and mimo enabled */ 2198 } 2199 2200 static void 2201 iwm_vap_update_slot(struct ieee80211vap *vap) 2202 { 2203 struct ieee80211com *ic = vap->iv_ic; 2204 struct iwm_softc *sc = ic->ic_softc; 2205 2206 IWM_LOCK_ASSERT_UNLOCKED(sc); 2207 2208 IWM_LOCK(sc); 2209 if ((sc->sc_flags & IWM_FLAG_STOPPED) == 0) { 2210 taskqueue_enqueue(sc->sc_tq, &sc->mac_ctxt_task); 2211 } 2212 IWM_UNLOCK(sc); 2213 } 2214 2215 static void 2216 iwm_vap_update_preamble(struct ieee80211vap *vap) 2217 { 2218 struct ieee80211com *ic = vap->iv_ic; 2219 struct iwm_softc *sc = ic->ic_softc; 2220 2221 IWM_LOCK_ASSERT_UNLOCKED(sc); 2222 2223 IWM_LOCK(sc); 2224 if ((sc->sc_flags & IWM_FLAG_STOPPED) == 0) { 2225 taskqueue_enqueue(sc->sc_tq, &sc->mac_ctxt_task); 2226 } 2227 IWM_UNLOCK(sc); 2228 } 2229 2230 static int 2231 iwm_vap_update_wme(struct ieee80211vap *vap, 2232 const struct wmeParams *wme_params) 2233 { 2234 struct ieee80211com *ic = vap->iv_ic; 2235 struct iwm_softc *sc = ic->ic_softc; 2236 2237 IWM_LOCK_ASSERT_UNLOCKED(sc); 2238 2239 IWM_LOCK(sc); 2240 if ((sc->sc_flags & IWM_FLAG_STOPPED) == 0) { 2241 taskqueue_enqueue(sc->sc_tq, &sc->mac_ctxt_task); 2242 } 2243 IWM_UNLOCK(sc); 2244 2245 return (0); 2246 } 2247 2248 static void 2249 iwm_vap_update_erp_protmode(struct ieee80211vap *vap) 2250 { 2251 struct ieee80211com *ic = vap->iv_ic; 2252 struct iwm_softc *sc = ic->ic_softc; 2253 2254 IWM_LOCK_ASSERT_UNLOCKED(sc); 2255 2256 IWM_LOCK(sc); 2257 if ((sc->sc_flags & IWM_FLAG_STOPPED) == 0) { 2258 taskqueue_enqueue(sc->sc_tq, &sc->mac_ctxt_task); 2259 } 2260 IWM_UNLOCK(sc); 2261 } 2262 2263 static void 2264 iwm_set_hw_address_family_8000(struct iwm_softc *sc, struct iwm_nvm_data *data, 2265 const uint16_t *mac_override, const uint16_t *nvm_hw) 2266 { 2267 const uint8_t *hw_addr; 2268 2269 if (mac_override) { 2270 static const uint8_t reserved_mac[] = { 2271 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 2272 }; 2273 2274 hw_addr = (const uint8_t *)(mac_override + 2275 IWM_MAC_ADDRESS_OVERRIDE_8000); 2276 2277 /* 2278 * Store the MAC address from MAO section. 2279 * No byte swapping is required in MAO section 2280 */ 2281 IEEE80211_ADDR_COPY(data->hw_addr, hw_addr); 2282 2283 /* 2284 * Force the use of the OTP MAC address in case of reserved MAC 2285 * address in the NVM, or if address is given but invalid. 2286 */ 2287 if (!IEEE80211_ADDR_EQ(reserved_mac, hw_addr) && 2288 !IEEE80211_ADDR_EQ(ieee80211broadcastaddr, data->hw_addr) && 2289 iwm_is_valid_ether_addr(data->hw_addr) && 2290 !IEEE80211_IS_MULTICAST(data->hw_addr)) 2291 return; 2292 2293 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2294 "%s: mac address from nvm override section invalid\n", 2295 __func__); 2296 } 2297 2298 if (nvm_hw) { 2299 /* read the mac address from WFMP registers */ 2300 uint32_t mac_addr0 = 2301 htole32(iwm_read_prph(sc, IWM_WFMP_MAC_ADDR_0)); 2302 uint32_t mac_addr1 = 2303 htole32(iwm_read_prph(sc, IWM_WFMP_MAC_ADDR_1)); 2304 2305 hw_addr = (const uint8_t *)&mac_addr0; 2306 data->hw_addr[0] = hw_addr[3]; 2307 data->hw_addr[1] = hw_addr[2]; 2308 data->hw_addr[2] = hw_addr[1]; 2309 data->hw_addr[3] = hw_addr[0]; 2310 2311 hw_addr = (const uint8_t *)&mac_addr1; 2312 data->hw_addr[4] = hw_addr[1]; 2313 data->hw_addr[5] = hw_addr[0]; 2314 2315 return; 2316 } 2317 2318 device_printf(sc->sc_dev, "%s: mac address not found\n", __func__); 2319 memset(data->hw_addr, 0, sizeof(data->hw_addr)); 2320 } 2321 2322 static int 2323 iwm_get_sku(const struct iwm_softc *sc, const uint16_t *nvm_sw, 2324 const uint16_t *phy_sku) 2325 { 2326 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) 2327 return le16_to_cpup(nvm_sw + IWM_SKU); 2328 2329 return le32_to_cpup((const uint32_t *)(phy_sku + IWM_SKU_8000)); 2330 } 2331 2332 static int 2333 iwm_get_nvm_version(const struct iwm_softc *sc, const uint16_t *nvm_sw) 2334 { 2335 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) 2336 return le16_to_cpup(nvm_sw + IWM_NVM_VERSION); 2337 else 2338 return le32_to_cpup((const uint32_t *)(nvm_sw + 2339 IWM_NVM_VERSION_8000)); 2340 } 2341 2342 static int 2343 iwm_get_radio_cfg(const struct iwm_softc *sc, const uint16_t *nvm_sw, 2344 const uint16_t *phy_sku) 2345 { 2346 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) 2347 return le16_to_cpup(nvm_sw + IWM_RADIO_CFG); 2348 2349 return le32_to_cpup((const uint32_t *)(phy_sku + IWM_RADIO_CFG_8000)); 2350 } 2351 2352 static int 2353 iwm_get_n_hw_addrs(const struct iwm_softc *sc, const uint16_t *nvm_sw) 2354 { 2355 int n_hw_addr; 2356 2357 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) 2358 return le16_to_cpup(nvm_sw + IWM_N_HW_ADDRS); 2359 2360 n_hw_addr = le32_to_cpup((const uint32_t *)(nvm_sw + IWM_N_HW_ADDRS_8000)); 2361 2362 return n_hw_addr & IWM_N_HW_ADDR_MASK; 2363 } 2364 2365 static void 2366 iwm_set_radio_cfg(const struct iwm_softc *sc, struct iwm_nvm_data *data, 2367 uint32_t radio_cfg) 2368 { 2369 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 2370 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK(radio_cfg); 2371 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK(radio_cfg); 2372 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK(radio_cfg); 2373 data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK(radio_cfg); 2374 return; 2375 } 2376 2377 /* set the radio configuration for family 8000 */ 2378 data->radio_cfg_type = IWM_NVM_RF_CFG_TYPE_MSK_8000(radio_cfg); 2379 data->radio_cfg_step = IWM_NVM_RF_CFG_STEP_MSK_8000(radio_cfg); 2380 data->radio_cfg_dash = IWM_NVM_RF_CFG_DASH_MSK_8000(radio_cfg); 2381 data->radio_cfg_pnum = IWM_NVM_RF_CFG_PNUM_MSK_8000(radio_cfg); 2382 data->valid_tx_ant = IWM_NVM_RF_CFG_TX_ANT_MSK_8000(radio_cfg); 2383 data->valid_rx_ant = IWM_NVM_RF_CFG_RX_ANT_MSK_8000(radio_cfg); 2384 } 2385 2386 static int 2387 iwm_set_hw_address(struct iwm_softc *sc, struct iwm_nvm_data *data, 2388 const uint16_t *nvm_hw, const uint16_t *mac_override) 2389 { 2390 #ifdef notyet /* for FAMILY 9000 */ 2391 if (cfg->mac_addr_from_csr) { 2392 iwm_set_hw_address_from_csr(sc, data); 2393 } else 2394 #endif 2395 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 2396 const uint8_t *hw_addr = (const uint8_t *)(nvm_hw + IWM_HW_ADDR); 2397 2398 /* The byte order is little endian 16 bit, meaning 214365 */ 2399 data->hw_addr[0] = hw_addr[1]; 2400 data->hw_addr[1] = hw_addr[0]; 2401 data->hw_addr[2] = hw_addr[3]; 2402 data->hw_addr[3] = hw_addr[2]; 2403 data->hw_addr[4] = hw_addr[5]; 2404 data->hw_addr[5] = hw_addr[4]; 2405 } else { 2406 iwm_set_hw_address_family_8000(sc, data, mac_override, nvm_hw); 2407 } 2408 2409 if (!iwm_is_valid_ether_addr(data->hw_addr)) { 2410 device_printf(sc->sc_dev, "no valid mac address was found\n"); 2411 return EINVAL; 2412 } 2413 2414 return 0; 2415 } 2416 2417 static struct iwm_nvm_data * 2418 iwm_parse_nvm_data(struct iwm_softc *sc, 2419 const uint16_t *nvm_hw, const uint16_t *nvm_sw, 2420 const uint16_t *nvm_calib, const uint16_t *mac_override, 2421 const uint16_t *phy_sku, const uint16_t *regulatory) 2422 { 2423 struct iwm_nvm_data *data; 2424 uint32_t sku, radio_cfg; 2425 uint16_t lar_config; 2426 2427 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 2428 data = malloc(sizeof(*data) + 2429 IWM_NUM_CHANNELS * sizeof(uint16_t), 2430 M_DEVBUF, M_NOWAIT | M_ZERO); 2431 } else { 2432 data = malloc(sizeof(*data) + 2433 IWM_NUM_CHANNELS_8000 * sizeof(uint16_t), 2434 M_DEVBUF, M_NOWAIT | M_ZERO); 2435 } 2436 if (!data) 2437 return NULL; 2438 2439 data->nvm_version = iwm_get_nvm_version(sc, nvm_sw); 2440 2441 radio_cfg = iwm_get_radio_cfg(sc, nvm_sw, phy_sku); 2442 iwm_set_radio_cfg(sc, data, radio_cfg); 2443 2444 sku = iwm_get_sku(sc, nvm_sw, phy_sku); 2445 data->sku_cap_band_24GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_24GHZ; 2446 data->sku_cap_band_52GHz_enable = sku & IWM_NVM_SKU_CAP_BAND_52GHZ; 2447 data->sku_cap_11n_enable = sku & IWM_NVM_SKU_CAP_11N_ENABLE; 2448 data->sku_cap_mimo_disable = sku & IWM_NVM_SKU_CAP_MIMO_DISABLE; 2449 2450 data->n_hw_addrs = iwm_get_n_hw_addrs(sc, nvm_sw); 2451 2452 data->calib_version = 255; /* TODO: 2453 this value will prevent some checks from 2454 failing, we need to check if this 2455 field is still needed, and if it does, 2456 where is it in the NVM */ 2457 2458 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) { 2459 /* TODO: use IWL_NVM_EXT */ 2460 uint16_t lar_offset = data->nvm_version < 0xE39 ? 2461 IWM_NVM_LAR_OFFSET_8000_OLD : 2462 IWM_NVM_LAR_OFFSET_8000; 2463 2464 lar_config = le16_to_cpup(regulatory + lar_offset); 2465 data->lar_enabled = !!(lar_config & 2466 IWM_NVM_LAR_ENABLED_8000); 2467 } 2468 2469 /* If no valid mac address was found - bail out */ 2470 if (iwm_set_hw_address(sc, data, nvm_hw, mac_override)) { 2471 free(data, M_DEVBUF); 2472 return NULL; 2473 } 2474 2475 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 2476 memcpy(data->nvm_ch_flags, sc->cfg->nvm_type == IWM_NVM_SDP ? 2477 ®ulatory[0] : &nvm_sw[IWM_NVM_CHANNELS], 2478 IWM_NUM_CHANNELS * sizeof(uint16_t)); 2479 } else { 2480 memcpy(data->nvm_ch_flags, ®ulatory[IWM_NVM_CHANNELS_8000], 2481 IWM_NUM_CHANNELS_8000 * sizeof(uint16_t)); 2482 } 2483 2484 return data; 2485 } 2486 2487 static void 2488 iwm_free_nvm_data(struct iwm_nvm_data *data) 2489 { 2490 if (data != NULL) 2491 free(data, M_DEVBUF); 2492 } 2493 2494 static struct iwm_nvm_data * 2495 iwm_parse_nvm_sections(struct iwm_softc *sc, struct iwm_nvm_section *sections) 2496 { 2497 const uint16_t *hw, *sw, *calib, *regulatory, *mac_override, *phy_sku; 2498 2499 /* Checking for required sections */ 2500 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 2501 if (!sections[IWM_NVM_SECTION_TYPE_SW].data || 2502 !sections[sc->cfg->nvm_hw_section_num].data) { 2503 device_printf(sc->sc_dev, 2504 "Can't parse empty OTP/NVM sections\n"); 2505 return NULL; 2506 } 2507 } else if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) { 2508 /* SW and REGULATORY sections are mandatory */ 2509 if (!sections[IWM_NVM_SECTION_TYPE_SW].data || 2510 !sections[IWM_NVM_SECTION_TYPE_REGULATORY].data) { 2511 device_printf(sc->sc_dev, 2512 "Can't parse empty OTP/NVM sections\n"); 2513 return NULL; 2514 } 2515 /* MAC_OVERRIDE or at least HW section must exist */ 2516 if (!sections[sc->cfg->nvm_hw_section_num].data && 2517 !sections[IWM_NVM_SECTION_TYPE_MAC_OVERRIDE].data) { 2518 device_printf(sc->sc_dev, 2519 "Can't parse mac_address, empty sections\n"); 2520 return NULL; 2521 } 2522 2523 /* PHY_SKU section is mandatory in B0 */ 2524 if (!sections[IWM_NVM_SECTION_TYPE_PHY_SKU].data) { 2525 device_printf(sc->sc_dev, 2526 "Can't parse phy_sku in B0, empty sections\n"); 2527 return NULL; 2528 } 2529 } else { 2530 panic("unknown device family %d\n", sc->cfg->device_family); 2531 } 2532 2533 hw = (const uint16_t *) sections[sc->cfg->nvm_hw_section_num].data; 2534 sw = (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_SW].data; 2535 calib = (const uint16_t *) 2536 sections[IWM_NVM_SECTION_TYPE_CALIBRATION].data; 2537 regulatory = sc->cfg->nvm_type == IWM_NVM_SDP ? 2538 (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_REGULATORY_SDP].data : 2539 (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_REGULATORY].data; 2540 mac_override = (const uint16_t *) 2541 sections[IWM_NVM_SECTION_TYPE_MAC_OVERRIDE].data; 2542 phy_sku = (const uint16_t *)sections[IWM_NVM_SECTION_TYPE_PHY_SKU].data; 2543 2544 return iwm_parse_nvm_data(sc, hw, sw, calib, mac_override, 2545 phy_sku, regulatory); 2546 } 2547 2548 static int 2549 iwm_nvm_init(struct iwm_softc *sc) 2550 { 2551 struct iwm_nvm_section nvm_sections[IWM_NVM_NUM_OF_SECTIONS]; 2552 int i, ret, section; 2553 uint32_t size_read = 0; 2554 uint8_t *nvm_buffer, *temp; 2555 uint16_t len; 2556 2557 memset(nvm_sections, 0, sizeof(nvm_sections)); 2558 2559 if (sc->cfg->nvm_hw_section_num >= IWM_NVM_NUM_OF_SECTIONS) 2560 return EINVAL; 2561 2562 /* load NVM values from nic */ 2563 /* Read From FW NVM */ 2564 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM, "Read from NVM\n"); 2565 2566 nvm_buffer = malloc(sc->cfg->eeprom_size, M_DEVBUF, M_NOWAIT | M_ZERO); 2567 if (!nvm_buffer) 2568 return ENOMEM; 2569 for (section = 0; section < IWM_NVM_NUM_OF_SECTIONS; section++) { 2570 /* we override the constness for initial read */ 2571 ret = iwm_nvm_read_section(sc, section, nvm_buffer, 2572 &len, size_read); 2573 if (ret) 2574 continue; 2575 size_read += len; 2576 temp = malloc(len, M_DEVBUF, M_NOWAIT); 2577 if (!temp) { 2578 ret = ENOMEM; 2579 break; 2580 } 2581 memcpy(temp, nvm_buffer, len); 2582 2583 nvm_sections[section].data = temp; 2584 nvm_sections[section].length = len; 2585 } 2586 if (!size_read) 2587 device_printf(sc->sc_dev, "OTP is blank\n"); 2588 free(nvm_buffer, M_DEVBUF); 2589 2590 sc->nvm_data = iwm_parse_nvm_sections(sc, nvm_sections); 2591 if (!sc->nvm_data) 2592 return EINVAL; 2593 IWM_DPRINTF(sc, IWM_DEBUG_EEPROM | IWM_DEBUG_RESET, 2594 "nvm version = %x\n", sc->nvm_data->nvm_version); 2595 2596 for (i = 0; i < IWM_NVM_NUM_OF_SECTIONS; i++) { 2597 if (nvm_sections[i].data != NULL) 2598 free(nvm_sections[i].data, M_DEVBUF); 2599 } 2600 2601 return 0; 2602 } 2603 2604 static int 2605 iwm_pcie_load_section(struct iwm_softc *sc, uint8_t section_num, 2606 const struct iwm_fw_desc *section) 2607 { 2608 struct iwm_dma_info *dma = &sc->fw_dma; 2609 uint8_t *v_addr; 2610 bus_addr_t p_addr; 2611 uint32_t offset, chunk_sz = MIN(IWM_FH_MEM_TB_MAX_LENGTH, section->len); 2612 int ret = 0; 2613 2614 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2615 "%s: [%d] uCode section being loaded...\n", 2616 __func__, section_num); 2617 2618 v_addr = dma->vaddr; 2619 p_addr = dma->paddr; 2620 2621 for (offset = 0; offset < section->len; offset += chunk_sz) { 2622 uint32_t copy_size, dst_addr; 2623 int extended_addr = FALSE; 2624 2625 copy_size = MIN(chunk_sz, section->len - offset); 2626 dst_addr = section->offset + offset; 2627 2628 if (dst_addr >= IWM_FW_MEM_EXTENDED_START && 2629 dst_addr <= IWM_FW_MEM_EXTENDED_END) 2630 extended_addr = TRUE; 2631 2632 if (extended_addr) 2633 iwm_set_bits_prph(sc, IWM_LMPM_CHICK, 2634 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE); 2635 2636 memcpy(v_addr, (const uint8_t *)section->data + offset, 2637 copy_size); 2638 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 2639 ret = iwm_pcie_load_firmware_chunk(sc, dst_addr, p_addr, 2640 copy_size); 2641 2642 if (extended_addr) 2643 iwm_clear_bits_prph(sc, IWM_LMPM_CHICK, 2644 IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE); 2645 2646 if (ret) { 2647 device_printf(sc->sc_dev, 2648 "%s: Could not load the [%d] uCode section\n", 2649 __func__, section_num); 2650 break; 2651 } 2652 } 2653 2654 return ret; 2655 } 2656 2657 /* 2658 * ucode 2659 */ 2660 static int 2661 iwm_pcie_load_firmware_chunk(struct iwm_softc *sc, uint32_t dst_addr, 2662 bus_addr_t phy_addr, uint32_t byte_cnt) 2663 { 2664 sc->sc_fw_chunk_done = 0; 2665 2666 if (!iwm_nic_lock(sc)) 2667 return EBUSY; 2668 2669 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL), 2670 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 2671 2672 IWM_WRITE(sc, IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(IWM_FH_SRVC_CHNL), 2673 dst_addr); 2674 2675 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL0_REG(IWM_FH_SRVC_CHNL), 2676 phy_addr & IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 2677 2678 IWM_WRITE(sc, IWM_FH_TFDIB_CTRL1_REG(IWM_FH_SRVC_CHNL), 2679 (iwm_get_dma_hi_addr(phy_addr) 2680 << IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 2681 2682 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(IWM_FH_SRVC_CHNL), 2683 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 2684 1 << IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 2685 IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 2686 2687 IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL), 2688 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 2689 IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 2690 IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 2691 2692 iwm_nic_unlock(sc); 2693 2694 /* wait up to 5s for this segment to load */ 2695 msleep(&sc->sc_fw, &sc->sc_mtx, 0, "iwmfw", hz * 5); 2696 2697 if (!sc->sc_fw_chunk_done) { 2698 device_printf(sc->sc_dev, 2699 "fw chunk addr 0x%x len %d failed to load\n", 2700 dst_addr, byte_cnt); 2701 return ETIMEDOUT; 2702 } 2703 2704 return 0; 2705 } 2706 2707 static int 2708 iwm_pcie_load_cpu_sections_8000(struct iwm_softc *sc, 2709 const struct iwm_fw_img *image, int cpu, int *first_ucode_section) 2710 { 2711 int shift_param; 2712 int i, ret = 0, sec_num = 0x1; 2713 uint32_t val, last_read_idx = 0; 2714 2715 if (cpu == 1) { 2716 shift_param = 0; 2717 *first_ucode_section = 0; 2718 } else { 2719 shift_param = 16; 2720 (*first_ucode_section)++; 2721 } 2722 2723 for (i = *first_ucode_section; i < IWM_UCODE_SECTION_MAX; i++) { 2724 last_read_idx = i; 2725 2726 /* 2727 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 2728 * CPU1 to CPU2. 2729 * PAGING_SEPARATOR_SECTION delimiter - separate between 2730 * CPU2 non paged to CPU2 paging sec. 2731 */ 2732 if (!image->sec[i].data || 2733 image->sec[i].offset == IWM_CPU1_CPU2_SEPARATOR_SECTION || 2734 image->sec[i].offset == IWM_PAGING_SEPARATOR_SECTION) { 2735 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2736 "Break since Data not valid or Empty section, sec = %d\n", 2737 i); 2738 break; 2739 } 2740 ret = iwm_pcie_load_section(sc, i, &image->sec[i]); 2741 if (ret) 2742 return ret; 2743 2744 /* Notify the ucode of the loaded section number and status */ 2745 if (iwm_nic_lock(sc)) { 2746 val = IWM_READ(sc, IWM_FH_UCODE_LOAD_STATUS); 2747 val = val | (sec_num << shift_param); 2748 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, val); 2749 sec_num = (sec_num << 1) | 0x1; 2750 iwm_nic_unlock(sc); 2751 } 2752 } 2753 2754 *first_ucode_section = last_read_idx; 2755 2756 iwm_enable_interrupts(sc); 2757 2758 if (iwm_nic_lock(sc)) { 2759 if (cpu == 1) 2760 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFF); 2761 else 2762 IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); 2763 iwm_nic_unlock(sc); 2764 } 2765 2766 return 0; 2767 } 2768 2769 static int 2770 iwm_pcie_load_cpu_sections(struct iwm_softc *sc, 2771 const struct iwm_fw_img *image, int cpu, int *first_ucode_section) 2772 { 2773 int i, ret = 0; 2774 uint32_t last_read_idx = 0; 2775 2776 if (cpu == 1) { 2777 *first_ucode_section = 0; 2778 } else { 2779 (*first_ucode_section)++; 2780 } 2781 2782 for (i = *first_ucode_section; i < IWM_UCODE_SECTION_MAX; i++) { 2783 last_read_idx = i; 2784 2785 /* 2786 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 2787 * CPU1 to CPU2. 2788 * PAGING_SEPARATOR_SECTION delimiter - separate between 2789 * CPU2 non paged to CPU2 paging sec. 2790 */ 2791 if (!image->sec[i].data || 2792 image->sec[i].offset == IWM_CPU1_CPU2_SEPARATOR_SECTION || 2793 image->sec[i].offset == IWM_PAGING_SEPARATOR_SECTION) { 2794 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 2795 "Break since Data not valid or Empty section, sec = %d\n", 2796 i); 2797 break; 2798 } 2799 2800 ret = iwm_pcie_load_section(sc, i, &image->sec[i]); 2801 if (ret) 2802 return ret; 2803 } 2804 2805 *first_ucode_section = last_read_idx; 2806 2807 return 0; 2808 2809 } 2810 2811 static int 2812 iwm_pcie_load_given_ucode(struct iwm_softc *sc, const struct iwm_fw_img *image) 2813 { 2814 int ret = 0; 2815 int first_ucode_section; 2816 2817 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "working with %s CPU\n", 2818 image->is_dual_cpus ? "Dual" : "Single"); 2819 2820 /* load to FW the binary non secured sections of CPU1 */ 2821 ret = iwm_pcie_load_cpu_sections(sc, image, 1, &first_ucode_section); 2822 if (ret) 2823 return ret; 2824 2825 if (image->is_dual_cpus) { 2826 /* set CPU2 header address */ 2827 if (iwm_nic_lock(sc)) { 2828 iwm_write_prph(sc, 2829 IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 2830 IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE); 2831 iwm_nic_unlock(sc); 2832 } 2833 2834 /* load to FW the binary sections of CPU2 */ 2835 ret = iwm_pcie_load_cpu_sections(sc, image, 2, 2836 &first_ucode_section); 2837 if (ret) 2838 return ret; 2839 } 2840 2841 iwm_enable_interrupts(sc); 2842 2843 /* release CPU reset */ 2844 IWM_WRITE(sc, IWM_CSR_RESET, 0); 2845 2846 return 0; 2847 } 2848 2849 int 2850 iwm_pcie_load_given_ucode_8000(struct iwm_softc *sc, 2851 const struct iwm_fw_img *image) 2852 { 2853 int ret = 0; 2854 int first_ucode_section; 2855 2856 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "working with %s CPU\n", 2857 image->is_dual_cpus ? "Dual" : "Single"); 2858 2859 /* configure the ucode to be ready to get the secured image */ 2860 /* release CPU reset */ 2861 if (iwm_nic_lock(sc)) { 2862 iwm_write_prph(sc, IWM_RELEASE_CPU_RESET, 2863 IWM_RELEASE_CPU_RESET_BIT); 2864 iwm_nic_unlock(sc); 2865 } 2866 2867 /* load to FW the binary Secured sections of CPU1 */ 2868 ret = iwm_pcie_load_cpu_sections_8000(sc, image, 1, 2869 &first_ucode_section); 2870 if (ret) 2871 return ret; 2872 2873 /* load to FW the binary sections of CPU2 */ 2874 return iwm_pcie_load_cpu_sections_8000(sc, image, 2, 2875 &first_ucode_section); 2876 } 2877 2878 /* XXX Get rid of this definition */ 2879 static inline void 2880 iwm_enable_fw_load_int(struct iwm_softc *sc) 2881 { 2882 IWM_DPRINTF(sc, IWM_DEBUG_INTR, "Enabling FW load interrupt\n"); 2883 2884 if (!sc->sc_msix) { 2885 sc->sc_intmask = IWM_CSR_INT_BIT_FH_TX; 2886 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 2887 } else { 2888 IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_MASK_AD, 2889 sc->sc_hw_init_mask); 2890 IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_MASK_AD, 2891 ~IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 2892 sc->sc_fh_mask = IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM; 2893 } 2894 } 2895 2896 /* XXX Add proper rfkill support code */ 2897 static int 2898 iwm_start_fw(struct iwm_softc *sc, const struct iwm_fw_img *fw) 2899 { 2900 int ret; 2901 2902 /* This may fail if AMT took ownership of the device */ 2903 if (iwm_prepare_card_hw(sc)) { 2904 device_printf(sc->sc_dev, 2905 "%s: Exit HW not ready\n", __func__); 2906 ret = EIO; 2907 goto out; 2908 } 2909 2910 IWM_WRITE(sc, IWM_CSR_INT, 0xFFFFFFFF); 2911 2912 iwm_disable_interrupts(sc); 2913 2914 /* make sure rfkill handshake bits are cleared */ 2915 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL); 2916 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, 2917 IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 2918 2919 /* clear (again), then enable host interrupts */ 2920 IWM_WRITE(sc, IWM_CSR_INT, 0xFFFFFFFF); 2921 2922 ret = iwm_nic_init(sc); 2923 if (ret) { 2924 device_printf(sc->sc_dev, "%s: Unable to init nic\n", __func__); 2925 goto out; 2926 } 2927 2928 /* 2929 * Now, we load the firmware and don't want to be interrupted, even 2930 * by the RF-Kill interrupt (hence mask all the interrupt besides the 2931 * FH_TX interrupt which is needed to load the firmware). If the 2932 * RF-Kill switch is toggled, we will find out after having loaded 2933 * the firmware and return the proper value to the caller. 2934 */ 2935 iwm_enable_fw_load_int(sc); 2936 2937 /* really make sure rfkill handshake bits are cleared */ 2938 /* maybe we should write a few times more? just to make sure */ 2939 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL); 2940 IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL); 2941 2942 /* Load the given image to the HW */ 2943 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) 2944 ret = iwm_pcie_load_given_ucode_8000(sc, fw); 2945 else 2946 ret = iwm_pcie_load_given_ucode(sc, fw); 2947 2948 /* XXX re-check RF-Kill state */ 2949 2950 out: 2951 return ret; 2952 } 2953 2954 static int 2955 iwm_send_tx_ant_cfg(struct iwm_softc *sc, uint8_t valid_tx_ant) 2956 { 2957 struct iwm_tx_ant_cfg_cmd tx_ant_cmd = { 2958 .valid = htole32(valid_tx_ant), 2959 }; 2960 2961 return iwm_send_cmd_pdu(sc, IWM_TX_ANT_CONFIGURATION_CMD, 2962 IWM_CMD_SYNC, sizeof(tx_ant_cmd), &tx_ant_cmd); 2963 } 2964 2965 /* iwlwifi: mvm/fw.c */ 2966 static int 2967 iwm_send_phy_cfg_cmd(struct iwm_softc *sc) 2968 { 2969 struct iwm_phy_cfg_cmd phy_cfg_cmd; 2970 enum iwm_ucode_type ucode_type = sc->cur_ucode; 2971 2972 /* Set parameters */ 2973 phy_cfg_cmd.phy_cfg = htole32(iwm_get_phy_config(sc)); 2974 phy_cfg_cmd.calib_control.event_trigger = 2975 sc->sc_default_calib[ucode_type].event_trigger; 2976 phy_cfg_cmd.calib_control.flow_trigger = 2977 sc->sc_default_calib[ucode_type].flow_trigger; 2978 2979 IWM_DPRINTF(sc, IWM_DEBUG_CMD | IWM_DEBUG_RESET, 2980 "Sending Phy CFG command: 0x%x\n", phy_cfg_cmd.phy_cfg); 2981 return iwm_send_cmd_pdu(sc, IWM_PHY_CONFIGURATION_CMD, IWM_CMD_SYNC, 2982 sizeof(phy_cfg_cmd), &phy_cfg_cmd); 2983 } 2984 2985 static int 2986 iwm_alive_fn(struct iwm_softc *sc, struct iwm_rx_packet *pkt, void *data) 2987 { 2988 struct iwm_alive_data *alive_data = data; 2989 struct iwm_alive_resp_v3 *palive3; 2990 struct iwm_alive_resp *palive; 2991 struct iwm_umac_alive *umac; 2992 struct iwm_lmac_alive *lmac1; 2993 struct iwm_lmac_alive *lmac2 = NULL; 2994 uint16_t status; 2995 2996 if (iwm_rx_packet_payload_len(pkt) == sizeof(*palive)) { 2997 palive = (void *)pkt->data; 2998 umac = &palive->umac_data; 2999 lmac1 = &palive->lmac_data[0]; 3000 lmac2 = &palive->lmac_data[1]; 3001 status = le16toh(palive->status); 3002 } else { 3003 palive3 = (void *)pkt->data; 3004 umac = &palive3->umac_data; 3005 lmac1 = &palive3->lmac_data; 3006 status = le16toh(palive3->status); 3007 } 3008 3009 sc->error_event_table[0] = le32toh(lmac1->error_event_table_ptr); 3010 if (lmac2) 3011 sc->error_event_table[1] = 3012 le32toh(lmac2->error_event_table_ptr); 3013 sc->log_event_table = le32toh(lmac1->log_event_table_ptr); 3014 sc->umac_error_event_table = le32toh(umac->error_info_addr); 3015 alive_data->scd_base_addr = le32toh(lmac1->scd_base_ptr); 3016 alive_data->valid = status == IWM_ALIVE_STATUS_OK; 3017 if (sc->umac_error_event_table) 3018 sc->support_umac_log = TRUE; 3019 3020 IWM_DPRINTF(sc, IWM_DEBUG_FW, 3021 "Alive ucode status 0x%04x revision 0x%01X 0x%01X\n", 3022 status, lmac1->ver_type, lmac1->ver_subtype); 3023 3024 if (lmac2) 3025 IWM_DPRINTF(sc, IWM_DEBUG_FW, "Alive ucode CDB\n"); 3026 3027 IWM_DPRINTF(sc, IWM_DEBUG_FW, 3028 "UMAC version: Major - 0x%x, Minor - 0x%x\n", 3029 le32toh(umac->umac_major), 3030 le32toh(umac->umac_minor)); 3031 3032 return TRUE; 3033 } 3034 3035 static int 3036 iwm_wait_phy_db_entry(struct iwm_softc *sc, 3037 struct iwm_rx_packet *pkt, void *data) 3038 { 3039 struct iwm_phy_db *phy_db = data; 3040 3041 if (pkt->hdr.code != IWM_CALIB_RES_NOTIF_PHY_DB) { 3042 if(pkt->hdr.code != IWM_INIT_COMPLETE_NOTIF) { 3043 device_printf(sc->sc_dev, "%s: Unexpected cmd: %d\n", 3044 __func__, pkt->hdr.code); 3045 } 3046 return TRUE; 3047 } 3048 3049 if (iwm_phy_db_set_section(phy_db, pkt)) { 3050 device_printf(sc->sc_dev, 3051 "%s: iwm_phy_db_set_section failed\n", __func__); 3052 } 3053 3054 return FALSE; 3055 } 3056 3057 static int 3058 iwm_load_ucode_wait_alive(struct iwm_softc *sc, 3059 enum iwm_ucode_type ucode_type) 3060 { 3061 struct iwm_notification_wait alive_wait; 3062 struct iwm_alive_data alive_data; 3063 const struct iwm_fw_img *fw; 3064 enum iwm_ucode_type old_type = sc->cur_ucode; 3065 int error; 3066 static const uint16_t alive_cmd[] = { IWM_ALIVE }; 3067 3068 fw = &sc->sc_fw.img[ucode_type]; 3069 sc->cur_ucode = ucode_type; 3070 sc->ucode_loaded = FALSE; 3071 3072 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_DQA_SUPPORT)) 3073 sc->cmdqid = IWM_DQA_CMD_QUEUE; 3074 else 3075 sc->cmdqid = IWM_CMD_QUEUE; 3076 3077 memset(&alive_data, 0, sizeof(alive_data)); 3078 iwm_init_notification_wait(sc->sc_notif_wait, &alive_wait, 3079 alive_cmd, nitems(alive_cmd), 3080 iwm_alive_fn, &alive_data); 3081 3082 error = iwm_start_fw(sc, fw); 3083 if (error) { 3084 device_printf(sc->sc_dev, "iwm_start_fw: failed %d\n", error); 3085 sc->cur_ucode = old_type; 3086 iwm_remove_notification(sc->sc_notif_wait, &alive_wait); 3087 return error; 3088 } 3089 3090 /* 3091 * Some things may run in the background now, but we 3092 * just wait for the ALIVE notification here. 3093 */ 3094 IWM_UNLOCK(sc); 3095 error = iwm_wait_notification(sc->sc_notif_wait, &alive_wait, 3096 IWM_UCODE_ALIVE_TIMEOUT); 3097 IWM_LOCK(sc); 3098 if (error) { 3099 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) { 3100 uint32_t a = 0x5a5a5a5a, b = 0x5a5a5a5a; 3101 if (iwm_nic_lock(sc)) { 3102 a = iwm_read_prph(sc, IWM_SB_CPU_1_STATUS); 3103 b = iwm_read_prph(sc, IWM_SB_CPU_2_STATUS); 3104 iwm_nic_unlock(sc); 3105 } 3106 device_printf(sc->sc_dev, 3107 "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n", 3108 a, b); 3109 } 3110 sc->cur_ucode = old_type; 3111 return error; 3112 } 3113 3114 if (!alive_data.valid) { 3115 device_printf(sc->sc_dev, "%s: Loaded ucode is not valid\n", 3116 __func__); 3117 sc->cur_ucode = old_type; 3118 return EIO; 3119 } 3120 3121 iwm_trans_pcie_fw_alive(sc, alive_data.scd_base_addr); 3122 3123 /* 3124 * configure and operate fw paging mechanism. 3125 * driver configures the paging flow only once, CPU2 paging image 3126 * included in the IWM_UCODE_INIT image. 3127 */ 3128 if (fw->paging_mem_size) { 3129 error = iwm_save_fw_paging(sc, fw); 3130 if (error) { 3131 device_printf(sc->sc_dev, 3132 "%s: failed to save the FW paging image\n", 3133 __func__); 3134 return error; 3135 } 3136 3137 error = iwm_send_paging_cmd(sc, fw); 3138 if (error) { 3139 device_printf(sc->sc_dev, 3140 "%s: failed to send the paging cmd\n", __func__); 3141 iwm_free_fw_paging(sc); 3142 return error; 3143 } 3144 } 3145 3146 if (!error) 3147 sc->ucode_loaded = TRUE; 3148 return error; 3149 } 3150 3151 /* 3152 * mvm misc bits 3153 */ 3154 3155 /* 3156 * follows iwlwifi/fw.c 3157 */ 3158 static int 3159 iwm_run_init_ucode(struct iwm_softc *sc, int justnvm) 3160 { 3161 struct iwm_notification_wait calib_wait; 3162 static const uint16_t init_complete[] = { 3163 IWM_INIT_COMPLETE_NOTIF, 3164 IWM_CALIB_RES_NOTIF_PHY_DB 3165 }; 3166 int ret; 3167 3168 /* do not operate with rfkill switch turned on */ 3169 if ((sc->sc_flags & IWM_FLAG_RFKILL) && !justnvm) { 3170 device_printf(sc->sc_dev, 3171 "radio is disabled by hardware switch\n"); 3172 return EPERM; 3173 } 3174 3175 iwm_init_notification_wait(sc->sc_notif_wait, 3176 &calib_wait, 3177 init_complete, 3178 nitems(init_complete), 3179 iwm_wait_phy_db_entry, 3180 sc->sc_phy_db); 3181 3182 /* Will also start the device */ 3183 ret = iwm_load_ucode_wait_alive(sc, IWM_UCODE_INIT); 3184 if (ret) { 3185 device_printf(sc->sc_dev, "Failed to start INIT ucode: %d\n", 3186 ret); 3187 goto error; 3188 } 3189 3190 if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) { 3191 ret = iwm_send_bt_init_conf(sc); 3192 if (ret) { 3193 device_printf(sc->sc_dev, 3194 "failed to send bt coex configuration: %d\n", ret); 3195 goto error; 3196 } 3197 } 3198 3199 if (justnvm) { 3200 /* Read nvm */ 3201 ret = iwm_nvm_init(sc); 3202 if (ret) { 3203 device_printf(sc->sc_dev, "failed to read nvm\n"); 3204 goto error; 3205 } 3206 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, sc->nvm_data->hw_addr); 3207 goto error; 3208 } 3209 3210 /* Send TX valid antennas before triggering calibrations */ 3211 ret = iwm_send_tx_ant_cfg(sc, iwm_get_valid_tx_ant(sc)); 3212 if (ret) { 3213 device_printf(sc->sc_dev, 3214 "failed to send antennas before calibration: %d\n", ret); 3215 goto error; 3216 } 3217 3218 /* 3219 * Send phy configurations command to init uCode 3220 * to start the 16.0 uCode init image internal calibrations. 3221 */ 3222 ret = iwm_send_phy_cfg_cmd(sc); 3223 if (ret) { 3224 device_printf(sc->sc_dev, 3225 "%s: Failed to run INIT calibrations: %d\n", 3226 __func__, ret); 3227 goto error; 3228 } 3229 3230 /* 3231 * Nothing to do but wait for the init complete notification 3232 * from the firmware. 3233 */ 3234 IWM_UNLOCK(sc); 3235 ret = iwm_wait_notification(sc->sc_notif_wait, &calib_wait, 3236 IWM_UCODE_CALIB_TIMEOUT); 3237 IWM_LOCK(sc); 3238 3239 3240 goto out; 3241 3242 error: 3243 iwm_remove_notification(sc->sc_notif_wait, &calib_wait); 3244 out: 3245 return ret; 3246 } 3247 3248 static int 3249 iwm_config_ltr(struct iwm_softc *sc) 3250 { 3251 struct iwm_ltr_config_cmd cmd = { 3252 .flags = htole32(IWM_LTR_CFG_FLAG_FEATURE_ENABLE), 3253 }; 3254 3255 if (!sc->sc_ltr_enabled) 3256 return 0; 3257 3258 return iwm_send_cmd_pdu(sc, IWM_LTR_CONFIG, 0, sizeof(cmd), &cmd); 3259 } 3260 3261 /* 3262 * receive side 3263 */ 3264 3265 /* (re)stock rx ring, called at init-time and at runtime */ 3266 static int 3267 iwm_rx_addbuf(struct iwm_softc *sc, int size, int idx) 3268 { 3269 struct iwm_rx_ring *ring = &sc->rxq; 3270 struct iwm_rx_data *data = &ring->data[idx]; 3271 struct mbuf *m; 3272 bus_dmamap_t dmamap; 3273 bus_dma_segment_t seg; 3274 int nsegs, error; 3275 3276 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWM_RBUF_SIZE); 3277 if (m == NULL) 3278 return ENOBUFS; 3279 3280 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3281 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, ring->spare_map, m, 3282 &seg, &nsegs, BUS_DMA_NOWAIT); 3283 if (error != 0) { 3284 device_printf(sc->sc_dev, 3285 "%s: can't map mbuf, error %d\n", __func__, error); 3286 m_freem(m); 3287 return error; 3288 } 3289 3290 if (data->m != NULL) 3291 bus_dmamap_unload(ring->data_dmat, data->map); 3292 3293 /* Swap ring->spare_map with data->map */ 3294 dmamap = data->map; 3295 data->map = ring->spare_map; 3296 ring->spare_map = dmamap; 3297 3298 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREREAD); 3299 data->m = m; 3300 3301 /* Update RX descriptor. */ 3302 KASSERT((seg.ds_addr & 255) == 0, ("seg.ds_addr not aligned")); 3303 if (sc->cfg->mqrx_supported) 3304 ((uint64_t *)ring->desc)[idx] = htole64(seg.ds_addr); 3305 else 3306 ((uint32_t *)ring->desc)[idx] = htole32(seg.ds_addr >> 8); 3307 bus_dmamap_sync(ring->free_desc_dma.tag, ring->free_desc_dma.map, 3308 BUS_DMASYNC_PREWRITE); 3309 3310 return 0; 3311 } 3312 3313 static void 3314 iwm_rx_rx_phy_cmd(struct iwm_softc *sc, struct iwm_rx_packet *pkt) 3315 { 3316 struct iwm_rx_phy_info *phy_info = (void *)pkt->data; 3317 3318 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "received PHY stats\n"); 3319 3320 memcpy(&sc->sc_last_phy_info, phy_info, sizeof(sc->sc_last_phy_info)); 3321 } 3322 3323 /* 3324 * Retrieve the average noise (in dBm) among receivers. 3325 */ 3326 static int 3327 iwm_get_noise(struct iwm_softc *sc, 3328 const struct iwm_statistics_rx_non_phy *stats) 3329 { 3330 int i, noise; 3331 #ifdef IWM_DEBUG 3332 int nbant, total; 3333 #else 3334 int nbant __unused, total __unused; 3335 #endif 3336 3337 total = nbant = noise = 0; 3338 for (i = 0; i < 3; i++) { 3339 noise = le32toh(stats->beacon_silence_rssi[i]) & 0xff; 3340 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "%s: i=%d, noise=%d\n", 3341 __func__, 3342 i, 3343 noise); 3344 3345 if (noise) { 3346 total += noise; 3347 nbant++; 3348 } 3349 } 3350 3351 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "%s: nbant=%d, total=%d\n", 3352 __func__, nbant, total); 3353 #if 0 3354 /* There should be at least one antenna but check anyway. */ 3355 return (nbant == 0) ? -127 : (total / nbant) - 107; 3356 #else 3357 /* For now, just hard-code it to -96 to be safe */ 3358 return (-96); 3359 #endif 3360 } 3361 3362 static void 3363 iwm_handle_rx_statistics(struct iwm_softc *sc, struct iwm_rx_packet *pkt) 3364 { 3365 struct iwm_notif_statistics *stats = (void *)&pkt->data; 3366 3367 memcpy(&sc->sc_stats, stats, sizeof(sc->sc_stats)); 3368 sc->sc_noise = iwm_get_noise(sc, &stats->rx.general); 3369 } 3370 3371 /* iwlwifi: mvm/rx.c */ 3372 /* 3373 * iwm_get_signal_strength - use new rx PHY INFO API 3374 * values are reported by the fw as positive values - need to negate 3375 * to obtain their dBM. Account for missing antennas by replacing 0 3376 * values by -256dBm: practically 0 power and a non-feasible 8 bit value. 3377 */ 3378 static int 3379 iwm_rx_get_signal_strength(struct iwm_softc *sc, 3380 struct iwm_rx_phy_info *phy_info) 3381 { 3382 int energy_a, energy_b, energy_c, max_energy; 3383 uint32_t val; 3384 3385 val = le32toh(phy_info->non_cfg_phy[IWM_RX_INFO_ENERGY_ANT_ABC_IDX]); 3386 energy_a = (val & IWM_RX_INFO_ENERGY_ANT_A_MSK) >> 3387 IWM_RX_INFO_ENERGY_ANT_A_POS; 3388 energy_a = energy_a ? -energy_a : -256; 3389 energy_b = (val & IWM_RX_INFO_ENERGY_ANT_B_MSK) >> 3390 IWM_RX_INFO_ENERGY_ANT_B_POS; 3391 energy_b = energy_b ? -energy_b : -256; 3392 energy_c = (val & IWM_RX_INFO_ENERGY_ANT_C_MSK) >> 3393 IWM_RX_INFO_ENERGY_ANT_C_POS; 3394 energy_c = energy_c ? -energy_c : -256; 3395 max_energy = MAX(energy_a, energy_b); 3396 max_energy = MAX(max_energy, energy_c); 3397 3398 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3399 "energy In A %d B %d C %d , and max %d\n", 3400 energy_a, energy_b, energy_c, max_energy); 3401 3402 return max_energy; 3403 } 3404 3405 static int 3406 iwm_rxmq_get_signal_strength(struct iwm_softc *sc, 3407 struct iwm_rx_mpdu_desc *desc) 3408 { 3409 int energy_a, energy_b; 3410 3411 energy_a = desc->v1.energy_a; 3412 energy_b = desc->v1.energy_b; 3413 energy_a = energy_a ? -energy_a : -256; 3414 energy_b = energy_b ? -energy_b : -256; 3415 return MAX(energy_a, energy_b); 3416 } 3417 3418 /* 3419 * iwm_rx_rx_mpdu - IWM_REPLY_RX_MPDU_CMD handler 3420 * 3421 * Handles the actual data of the Rx packet from the fw 3422 */ 3423 static bool 3424 iwm_rx_rx_mpdu(struct iwm_softc *sc, struct mbuf *m, uint32_t offset, 3425 bool stolen) 3426 { 3427 struct ieee80211com *ic = &sc->sc_ic; 3428 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3429 struct ieee80211_rx_stats rxs; 3430 struct iwm_rx_phy_info *phy_info; 3431 struct iwm_rx_mpdu_res_start *rx_res; 3432 struct iwm_rx_packet *pkt = mtodoff(m, struct iwm_rx_packet *, offset); 3433 uint32_t len; 3434 uint32_t rx_pkt_status; 3435 int rssi; 3436 3437 phy_info = &sc->sc_last_phy_info; 3438 rx_res = (struct iwm_rx_mpdu_res_start *)pkt->data; 3439 len = le16toh(rx_res->byte_count); 3440 rx_pkt_status = le32toh(*(uint32_t *)(pkt->data + sizeof(*rx_res) + len)); 3441 3442 if (__predict_false(phy_info->cfg_phy_cnt > 20)) { 3443 device_printf(sc->sc_dev, 3444 "dsp size out of range [0,20]: %d\n", 3445 phy_info->cfg_phy_cnt); 3446 return false; 3447 } 3448 3449 if (!(rx_pkt_status & IWM_RX_MPDU_RES_STATUS_CRC_OK) || 3450 !(rx_pkt_status & IWM_RX_MPDU_RES_STATUS_OVERRUN_OK)) { 3451 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3452 "Bad CRC or FIFO: 0x%08X.\n", rx_pkt_status); 3453 return false; 3454 } 3455 3456 rssi = iwm_rx_get_signal_strength(sc, phy_info); 3457 3458 /* Map it to relative value */ 3459 rssi = rssi - sc->sc_noise; 3460 3461 /* replenish ring for the buffer we're going to feed to the sharks */ 3462 if (!stolen && iwm_rx_addbuf(sc, IWM_RBUF_SIZE, sc->rxq.cur) != 0) { 3463 device_printf(sc->sc_dev, "%s: unable to add more buffers\n", 3464 __func__); 3465 return false; 3466 } 3467 3468 m->m_data = pkt->data + sizeof(*rx_res); 3469 m->m_pkthdr.len = m->m_len = len; 3470 3471 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3472 "%s: rssi=%d, noise=%d\n", __func__, rssi, sc->sc_noise); 3473 3474 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3475 "%s: phy_info: channel=%d, flags=0x%08x\n", 3476 __func__, 3477 le16toh(phy_info->channel), 3478 le16toh(phy_info->phy_flags)); 3479 3480 /* 3481 * Populate an RX state struct with the provided information. 3482 */ 3483 bzero(&rxs, sizeof(rxs)); 3484 rxs.r_flags |= IEEE80211_R_IEEE | IEEE80211_R_FREQ; 3485 rxs.r_flags |= IEEE80211_R_BAND; 3486 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI; 3487 rxs.c_ieee = le16toh(phy_info->channel); 3488 if (le16toh(phy_info->phy_flags & IWM_RX_RES_PHY_FLAGS_BAND_24)) { 3489 rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, IEEE80211_CHAN_2GHZ); 3490 rxs.c_band = IEEE80211_CHAN_2GHZ; 3491 } else { 3492 rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, IEEE80211_CHAN_5GHZ); 3493 rxs.c_band = IEEE80211_CHAN_5GHZ; 3494 } 3495 3496 /* rssi is in 1/2db units */ 3497 rxs.c_rssi = rssi * 2; 3498 rxs.c_nf = sc->sc_noise; 3499 if (ieee80211_add_rx_params(m, &rxs) == 0) 3500 return false; 3501 3502 if (ieee80211_radiotap_active_vap(vap)) { 3503 struct iwm_rx_radiotap_header *tap = &sc->sc_rxtap; 3504 3505 tap->wr_flags = 0; 3506 if (phy_info->phy_flags & htole16(IWM_PHY_INFO_FLAG_SHPREAMBLE)) 3507 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3508 tap->wr_chan_freq = htole16(rxs.c_freq); 3509 /* XXX only if ic->ic_curchan->ic_ieee == rxs.c_ieee */ 3510 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 3511 tap->wr_dbm_antsignal = (int8_t)rssi; 3512 tap->wr_dbm_antnoise = (int8_t)sc->sc_noise; 3513 tap->wr_tsft = phy_info->system_timestamp; 3514 switch (phy_info->rate) { 3515 /* CCK rates. */ 3516 case 10: tap->wr_rate = 2; break; 3517 case 20: tap->wr_rate = 4; break; 3518 case 55: tap->wr_rate = 11; break; 3519 case 110: tap->wr_rate = 22; break; 3520 /* OFDM rates. */ 3521 case 0xd: tap->wr_rate = 12; break; 3522 case 0xf: tap->wr_rate = 18; break; 3523 case 0x5: tap->wr_rate = 24; break; 3524 case 0x7: tap->wr_rate = 36; break; 3525 case 0x9: tap->wr_rate = 48; break; 3526 case 0xb: tap->wr_rate = 72; break; 3527 case 0x1: tap->wr_rate = 96; break; 3528 case 0x3: tap->wr_rate = 108; break; 3529 /* Unknown rate: should not happen. */ 3530 default: tap->wr_rate = 0; 3531 } 3532 } 3533 3534 return true; 3535 } 3536 3537 static bool 3538 iwm_rx_mpdu_mq(struct iwm_softc *sc, struct mbuf *m, uint32_t offset, 3539 bool stolen) 3540 { 3541 struct ieee80211com *ic = &sc->sc_ic; 3542 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3543 struct ieee80211_frame *wh; 3544 struct ieee80211_rx_stats rxs; 3545 struct iwm_rx_mpdu_desc *desc; 3546 struct iwm_rx_packet *pkt; 3547 int rssi; 3548 uint32_t hdrlen, len, rate_n_flags; 3549 uint16_t phy_info; 3550 uint8_t channel; 3551 3552 pkt = mtodo(m, offset); 3553 desc = (void *)pkt->data; 3554 3555 if (!(desc->status & htole16(IWM_RX_MPDU_RES_STATUS_CRC_OK)) || 3556 !(desc->status & htole16(IWM_RX_MPDU_RES_STATUS_OVERRUN_OK))) { 3557 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3558 "Bad CRC or FIFO: 0x%08X.\n", desc->status); 3559 return false; 3560 } 3561 3562 channel = desc->v1.channel; 3563 len = le16toh(desc->mpdu_len); 3564 phy_info = le16toh(desc->phy_info); 3565 rate_n_flags = desc->v1.rate_n_flags; 3566 3567 wh = mtodo(m, sizeof(*desc)); 3568 m->m_data = pkt->data + sizeof(*desc); 3569 m->m_pkthdr.len = m->m_len = len; 3570 m->m_len = len; 3571 3572 /* Account for padding following the frame header. */ 3573 if ((desc->mac_flags2 & IWM_RX_MPDU_MFLG2_PAD)) { 3574 hdrlen = ieee80211_anyhdrsize(wh); 3575 memmove(mtodo(m, 2), mtodo(m, 0), hdrlen); 3576 m->m_data = mtodo(m, 2); 3577 wh = mtod(m, struct ieee80211_frame *); 3578 } 3579 3580 /* Map it to relative value */ 3581 rssi = iwm_rxmq_get_signal_strength(sc, desc); 3582 rssi = rssi - sc->sc_noise; 3583 3584 /* replenish ring for the buffer we're going to feed to the sharks */ 3585 if (!stolen && iwm_rx_addbuf(sc, IWM_RBUF_SIZE, sc->rxq.cur) != 0) { 3586 device_printf(sc->sc_dev, "%s: unable to add more buffers\n", 3587 __func__); 3588 return false; 3589 } 3590 3591 IWM_DPRINTF(sc, IWM_DEBUG_RECV, 3592 "%s: rssi=%d, noise=%d\n", __func__, rssi, sc->sc_noise); 3593 3594 /* 3595 * Populate an RX state struct with the provided information. 3596 */ 3597 bzero(&rxs, sizeof(rxs)); 3598 rxs.r_flags |= IEEE80211_R_IEEE | IEEE80211_R_FREQ; 3599 rxs.r_flags |= IEEE80211_R_BAND; 3600 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI; 3601 rxs.c_ieee = channel; 3602 rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, 3603 channel <= 14 ? IEEE80211_CHAN_2GHZ : IEEE80211_CHAN_5GHZ); 3604 rxs.c_band = channel <= 14 ? IEEE80211_CHAN_2GHZ : IEEE80211_CHAN_5GHZ; 3605 3606 /* rssi is in 1/2db units */ 3607 rxs.c_rssi = rssi * 2; 3608 rxs.c_nf = sc->sc_noise; 3609 if (ieee80211_add_rx_params(m, &rxs) == 0) 3610 return false; 3611 3612 if (ieee80211_radiotap_active_vap(vap)) { 3613 struct iwm_rx_radiotap_header *tap = &sc->sc_rxtap; 3614 3615 tap->wr_flags = 0; 3616 if ((phy_info & IWM_RX_MPDU_PHY_SHORT_PREAMBLE) != 0) 3617 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3618 tap->wr_chan_freq = htole16(rxs.c_freq); 3619 /* XXX only if ic->ic_curchan->ic_ieee == rxs.c_ieee */ 3620 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 3621 tap->wr_dbm_antsignal = (int8_t)rssi; 3622 tap->wr_dbm_antnoise = (int8_t)sc->sc_noise; 3623 tap->wr_tsft = desc->v1.gp2_on_air_rise; 3624 switch ((rate_n_flags & 0xff)) { 3625 /* CCK rates. */ 3626 case 10: tap->wr_rate = 2; break; 3627 case 20: tap->wr_rate = 4; break; 3628 case 55: tap->wr_rate = 11; break; 3629 case 110: tap->wr_rate = 22; break; 3630 /* OFDM rates. */ 3631 case 0xd: tap->wr_rate = 12; break; 3632 case 0xf: tap->wr_rate = 18; break; 3633 case 0x5: tap->wr_rate = 24; break; 3634 case 0x7: tap->wr_rate = 36; break; 3635 case 0x9: tap->wr_rate = 48; break; 3636 case 0xb: tap->wr_rate = 72; break; 3637 case 0x1: tap->wr_rate = 96; break; 3638 case 0x3: tap->wr_rate = 108; break; 3639 /* Unknown rate: should not happen. */ 3640 default: tap->wr_rate = 0; 3641 } 3642 } 3643 3644 return true; 3645 } 3646 3647 static bool 3648 iwm_rx_mpdu(struct iwm_softc *sc, struct mbuf *m, uint32_t offset, 3649 bool stolen) 3650 { 3651 struct ieee80211com *ic; 3652 struct ieee80211_frame *wh; 3653 struct ieee80211_node *ni; 3654 bool ret; 3655 3656 ic = &sc->sc_ic; 3657 3658 ret = sc->cfg->mqrx_supported ? 3659 iwm_rx_mpdu_mq(sc, m, offset, stolen) : 3660 iwm_rx_rx_mpdu(sc, m, offset, stolen); 3661 if (!ret) { 3662 counter_u64_add(ic->ic_ierrors, 1); 3663 return (ret); 3664 } 3665 3666 wh = mtod(m, struct ieee80211_frame *); 3667 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3668 3669 IWM_UNLOCK(sc); 3670 if (ni != NULL) { 3671 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "input m %p\n", m); 3672 ieee80211_input_mimo(ni, m); 3673 ieee80211_free_node(ni); 3674 } else { 3675 IWM_DPRINTF(sc, IWM_DEBUG_RECV, "inputall m %p\n", m); 3676 ieee80211_input_mimo_all(ic, m); 3677 } 3678 IWM_LOCK(sc); 3679 3680 return true; 3681 } 3682 3683 static int 3684 iwm_rx_tx_cmd_single(struct iwm_softc *sc, struct iwm_rx_packet *pkt, 3685 struct iwm_node *in) 3686 { 3687 struct iwm_tx_resp *tx_resp = (void *)pkt->data; 3688 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 3689 struct ieee80211_node *ni = &in->in_ni; 3690 struct ieee80211vap *vap = ni->ni_vap; 3691 int status = le16toh(tx_resp->status.status) & IWM_TX_STATUS_MSK; 3692 int new_rate, cur_rate; 3693 boolean_t rate_matched; 3694 uint8_t tx_resp_rate; 3695 3696 KASSERT(tx_resp->frame_count == 1, ("too many frames")); 3697 3698 /* Update rate control statistics. */ 3699 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, "%s: status=0x%04x, seq=%d, fc=%d, btc=%d, frts=%d, ff=%d, irate=%08x, wmt=%d\n", 3700 __func__, 3701 (int) le16toh(tx_resp->status.status), 3702 (int) le16toh(tx_resp->status.sequence), 3703 tx_resp->frame_count, 3704 tx_resp->bt_kill_count, 3705 tx_resp->failure_rts, 3706 tx_resp->failure_frame, 3707 le32toh(tx_resp->initial_rate), 3708 (int) le16toh(tx_resp->wireless_media_time)); 3709 3710 cur_rate = ieee80211_node_get_txrate_dot11rate(vap->iv_bss); 3711 tx_resp_rate = iwm_rate_from_ucode_rate(le32toh(tx_resp->initial_rate)); 3712 3713 /* For rate control, ignore frames sent at different initial rate */ 3714 rate_matched = (tx_resp_rate != 0 && tx_resp_rate == cur_rate); 3715 3716 if (tx_resp_rate != 0 && cur_rate != 0 && !rate_matched) { 3717 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3718 "tx_resp_rate doesn't match ni_txrate (tx_resp_rate=%u " 3719 "ni_txrate=%d)\n", tx_resp_rate, cur_rate); 3720 } 3721 3722 txs->flags = IEEE80211_RATECTL_STATUS_SHORT_RETRY | 3723 IEEE80211_RATECTL_STATUS_LONG_RETRY; 3724 txs->short_retries = tx_resp->failure_rts; 3725 txs->long_retries = tx_resp->failure_frame; 3726 if (status != IWM_TX_STATUS_SUCCESS && 3727 status != IWM_TX_STATUS_DIRECT_DONE) { 3728 switch (status) { 3729 case IWM_TX_STATUS_FAIL_SHORT_LIMIT: 3730 txs->status = IEEE80211_RATECTL_TX_FAIL_SHORT; 3731 break; 3732 case IWM_TX_STATUS_FAIL_LONG_LIMIT: 3733 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG; 3734 break; 3735 case IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 3736 txs->status = IEEE80211_RATECTL_TX_FAIL_EXPIRED; 3737 break; 3738 default: 3739 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3740 break; 3741 } 3742 } else { 3743 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 3744 } 3745 3746 if (rate_matched) { 3747 ieee80211_ratectl_tx_complete(ni, txs); 3748 3749 ieee80211_ratectl_rate(vap->iv_bss, NULL, 0); 3750 new_rate = ieee80211_node_get_txrate_dot11rate(vap->iv_bss); 3751 if (new_rate != 0 && new_rate != cur_rate) { 3752 struct iwm_node *in = IWM_NODE(vap->iv_bss); 3753 iwm_setrates(sc, in, new_rate); 3754 iwm_send_lq_cmd(sc, &in->in_lq, FALSE); 3755 } 3756 } 3757 3758 return (txs->status != IEEE80211_RATECTL_TX_SUCCESS); 3759 } 3760 3761 static void 3762 iwm_rx_tx_cmd(struct iwm_softc *sc, struct iwm_rx_packet *pkt) 3763 { 3764 struct iwm_cmd_header *cmd_hdr; 3765 struct iwm_tx_ring *ring; 3766 struct iwm_tx_data *txd; 3767 struct iwm_node *in; 3768 struct mbuf *m; 3769 int idx, qid, qmsk, status; 3770 3771 cmd_hdr = &pkt->hdr; 3772 idx = cmd_hdr->idx; 3773 qid = cmd_hdr->qid; 3774 3775 ring = &sc->txq[qid]; 3776 txd = &ring->data[idx]; 3777 in = txd->in; 3778 m = txd->m; 3779 3780 KASSERT(txd->done == 0, ("txd not done")); 3781 KASSERT(txd->in != NULL, ("txd without node")); 3782 KASSERT(txd->m != NULL, ("txd without mbuf")); 3783 3784 sc->sc_tx_timer = 0; 3785 3786 status = iwm_rx_tx_cmd_single(sc, pkt, in); 3787 3788 /* Unmap and free mbuf. */ 3789 bus_dmamap_sync(ring->data_dmat, txd->map, BUS_DMASYNC_POSTWRITE); 3790 bus_dmamap_unload(ring->data_dmat, txd->map); 3791 3792 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 3793 "free txd %p, in %p\n", txd, txd->in); 3794 txd->done = 1; 3795 txd->m = NULL; 3796 txd->in = NULL; 3797 3798 ieee80211_tx_complete(&in->in_ni, m, status); 3799 3800 qmsk = 1 << qid; 3801 if (--ring->queued < IWM_TX_RING_LOMARK && (sc->qfullmsk & qmsk) != 0) { 3802 sc->qfullmsk &= ~qmsk; 3803 if (sc->qfullmsk == 0) 3804 iwm_start(sc); 3805 } 3806 } 3807 3808 /* 3809 * transmit side 3810 */ 3811 3812 /* 3813 * Process a "command done" firmware notification. This is where we wakeup 3814 * processes waiting for a synchronous command completion. 3815 * from if_iwn 3816 */ 3817 static void 3818 iwm_cmd_done(struct iwm_softc *sc, struct iwm_rx_packet *pkt) 3819 { 3820 struct iwm_tx_ring *ring = &sc->txq[sc->cmdqid]; 3821 struct iwm_tx_data *data; 3822 3823 if (pkt->hdr.qid != sc->cmdqid) { 3824 return; /* Not a command ack. */ 3825 } 3826 3827 /* XXX wide commands? */ 3828 IWM_DPRINTF(sc, IWM_DEBUG_CMD, 3829 "cmd notification type 0x%x qid %d idx %d\n", 3830 pkt->hdr.code, pkt->hdr.qid, pkt->hdr.idx); 3831 3832 data = &ring->data[pkt->hdr.idx]; 3833 3834 /* If the command was mapped in an mbuf, free it. */ 3835 if (data->m != NULL) { 3836 bus_dmamap_sync(ring->data_dmat, data->map, 3837 BUS_DMASYNC_POSTWRITE); 3838 bus_dmamap_unload(ring->data_dmat, data->map); 3839 m_freem(data->m); 3840 data->m = NULL; 3841 } 3842 wakeup(&ring->desc[pkt->hdr.idx]); 3843 3844 if (((pkt->hdr.idx + ring->queued) % IWM_TX_RING_COUNT) != ring->cur) { 3845 device_printf(sc->sc_dev, 3846 "%s: Some HCMDs skipped?: idx=%d queued=%d cur=%d\n", 3847 __func__, pkt->hdr.idx, ring->queued, ring->cur); 3848 /* XXX call iwm_force_nmi() */ 3849 } 3850 3851 KASSERT(ring->queued > 0, ("ring->queued is empty?")); 3852 ring->queued--; 3853 if (ring->queued == 0) 3854 iwm_pcie_clear_cmd_in_flight(sc); 3855 } 3856 3857 #if 0 3858 /* 3859 * necessary only for block ack mode 3860 */ 3861 void 3862 iwm_update_sched(struct iwm_softc *sc, int qid, int idx, uint8_t sta_id, 3863 uint16_t len) 3864 { 3865 struct iwm_agn_scd_bc_tbl *scd_bc_tbl; 3866 uint16_t w_val; 3867 3868 scd_bc_tbl = sc->sched_dma.vaddr; 3869 3870 len += 8; /* magic numbers came naturally from paris */ 3871 len = roundup(len, 4) / 4; 3872 3873 w_val = htole16(sta_id << 12 | len); 3874 3875 /* Update TX scheduler. */ 3876 scd_bc_tbl[qid].tfd_offset[idx] = w_val; 3877 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3878 BUS_DMASYNC_PREWRITE); 3879 3880 /* I really wonder what this is ?!? */ 3881 if (idx < IWM_TFD_QUEUE_SIZE_BC_DUP) { 3882 scd_bc_tbl[qid].tfd_offset[IWM_TFD_QUEUE_SIZE_MAX + idx] = w_val; 3883 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 3884 BUS_DMASYNC_PREWRITE); 3885 } 3886 } 3887 #endif 3888 3889 static int 3890 iwm_tx_rateidx_global_lookup(struct iwm_softc *sc, uint8_t rate) 3891 { 3892 int i; 3893 3894 for (i = 0; i < nitems(iwm_rates); i++) { 3895 if (iwm_rates[i].rate == rate) 3896 return (i); 3897 } 3898 /* XXX error? */ 3899 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE, 3900 "%s: couldn't find an entry for rate=%d\n", 3901 __func__, 3902 rate); 3903 return (0); 3904 } 3905 3906 /* 3907 * Fill in the rate related information for a transmit command. 3908 */ 3909 static const struct iwm_rate * 3910 iwm_tx_fill_cmd(struct iwm_softc *sc, struct iwm_node *in, 3911 struct mbuf *m, struct iwm_tx_cmd *tx) 3912 { 3913 struct ieee80211_node *ni = &in->in_ni; 3914 struct ieee80211_frame *wh; 3915 const struct ieee80211_txparam *tp = ni->ni_txparms; 3916 const struct iwm_rate *rinfo; 3917 int type; 3918 int ridx, rate_flags; 3919 3920 wh = mtod(m, struct ieee80211_frame *); 3921 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3922 3923 tx->rts_retry_limit = IWM_RTS_DFAULT_RETRY_LIMIT; 3924 tx->data_retry_limit = IWM_DEFAULT_TX_RETRY; 3925 3926 if (type == IEEE80211_FC0_TYPE_MGT || 3927 type == IEEE80211_FC0_TYPE_CTL || 3928 (m->m_flags & M_EAPOL) != 0) { 3929 ridx = iwm_tx_rateidx_global_lookup(sc, tp->mgmtrate); 3930 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3931 "%s: MGT (%d)\n", __func__, tp->mgmtrate); 3932 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3933 ridx = iwm_tx_rateidx_global_lookup(sc, tp->mcastrate); 3934 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3935 "%s: MCAST (%d)\n", __func__, tp->mcastrate); 3936 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 3937 ridx = iwm_tx_rateidx_global_lookup(sc, tp->ucastrate); 3938 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 3939 "%s: FIXED_RATE (%d)\n", __func__, tp->ucastrate); 3940 } else { 3941 /* for data frames, use RS table */ 3942 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: DATA\n", __func__); 3943 ridx = iwm_rate2ridx(sc, 3944 ieee80211_node_get_txrate_dot11rate(ni)); 3945 if (ridx == -1) 3946 ridx = 0; 3947 3948 /* This is the index into the programmed table */ 3949 tx->initial_rate_index = 0; 3950 tx->tx_flags |= htole32(IWM_TX_CMD_FLG_STA_RATE); 3951 } 3952 3953 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TXRATE, 3954 "%s: frame type=%d txrate %d\n", 3955 __func__, type, iwm_rates[ridx].rate); 3956 3957 rinfo = &iwm_rates[ridx]; 3958 3959 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, "%s: ridx=%d; rate=%d, CCK=%d\n", 3960 __func__, ridx, 3961 rinfo->rate, 3962 !! (IWM_RIDX_IS_CCK(ridx)) 3963 ); 3964 3965 /* XXX TODO: hard-coded TX antenna? */ 3966 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_9000) 3967 rate_flags = IWM_RATE_MCS_ANT_B_MSK; 3968 else 3969 rate_flags = IWM_RATE_MCS_ANT_A_MSK; 3970 if (IWM_RIDX_IS_CCK(ridx)) 3971 rate_flags |= IWM_RATE_MCS_CCK_MSK; 3972 tx->rate_n_flags = htole32(rate_flags | rinfo->plcp); 3973 3974 return rinfo; 3975 } 3976 3977 #define TB0_SIZE 16 3978 static int 3979 iwm_tx(struct iwm_softc *sc, struct mbuf *m, struct ieee80211_node *ni, int ac) 3980 { 3981 struct ieee80211com *ic = &sc->sc_ic; 3982 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3983 struct iwm_node *in = IWM_NODE(ni); 3984 struct iwm_tx_ring *ring; 3985 struct iwm_tx_data *data; 3986 struct iwm_tfd *desc; 3987 struct iwm_device_cmd *cmd; 3988 struct iwm_tx_cmd *tx; 3989 struct ieee80211_frame *wh; 3990 struct ieee80211_key *k = NULL; 3991 struct mbuf *m1; 3992 const struct iwm_rate *rinfo; 3993 uint32_t flags; 3994 u_int hdrlen; 3995 bus_dma_segment_t *seg, segs[IWM_MAX_SCATTER]; 3996 int nsegs; 3997 uint8_t tid, type; 3998 int i, totlen, error, pad; 3999 int qid; 4000 4001 wh = mtod(m, struct ieee80211_frame *); 4002 hdrlen = ieee80211_anyhdrsize(wh); 4003 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4004 tid = 0; 4005 4006 /* Map EDCA categories to Tx data queues. */ 4007 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_DQA_SUPPORT)) 4008 qid = IWM_DQA_MIN_MGMT_QUEUE + ac; 4009 else 4010 qid = ac; 4011 4012 ring = &sc->txq[qid]; 4013 desc = &ring->desc[ring->cur]; 4014 memset(desc, 0, sizeof(*desc)); 4015 data = &ring->data[ring->cur]; 4016 4017 /* Fill out iwm_tx_cmd to send to the firmware */ 4018 cmd = &ring->cmd[ring->cur]; 4019 cmd->hdr.code = IWM_TX_CMD; 4020 cmd->hdr.flags = 0; 4021 cmd->hdr.qid = ring->qid; 4022 cmd->hdr.idx = ring->cur; 4023 4024 tx = (void *)cmd->data; 4025 memset(tx, 0, sizeof(*tx)); 4026 4027 rinfo = iwm_tx_fill_cmd(sc, in, m, tx); 4028 4029 /* Offloaded sequence number assignment; non-AMPDU case */ 4030 if ((m->m_flags & M_AMPDU_MPDU) == 0) 4031 ieee80211_output_seqno_assign(ni, -1, m); 4032 4033 /* Encrypt the frame if need be. */ 4034 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 4035 /* Retrieve key for TX && do software encryption. */ 4036 k = ieee80211_crypto_encap(ni, m); 4037 if (k == NULL) { 4038 m_freem(m); 4039 return (ENOBUFS); 4040 } 4041 /* 802.11 header may have moved. */ 4042 wh = mtod(m, struct ieee80211_frame *); 4043 } 4044 4045 if (ieee80211_radiotap_active_vap(vap)) { 4046 struct iwm_tx_radiotap_header *tap = &sc->sc_txtap; 4047 4048 tap->wt_flags = 0; 4049 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 4050 tap->wt_chan_flags = htole16(ni->ni_chan->ic_flags); 4051 tap->wt_rate = rinfo->rate; 4052 if (k != NULL) 4053 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4054 ieee80211_radiotap_tx(vap, m); 4055 } 4056 4057 flags = 0; 4058 totlen = m->m_pkthdr.len; 4059 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4060 flags |= IWM_TX_CMD_FLG_ACK; 4061 } 4062 4063 if (type == IEEE80211_FC0_TYPE_DATA && 4064 totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold && 4065 !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4066 flags |= IWM_TX_CMD_FLG_PROT_REQUIRE; 4067 } 4068 4069 tx->sta_id = IWM_STATION_ID; 4070 4071 if (type == IEEE80211_FC0_TYPE_MGT) { 4072 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4073 4074 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4075 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) { 4076 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_ASSOC); 4077 } else if (subtype == IEEE80211_FC0_SUBTYPE_ACTION) { 4078 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_NONE); 4079 } else { 4080 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_MGMT); 4081 } 4082 } else { 4083 tx->pm_frame_timeout = htole16(IWM_PM_FRAME_NONE); 4084 } 4085 4086 if (hdrlen & 3) { 4087 /* First segment length must be a multiple of 4. */ 4088 flags |= IWM_TX_CMD_FLG_MH_PAD; 4089 tx->offload_assist |= htole16(IWM_TX_CMD_OFFLD_PAD); 4090 pad = 4 - (hdrlen & 3); 4091 } else { 4092 tx->offload_assist = 0; 4093 pad = 0; 4094 } 4095 4096 tx->len = htole16(totlen); 4097 tx->tid_tspec = tid; 4098 tx->life_time = htole32(IWM_TX_CMD_LIFE_TIME_INFINITE); 4099 4100 /* Set physical address of "scratch area". */ 4101 tx->dram_lsb_ptr = htole32(data->scratch_paddr); 4102 tx->dram_msb_ptr = iwm_get_dma_hi_addr(data->scratch_paddr); 4103 4104 /* Copy 802.11 header in TX command. */ 4105 memcpy((uint8_t *)tx + sizeof(*tx), wh, hdrlen); 4106 4107 flags |= IWM_TX_CMD_FLG_BT_DIS | IWM_TX_CMD_FLG_SEQ_CTL; 4108 4109 tx->sec_ctl = 0; 4110 tx->tx_flags |= htole32(flags); 4111 4112 /* Trim 802.11 header. */ 4113 m_adj(m, hdrlen); 4114 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4115 segs, &nsegs, BUS_DMA_NOWAIT); 4116 if (error != 0) { 4117 if (error != EFBIG) { 4118 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 4119 error); 4120 m_freem(m); 4121 return error; 4122 } 4123 /* Too many DMA segments, linearize mbuf. */ 4124 m1 = m_collapse(m, M_NOWAIT, IWM_MAX_SCATTER - 2); 4125 if (m1 == NULL) { 4126 device_printf(sc->sc_dev, 4127 "%s: could not defrag mbuf\n", __func__); 4128 m_freem(m); 4129 return (ENOBUFS); 4130 } 4131 m = m1; 4132 4133 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4134 segs, &nsegs, BUS_DMA_NOWAIT); 4135 if (error != 0) { 4136 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 4137 error); 4138 m_freem(m); 4139 return error; 4140 } 4141 } 4142 data->m = m; 4143 data->in = in; 4144 data->done = 0; 4145 4146 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 4147 "sending txd %p, in %p\n", data, data->in); 4148 KASSERT(data->in != NULL, ("node is NULL")); 4149 4150 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 4151 "sending data: qid=%d idx=%d len=%d nsegs=%d txflags=0x%08x rate_n_flags=0x%08x rateidx=%u\n", 4152 ring->qid, ring->cur, totlen, nsegs, 4153 le32toh(tx->tx_flags), 4154 le32toh(tx->rate_n_flags), 4155 tx->initial_rate_index 4156 ); 4157 4158 /* Fill TX descriptor. */ 4159 memset(desc, 0, sizeof(*desc)); 4160 desc->num_tbs = 2 + nsegs; 4161 4162 desc->tbs[0].lo = htole32(data->cmd_paddr); 4163 desc->tbs[0].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr) | 4164 (TB0_SIZE << 4)); 4165 desc->tbs[1].lo = htole32(data->cmd_paddr + TB0_SIZE); 4166 desc->tbs[1].hi_n_len = htole16(iwm_get_dma_hi_addr(data->cmd_paddr) | 4167 ((sizeof(struct iwm_cmd_header) + sizeof(*tx) + 4168 hdrlen + pad - TB0_SIZE) << 4)); 4169 4170 /* Other DMA segments are for data payload. */ 4171 for (i = 0; i < nsegs; i++) { 4172 seg = &segs[i]; 4173 desc->tbs[i + 2].lo = htole32(seg->ds_addr); 4174 desc->tbs[i + 2].hi_n_len = 4175 htole16(iwm_get_dma_hi_addr(seg->ds_addr)) | 4176 (seg->ds_len << 4); 4177 } 4178 4179 bus_dmamap_sync(ring->data_dmat, data->map, 4180 BUS_DMASYNC_PREWRITE); 4181 bus_dmamap_sync(ring->cmd_dma.tag, ring->cmd_dma.map, 4182 BUS_DMASYNC_PREWRITE); 4183 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4184 BUS_DMASYNC_PREWRITE); 4185 4186 #if 0 4187 iwm_update_sched(sc, ring->qid, ring->cur, tx->sta_id, le16toh(tx->len)); 4188 #endif 4189 4190 /* Kick TX ring. */ 4191 ring->cur = (ring->cur + 1) % IWM_TX_RING_COUNT; 4192 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4193 4194 /* Mark TX ring as full if we reach a certain threshold. */ 4195 if (++ring->queued > IWM_TX_RING_HIMARK) { 4196 sc->qfullmsk |= 1 << ring->qid; 4197 } 4198 4199 return 0; 4200 } 4201 4202 static int 4203 iwm_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4204 const struct ieee80211_bpf_params *params) 4205 { 4206 struct ieee80211com *ic = ni->ni_ic; 4207 struct iwm_softc *sc = ic->ic_softc; 4208 int error = 0; 4209 4210 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 4211 "->%s begin\n", __func__); 4212 4213 if ((sc->sc_flags & IWM_FLAG_HW_INITED) == 0) { 4214 m_freem(m); 4215 IWM_DPRINTF(sc, IWM_DEBUG_XMIT, 4216 "<-%s not RUNNING\n", __func__); 4217 return (ENETDOWN); 4218 } 4219 4220 IWM_LOCK(sc); 4221 /* XXX fix this */ 4222 if (params == NULL) { 4223 error = iwm_tx(sc, m, ni, 0); 4224 } else { 4225 error = iwm_tx(sc, m, ni, 0); 4226 } 4227 if (sc->sc_tx_timer == 0) 4228 callout_reset(&sc->sc_watchdog_to, hz, iwm_watchdog, sc); 4229 sc->sc_tx_timer = 5; 4230 IWM_UNLOCK(sc); 4231 4232 return (error); 4233 } 4234 4235 /* 4236 * mvm/tx.c 4237 */ 4238 4239 /* 4240 * Note that there are transports that buffer frames before they reach 4241 * the firmware. This means that after flush_tx_path is called, the 4242 * queue might not be empty. The race-free way to handle this is to: 4243 * 1) set the station as draining 4244 * 2) flush the Tx path 4245 * 3) wait for the transport queues to be empty 4246 */ 4247 int 4248 iwm_flush_tx_path(struct iwm_softc *sc, uint32_t tfd_msk, uint32_t flags) 4249 { 4250 int ret; 4251 struct iwm_tx_path_flush_cmd_v1 flush_cmd = { 4252 .queues_ctl = htole32(tfd_msk), 4253 .flush_ctl = htole16(IWM_DUMP_TX_FIFO_FLUSH), 4254 }; 4255 4256 ret = iwm_send_cmd_pdu(sc, IWM_TXPATH_FLUSH, flags, 4257 sizeof(flush_cmd), &flush_cmd); 4258 if (ret) 4259 device_printf(sc->sc_dev, 4260 "Flushing tx queue failed: %d\n", ret); 4261 return ret; 4262 } 4263 4264 /* 4265 * BEGIN mvm/quota.c 4266 */ 4267 4268 static int 4269 iwm_update_quotas(struct iwm_softc *sc, struct iwm_vap *ivp) 4270 { 4271 struct iwm_time_quota_cmd_v1 cmd; 4272 int i, idx, ret, num_active_macs, quota, quota_rem; 4273 int colors[IWM_MAX_BINDINGS] = { -1, -1, -1, -1, }; 4274 int n_ifs[IWM_MAX_BINDINGS] = {0, }; 4275 uint16_t id; 4276 4277 memset(&cmd, 0, sizeof(cmd)); 4278 4279 /* currently, PHY ID == binding ID */ 4280 if (ivp) { 4281 id = ivp->phy_ctxt->id; 4282 KASSERT(id < IWM_MAX_BINDINGS, ("invalid id")); 4283 colors[id] = ivp->phy_ctxt->color; 4284 4285 if (1) 4286 n_ifs[id] = 1; 4287 } 4288 4289 /* 4290 * The FW's scheduling session consists of 4291 * IWM_MAX_QUOTA fragments. Divide these fragments 4292 * equally between all the bindings that require quota 4293 */ 4294 num_active_macs = 0; 4295 for (i = 0; i < IWM_MAX_BINDINGS; i++) { 4296 cmd.quotas[i].id_and_color = htole32(IWM_FW_CTXT_INVALID); 4297 num_active_macs += n_ifs[i]; 4298 } 4299 4300 quota = 0; 4301 quota_rem = 0; 4302 if (num_active_macs) { 4303 quota = IWM_MAX_QUOTA / num_active_macs; 4304 quota_rem = IWM_MAX_QUOTA % num_active_macs; 4305 } 4306 4307 for (idx = 0, i = 0; i < IWM_MAX_BINDINGS; i++) { 4308 if (colors[i] < 0) 4309 continue; 4310 4311 cmd.quotas[idx].id_and_color = 4312 htole32(IWM_FW_CMD_ID_AND_COLOR(i, colors[i])); 4313 4314 if (n_ifs[i] <= 0) { 4315 cmd.quotas[idx].quota = htole32(0); 4316 cmd.quotas[idx].max_duration = htole32(0); 4317 } else { 4318 cmd.quotas[idx].quota = htole32(quota * n_ifs[i]); 4319 cmd.quotas[idx].max_duration = htole32(0); 4320 } 4321 idx++; 4322 } 4323 4324 /* Give the remainder of the session to the first binding */ 4325 cmd.quotas[0].quota = htole32(le32toh(cmd.quotas[0].quota) + quota_rem); 4326 4327 ret = iwm_send_cmd_pdu(sc, IWM_TIME_QUOTA_CMD, IWM_CMD_SYNC, 4328 sizeof(cmd), &cmd); 4329 if (ret) 4330 device_printf(sc->sc_dev, 4331 "%s: Failed to send quota: %d\n", __func__, ret); 4332 return ret; 4333 } 4334 4335 /* 4336 * END mvm/quota.c 4337 */ 4338 4339 /* 4340 * ieee80211 routines 4341 */ 4342 4343 /* 4344 * Change to AUTH state in 80211 state machine. Roughly matches what 4345 * Linux does in bss_info_changed(). 4346 */ 4347 static int 4348 iwm_auth(struct ieee80211vap *vap, struct iwm_softc *sc) 4349 { 4350 struct ieee80211_node *ni; 4351 struct iwm_node *in; 4352 struct iwm_vap *iv = IWM_VAP(vap); 4353 uint32_t duration; 4354 int error; 4355 4356 /* 4357 * XXX i have a feeling that the vap node is being 4358 * freed from underneath us. Grr. 4359 */ 4360 ni = ieee80211_ref_node(vap->iv_bss); 4361 in = IWM_NODE(ni); 4362 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_STATE, 4363 "%s: called; vap=%p, bss ni=%p\n", 4364 __func__, 4365 vap, 4366 ni); 4367 IWM_DPRINTF(sc, IWM_DEBUG_STATE, "%s: Current node bssid: %s\n", 4368 __func__, ether_sprintf(ni->ni_bssid)); 4369 4370 in->in_assoc = 0; 4371 iv->iv_auth = 1; 4372 4373 /* 4374 * Firmware bug - it'll crash if the beacon interval is less 4375 * than 16. We can't avoid connecting at all, so refuse the 4376 * station state change, this will cause net80211 to abandon 4377 * attempts to connect to this AP, and eventually wpa_s will 4378 * blacklist the AP... 4379 */ 4380 if (ni->ni_intval < 16) { 4381 device_printf(sc->sc_dev, 4382 "AP %s beacon interval is %d, refusing due to firmware bug!\n", 4383 ether_sprintf(ni->ni_bssid), ni->ni_intval); 4384 error = EINVAL; 4385 goto out; 4386 } 4387 4388 error = iwm_allow_mcast(vap, sc); 4389 if (error) { 4390 device_printf(sc->sc_dev, 4391 "%s: failed to set multicast\n", __func__); 4392 goto out; 4393 } 4394 4395 /* 4396 * This is where it deviates from what Linux does. 4397 * 4398 * Linux iwlwifi doesn't reset the nic each time, nor does it 4399 * call ctxt_add() here. Instead, it adds it during vap creation, 4400 * and always does a mac_ctx_changed(). 4401 * 4402 * The openbsd port doesn't attempt to do that - it reset things 4403 * at odd states and does the add here. 4404 * 4405 * So, until the state handling is fixed (ie, we never reset 4406 * the NIC except for a firmware failure, which should drag 4407 * the NIC back to IDLE, re-setup and re-add all the mac/phy 4408 * contexts that are required), let's do a dirty hack here. 4409 */ 4410 if (iv->is_uploaded) { 4411 if ((error = iwm_mac_ctxt_changed(sc, vap)) != 0) { 4412 device_printf(sc->sc_dev, 4413 "%s: failed to update MAC\n", __func__); 4414 goto out; 4415 } 4416 } else { 4417 if ((error = iwm_mac_ctxt_add(sc, vap)) != 0) { 4418 device_printf(sc->sc_dev, 4419 "%s: failed to add MAC\n", __func__); 4420 goto out; 4421 } 4422 } 4423 sc->sc_firmware_state = 1; 4424 4425 if ((error = iwm_phy_ctxt_changed(sc, &sc->sc_phyctxt[0], 4426 in->in_ni.ni_chan, 1, 1)) != 0) { 4427 device_printf(sc->sc_dev, 4428 "%s: failed update phy ctxt\n", __func__); 4429 goto out; 4430 } 4431 iv->phy_ctxt = &sc->sc_phyctxt[0]; 4432 4433 if ((error = iwm_binding_add_vif(sc, iv)) != 0) { 4434 device_printf(sc->sc_dev, 4435 "%s: binding update cmd\n", __func__); 4436 goto out; 4437 } 4438 sc->sc_firmware_state = 2; 4439 /* 4440 * Authentication becomes unreliable when powersaving is left enabled 4441 * here. Powersaving will be activated again when association has 4442 * finished or is aborted. 4443 */ 4444 iv->ps_disabled = TRUE; 4445 error = iwm_power_update_mac(sc); 4446 iv->ps_disabled = FALSE; 4447 if (error != 0) { 4448 device_printf(sc->sc_dev, 4449 "%s: failed to update power management\n", 4450 __func__); 4451 goto out; 4452 } 4453 if ((error = iwm_add_sta(sc, in)) != 0) { 4454 device_printf(sc->sc_dev, 4455 "%s: failed to add sta\n", __func__); 4456 goto out; 4457 } 4458 sc->sc_firmware_state = 3; 4459 4460 /* 4461 * Prevent the FW from wandering off channel during association 4462 * by "protecting" the session with a time event. 4463 */ 4464 /* XXX duration is in units of TU, not MS */ 4465 duration = IWM_TE_SESSION_PROTECTION_MAX_TIME_MS; 4466 iwm_protect_session(sc, iv, duration, 500 /* XXX magic number */, TRUE); 4467 4468 error = 0; 4469 out: 4470 if (error != 0) 4471 iv->iv_auth = 0; 4472 ieee80211_free_node(ni); 4473 return (error); 4474 } 4475 4476 static struct ieee80211_node * 4477 iwm_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 4478 { 4479 return malloc(sizeof (struct iwm_node), M_80211_NODE, 4480 M_NOWAIT | M_ZERO); 4481 } 4482 4483 static uint8_t 4484 iwm_rate_from_ucode_rate(uint32_t rate_n_flags) 4485 { 4486 uint8_t plcp = rate_n_flags & 0xff; 4487 int i; 4488 4489 for (i = 0; i <= IWM_RIDX_MAX; i++) { 4490 if (iwm_rates[i].plcp == plcp) 4491 return iwm_rates[i].rate; 4492 } 4493 return 0; 4494 } 4495 4496 uint8_t 4497 iwm_ridx2rate(struct ieee80211_rateset *rs, int ridx) 4498 { 4499 int i; 4500 uint8_t rval; 4501 4502 for (i = 0; i < rs->rs_nrates; i++) { 4503 rval = (rs->rs_rates[i] & IEEE80211_RATE_VAL); 4504 if (rval == iwm_rates[ridx].rate) 4505 return rs->rs_rates[i]; 4506 } 4507 4508 return 0; 4509 } 4510 4511 static int 4512 iwm_rate2ridx(struct iwm_softc *sc, uint8_t rate) 4513 { 4514 int i; 4515 4516 for (i = 0; i <= IWM_RIDX_MAX; i++) { 4517 if (iwm_rates[i].rate == rate) 4518 return i; 4519 } 4520 4521 device_printf(sc->sc_dev, 4522 "%s: WARNING: device rate for %u not found!\n", 4523 __func__, rate); 4524 4525 return -1; 4526 } 4527 4528 4529 static void 4530 iwm_setrates(struct iwm_softc *sc, struct iwm_node *in, int dot11rate) 4531 { 4532 struct ieee80211_node *ni = &in->in_ni; 4533 struct iwm_lq_cmd *lq = &in->in_lq; 4534 struct ieee80211_rateset *rs = &ni->ni_rates; 4535 int nrates = rs->rs_nrates; 4536 int i, ridx, tab = 0; 4537 // int txant = 0; 4538 int rix; 4539 4540 /* 4541 * Look up the rate index for the given legacy rate from 4542 * the rs_rates table. Default to the lowest rate if it's 4543 * not found (which is obviously hugely problematic.) 4544 */ 4545 rix = -1; 4546 for (i = 0; i < nrates; i++) { 4547 int rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 4548 if (rate == dot11rate) { 4549 rix = i; 4550 break; 4551 } 4552 } 4553 if (rix < 0) { 4554 device_printf(sc->sc_dev, 4555 "%s: failed to lookup dot11rate (%d)\n", 4556 __func__, dot11rate); 4557 rix = 0; 4558 } 4559 4560 if (nrates > nitems(lq->rs_table)) { 4561 device_printf(sc->sc_dev, 4562 "%s: node supports %d rates, driver handles " 4563 "only %zu\n", __func__, nrates, nitems(lq->rs_table)); 4564 return; 4565 } 4566 if (nrates == 0) { 4567 device_printf(sc->sc_dev, 4568 "%s: node supports 0 rates, odd!\n", __func__); 4569 return; 4570 } 4571 nrates = imin(rix + 1, nrates); 4572 4573 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 4574 "%s: nrates=%d\n", __func__, nrates); 4575 4576 /* then construct a lq_cmd based on those */ 4577 memset(lq, 0, sizeof(*lq)); 4578 lq->sta_id = IWM_STATION_ID; 4579 4580 /* For HT, always enable RTS/CTS to avoid excessive retries. */ 4581 if (ni->ni_flags & IEEE80211_NODE_HT) 4582 lq->flags |= IWM_LQ_FLAG_USE_RTS_MSK; 4583 4584 /* 4585 * are these used? (we don't do SISO or MIMO) 4586 * need to set them to non-zero, though, or we get an error. 4587 */ 4588 lq->single_stream_ant_msk = 1; 4589 lq->dual_stream_ant_msk = 1; 4590 4591 /* 4592 * Build the actual rate selection table. 4593 * The lowest bits are the rates. Additionally, 4594 * CCK needs bit 9 to be set. The rest of the bits 4595 * we add to the table select the tx antenna 4596 * Note that we add the rates in the highest rate first 4597 * (opposite of ni_rates). 4598 */ 4599 for (i = 0; i < nrates; i++) { 4600 int rate = rs->rs_rates[rix - i] & IEEE80211_RATE_VAL; 4601 int nextant; 4602 4603 /* Map 802.11 rate to HW rate index. */ 4604 ridx = iwm_rate2ridx(sc, rate); 4605 if (ridx == -1) 4606 continue; 4607 4608 #if 0 4609 if (txant == 0) 4610 txant = iwm_get_valid_tx_ant(sc); 4611 nextant = 1<<(ffs(txant)-1); 4612 txant &= ~nextant; 4613 #else 4614 nextant = iwm_get_valid_tx_ant(sc); 4615 #endif 4616 tab = iwm_rates[ridx].plcp; 4617 tab |= nextant << IWM_RATE_MCS_ANT_POS; 4618 if (IWM_RIDX_IS_CCK(ridx)) 4619 tab |= IWM_RATE_MCS_CCK_MSK; 4620 IWM_DPRINTF(sc, IWM_DEBUG_TXRATE, 4621 "station rate i=%d, rate=%d, hw=%x\n", 4622 i, iwm_rates[ridx].rate, tab); 4623 lq->rs_table[i] = htole32(tab); 4624 } 4625 /* then fill the rest with the lowest possible rate */ 4626 for (i = nrates; i < nitems(lq->rs_table); i++) { 4627 KASSERT(tab != 0, ("invalid tab")); 4628 lq->rs_table[i] = htole32(tab); 4629 } 4630 } 4631 4632 static void 4633 iwm_bring_down_firmware(struct iwm_softc *sc, struct ieee80211vap *vap) 4634 { 4635 struct iwm_vap *ivp = IWM_VAP(vap); 4636 int error; 4637 4638 /* Avoid Tx watchdog triggering, when transfers get dropped here. */ 4639 sc->sc_tx_timer = 0; 4640 4641 ivp->iv_auth = 0; 4642 if (sc->sc_firmware_state == 3) { 4643 iwm_xmit_queue_drain(sc); 4644 // iwm_flush_tx_path(sc, 0xf, IWM_CMD_SYNC); 4645 error = iwm_rm_sta(sc, vap, TRUE); 4646 if (error) { 4647 device_printf(sc->sc_dev, 4648 "%s: Failed to remove station: %d\n", 4649 __func__, error); 4650 } 4651 } 4652 if (sc->sc_firmware_state == 3) { 4653 error = iwm_mac_ctxt_changed(sc, vap); 4654 if (error) { 4655 device_printf(sc->sc_dev, 4656 "%s: Failed to change mac context: %d\n", 4657 __func__, error); 4658 } 4659 } 4660 if (sc->sc_firmware_state == 3) { 4661 error = iwm_sf_update(sc, vap, FALSE); 4662 if (error) { 4663 device_printf(sc->sc_dev, 4664 "%s: Failed to update smart FIFO: %d\n", 4665 __func__, error); 4666 } 4667 } 4668 if (sc->sc_firmware_state == 3) { 4669 error = iwm_rm_sta_id(sc, vap); 4670 if (error) { 4671 device_printf(sc->sc_dev, 4672 "%s: Failed to remove station id: %d\n", 4673 __func__, error); 4674 } 4675 } 4676 if (sc->sc_firmware_state == 3) { 4677 error = iwm_update_quotas(sc, NULL); 4678 if (error) { 4679 device_printf(sc->sc_dev, 4680 "%s: Failed to update PHY quota: %d\n", 4681 __func__, error); 4682 } 4683 } 4684 if (sc->sc_firmware_state == 3) { 4685 /* XXX Might need to specify bssid correctly. */ 4686 error = iwm_mac_ctxt_changed(sc, vap); 4687 if (error) { 4688 device_printf(sc->sc_dev, 4689 "%s: Failed to change mac context: %d\n", 4690 __func__, error); 4691 } 4692 } 4693 if (sc->sc_firmware_state == 3) { 4694 sc->sc_firmware_state = 2; 4695 } 4696 if (sc->sc_firmware_state > 1) { 4697 error = iwm_binding_remove_vif(sc, ivp); 4698 if (error) { 4699 device_printf(sc->sc_dev, 4700 "%s: Failed to remove channel ctx: %d\n", 4701 __func__, error); 4702 } 4703 } 4704 if (sc->sc_firmware_state > 1) { 4705 sc->sc_firmware_state = 1; 4706 } 4707 ivp->phy_ctxt = NULL; 4708 if (sc->sc_firmware_state > 0) { 4709 error = iwm_mac_ctxt_changed(sc, vap); 4710 if (error) { 4711 device_printf(sc->sc_dev, 4712 "%s: Failed to change mac context: %d\n", 4713 __func__, error); 4714 } 4715 } 4716 if (sc->sc_firmware_state > 0) { 4717 error = iwm_power_update_mac(sc); 4718 if (error != 0) { 4719 device_printf(sc->sc_dev, 4720 "%s: failed to update power management\n", 4721 __func__); 4722 } 4723 } 4724 sc->sc_firmware_state = 0; 4725 } 4726 4727 static int 4728 iwm_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4729 { 4730 struct iwm_vap *ivp = IWM_VAP(vap); 4731 struct ieee80211com *ic = vap->iv_ic; 4732 struct iwm_softc *sc = ic->ic_softc; 4733 struct iwm_node *in; 4734 int error; 4735 4736 IWM_DPRINTF(sc, IWM_DEBUG_STATE, 4737 "switching state %s -> %s arg=0x%x\n", 4738 ieee80211_state_name[vap->iv_state], 4739 ieee80211_state_name[nstate], 4740 arg); 4741 4742 IEEE80211_UNLOCK(ic); 4743 IWM_LOCK(sc); 4744 4745 if ((sc->sc_flags & IWM_FLAG_SCAN_RUNNING) && 4746 (nstate == IEEE80211_S_AUTH || 4747 nstate == IEEE80211_S_ASSOC || 4748 nstate == IEEE80211_S_RUN)) { 4749 /* Stop blinking for a scan, when authenticating. */ 4750 iwm_led_blink_stop(sc); 4751 } 4752 4753 if (vap->iv_state == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 4754 iwm_led_disable(sc); 4755 /* disable beacon filtering if we're hopping out of RUN */ 4756 iwm_disable_beacon_filter(sc); 4757 if (((in = IWM_NODE(vap->iv_bss)) != NULL)) 4758 in->in_assoc = 0; 4759 } 4760 4761 if ((vap->iv_state == IEEE80211_S_AUTH || 4762 vap->iv_state == IEEE80211_S_ASSOC || 4763 vap->iv_state == IEEE80211_S_RUN) && 4764 (nstate == IEEE80211_S_INIT || 4765 nstate == IEEE80211_S_SCAN || 4766 nstate == IEEE80211_S_AUTH)) { 4767 iwm_unprotect_session(sc, ivp); 4768 } 4769 4770 if ((vap->iv_state == IEEE80211_S_RUN || 4771 vap->iv_state == IEEE80211_S_ASSOC) && 4772 nstate == IEEE80211_S_INIT) { 4773 /* 4774 * In this case, iv_newstate() wants to send an 80211 frame on 4775 * the network that we are leaving. So we need to call it, 4776 * before tearing down all the firmware state. 4777 */ 4778 IWM_UNLOCK(sc); 4779 IEEE80211_LOCK(ic); 4780 ivp->iv_newstate(vap, nstate, arg); 4781 IEEE80211_UNLOCK(ic); 4782 IWM_LOCK(sc); 4783 iwm_bring_down_firmware(sc, vap); 4784 IWM_UNLOCK(sc); 4785 IEEE80211_LOCK(ic); 4786 return 0; 4787 } 4788 4789 switch (nstate) { 4790 case IEEE80211_S_INIT: 4791 case IEEE80211_S_SCAN: 4792 break; 4793 4794 case IEEE80211_S_AUTH: 4795 iwm_bring_down_firmware(sc, vap); 4796 if ((error = iwm_auth(vap, sc)) != 0) { 4797 device_printf(sc->sc_dev, 4798 "%s: could not move to auth state: %d\n", 4799 __func__, error); 4800 iwm_bring_down_firmware(sc, vap); 4801 IWM_UNLOCK(sc); 4802 IEEE80211_LOCK(ic); 4803 return 1; 4804 } 4805 break; 4806 4807 case IEEE80211_S_ASSOC: 4808 /* 4809 * EBS may be disabled due to previous failures reported by FW. 4810 * Reset EBS status here assuming environment has been changed. 4811 */ 4812 sc->last_ebs_successful = TRUE; 4813 break; 4814 4815 case IEEE80211_S_RUN: 4816 in = IWM_NODE(vap->iv_bss); 4817 /* Update the association state, now we have it all */ 4818 /* (eg associd comes in at this point */ 4819 error = iwm_update_sta(sc, in); 4820 if (error != 0) { 4821 device_printf(sc->sc_dev, 4822 "%s: failed to update STA\n", __func__); 4823 IWM_UNLOCK(sc); 4824 IEEE80211_LOCK(ic); 4825 return error; 4826 } 4827 in->in_assoc = 1; 4828 error = iwm_mac_ctxt_changed(sc, vap); 4829 if (error != 0) { 4830 device_printf(sc->sc_dev, 4831 "%s: failed to update MAC: %d\n", __func__, error); 4832 } 4833 4834 iwm_sf_update(sc, vap, FALSE); 4835 iwm_enable_beacon_filter(sc, ivp); 4836 iwm_power_update_mac(sc); 4837 iwm_update_quotas(sc, ivp); 4838 ieee80211_ratectl_rate(&in->in_ni, NULL, 0); 4839 iwm_setrates(sc, in, 4840 ieee80211_node_get_txrate_dot11rate(&in->in_ni)); 4841 4842 if ((error = iwm_send_lq_cmd(sc, &in->in_lq, TRUE)) != 0) { 4843 device_printf(sc->sc_dev, 4844 "%s: IWM_LQ_CMD failed: %d\n", __func__, error); 4845 } 4846 4847 iwm_led_enable(sc); 4848 break; 4849 4850 default: 4851 break; 4852 } 4853 IWM_UNLOCK(sc); 4854 IEEE80211_LOCK(ic); 4855 4856 return (ivp->iv_newstate(vap, nstate, arg)); 4857 } 4858 4859 void 4860 iwm_endscan_cb(void *arg, int pending) 4861 { 4862 struct iwm_softc *sc = arg; 4863 struct ieee80211com *ic = &sc->sc_ic; 4864 4865 IWM_DPRINTF(sc, IWM_DEBUG_SCAN | IWM_DEBUG_TRACE, 4866 "%s: scan ended\n", 4867 __func__); 4868 4869 ieee80211_scan_done(TAILQ_FIRST(&ic->ic_vaps)); 4870 } 4871 4872 static int 4873 iwm_send_bt_init_conf(struct iwm_softc *sc) 4874 { 4875 struct iwm_bt_coex_cmd bt_cmd; 4876 4877 bt_cmd.mode = htole32(IWM_BT_COEX_WIFI); 4878 bt_cmd.enabled_modules = htole32(IWM_BT_COEX_HIGH_BAND_RET); 4879 4880 return iwm_send_cmd_pdu(sc, IWM_BT_CONFIG, 0, sizeof(bt_cmd), 4881 &bt_cmd); 4882 } 4883 4884 static int 4885 iwm_send_soc_conf(struct iwm_softc *sc) 4886 { 4887 struct iwm_soc_configuration_cmd cmd; 4888 int err; 4889 uint32_t cmd_id, flags = 0; 4890 4891 memset(&cmd, 0, sizeof(cmd)); 4892 4893 /* 4894 * In VER_1 of this command, the discrete value is considered 4895 * an integer; In VER_2, it's a bitmask. Since we have only 2 4896 * values in VER_1, this is backwards-compatible with VER_2, 4897 * as long as we don't set any other flag bits. 4898 */ 4899 if (!sc->cfg->integrated) { /* VER_1 */ 4900 flags = IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE; 4901 } else { /* VER_2 */ 4902 uint8_t scan_cmd_ver; 4903 if (sc->cfg->ltr_delay != IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE) 4904 flags |= (sc->cfg->ltr_delay & 4905 IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK); 4906 scan_cmd_ver = iwm_lookup_cmd_ver(sc, IWM_LONG_GROUP, 4907 IWM_SCAN_REQ_UMAC); 4908 if (scan_cmd_ver != IWM_FW_CMD_VER_UNKNOWN && 4909 scan_cmd_ver >= 2 && sc->cfg->low_latency_xtal) 4910 flags |= IWM_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY; 4911 } 4912 cmd.flags = htole32(flags); 4913 4914 cmd.latency = htole32(sc->cfg->xtal_latency); 4915 4916 cmd_id = iwm_cmd_id(IWM_SOC_CONFIGURATION_CMD, IWM_SYSTEM_GROUP, 0); 4917 err = iwm_send_cmd_pdu(sc, cmd_id, 0, sizeof(cmd), &cmd); 4918 if (err) 4919 device_printf(sc->sc_dev, "failed to set soc latency: %d\n", 4920 err); 4921 return err; 4922 } 4923 4924 static int 4925 iwm_send_dqa_cmd(struct iwm_softc *sc) 4926 { 4927 struct iwm_dqa_enable_cmd dqa_cmd; 4928 uint32_t cmd_id; 4929 4930 dqa_cmd.cmd_queue = htole32(IWM_DQA_CMD_QUEUE); 4931 cmd_id = iwm_cmd_id(IWM_DQA_ENABLE_CMD, IWM_DATA_PATH_GROUP, 0); 4932 return iwm_send_cmd_pdu(sc, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); 4933 } 4934 4935 static int 4936 iwm_send_temp_report_ths_cmd(struct iwm_softc *sc) 4937 { 4938 struct iwm_temp_report_ths_cmd cmd; 4939 int err; 4940 4941 /* 4942 * In order to give responsibility for critical-temperature-kill 4943 * and TX backoff to FW we need to send an empty temperature 4944 * reporting command at init time. 4945 */ 4946 memset(&cmd, 0, sizeof(cmd)); 4947 4948 err = iwm_send_cmd_pdu(sc, 4949 IWM_WIDE_ID(IWM_PHY_OPS_GROUP, IWM_TEMP_REPORTING_THRESHOLDS_CMD), 4950 0, sizeof(cmd), &cmd); 4951 if (err) 4952 device_printf(sc->sc_dev, 4953 "TEMP_REPORT_THS_CMD command failed (error %d)\n", err); 4954 4955 return err; 4956 } 4957 4958 static boolean_t 4959 iwm_is_lar_supported(struct iwm_softc *sc) 4960 { 4961 boolean_t nvm_lar = sc->nvm_data->lar_enabled; 4962 boolean_t tlv_lar = iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_LAR_SUPPORT); 4963 4964 if (iwm_lar_disable) 4965 return FALSE; 4966 4967 /* 4968 * Enable LAR only if it is supported by the FW (TLV) && 4969 * enabled in the NVM 4970 */ 4971 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) 4972 return nvm_lar && tlv_lar; 4973 else 4974 return tlv_lar; 4975 } 4976 4977 static boolean_t 4978 iwm_is_wifi_mcc_supported(struct iwm_softc *sc) 4979 { 4980 return iwm_fw_has_api(sc, IWM_UCODE_TLV_API_WIFI_MCC_UPDATE) || 4981 iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC); 4982 } 4983 4984 static int 4985 iwm_send_update_mcc_cmd(struct iwm_softc *sc, const char *alpha2) 4986 { 4987 struct iwm_mcc_update_cmd mcc_cmd; 4988 struct iwm_host_cmd hcmd = { 4989 .id = IWM_MCC_UPDATE_CMD, 4990 .flags = (IWM_CMD_SYNC | IWM_CMD_WANT_SKB), 4991 .data = { &mcc_cmd }, 4992 }; 4993 int ret; 4994 #ifdef IWM_DEBUG 4995 struct iwm_rx_packet *pkt; 4996 struct iwm_mcc_update_resp_v1 *mcc_resp_v1 = NULL; 4997 struct iwm_mcc_update_resp_v2 *mcc_resp; 4998 int n_channels; 4999 uint16_t mcc; 5000 #endif 5001 int resp_v3 = iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V3); 5002 5003 if (!iwm_is_lar_supported(sc)) { 5004 IWM_DPRINTF(sc, IWM_DEBUG_LAR, "%s: no LAR support\n", 5005 __func__); 5006 return 0; 5007 } 5008 5009 memset(&mcc_cmd, 0, sizeof(mcc_cmd)); 5010 mcc_cmd.mcc = htole16(alpha2[0] << 8 | alpha2[1]); 5011 if (iwm_is_wifi_mcc_supported(sc)) 5012 mcc_cmd.source_id = IWM_MCC_SOURCE_GET_CURRENT; 5013 else 5014 mcc_cmd.source_id = IWM_MCC_SOURCE_OLD_FW; 5015 5016 if (resp_v3) 5017 hcmd.len[0] = sizeof(struct iwm_mcc_update_cmd); 5018 else 5019 hcmd.len[0] = sizeof(struct iwm_mcc_update_cmd_v1); 5020 5021 IWM_DPRINTF(sc, IWM_DEBUG_LAR, 5022 "send MCC update to FW with '%c%c' src = %d\n", 5023 alpha2[0], alpha2[1], mcc_cmd.source_id); 5024 5025 ret = iwm_send_cmd(sc, &hcmd); 5026 if (ret) 5027 return ret; 5028 5029 #ifdef IWM_DEBUG 5030 pkt = hcmd.resp_pkt; 5031 5032 /* Extract MCC response */ 5033 if (resp_v3) { 5034 mcc_resp = (void *)pkt->data; 5035 mcc = mcc_resp->mcc; 5036 n_channels = le32toh(mcc_resp->n_channels); 5037 } else { 5038 mcc_resp_v1 = (void *)pkt->data; 5039 mcc = mcc_resp_v1->mcc; 5040 n_channels = le32toh(mcc_resp_v1->n_channels); 5041 } 5042 5043 /* W/A for a FW/NVM issue - returns 0x00 for the world domain */ 5044 if (mcc == 0) 5045 mcc = 0x3030; /* "00" - world */ 5046 5047 IWM_DPRINTF(sc, IWM_DEBUG_LAR, 5048 "regulatory domain '%c%c' (%d channels available)\n", 5049 mcc >> 8, mcc & 0xff, n_channels); 5050 #endif 5051 iwm_free_resp(sc, &hcmd); 5052 5053 return 0; 5054 } 5055 5056 static void 5057 iwm_tt_tx_backoff(struct iwm_softc *sc, uint32_t backoff) 5058 { 5059 struct iwm_host_cmd cmd = { 5060 .id = IWM_REPLY_THERMAL_MNG_BACKOFF, 5061 .len = { sizeof(uint32_t), }, 5062 .data = { &backoff, }, 5063 }; 5064 5065 if (iwm_send_cmd(sc, &cmd) != 0) { 5066 device_printf(sc->sc_dev, 5067 "failed to change thermal tx backoff\n"); 5068 } 5069 } 5070 5071 static int 5072 iwm_init_hw(struct iwm_softc *sc) 5073 { 5074 struct ieee80211com *ic = &sc->sc_ic; 5075 int error, i, ac, qid; 5076 5077 sc->sf_state = IWM_SF_UNINIT; 5078 5079 if ((error = iwm_start_hw(sc)) != 0) { 5080 printf("iwm_start_hw: failed %d\n", error); 5081 return error; 5082 } 5083 5084 if ((error = iwm_run_init_ucode(sc, 0)) != 0) { 5085 printf("iwm_run_init_ucode: failed %d\n", error); 5086 return error; 5087 } 5088 5089 /* 5090 * should stop and start HW since that INIT 5091 * image just loaded 5092 */ 5093 iwm_stop_device(sc); 5094 sc->sc_ps_disabled = FALSE; 5095 if ((error = iwm_start_hw(sc)) != 0) { 5096 device_printf(sc->sc_dev, "could not initialize hardware\n"); 5097 return error; 5098 } 5099 5100 /* omstart, this time with the regular firmware */ 5101 error = iwm_load_ucode_wait_alive(sc, IWM_UCODE_REGULAR); 5102 if (error) { 5103 device_printf(sc->sc_dev, "could not load firmware\n"); 5104 goto error; 5105 } 5106 5107 error = iwm_sf_update(sc, NULL, FALSE); 5108 if (error) 5109 device_printf(sc->sc_dev, "Failed to initialize Smart Fifo\n"); 5110 5111 if ((error = iwm_send_bt_init_conf(sc)) != 0) { 5112 device_printf(sc->sc_dev, "bt init conf failed\n"); 5113 goto error; 5114 } 5115 5116 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT)) { 5117 if ((error = iwm_send_soc_conf(sc)) != 0) 5118 goto error; 5119 } 5120 5121 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW)) { 5122 if ((error = iwm_send_temp_report_ths_cmd(sc)) != 0) 5123 goto error; 5124 } 5125 5126 error = iwm_send_tx_ant_cfg(sc, iwm_get_valid_tx_ant(sc)); 5127 if (error != 0) { 5128 device_printf(sc->sc_dev, "antenna config failed\n"); 5129 goto error; 5130 } 5131 5132 /* Send phy db control command and then phy db calibration */ 5133 if ((error = iwm_send_phy_db_data(sc->sc_phy_db)) != 0) 5134 goto error; 5135 5136 if ((error = iwm_send_phy_cfg_cmd(sc)) != 0) { 5137 device_printf(sc->sc_dev, "phy_cfg_cmd failed\n"); 5138 goto error; 5139 } 5140 5141 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_DQA_SUPPORT)) { 5142 if ((error = iwm_send_dqa_cmd(sc)) != 0) 5143 goto error; 5144 } 5145 5146 /* Add auxiliary station for scanning */ 5147 if ((error = iwm_add_aux_sta(sc)) != 0) { 5148 device_printf(sc->sc_dev, "add_aux_sta failed\n"); 5149 goto error; 5150 } 5151 5152 for (i = 0; i < IWM_NUM_PHY_CTX; i++) { 5153 /* 5154 * The channel used here isn't relevant as it's 5155 * going to be overwritten in the other flows. 5156 * For now use the first channel we have. 5157 */ 5158 sc->sc_phyctxt[i].id = i; 5159 sc->sc_phyctxt[i].channel = &ic->ic_channels[1]; 5160 error = iwm_phy_ctxt_cmd(sc, &sc->sc_phyctxt[i], 1, 1, 5161 IWM_FW_CTXT_ACTION_ADD, 0, IEEE80211_HTINFO_2NDCHAN_NONE); 5162 if (error) 5163 goto error; 5164 } 5165 5166 /* Initialize tx backoffs to the minimum. */ 5167 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) 5168 iwm_tt_tx_backoff(sc, 0); 5169 5170 if (iwm_config_ltr(sc) != 0) 5171 device_printf(sc->sc_dev, "PCIe LTR configuration failed\n"); 5172 5173 error = iwm_power_update_device(sc); 5174 if (error) 5175 goto error; 5176 5177 if ((error = iwm_send_update_mcc_cmd(sc, "ZZ")) != 0) 5178 goto error; 5179 5180 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_UMAC_SCAN)) { 5181 if ((error = iwm_config_umac_scan(sc)) != 0) 5182 goto error; 5183 } 5184 5185 /* Enable Tx queues. */ 5186 for (ac = 0; ac < WME_NUM_AC; ac++) { 5187 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_DQA_SUPPORT)) 5188 qid = ac + IWM_DQA_MIN_MGMT_QUEUE; 5189 else 5190 qid = ac; 5191 5192 error = iwm_enable_txq(sc, IWM_STATION_ID, qid, 5193 iwm_ac_to_tx_fifo[ac]); 5194 if (error) 5195 goto error; 5196 } 5197 5198 if ((error = iwm_disable_beacon_filter(sc)) != 0) { 5199 device_printf(sc->sc_dev, "failed to disable beacon filter\n"); 5200 goto error; 5201 } 5202 5203 return 0; 5204 5205 error: 5206 iwm_stop_device(sc); 5207 return error; 5208 } 5209 5210 /* Allow multicast from our BSSID. */ 5211 static int 5212 iwm_allow_mcast(struct ieee80211vap *vap, struct iwm_softc *sc) 5213 { 5214 struct ieee80211_node *ni = vap->iv_bss; 5215 struct iwm_mcast_filter_cmd *cmd; 5216 size_t size; 5217 int error; 5218 5219 size = roundup(sizeof(*cmd), 4); 5220 cmd = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 5221 if (cmd == NULL) 5222 return ENOMEM; 5223 cmd->filter_own = 1; 5224 cmd->port_id = 0; 5225 cmd->count = 0; 5226 cmd->pass_all = 1; 5227 IEEE80211_ADDR_COPY(cmd->bssid, ni->ni_bssid); 5228 5229 error = iwm_send_cmd_pdu(sc, IWM_MCAST_FILTER_CMD, 5230 IWM_CMD_SYNC, size, cmd); 5231 free(cmd, M_DEVBUF); 5232 5233 return (error); 5234 } 5235 5236 /* 5237 * ifnet interfaces 5238 */ 5239 5240 static void 5241 iwm_init(struct iwm_softc *sc) 5242 { 5243 int error; 5244 5245 IWM_LOCK_ASSERT_LOCKED(sc); 5246 5247 if (sc->sc_flags & IWM_FLAG_HW_INITED) { 5248 return; 5249 } 5250 sc->sc_generation++; 5251 sc->sc_flags &= ~IWM_FLAG_STOPPED; 5252 5253 if ((error = iwm_init_hw(sc)) != 0) { 5254 printf("iwm_init_hw failed %d\n", error); 5255 iwm_stop(sc); 5256 return; 5257 } 5258 5259 if (sc->nvm_data->sku_cap_11n_enable) 5260 iwm_setup_ht_rates(sc); 5261 5262 /* 5263 * Ok, firmware loaded and we are jogging 5264 */ 5265 sc->sc_flags |= IWM_FLAG_HW_INITED; 5266 } 5267 5268 static int 5269 iwm_transmit(struct ieee80211com *ic, struct mbuf *m) 5270 { 5271 struct iwm_softc *sc; 5272 int error; 5273 5274 sc = ic->ic_softc; 5275 5276 IWM_LOCK(sc); 5277 if ((sc->sc_flags & IWM_FLAG_HW_INITED) == 0) { 5278 IWM_UNLOCK(sc); 5279 return (ENXIO); 5280 } 5281 error = mbufq_enqueue(&sc->sc_snd, m); 5282 if (error) { 5283 IWM_UNLOCK(sc); 5284 return (error); 5285 } 5286 iwm_start(sc); 5287 IWM_UNLOCK(sc); 5288 return (0); 5289 } 5290 5291 /* 5292 * Dequeue packets from sendq and call send. 5293 */ 5294 static void 5295 iwm_start(struct iwm_softc *sc) 5296 { 5297 struct ieee80211_node *ni; 5298 struct mbuf *m; 5299 int ac = 0; 5300 5301 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TRACE, "->%s\n", __func__); 5302 while (sc->qfullmsk == 0 && 5303 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 5304 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 5305 if (iwm_tx(sc, m, ni, ac) != 0) { 5306 if_inc_counter(ni->ni_vap->iv_ifp, 5307 IFCOUNTER_OERRORS, 1); 5308 ieee80211_free_node(ni); 5309 continue; 5310 } 5311 if (sc->sc_tx_timer == 0) { 5312 callout_reset(&sc->sc_watchdog_to, hz, iwm_watchdog, 5313 sc); 5314 } 5315 sc->sc_tx_timer = 15; 5316 } 5317 IWM_DPRINTF(sc, IWM_DEBUG_XMIT | IWM_DEBUG_TRACE, "<-%s\n", __func__); 5318 } 5319 5320 static void 5321 iwm_stop(struct iwm_softc *sc) 5322 { 5323 IWM_LOCK_ASSERT_LOCKED(sc); 5324 5325 sc->sc_flags &= ~IWM_FLAG_HW_INITED; 5326 sc->sc_flags |= IWM_FLAG_STOPPED; 5327 5328 /* 5329 * Attempt to cancel; but if we can't, then don't call drain as 5330 * that can't be done with the lock held. 5331 */ 5332 if (sc->sc_tq != NULL) { 5333 taskqueue_cancel(sc->sc_tq, &sc->mac_ctxt_task, NULL); 5334 taskqueue_cancel(sc->sc_tq, &sc->phy_ctxt_task, NULL); 5335 } 5336 5337 sc->sc_generation++; 5338 iwm_led_blink_stop(sc); 5339 sc->sc_tx_timer = 0; 5340 iwm_stop_device(sc); 5341 sc->sc_flags &= ~IWM_FLAG_SCAN_RUNNING; 5342 } 5343 5344 static void 5345 iwm_watchdog(void *arg) 5346 { 5347 struct iwm_softc *sc = arg; 5348 struct ieee80211com *ic = &sc->sc_ic; 5349 5350 if (sc->sc_attached == 0) 5351 return; 5352 5353 if (sc->sc_tx_timer > 0) { 5354 if (--sc->sc_tx_timer == 0) { 5355 device_printf(sc->sc_dev, "device timeout\n"); 5356 #ifdef IWM_DEBUG 5357 iwm_nic_error(sc); 5358 #endif 5359 ieee80211_restart_all(ic); 5360 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 5361 return; 5362 } 5363 callout_reset(&sc->sc_watchdog_to, hz, iwm_watchdog, sc); 5364 } 5365 } 5366 5367 static void 5368 iwm_parent(struct ieee80211com *ic) 5369 { 5370 struct iwm_softc *sc = ic->ic_softc; 5371 int startall = 0; 5372 int rfkill = 0; 5373 5374 IWM_LOCK_ASSERT_UNLOCKED(sc); 5375 5376 IWM_LOCK(sc); 5377 if (ic->ic_nrunning > 0) { 5378 if (!(sc->sc_flags & IWM_FLAG_HW_INITED)) { 5379 iwm_init(sc); 5380 rfkill = iwm_check_rfkill(sc); 5381 if (!rfkill) 5382 startall = 1; 5383 } 5384 } else if (sc->sc_flags & IWM_FLAG_HW_INITED) 5385 iwm_stop(sc); 5386 IWM_UNLOCK(sc); 5387 if (startall) 5388 ieee80211_start_all(ic); 5389 else if (rfkill) 5390 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 5391 } 5392 5393 static void 5394 iwm_rftoggle_task(void *arg, int npending __unused) 5395 { 5396 struct iwm_softc *sc = arg; 5397 struct ieee80211com *ic = &sc->sc_ic; 5398 int rfkill; 5399 5400 IWM_LOCK_ASSERT_UNLOCKED(sc); 5401 5402 IWM_LOCK(sc); 5403 rfkill = iwm_check_rfkill(sc); 5404 IWM_UNLOCK(sc); 5405 if (rfkill) { 5406 device_printf(sc->sc_dev, 5407 "%s: rfkill switch, disabling interface\n", __func__); 5408 ieee80211_suspend_all(ic); 5409 ieee80211_notify_radio(ic, 0); 5410 } else { 5411 device_printf(sc->sc_dev, 5412 "%s: rfkill cleared, re-enabling interface\n", __func__); 5413 ieee80211_resume_all(ic); 5414 ieee80211_notify_radio(ic, 1); 5415 } 5416 } 5417 5418 /* 5419 * Deferred MAC related task updates. 5420 * 5421 * This is scheduled whenever something in the STA MAC 5422 * config has changed. This driver currently only supports 5423 * a single STA interface, so that's the assumption made 5424 * here. 5425 */ 5426 static void 5427 iwm_mac_ctxt_task(void *arg, int npending __unused) 5428 { 5429 struct iwm_softc *sc = arg; 5430 struct ieee80211com *ic = &sc->sc_ic; 5431 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5432 const struct iwm_vap *iv; 5433 int error; 5434 5435 IWM_LOCK_ASSERT_UNLOCKED(sc); 5436 5437 if (vap == NULL) 5438 return; 5439 5440 iv = IWM_VAP(vap); 5441 5442 IWM_LOCK(sc); 5443 5444 /* Don't scheduled work if the driver is stopped */ 5445 if (sc->sc_flags & IWM_FLAG_STOPPED) { 5446 IWM_UNLOCK(sc); 5447 return; 5448 } 5449 5450 /* 5451 * Only trigger an update if we've already programmed in a 5452 * MAC context. 5453 */ 5454 if (iv->is_uploaded) { 5455 if ((error = iwm_mac_ctxt_changed(sc, vap)) != 0) { 5456 device_printf(sc->sc_dev, 5457 "%s: failed to update MAC\n", __func__); 5458 } 5459 } 5460 IWM_UNLOCK(sc); 5461 } 5462 5463 /* 5464 * Deferred PHY related task updates. 5465 * 5466 * This is scheduled whenever something in the STA PHY 5467 * config has changed. This driver currently only supports 5468 * a single STA interface, so that's the assumption made 5469 * here. 5470 */ 5471 static void 5472 iwm_phy_ctxt_task(void *arg, int npending __unused) 5473 { 5474 struct iwm_softc *sc = arg; 5475 /* TODO */ 5476 5477 device_printf(sc->sc_dev, "%s: called\n", __func__); 5478 } 5479 5480 /* 5481 * The interrupt side of things 5482 */ 5483 5484 /* 5485 * error dumping routines are from iwlwifi/mvm/utils.c 5486 */ 5487 5488 /* 5489 * Note: This structure is read from the device with IO accesses, 5490 * and the reading already does the endian conversion. As it is 5491 * read with uint32_t-sized accesses, any members with a different size 5492 * need to be ordered correctly though! 5493 */ 5494 struct iwm_error_event_table { 5495 uint32_t valid; /* (nonzero) valid, (0) log is empty */ 5496 uint32_t error_id; /* type of error */ 5497 uint32_t trm_hw_status0; /* TRM HW status */ 5498 uint32_t trm_hw_status1; /* TRM HW status */ 5499 uint32_t blink2; /* branch link */ 5500 uint32_t ilink1; /* interrupt link */ 5501 uint32_t ilink2; /* interrupt link */ 5502 uint32_t data1; /* error-specific data */ 5503 uint32_t data2; /* error-specific data */ 5504 uint32_t data3; /* error-specific data */ 5505 uint32_t bcon_time; /* beacon timer */ 5506 uint32_t tsf_low; /* network timestamp function timer */ 5507 uint32_t tsf_hi; /* network timestamp function timer */ 5508 uint32_t gp1; /* GP1 timer register */ 5509 uint32_t gp2; /* GP2 timer register */ 5510 uint32_t fw_rev_type; /* firmware revision type */ 5511 uint32_t major; /* uCode version major */ 5512 uint32_t minor; /* uCode version minor */ 5513 uint32_t hw_ver; /* HW Silicon version */ 5514 uint32_t brd_ver; /* HW board version */ 5515 uint32_t log_pc; /* log program counter */ 5516 uint32_t frame_ptr; /* frame pointer */ 5517 uint32_t stack_ptr; /* stack pointer */ 5518 uint32_t hcmd; /* last host command header */ 5519 uint32_t isr0; /* isr status register LMPM_NIC_ISR0: 5520 * rxtx_flag */ 5521 uint32_t isr1; /* isr status register LMPM_NIC_ISR1: 5522 * host_flag */ 5523 uint32_t isr2; /* isr status register LMPM_NIC_ISR2: 5524 * enc_flag */ 5525 uint32_t isr3; /* isr status register LMPM_NIC_ISR3: 5526 * time_flag */ 5527 uint32_t isr4; /* isr status register LMPM_NIC_ISR4: 5528 * wico interrupt */ 5529 uint32_t last_cmd_id; /* last HCMD id handled by the firmware */ 5530 uint32_t wait_event; /* wait event() caller address */ 5531 uint32_t l2p_control; /* L2pControlField */ 5532 uint32_t l2p_duration; /* L2pDurationField */ 5533 uint32_t l2p_mhvalid; /* L2pMhValidBits */ 5534 uint32_t l2p_addr_match; /* L2pAddrMatchStat */ 5535 uint32_t lmpm_pmg_sel; /* indicate which clocks are turned on 5536 * (LMPM_PMG_SEL) */ 5537 uint32_t u_timestamp; /* indicate when the date and time of the 5538 * compilation */ 5539 uint32_t flow_handler; /* FH read/write pointers, RX credit */ 5540 } __packed /* LOG_ERROR_TABLE_API_S_VER_3 */; 5541 5542 /* 5543 * UMAC error struct - relevant starting from family 8000 chip. 5544 * Note: This structure is read from the device with IO accesses, 5545 * and the reading already does the endian conversion. As it is 5546 * read with u32-sized accesses, any members with a different size 5547 * need to be ordered correctly though! 5548 */ 5549 struct iwm_umac_error_event_table { 5550 uint32_t valid; /* (nonzero) valid, (0) log is empty */ 5551 uint32_t error_id; /* type of error */ 5552 uint32_t blink1; /* branch link */ 5553 uint32_t blink2; /* branch link */ 5554 uint32_t ilink1; /* interrupt link */ 5555 uint32_t ilink2; /* interrupt link */ 5556 uint32_t data1; /* error-specific data */ 5557 uint32_t data2; /* error-specific data */ 5558 uint32_t data3; /* error-specific data */ 5559 uint32_t umac_major; 5560 uint32_t umac_minor; 5561 uint32_t frame_pointer; /* core register 27*/ 5562 uint32_t stack_pointer; /* core register 28 */ 5563 uint32_t cmd_header; /* latest host cmd sent to UMAC */ 5564 uint32_t nic_isr_pref; /* ISR status register */ 5565 } __packed; 5566 5567 #define ERROR_START_OFFSET (1 * sizeof(uint32_t)) 5568 #define ERROR_ELEM_SIZE (7 * sizeof(uint32_t)) 5569 5570 #ifdef IWM_DEBUG 5571 struct { 5572 const char *name; 5573 uint8_t num; 5574 } advanced_lookup[] = { 5575 { "NMI_INTERRUPT_WDG", 0x34 }, 5576 { "SYSASSERT", 0x35 }, 5577 { "UCODE_VERSION_MISMATCH", 0x37 }, 5578 { "BAD_COMMAND", 0x38 }, 5579 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, 5580 { "FATAL_ERROR", 0x3D }, 5581 { "NMI_TRM_HW_ERR", 0x46 }, 5582 { "NMI_INTERRUPT_TRM", 0x4C }, 5583 { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, 5584 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, 5585 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, 5586 { "NMI_INTERRUPT_HOST", 0x66 }, 5587 { "NMI_INTERRUPT_ACTION_PT", 0x7C }, 5588 { "NMI_INTERRUPT_UNKNOWN", 0x84 }, 5589 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, 5590 { "ADVANCED_SYSASSERT", 0 }, 5591 }; 5592 5593 static const char * 5594 iwm_desc_lookup(uint32_t num) 5595 { 5596 int i; 5597 5598 for (i = 0; i < nitems(advanced_lookup) - 1; i++) 5599 if (advanced_lookup[i].num == num) 5600 return advanced_lookup[i].name; 5601 5602 /* No entry matches 'num', so it is the last: ADVANCED_SYSASSERT */ 5603 return advanced_lookup[i].name; 5604 } 5605 5606 static void 5607 iwm_nic_umac_error(struct iwm_softc *sc) 5608 { 5609 struct iwm_umac_error_event_table table; 5610 uint32_t base; 5611 5612 base = sc->umac_error_event_table; 5613 5614 if (base < 0x800000) { 5615 device_printf(sc->sc_dev, "Invalid error log pointer 0x%08x\n", 5616 base); 5617 return; 5618 } 5619 5620 if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) { 5621 device_printf(sc->sc_dev, "reading errlog failed\n"); 5622 return; 5623 } 5624 5625 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 5626 device_printf(sc->sc_dev, "Start UMAC Error Log Dump:\n"); 5627 device_printf(sc->sc_dev, "Status: 0x%x, count: %d\n", 5628 sc->sc_flags, table.valid); 5629 } 5630 5631 device_printf(sc->sc_dev, "0x%08X | %s\n", table.error_id, 5632 iwm_desc_lookup(table.error_id)); 5633 device_printf(sc->sc_dev, "0x%08X | umac branchlink1\n", table.blink1); 5634 device_printf(sc->sc_dev, "0x%08X | umac branchlink2\n", table.blink2); 5635 device_printf(sc->sc_dev, "0x%08X | umac interruptlink1\n", 5636 table.ilink1); 5637 device_printf(sc->sc_dev, "0x%08X | umac interruptlink2\n", 5638 table.ilink2); 5639 device_printf(sc->sc_dev, "0x%08X | umac data1\n", table.data1); 5640 device_printf(sc->sc_dev, "0x%08X | umac data2\n", table.data2); 5641 device_printf(sc->sc_dev, "0x%08X | umac data3\n", table.data3); 5642 device_printf(sc->sc_dev, "0x%08X | umac major\n", table.umac_major); 5643 device_printf(sc->sc_dev, "0x%08X | umac minor\n", table.umac_minor); 5644 device_printf(sc->sc_dev, "0x%08X | frame pointer\n", 5645 table.frame_pointer); 5646 device_printf(sc->sc_dev, "0x%08X | stack pointer\n", 5647 table.stack_pointer); 5648 device_printf(sc->sc_dev, "0x%08X | last host cmd\n", table.cmd_header); 5649 device_printf(sc->sc_dev, "0x%08X | isr status reg\n", 5650 table.nic_isr_pref); 5651 } 5652 5653 /* 5654 * Support for dumping the error log seemed like a good idea ... 5655 * but it's mostly hex junk and the only sensible thing is the 5656 * hw/ucode revision (which we know anyway). Since it's here, 5657 * I'll just leave it in, just in case e.g. the Intel guys want to 5658 * help us decipher some "ADVANCED_SYSASSERT" later. 5659 */ 5660 static void 5661 iwm_nic_error(struct iwm_softc *sc) 5662 { 5663 struct iwm_error_event_table table; 5664 uint32_t base; 5665 5666 device_printf(sc->sc_dev, "dumping device error log\n"); 5667 base = sc->error_event_table[0]; 5668 if (base < 0x800000) { 5669 device_printf(sc->sc_dev, 5670 "Invalid error log pointer 0x%08x\n", base); 5671 return; 5672 } 5673 5674 if (iwm_read_mem(sc, base, &table, sizeof(table)/sizeof(uint32_t))) { 5675 device_printf(sc->sc_dev, "reading errlog failed\n"); 5676 return; 5677 } 5678 5679 if (!table.valid) { 5680 device_printf(sc->sc_dev, "errlog not found, skipping\n"); 5681 return; 5682 } 5683 5684 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 5685 device_printf(sc->sc_dev, "Start Error Log Dump:\n"); 5686 device_printf(sc->sc_dev, "Status: 0x%x, count: %d\n", 5687 sc->sc_flags, table.valid); 5688 } 5689 5690 device_printf(sc->sc_dev, "0x%08X | %-28s\n", table.error_id, 5691 iwm_desc_lookup(table.error_id)); 5692 device_printf(sc->sc_dev, "%08X | trm_hw_status0\n", 5693 table.trm_hw_status0); 5694 device_printf(sc->sc_dev, "%08X | trm_hw_status1\n", 5695 table.trm_hw_status1); 5696 device_printf(sc->sc_dev, "%08X | branchlink2\n", table.blink2); 5697 device_printf(sc->sc_dev, "%08X | interruptlink1\n", table.ilink1); 5698 device_printf(sc->sc_dev, "%08X | interruptlink2\n", table.ilink2); 5699 device_printf(sc->sc_dev, "%08X | data1\n", table.data1); 5700 device_printf(sc->sc_dev, "%08X | data2\n", table.data2); 5701 device_printf(sc->sc_dev, "%08X | data3\n", table.data3); 5702 device_printf(sc->sc_dev, "%08X | beacon time\n", table.bcon_time); 5703 device_printf(sc->sc_dev, "%08X | tsf low\n", table.tsf_low); 5704 device_printf(sc->sc_dev, "%08X | tsf hi\n", table.tsf_hi); 5705 device_printf(sc->sc_dev, "%08X | time gp1\n", table.gp1); 5706 device_printf(sc->sc_dev, "%08X | time gp2\n", table.gp2); 5707 device_printf(sc->sc_dev, "%08X | uCode revision type\n", 5708 table.fw_rev_type); 5709 device_printf(sc->sc_dev, "%08X | uCode version major\n", table.major); 5710 device_printf(sc->sc_dev, "%08X | uCode version minor\n", table.minor); 5711 device_printf(sc->sc_dev, "%08X | hw version\n", table.hw_ver); 5712 device_printf(sc->sc_dev, "%08X | board version\n", table.brd_ver); 5713 device_printf(sc->sc_dev, "%08X | hcmd\n", table.hcmd); 5714 device_printf(sc->sc_dev, "%08X | isr0\n", table.isr0); 5715 device_printf(sc->sc_dev, "%08X | isr1\n", table.isr1); 5716 device_printf(sc->sc_dev, "%08X | isr2\n", table.isr2); 5717 device_printf(sc->sc_dev, "%08X | isr3\n", table.isr3); 5718 device_printf(sc->sc_dev, "%08X | isr4\n", table.isr4); 5719 device_printf(sc->sc_dev, "%08X | last cmd Id\n", table.last_cmd_id); 5720 device_printf(sc->sc_dev, "%08X | wait_event\n", table.wait_event); 5721 device_printf(sc->sc_dev, "%08X | l2p_control\n", table.l2p_control); 5722 device_printf(sc->sc_dev, "%08X | l2p_duration\n", table.l2p_duration); 5723 device_printf(sc->sc_dev, "%08X | l2p_mhvalid\n", table.l2p_mhvalid); 5724 device_printf(sc->sc_dev, "%08X | l2p_addr_match\n", table.l2p_addr_match); 5725 device_printf(sc->sc_dev, "%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel); 5726 device_printf(sc->sc_dev, "%08X | timestamp\n", table.u_timestamp); 5727 device_printf(sc->sc_dev, "%08X | flow_handler\n", table.flow_handler); 5728 5729 if (sc->umac_error_event_table) 5730 iwm_nic_umac_error(sc); 5731 } 5732 #endif 5733 5734 static void 5735 iwm_handle_rxb(struct iwm_softc *sc, struct mbuf *m) 5736 { 5737 struct ieee80211com *ic = &sc->sc_ic; 5738 struct iwm_cmd_response *cresp; 5739 struct mbuf *m1; 5740 uint32_t offset = 0; 5741 uint32_t maxoff = IWM_RBUF_SIZE; 5742 uint32_t nextoff; 5743 boolean_t stolen = FALSE; 5744 5745 #define HAVEROOM(a) \ 5746 ((a) + sizeof(uint32_t) + sizeof(struct iwm_cmd_header) < maxoff) 5747 5748 while (HAVEROOM(offset)) { 5749 struct iwm_rx_packet *pkt = mtodoff(m, struct iwm_rx_packet *, 5750 offset); 5751 int qid, idx, code, len; 5752 5753 qid = pkt->hdr.qid; 5754 idx = pkt->hdr.idx; 5755 5756 code = IWM_WIDE_ID(pkt->hdr.flags, pkt->hdr.code); 5757 5758 /* 5759 * randomly get these from the firmware, no idea why. 5760 * they at least seem harmless, so just ignore them for now 5761 */ 5762 if ((pkt->hdr.code == 0 && (qid & ~0x80) == 0 && idx == 0) || 5763 pkt->len_n_flags == htole32(IWM_FH_RSCSR_FRAME_INVALID)) { 5764 break; 5765 } 5766 5767 IWM_DPRINTF(sc, IWM_DEBUG_INTR, 5768 "rx packet qid=%d idx=%d type=%x\n", 5769 qid & ~0x80, pkt->hdr.idx, code); 5770 5771 len = iwm_rx_packet_len(pkt); 5772 len += sizeof(uint32_t); /* account for status word */ 5773 nextoff = offset + roundup2(len, IWM_FH_RSCSR_FRAME_ALIGN); 5774 5775 iwm_notification_wait_notify(sc->sc_notif_wait, code, pkt); 5776 5777 switch (code) { 5778 case IWM_REPLY_RX_PHY_CMD: 5779 iwm_rx_rx_phy_cmd(sc, pkt); 5780 break; 5781 5782 case IWM_REPLY_RX_MPDU_CMD: { 5783 /* 5784 * If this is the last frame in the RX buffer, we 5785 * can directly feed the mbuf to the sharks here. 5786 */ 5787 struct iwm_rx_packet *nextpkt = mtodoff(m, 5788 struct iwm_rx_packet *, nextoff); 5789 if (!HAVEROOM(nextoff) || 5790 (nextpkt->hdr.code == 0 && 5791 (nextpkt->hdr.qid & ~0x80) == 0 && 5792 nextpkt->hdr.idx == 0) || 5793 (nextpkt->len_n_flags == 5794 htole32(IWM_FH_RSCSR_FRAME_INVALID))) { 5795 if (iwm_rx_mpdu(sc, m, offset, stolen)) { 5796 stolen = FALSE; 5797 /* Make sure we abort the loop */ 5798 nextoff = maxoff; 5799 } 5800 break; 5801 } 5802 5803 /* 5804 * Use m_copym instead of m_split, because that 5805 * makes it easier to keep a valid rx buffer in 5806 * the ring, when iwm_rx_mpdu() fails. 5807 * 5808 * We need to start m_copym() at offset 0, to get the 5809 * M_PKTHDR flag preserved. 5810 */ 5811 m1 = m_copym(m, 0, M_COPYALL, M_NOWAIT); 5812 if (m1) { 5813 if (iwm_rx_mpdu(sc, m1, offset, stolen)) 5814 stolen = TRUE; 5815 else 5816 m_freem(m1); 5817 } 5818 break; 5819 } 5820 5821 case IWM_TX_CMD: 5822 iwm_rx_tx_cmd(sc, pkt); 5823 break; 5824 5825 case IWM_MISSED_BEACONS_NOTIFICATION: { 5826 struct iwm_missed_beacons_notif *resp; 5827 int missed; 5828 5829 /* XXX look at mac_id to determine interface ID */ 5830 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5831 5832 resp = (void *)pkt->data; 5833 missed = le32toh(resp->consec_missed_beacons); 5834 5835 IWM_DPRINTF(sc, IWM_DEBUG_BEACON | IWM_DEBUG_STATE, 5836 "%s: MISSED_BEACON: mac_id=%d, " 5837 "consec_since_last_rx=%d, consec=%d, num_expect=%d " 5838 "num_rx=%d\n", 5839 __func__, 5840 le32toh(resp->mac_id), 5841 le32toh(resp->consec_missed_beacons_since_last_rx), 5842 le32toh(resp->consec_missed_beacons), 5843 le32toh(resp->num_expected_beacons), 5844 le32toh(resp->num_recvd_beacons)); 5845 5846 /* Be paranoid */ 5847 if (vap == NULL) 5848 break; 5849 5850 /* XXX no net80211 locking? */ 5851 if (vap->iv_state == IEEE80211_S_RUN && 5852 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 5853 if (missed > vap->iv_bmissthreshold) { 5854 /* XXX bad locking; turn into task */ 5855 IWM_UNLOCK(sc); 5856 ieee80211_beacon_miss(ic); 5857 IWM_LOCK(sc); 5858 } 5859 } 5860 5861 break; 5862 } 5863 5864 case IWM_MFUART_LOAD_NOTIFICATION: 5865 break; 5866 5867 case IWM_ALIVE: 5868 break; 5869 5870 case IWM_CALIB_RES_NOTIF_PHY_DB: 5871 break; 5872 5873 case IWM_STATISTICS_NOTIFICATION: 5874 iwm_handle_rx_statistics(sc, pkt); 5875 break; 5876 5877 case IWM_NVM_ACCESS_CMD: 5878 case IWM_MCC_UPDATE_CMD: 5879 if (sc->sc_wantresp == (((qid & ~0x80) << 16) | idx)) { 5880 memcpy(sc->sc_cmd_resp, 5881 pkt, sizeof(sc->sc_cmd_resp)); 5882 } 5883 break; 5884 5885 case IWM_MCC_CHUB_UPDATE_CMD: { 5886 struct iwm_mcc_chub_notif *notif; 5887 notif = (void *)pkt->data; 5888 5889 sc->sc_fw_mcc[0] = (notif->mcc & 0xff00) >> 8; 5890 sc->sc_fw_mcc[1] = notif->mcc & 0xff; 5891 sc->sc_fw_mcc[2] = '\0'; 5892 IWM_DPRINTF(sc, IWM_DEBUG_LAR, 5893 "fw source %d sent CC '%s'\n", 5894 notif->source_id, sc->sc_fw_mcc); 5895 break; 5896 } 5897 5898 case IWM_DTS_MEASUREMENT_NOTIFICATION: 5899 case IWM_WIDE_ID(IWM_PHY_OPS_GROUP, 5900 IWM_DTS_MEASUREMENT_NOTIF_WIDE): { 5901 struct iwm_dts_measurement_notif_v1 *notif; 5902 5903 if (iwm_rx_packet_payload_len(pkt) < sizeof(*notif)) { 5904 device_printf(sc->sc_dev, 5905 "Invalid DTS_MEASUREMENT_NOTIFICATION\n"); 5906 break; 5907 } 5908 notif = (void *)pkt->data; 5909 IWM_DPRINTF(sc, IWM_DEBUG_TEMP, 5910 "IWM_DTS_MEASUREMENT_NOTIFICATION - %d\n", 5911 notif->temp); 5912 break; 5913 } 5914 5915 case IWM_PHY_CONFIGURATION_CMD: 5916 case IWM_TX_ANT_CONFIGURATION_CMD: 5917 case IWM_ADD_STA: 5918 case IWM_MAC_CONTEXT_CMD: 5919 case IWM_REPLY_SF_CFG_CMD: 5920 case IWM_POWER_TABLE_CMD: 5921 case IWM_LTR_CONFIG: 5922 case IWM_PHY_CONTEXT_CMD: 5923 case IWM_BINDING_CONTEXT_CMD: 5924 case IWM_TIME_EVENT_CMD: 5925 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_CFG_CMD): 5926 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_REQ_UMAC): 5927 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, IWM_SCAN_ABORT_UMAC): 5928 case IWM_SCAN_OFFLOAD_REQUEST_CMD: 5929 case IWM_SCAN_OFFLOAD_ABORT_CMD: 5930 case IWM_REPLY_BEACON_FILTERING_CMD: 5931 case IWM_MAC_PM_POWER_TABLE: 5932 case IWM_TIME_QUOTA_CMD: 5933 case IWM_REMOVE_STA: 5934 case IWM_TXPATH_FLUSH: 5935 case IWM_LQ_CMD: 5936 case IWM_WIDE_ID(IWM_ALWAYS_LONG_GROUP, 5937 IWM_FW_PAGING_BLOCK_CMD): 5938 case IWM_BT_CONFIG: 5939 case IWM_REPLY_THERMAL_MNG_BACKOFF: 5940 cresp = (void *)pkt->data; 5941 if (sc->sc_wantresp == (((qid & ~0x80) << 16) | idx)) { 5942 memcpy(sc->sc_cmd_resp, 5943 pkt, sizeof(*pkt)+sizeof(*cresp)); 5944 } 5945 break; 5946 5947 /* ignore */ 5948 case IWM_PHY_DB_CMD: 5949 break; 5950 5951 case IWM_INIT_COMPLETE_NOTIF: 5952 break; 5953 5954 case IWM_SCAN_OFFLOAD_COMPLETE: 5955 iwm_rx_lmac_scan_complete_notif(sc, pkt); 5956 if (sc->sc_flags & IWM_FLAG_SCAN_RUNNING) { 5957 sc->sc_flags &= ~IWM_FLAG_SCAN_RUNNING; 5958 ieee80211_runtask(ic, &sc->sc_es_task); 5959 } 5960 break; 5961 5962 case IWM_SCAN_ITERATION_COMPLETE: { 5963 break; 5964 } 5965 5966 case IWM_SCAN_COMPLETE_UMAC: 5967 iwm_rx_umac_scan_complete_notif(sc, pkt); 5968 if (sc->sc_flags & IWM_FLAG_SCAN_RUNNING) { 5969 sc->sc_flags &= ~IWM_FLAG_SCAN_RUNNING; 5970 ieee80211_runtask(ic, &sc->sc_es_task); 5971 } 5972 break; 5973 5974 case IWM_SCAN_ITERATION_COMPLETE_UMAC: { 5975 #ifdef IWM_DEBUG 5976 struct iwm_umac_scan_iter_complete_notif *notif; 5977 notif = (void *)pkt->data; 5978 5979 IWM_DPRINTF(sc, IWM_DEBUG_SCAN, "UMAC scan iteration " 5980 "complete, status=0x%x, %d channels scanned\n", 5981 notif->status, notif->scanned_channels); 5982 #endif 5983 break; 5984 } 5985 5986 case IWM_REPLY_ERROR: { 5987 struct iwm_error_resp *resp; 5988 resp = (void *)pkt->data; 5989 5990 device_printf(sc->sc_dev, 5991 "firmware error 0x%x, cmd 0x%x\n", 5992 le32toh(resp->error_type), 5993 resp->cmd_id); 5994 break; 5995 } 5996 5997 case IWM_TIME_EVENT_NOTIFICATION: 5998 iwm_rx_time_event_notif(sc, pkt); 5999 break; 6000 6001 /* 6002 * Firmware versions 21 and 22 generate some DEBUG_LOG_MSG 6003 * messages. Just ignore them for now. 6004 */ 6005 case IWM_DEBUG_LOG_MSG: 6006 break; 6007 6008 case IWM_MCAST_FILTER_CMD: 6009 break; 6010 6011 case IWM_SCD_QUEUE_CFG: { 6012 #ifdef IWM_DEBUG 6013 struct iwm_scd_txq_cfg_rsp *rsp; 6014 rsp = (void *)pkt->data; 6015 6016 IWM_DPRINTF(sc, IWM_DEBUG_CMD, 6017 "queue cfg token=0x%x sta_id=%d " 6018 "tid=%d scd_queue=%d\n", 6019 rsp->token, rsp->sta_id, rsp->tid, 6020 rsp->scd_queue); 6021 #endif 6022 break; 6023 } 6024 6025 default: 6026 device_printf(sc->sc_dev, 6027 "code %x, frame %d/%d %x unhandled\n", 6028 code, qid & ~0x80, idx, pkt->len_n_flags); 6029 break; 6030 } 6031 6032 /* 6033 * Why test bit 0x80? The Linux driver: 6034 * 6035 * There is one exception: uCode sets bit 15 when it 6036 * originates the response/notification, i.e. when the 6037 * response/notification is not a direct response to a 6038 * command sent by the driver. For example, uCode issues 6039 * IWM_REPLY_RX when it sends a received frame to the driver; 6040 * it is not a direct response to any driver command. 6041 * 6042 * Ok, so since when is 7 == 15? Well, the Linux driver 6043 * uses a slightly different format for pkt->hdr, and "qid" 6044 * is actually the upper byte of a two-byte field. 6045 */ 6046 if (!(qid & (1 << 7))) 6047 iwm_cmd_done(sc, pkt); 6048 6049 offset = nextoff; 6050 } 6051 if (stolen) 6052 m_freem(m); 6053 #undef HAVEROOM 6054 } 6055 6056 /* 6057 * Process an IWM_CSR_INT_BIT_FH_RX or IWM_CSR_INT_BIT_SW_RX interrupt. 6058 * Basic structure from if_iwn 6059 */ 6060 static void 6061 iwm_notif_intr(struct iwm_softc *sc) 6062 { 6063 int count; 6064 uint32_t wreg; 6065 uint16_t hw; 6066 6067 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 6068 BUS_DMASYNC_POSTREAD); 6069 6070 if (sc->cfg->mqrx_supported) { 6071 count = IWM_RX_MQ_RING_COUNT; 6072 wreg = IWM_RFH_Q0_FRBDCB_WIDX_TRG; 6073 } else { 6074 count = IWM_RX_LEGACY_RING_COUNT; 6075 wreg = IWM_FH_RSCSR_CHNL0_WPTR; 6076 } 6077 6078 hw = le16toh(sc->rxq.stat->closed_rb_num) & 0xfff; 6079 6080 /* 6081 * Process responses 6082 */ 6083 while (sc->rxq.cur != hw) { 6084 struct iwm_rx_ring *ring = &sc->rxq; 6085 struct iwm_rx_data *data = &ring->data[ring->cur]; 6086 6087 bus_dmamap_sync(ring->data_dmat, data->map, 6088 BUS_DMASYNC_POSTREAD); 6089 6090 IWM_DPRINTF(sc, IWM_DEBUG_INTR, 6091 "%s: hw = %d cur = %d\n", __func__, hw, ring->cur); 6092 iwm_handle_rxb(sc, data->m); 6093 6094 ring->cur = (ring->cur + 1) % count; 6095 } 6096 6097 /* 6098 * Tell the firmware that it can reuse the ring entries that 6099 * we have just processed. 6100 * Seems like the hardware gets upset unless we align 6101 * the write by 8?? 6102 */ 6103 hw = (hw == 0) ? count - 1 : hw - 1; 6104 IWM_WRITE(sc, wreg, rounddown2(hw, 8)); 6105 } 6106 6107 static void 6108 iwm_intr(void *arg) 6109 { 6110 struct iwm_softc *sc = arg; 6111 int handled = 0; 6112 int r1, r2; 6113 int isperiodic = 0; 6114 6115 IWM_LOCK(sc); 6116 IWM_WRITE(sc, IWM_CSR_INT_MASK, 0); 6117 6118 if (sc->sc_flags & IWM_FLAG_USE_ICT) { 6119 uint32_t *ict = sc->ict_dma.vaddr; 6120 int tmp; 6121 6122 tmp = htole32(ict[sc->ict_cur]); 6123 if (!tmp) 6124 goto out_ena; 6125 6126 /* 6127 * ok, there was something. keep plowing until we have all. 6128 */ 6129 r1 = r2 = 0; 6130 while (tmp) { 6131 r1 |= tmp; 6132 ict[sc->ict_cur] = 0; 6133 sc->ict_cur = (sc->ict_cur+1) % IWM_ICT_COUNT; 6134 tmp = htole32(ict[sc->ict_cur]); 6135 } 6136 6137 /* this is where the fun begins. don't ask */ 6138 if (r1 == 0xffffffff) 6139 r1 = 0; 6140 6141 /* i am not expected to understand this */ 6142 if (r1 & 0xc0000) 6143 r1 |= 0x8000; 6144 r1 = (0xff & r1) | ((0xff00 & r1) << 16); 6145 } else { 6146 r1 = IWM_READ(sc, IWM_CSR_INT); 6147 /* "hardware gone" (where, fishing?) */ 6148 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 6149 goto out; 6150 r2 = IWM_READ(sc, IWM_CSR_FH_INT_STATUS); 6151 } 6152 if (r1 == 0 && r2 == 0) { 6153 goto out_ena; 6154 } 6155 6156 IWM_WRITE(sc, IWM_CSR_INT, r1 | ~sc->sc_intmask); 6157 6158 /* Safely ignore these bits for debug checks below */ 6159 r1 &= ~(IWM_CSR_INT_BIT_ALIVE | IWM_CSR_INT_BIT_SCD); 6160 6161 if (r1 & IWM_CSR_INT_BIT_SW_ERR) { 6162 int i; 6163 struct ieee80211com *ic = &sc->sc_ic; 6164 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6165 6166 #ifdef IWM_DEBUG 6167 iwm_nic_error(sc); 6168 #endif 6169 /* Dump driver status (TX and RX rings) while we're here. */ 6170 device_printf(sc->sc_dev, "driver status:\n"); 6171 for (i = 0; i < IWM_MAX_QUEUES; i++) { 6172 struct iwm_tx_ring *ring = &sc->txq[i]; 6173 device_printf(sc->sc_dev, 6174 " tx ring %2d: qid=%-2d cur=%-3d " 6175 "queued=%-3d\n", 6176 i, ring->qid, ring->cur, ring->queued); 6177 } 6178 device_printf(sc->sc_dev, 6179 " rx ring: cur=%d\n", sc->rxq.cur); 6180 device_printf(sc->sc_dev, 6181 " 802.11 state %d\n", (vap == NULL) ? -1 : vap->iv_state); 6182 6183 /* Reset our firmware state tracking. */ 6184 sc->sc_firmware_state = 0; 6185 /* Don't stop the device; just do a VAP restart */ 6186 IWM_UNLOCK(sc); 6187 6188 if (vap == NULL) { 6189 printf("%s: null vap\n", __func__); 6190 return; 6191 } 6192 6193 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 6194 "restarting\n", __func__, vap->iv_state); 6195 6196 ieee80211_restart_all(ic); 6197 return; 6198 } 6199 6200 if (r1 & IWM_CSR_INT_BIT_HW_ERR) { 6201 handled |= IWM_CSR_INT_BIT_HW_ERR; 6202 device_printf(sc->sc_dev, "hardware error, stopping device\n"); 6203 iwm_stop(sc); 6204 goto out; 6205 } 6206 6207 /* firmware chunk loaded */ 6208 if (r1 & IWM_CSR_INT_BIT_FH_TX) { 6209 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_TX_MASK); 6210 handled |= IWM_CSR_INT_BIT_FH_TX; 6211 sc->sc_fw_chunk_done = 1; 6212 wakeup(&sc->sc_fw); 6213 } 6214 6215 if (r1 & IWM_CSR_INT_BIT_RF_KILL) { 6216 handled |= IWM_CSR_INT_BIT_RF_KILL; 6217 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 6218 } 6219 6220 /* 6221 * The Linux driver uses periodic interrupts to avoid races. 6222 * We cargo-cult like it's going out of fashion. 6223 */ 6224 if (r1 & IWM_CSR_INT_BIT_RX_PERIODIC) { 6225 handled |= IWM_CSR_INT_BIT_RX_PERIODIC; 6226 IWM_WRITE(sc, IWM_CSR_INT, IWM_CSR_INT_BIT_RX_PERIODIC); 6227 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) == 0) 6228 IWM_WRITE_1(sc, 6229 IWM_CSR_INT_PERIODIC_REG, IWM_CSR_INT_PERIODIC_DIS); 6230 isperiodic = 1; 6231 } 6232 6233 if ((r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX)) || isperiodic) { 6234 handled |= (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX); 6235 IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_RX_MASK); 6236 6237 iwm_notif_intr(sc); 6238 6239 /* enable periodic interrupt, see above */ 6240 if (r1 & (IWM_CSR_INT_BIT_FH_RX | IWM_CSR_INT_BIT_SW_RX) && !isperiodic) 6241 IWM_WRITE_1(sc, IWM_CSR_INT_PERIODIC_REG, 6242 IWM_CSR_INT_PERIODIC_ENA); 6243 } 6244 6245 if (__predict_false(r1 & ~handled)) 6246 IWM_DPRINTF(sc, IWM_DEBUG_INTR, 6247 "%s: unhandled interrupts: %x\n", __func__, r1); 6248 out_ena: 6249 iwm_restore_interrupts(sc); 6250 out: 6251 IWM_UNLOCK(sc); 6252 return; 6253 } 6254 6255 static void 6256 iwm_intr_msix(void *arg) 6257 { 6258 struct iwm_softc *sc = arg; 6259 uint32_t inta_fh, inta_hw; 6260 int vector = 0; 6261 6262 IWM_LOCK(sc); 6263 6264 inta_fh = IWM_READ(sc, IWM_CSR_MSIX_FH_INT_CAUSES_AD); 6265 inta_hw = IWM_READ(sc, IWM_CSR_MSIX_HW_INT_CAUSES_AD); 6266 /* acknowledge all interrupts */ 6267 IWM_WRITE(sc, IWM_CSR_MSIX_FH_INT_CAUSES_AD, inta_fh); 6268 IWM_WRITE(sc, IWM_CSR_MSIX_HW_INT_CAUSES_AD, inta_hw); 6269 inta_fh &= sc->sc_fh_mask; 6270 inta_hw &= sc->sc_hw_mask; 6271 6272 if (inta_fh & IWM_MSIX_FH_INT_CAUSES_Q0 || 6273 inta_fh & IWM_MSIX_FH_INT_CAUSES_Q1) 6274 iwm_notif_intr(sc); 6275 6276 /* firmware chunk loaded */ 6277 if (inta_fh & IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM) { 6278 sc->sc_fw_chunk_done = 1; 6279 wakeup(&sc->sc_fw); 6280 } 6281 6282 if ((inta_fh & IWM_MSIX_FH_INT_CAUSES_FH_ERR) || 6283 (inta_hw & IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR) || 6284 (inta_hw & IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2)) { 6285 struct ieee80211com *ic = &sc->sc_ic; 6286 struct ieee80211vap *vap; 6287 int i; 6288 6289 #ifdef IWM_DEBUG 6290 iwm_nic_error(sc); 6291 #endif 6292 /* Dump driver status (TX and RX rings) while we're here. */ 6293 device_printf(sc->sc_dev, "driver status:\n"); 6294 for (i = 0; i < IWM_MAX_QUEUES; i++) { 6295 struct iwm_tx_ring *ring = &sc->txq[i]; 6296 device_printf(sc->sc_dev, 6297 " tx ring %2d: qid=%-2d cur=%-3d " 6298 "queued=%-3d\n", 6299 i, ring->qid, ring->cur, ring->queued); 6300 } 6301 device_printf(sc->sc_dev, " rx ring: cur=%d\n", sc->rxq.cur); 6302 6303 /* Reset our firmware state tracking. */ 6304 sc->sc_firmware_state = 0; 6305 IWM_UNLOCK(sc); 6306 6307 vap = TAILQ_FIRST(&ic->ic_vaps); 6308 if (vap == NULL) { 6309 printf("%s: null vap\n", __func__); 6310 return; 6311 } 6312 6313 device_printf(sc->sc_dev, 6314 "%s: controller panicked, iv_state = %d; restarting\n", 6315 __func__, vap->iv_state); 6316 6317 ieee80211_restart_all(ic); 6318 return; 6319 } 6320 6321 if (inta_hw & IWM_MSIX_HW_INT_CAUSES_REG_RF_KILL) 6322 taskqueue_enqueue(sc->sc_tq, &sc->sc_rftoggle_task); 6323 6324 if (inta_hw & IWM_MSIX_HW_INT_CAUSES_REG_HW_ERR) { 6325 device_printf(sc->sc_dev, "hardware error, stopping device\n"); 6326 iwm_stop(sc); 6327 goto out; 6328 } 6329 6330 /* 6331 * Before sending the interrupt the HW disables it to prevent 6332 * a nested interrupt. This is done by writing 1 to the 6333 * corresponding bit in the mask register. After handling the 6334 * interrupt, it should be re-enabled by clearing this bit. 6335 * This register is defined as a write 1 clear (W1C) register, 6336 * meaning that it's being cleared by writing 1 to the bit. 6337 */ 6338 IWM_WRITE(sc, IWM_CSR_MSIX_AUTOMASK_ST_AD, 1 << vector); 6339 6340 out: 6341 IWM_UNLOCK(sc); 6342 } 6343 6344 /* 6345 * Autoconf glue-sniffing 6346 */ 6347 #define PCI_VENDOR_INTEL 0x8086 6348 #define PCI_PRODUCT_INTEL_WL_3160_1 0x08b3 6349 #define PCI_PRODUCT_INTEL_WL_3160_2 0x08b4 6350 #define PCI_PRODUCT_INTEL_WL_3165_1 0x3165 6351 #define PCI_PRODUCT_INTEL_WL_3165_2 0x3166 6352 #define PCI_PRODUCT_INTEL_WL_3168_1 0x24fb 6353 #define PCI_PRODUCT_INTEL_WL_7260_1 0x08b1 6354 #define PCI_PRODUCT_INTEL_WL_7260_2 0x08b2 6355 #define PCI_PRODUCT_INTEL_WL_7265_1 0x095a 6356 #define PCI_PRODUCT_INTEL_WL_7265_2 0x095b 6357 #define PCI_PRODUCT_INTEL_WL_8260_1 0x24f3 6358 #define PCI_PRODUCT_INTEL_WL_8260_2 0x24f4 6359 #define PCI_PRODUCT_INTEL_WL_8265_1 0x24fd 6360 #define PCI_PRODUCT_INTEL_WL_9560_1 0x9df0 6361 #define PCI_PRODUCT_INTEL_WL_9560_2 0xa370 6362 #define PCI_PRODUCT_INTEL_WL_9560_3 0x31dc 6363 #define PCI_PRODUCT_INTEL_WL_9260_1 0x2526 6364 6365 static const struct iwm_devices { 6366 uint16_t device; 6367 const struct iwm_cfg *cfg; 6368 } iwm_devices[] = { 6369 { PCI_PRODUCT_INTEL_WL_3160_1, &iwm3160_cfg }, 6370 { PCI_PRODUCT_INTEL_WL_3160_2, &iwm3160_cfg }, 6371 { PCI_PRODUCT_INTEL_WL_3165_1, &iwm3165_cfg }, 6372 { PCI_PRODUCT_INTEL_WL_3165_2, &iwm3165_cfg }, 6373 { PCI_PRODUCT_INTEL_WL_3168_1, &iwm3168_cfg }, 6374 { PCI_PRODUCT_INTEL_WL_7260_1, &iwm7260_cfg }, 6375 { PCI_PRODUCT_INTEL_WL_7260_2, &iwm7260_cfg }, 6376 { PCI_PRODUCT_INTEL_WL_7265_1, &iwm7265_cfg }, 6377 { PCI_PRODUCT_INTEL_WL_7265_2, &iwm7265_cfg }, 6378 { PCI_PRODUCT_INTEL_WL_8260_1, &iwm8260_cfg }, 6379 { PCI_PRODUCT_INTEL_WL_8260_2, &iwm8260_cfg }, 6380 { PCI_PRODUCT_INTEL_WL_8265_1, &iwm8265_cfg }, 6381 { PCI_PRODUCT_INTEL_WL_9560_1, &iwm9560_cfg }, 6382 { PCI_PRODUCT_INTEL_WL_9560_2, &iwm9560_cfg }, 6383 { PCI_PRODUCT_INTEL_WL_9560_3, &iwm9560_cfg }, 6384 { PCI_PRODUCT_INTEL_WL_9260_1, &iwm9260_cfg }, 6385 }; 6386 6387 static int 6388 iwm_probe(device_t dev) 6389 { 6390 int i; 6391 6392 for (i = 0; i < nitems(iwm_devices); i++) { 6393 if (pci_get_vendor(dev) == PCI_VENDOR_INTEL && 6394 pci_get_device(dev) == iwm_devices[i].device) { 6395 device_set_desc(dev, iwm_devices[i].cfg->name); 6396 return (BUS_PROBE_DEFAULT); 6397 } 6398 } 6399 6400 return (ENXIO); 6401 } 6402 6403 static int 6404 iwm_dev_check(device_t dev) 6405 { 6406 struct iwm_softc *sc; 6407 uint16_t devid; 6408 int i; 6409 6410 sc = device_get_softc(dev); 6411 6412 devid = pci_get_device(dev); 6413 for (i = 0; i < nitems(iwm_devices); i++) { 6414 if (iwm_devices[i].device == devid) { 6415 sc->cfg = iwm_devices[i].cfg; 6416 return (0); 6417 } 6418 } 6419 device_printf(dev, "unknown adapter type\n"); 6420 return ENXIO; 6421 } 6422 6423 /* PCI registers */ 6424 #define PCI_CFG_RETRY_TIMEOUT 0x041 6425 6426 static int 6427 iwm_pci_attach(device_t dev) 6428 { 6429 struct iwm_softc *sc; 6430 int count, error, rid; 6431 uint16_t reg; 6432 6433 sc = device_get_softc(dev); 6434 6435 /* We disable the RETRY_TIMEOUT register (0x41) to keep 6436 * PCI Tx retries from interfering with C3 CPU state */ 6437 pci_write_config(dev, PCI_CFG_RETRY_TIMEOUT, 0x00, 1); 6438 6439 /* Enable bus-mastering and hardware bug workaround. */ 6440 pci_enable_busmaster(dev); 6441 reg = pci_read_config(dev, PCIR_STATUS, sizeof(reg)); 6442 /* if !MSI */ 6443 if (reg & PCIM_STATUS_INTxSTATE) { 6444 reg &= ~PCIM_STATUS_INTxSTATE; 6445 } 6446 pci_write_config(dev, PCIR_STATUS, reg, sizeof(reg)); 6447 6448 rid = PCIR_BAR(0); 6449 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 6450 RF_ACTIVE); 6451 if (sc->sc_mem == NULL) { 6452 device_printf(sc->sc_dev, "can't map mem space\n"); 6453 return (ENXIO); 6454 } 6455 sc->sc_st = rman_get_bustag(sc->sc_mem); 6456 sc->sc_sh = rman_get_bushandle(sc->sc_mem); 6457 6458 /* Install interrupt handler. */ 6459 count = 1; 6460 rid = 0; 6461 if (pci_alloc_msix(dev, &count) == 0) { 6462 rid = 1; 6463 sc->sc_msix = 1; 6464 } else if (pci_alloc_msi(dev, &count) == 0) { 6465 rid = 1; 6466 } 6467 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 6468 (rid != 0 ? 0 : RF_SHAREABLE)); 6469 if (sc->sc_irq == NULL) { 6470 device_printf(dev, "can't map interrupt\n"); 6471 return (ENXIO); 6472 } 6473 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 6474 NULL, sc->sc_msix ? iwm_intr_msix : iwm_intr, sc, &sc->sc_ih); 6475 if (error != 0) { 6476 device_printf(dev, "can't establish interrupt"); 6477 return (error); 6478 } 6479 sc->sc_dmat = bus_get_dma_tag(sc->sc_dev); 6480 6481 return (0); 6482 } 6483 6484 static void 6485 iwm_pci_detach(device_t dev) 6486 { 6487 struct iwm_softc *sc = device_get_softc(dev); 6488 6489 if (sc->sc_irq != NULL) { 6490 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 6491 bus_release_resource(dev, SYS_RES_IRQ, 6492 rman_get_rid(sc->sc_irq), sc->sc_irq); 6493 pci_release_msi(dev); 6494 } 6495 if (sc->sc_mem != NULL) 6496 bus_release_resource(dev, SYS_RES_MEMORY, 6497 rman_get_rid(sc->sc_mem), sc->sc_mem); 6498 } 6499 6500 static int 6501 iwm_attach(device_t dev) 6502 { 6503 struct iwm_softc *sc = device_get_softc(dev); 6504 struct ieee80211com *ic = &sc->sc_ic; 6505 int error; 6506 int txq_i, i; 6507 6508 sc->sc_dev = dev; 6509 sc->sc_attached = 1; 6510 IWM_LOCK_INIT(sc); 6511 mbufq_init(&sc->sc_snd, ifqmaxlen); 6512 callout_init_mtx(&sc->sc_watchdog_to, &sc->sc_mtx, 0); 6513 callout_init_mtx(&sc->sc_led_blink_to, &sc->sc_mtx, 0); 6514 TASK_INIT(&sc->sc_es_task, 0, iwm_endscan_cb, sc); 6515 TASK_INIT(&sc->sc_rftoggle_task, 0, iwm_rftoggle_task, sc); 6516 6517 /* 6518 * Note: these would be per-ctx, but right now the driver 6519 * only knows about a single VAP. This mirrors what 6520 * OpenBSD iwm does to make porting/updating easier. 6521 */ 6522 TASK_INIT(&sc->mac_ctxt_task, 0, iwm_mac_ctxt_task, sc); 6523 TASK_INIT(&sc->phy_ctxt_task, 0, iwm_phy_ctxt_task, sc); 6524 6525 sc->sc_tq = taskqueue_create("iwm_taskq", M_WAITOK, 6526 taskqueue_thread_enqueue, &sc->sc_tq); 6527 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwm_taskq"); 6528 if (error != 0) { 6529 device_printf(dev, "can't start taskq thread, error %d\n", 6530 error); 6531 goto fail; 6532 } 6533 6534 error = iwm_dev_check(dev); 6535 if (error != 0) 6536 goto fail; 6537 6538 sc->sc_notif_wait = iwm_notification_wait_init(sc); 6539 if (sc->sc_notif_wait == NULL) { 6540 device_printf(dev, "failed to init notification wait struct\n"); 6541 goto fail; 6542 } 6543 6544 sc->sf_state = IWM_SF_UNINIT; 6545 6546 /* Init phy db */ 6547 sc->sc_phy_db = iwm_phy_db_init(sc); 6548 if (!sc->sc_phy_db) { 6549 device_printf(dev, "Cannot init phy_db\n"); 6550 goto fail; 6551 } 6552 6553 /* Set EBS as successful as long as not stated otherwise by the FW. */ 6554 sc->last_ebs_successful = TRUE; 6555 6556 /* PCI attach */ 6557 error = iwm_pci_attach(dev); 6558 if (error != 0) 6559 goto fail; 6560 6561 sc->sc_wantresp = -1; 6562 6563 sc->sc_hw_rev = IWM_READ(sc, IWM_CSR_HW_REV); 6564 /* 6565 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 6566 * changed, and now the revision step also includes bit 0-1 (no more 6567 * "dash" value). To keep hw_rev backwards compatible - we'll store it 6568 * in the old format. 6569 */ 6570 if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000) { 6571 int ret; 6572 uint32_t hw_step; 6573 6574 sc->sc_hw_rev = (sc->sc_hw_rev & 0xfff0) | 6575 (IWM_CSR_HW_REV_STEP(sc->sc_hw_rev << 2) << 2); 6576 6577 if (iwm_prepare_card_hw(sc) != 0) { 6578 device_printf(dev, "could not initialize hardware\n"); 6579 goto fail; 6580 } 6581 6582 /* 6583 * In order to recognize C step the driver should read the 6584 * chip version id located at the AUX bus MISC address. 6585 */ 6586 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 6587 IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 6588 DELAY(2); 6589 6590 ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 6591 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 6592 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 6593 25000); 6594 if (!ret) { 6595 device_printf(sc->sc_dev, 6596 "Failed to wake up the nic\n"); 6597 goto fail; 6598 } 6599 6600 if (iwm_nic_lock(sc)) { 6601 hw_step = iwm_read_prph(sc, IWM_WFPM_CTRL_REG); 6602 hw_step |= IWM_ENABLE_WFPM; 6603 iwm_write_prph(sc, IWM_WFPM_CTRL_REG, hw_step); 6604 hw_step = iwm_read_prph(sc, IWM_AUX_MISC_REG); 6605 hw_step = (hw_step >> IWM_HW_STEP_LOCATION_BITS) & 0xF; 6606 if (hw_step == 0x3) 6607 sc->sc_hw_rev = (sc->sc_hw_rev & 0xFFFFFFF3) | 6608 (IWM_SILICON_C_STEP << 2); 6609 iwm_nic_unlock(sc); 6610 } else { 6611 device_printf(sc->sc_dev, "Failed to lock the nic\n"); 6612 goto fail; 6613 } 6614 } 6615 6616 /* special-case 7265D, it has the same PCI IDs. */ 6617 if (sc->cfg == &iwm7265_cfg && 6618 (sc->sc_hw_rev & IWM_CSR_HW_REV_TYPE_MSK) == IWM_CSR_HW_REV_TYPE_7265D) { 6619 sc->cfg = &iwm7265d_cfg; 6620 } 6621 6622 /* Allocate DMA memory for firmware transfers. */ 6623 if ((error = iwm_alloc_fwmem(sc)) != 0) { 6624 device_printf(dev, "could not allocate memory for firmware\n"); 6625 goto fail; 6626 } 6627 6628 /* Allocate "Keep Warm" page. */ 6629 if ((error = iwm_alloc_kw(sc)) != 0) { 6630 device_printf(dev, "could not allocate keep warm page\n"); 6631 goto fail; 6632 } 6633 6634 /* We use ICT interrupts */ 6635 if ((error = iwm_alloc_ict(sc)) != 0) { 6636 device_printf(dev, "could not allocate ICT table\n"); 6637 goto fail; 6638 } 6639 6640 /* Allocate TX scheduler "rings". */ 6641 if ((error = iwm_alloc_sched(sc)) != 0) { 6642 device_printf(dev, "could not allocate TX scheduler rings\n"); 6643 goto fail; 6644 } 6645 6646 /* Allocate TX rings */ 6647 for (txq_i = 0; txq_i < nitems(sc->txq); txq_i++) { 6648 if ((error = iwm_alloc_tx_ring(sc, 6649 &sc->txq[txq_i], txq_i)) != 0) { 6650 device_printf(dev, 6651 "could not allocate TX ring %d\n", 6652 txq_i); 6653 goto fail; 6654 } 6655 } 6656 6657 /* Allocate RX ring. */ 6658 if ((error = iwm_alloc_rx_ring(sc, &sc->rxq)) != 0) { 6659 device_printf(dev, "could not allocate RX ring\n"); 6660 goto fail; 6661 } 6662 6663 /* Clear pending interrupts. */ 6664 IWM_WRITE(sc, IWM_CSR_INT, 0xffffffff); 6665 6666 ic->ic_softc = sc; 6667 ic->ic_name = device_get_nameunit(sc->sc_dev); 6668 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 6669 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 6670 6671 /* Set device capabilities. */ 6672 ic->ic_caps = 6673 IEEE80211_C_STA | 6674 IEEE80211_C_WPA | /* WPA/RSN */ 6675 IEEE80211_C_WME | 6676 IEEE80211_C_PMGT | 6677 IEEE80211_C_SHSLOT | /* short slot time supported */ 6678 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 6679 // IEEE80211_C_BGSCAN /* capable of bg scanning */ 6680 ; 6681 /* Advertise full-offload scanning */ 6682 ic->ic_flags_ext |= IEEE80211_FEXT_SCAN_OFFLOAD; 6683 ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD; 6684 for (i = 0; i < nitems(sc->sc_phyctxt); i++) { 6685 sc->sc_phyctxt[i].id = i; 6686 sc->sc_phyctxt[i].sco = IEEE80211_HTINFO_2NDCHAN_NONE; 6687 sc->sc_phyctxt[i].color = 0; 6688 sc->sc_phyctxt[i].ref = 0; 6689 sc->sc_phyctxt[i].channel = NULL; 6690 } 6691 6692 /* Default noise floor */ 6693 sc->sc_noise = -96; 6694 6695 /* Max RSSI */ 6696 sc->sc_max_rssi = IWM_MAX_DBM - IWM_MIN_DBM; 6697 6698 #ifdef IWM_DEBUG 6699 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 6700 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "debug", 6701 CTLFLAG_RW, &sc->sc_debug, 0, "control debugging"); 6702 #endif 6703 6704 error = iwm_read_firmware(sc); 6705 if (error) { 6706 goto fail; 6707 } else if (sc->sc_fw.fw_fp == NULL) { 6708 /* 6709 * XXX Add a solution for properly deferring firmware load 6710 * during bootup. 6711 */ 6712 goto fail; 6713 } else { 6714 sc->sc_preinit_hook.ich_func = iwm_preinit; 6715 sc->sc_preinit_hook.ich_arg = sc; 6716 if (config_intrhook_establish(&sc->sc_preinit_hook) != 0) { 6717 device_printf(dev, 6718 "config_intrhook_establish failed\n"); 6719 goto fail; 6720 } 6721 } 6722 6723 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6724 "<-%s\n", __func__); 6725 6726 device_printf(dev, "%s: TX ant=0x%x, RX ant=0x%x\n", 6727 __func__, 6728 iwm_get_valid_tx_ant(sc), 6729 iwm_get_valid_rx_ant(sc)); 6730 6731 return 0; 6732 6733 /* Free allocated memory if something failed during attachment. */ 6734 fail: 6735 iwm_detach_local(sc, 0); 6736 6737 return ENXIO; 6738 } 6739 6740 static int 6741 iwm_is_valid_ether_addr(uint8_t *addr) 6742 { 6743 char zero_addr[IEEE80211_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 }; 6744 6745 if ((addr[0] & 1) || IEEE80211_ADDR_EQ(zero_addr, addr)) 6746 return (FALSE); 6747 6748 return (TRUE); 6749 } 6750 6751 static int 6752 iwm_wme_update(struct ieee80211com *ic) 6753 { 6754 #define IWM_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 6755 struct iwm_softc *sc = ic->ic_softc; 6756 struct chanAccParams chp; 6757 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6758 struct iwm_vap *ivp = IWM_VAP(vap); 6759 struct iwm_node *in; 6760 struct wmeParams tmp[WME_NUM_AC]; 6761 int aci, error; 6762 6763 if (vap == NULL) 6764 return (0); 6765 6766 ieee80211_wme_ic_getparams(ic, &chp); 6767 6768 IEEE80211_LOCK(ic); 6769 for (aci = 0; aci < WME_NUM_AC; aci++) 6770 tmp[aci] = chp.cap_wmeParams[aci]; 6771 IEEE80211_UNLOCK(ic); 6772 6773 IWM_LOCK(sc); 6774 for (aci = 0; aci < WME_NUM_AC; aci++) { 6775 const struct wmeParams *ac = &tmp[aci]; 6776 ivp->queue_params[aci].aifsn = ac->wmep_aifsn; 6777 ivp->queue_params[aci].cw_min = IWM_EXP2(ac->wmep_logcwmin); 6778 ivp->queue_params[aci].cw_max = IWM_EXP2(ac->wmep_logcwmax); 6779 ivp->queue_params[aci].edca_txop = 6780 IEEE80211_TXOP_TO_US(ac->wmep_txopLimit); 6781 } 6782 ivp->have_wme = TRUE; 6783 if (ivp->is_uploaded && vap->iv_bss != NULL) { 6784 in = IWM_NODE(vap->iv_bss); 6785 if (in->in_assoc) { 6786 if ((error = iwm_mac_ctxt_changed(sc, vap)) != 0) { 6787 device_printf(sc->sc_dev, 6788 "%s: failed to update MAC\n", __func__); 6789 } 6790 } 6791 } 6792 IWM_UNLOCK(sc); 6793 6794 return (0); 6795 #undef IWM_EXP2 6796 } 6797 6798 static void 6799 iwm_preinit(void *arg) 6800 { 6801 struct iwm_softc *sc = arg; 6802 device_t dev = sc->sc_dev; 6803 struct ieee80211com *ic = &sc->sc_ic; 6804 int error; 6805 6806 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6807 "->%s\n", __func__); 6808 6809 IWM_LOCK(sc); 6810 if ((error = iwm_start_hw(sc)) != 0) { 6811 device_printf(dev, "could not initialize hardware\n"); 6812 IWM_UNLOCK(sc); 6813 goto fail; 6814 } 6815 6816 error = iwm_run_init_ucode(sc, 1); 6817 iwm_stop_device(sc); 6818 if (error) { 6819 IWM_UNLOCK(sc); 6820 goto fail; 6821 } 6822 device_printf(dev, 6823 "hw rev 0x%x, fw ver %s, address %s\n", 6824 sc->sc_hw_rev & IWM_CSR_HW_REV_TYPE_MSK, 6825 sc->sc_fwver, ether_sprintf(sc->nvm_data->hw_addr)); 6826 6827 if (sc->nvm_data->sku_cap_11n_enable) 6828 iwm_setup_ht_rates(sc); 6829 6830 /* not all hardware can do 5GHz band */ 6831 if (!sc->nvm_data->sku_cap_band_52GHz_enable) 6832 memset(&ic->ic_sup_rates[IEEE80211_MODE_11A], 0, 6833 sizeof(ic->ic_sup_rates[IEEE80211_MODE_11A])); 6834 IWM_UNLOCK(sc); 6835 6836 iwm_init_channel_map(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 6837 ic->ic_channels); 6838 6839 /* 6840 * At this point we've committed - if we fail to do setup, 6841 * we now also have to tear down the net80211 state. 6842 */ 6843 ieee80211_ifattach(ic); 6844 ic->ic_vap_create = iwm_vap_create; 6845 ic->ic_vap_delete = iwm_vap_delete; 6846 ic->ic_raw_xmit = iwm_raw_xmit; 6847 ic->ic_node_alloc = iwm_node_alloc; 6848 ic->ic_scan_start = iwm_scan_start; 6849 ic->ic_scan_end = iwm_scan_end; 6850 ic->ic_update_mcast = iwm_update_mcast; 6851 ic->ic_getradiocaps = iwm_init_channel_map; 6852 ic->ic_set_channel = iwm_set_channel; 6853 ic->ic_scan_curchan = iwm_scan_curchan; 6854 ic->ic_scan_mindwell = iwm_scan_mindwell; 6855 ic->ic_wme.wme_update = iwm_wme_update; 6856 ic->ic_parent = iwm_parent; 6857 ic->ic_transmit = iwm_transmit; 6858 iwm_radiotap_attach(sc); 6859 if (bootverbose) 6860 ieee80211_announce(ic); 6861 6862 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6863 "<-%s\n", __func__); 6864 config_intrhook_disestablish(&sc->sc_preinit_hook); 6865 6866 return; 6867 fail: 6868 config_intrhook_disestablish(&sc->sc_preinit_hook); 6869 iwm_detach_local(sc, 0); 6870 } 6871 6872 /* 6873 * Attach the interface to 802.11 radiotap. 6874 */ 6875 static void 6876 iwm_radiotap_attach(struct iwm_softc *sc) 6877 { 6878 struct ieee80211com *ic = &sc->sc_ic; 6879 6880 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6881 "->%s begin\n", __func__); 6882 ieee80211_radiotap_attach(ic, 6883 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 6884 IWM_TX_RADIOTAP_PRESENT, 6885 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 6886 IWM_RX_RADIOTAP_PRESENT); 6887 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_TRACE, 6888 "->%s end\n", __func__); 6889 } 6890 6891 static struct ieee80211vap * 6892 iwm_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 6893 enum ieee80211_opmode opmode, int flags, 6894 const uint8_t bssid[IEEE80211_ADDR_LEN], 6895 const uint8_t mac[IEEE80211_ADDR_LEN]) 6896 { 6897 struct iwm_vap *ivp; 6898 struct ieee80211vap *vap; 6899 6900 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 6901 return NULL; 6902 ivp = malloc(sizeof(struct iwm_vap), M_80211_VAP, M_WAITOK | M_ZERO); 6903 vap = &ivp->iv_vap; 6904 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 6905 vap->iv_bmissthreshold = 10; /* override default */ 6906 /* Override with driver methods. */ 6907 ivp->iv_newstate = vap->iv_newstate; 6908 vap->iv_newstate = iwm_newstate; 6909 6910 vap->iv_updateslot = iwm_vap_update_slot; 6911 vap->iv_erp_protmode_update = iwm_vap_update_erp_protmode; 6912 vap->iv_preamble_update = iwm_vap_update_preamble; 6913 vap->iv_wme_update = iwm_vap_update_wme; 6914 6915 ivp->id = IWM_DEFAULT_MACID; 6916 ivp->color = IWM_DEFAULT_COLOR; 6917 6918 ivp->have_wme = FALSE; 6919 ivp->ps_disabled = FALSE; 6920 6921 ieee80211_ratectl_init(vap); 6922 /* Complete setup. */ 6923 ieee80211_vap_attach(vap, ieee80211_media_change, 6924 ieee80211_media_status, mac); 6925 ic->ic_opmode = opmode; 6926 6927 return vap; 6928 } 6929 6930 static void 6931 iwm_vap_delete(struct ieee80211vap *vap) 6932 { 6933 struct iwm_vap *ivp = IWM_VAP(vap); 6934 6935 ieee80211_ratectl_deinit(vap); 6936 ieee80211_vap_detach(vap); 6937 free(ivp, M_80211_VAP); 6938 } 6939 6940 static void 6941 iwm_xmit_queue_drain(struct iwm_softc *sc) 6942 { 6943 struct mbuf *m; 6944 struct ieee80211_node *ni; 6945 6946 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 6947 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 6948 ieee80211_free_node(ni); 6949 m_freem(m); 6950 } 6951 } 6952 6953 static void 6954 iwm_scan_start(struct ieee80211com *ic) 6955 { 6956 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6957 struct iwm_softc *sc = ic->ic_softc; 6958 int error; 6959 6960 IWM_LOCK(sc); 6961 if (sc->sc_flags & IWM_FLAG_SCAN_RUNNING) { 6962 /* This should not be possible */ 6963 device_printf(sc->sc_dev, 6964 "%s: Previous scan not completed yet\n", __func__); 6965 } 6966 if (iwm_fw_has_capa(sc, IWM_UCODE_TLV_CAPA_UMAC_SCAN)) 6967 error = iwm_umac_scan(sc); 6968 else 6969 error = iwm_lmac_scan(sc); 6970 if (error != 0) { 6971 device_printf(sc->sc_dev, "could not initiate scan\n"); 6972 IWM_UNLOCK(sc); 6973 ieee80211_cancel_scan(vap); 6974 } else { 6975 sc->sc_flags |= IWM_FLAG_SCAN_RUNNING; 6976 iwm_led_blink_start(sc); 6977 IWM_UNLOCK(sc); 6978 } 6979 } 6980 6981 static void 6982 iwm_scan_end(struct ieee80211com *ic) 6983 { 6984 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6985 struct iwm_softc *sc = ic->ic_softc; 6986 6987 IWM_LOCK(sc); 6988 iwm_led_blink_stop(sc); 6989 if (vap->iv_state == IEEE80211_S_RUN) 6990 iwm_led_enable(sc); 6991 if (sc->sc_flags & IWM_FLAG_SCAN_RUNNING) { 6992 /* 6993 * Removing IWM_FLAG_SCAN_RUNNING now, is fine because 6994 * both iwm_scan_end and iwm_scan_start run in the ic->ic_tq 6995 * taskqueue. 6996 */ 6997 sc->sc_flags &= ~IWM_FLAG_SCAN_RUNNING; 6998 iwm_scan_stop_wait(sc); 6999 } 7000 IWM_UNLOCK(sc); 7001 7002 /* 7003 * Make sure we don't race, if sc_es_task is still enqueued here. 7004 * This is to make sure that it won't call ieee80211_scan_done 7005 * when we have already started the next scan. 7006 */ 7007 taskqueue_cancel(ic->ic_tq, &sc->sc_es_task, NULL); 7008 } 7009 7010 static void 7011 iwm_update_mcast(struct ieee80211com *ic) 7012 { 7013 } 7014 7015 static void 7016 iwm_set_channel(struct ieee80211com *ic) 7017 { 7018 } 7019 7020 static void 7021 iwm_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 7022 { 7023 } 7024 7025 static void 7026 iwm_scan_mindwell(struct ieee80211_scan_state *ss) 7027 { 7028 } 7029 7030 void 7031 iwm_init_task(void *arg1) 7032 { 7033 struct iwm_softc *sc = arg1; 7034 7035 IWM_LOCK(sc); 7036 while (sc->sc_flags & IWM_FLAG_BUSY) 7037 msleep(&sc->sc_flags, &sc->sc_mtx, 0, "iwmpwr", 0); 7038 sc->sc_flags |= IWM_FLAG_BUSY; 7039 iwm_stop(sc); 7040 if (sc->sc_ic.ic_nrunning > 0) 7041 iwm_init(sc); 7042 sc->sc_flags &= ~IWM_FLAG_BUSY; 7043 wakeup(&sc->sc_flags); 7044 IWM_UNLOCK(sc); 7045 } 7046 7047 static int 7048 iwm_resume(device_t dev) 7049 { 7050 struct iwm_softc *sc = device_get_softc(dev); 7051 int do_reinit = 0; 7052 7053 /* 7054 * We disable the RETRY_TIMEOUT register (0x41) to keep 7055 * PCI Tx retries from interfering with C3 CPU state. 7056 */ 7057 pci_write_config(dev, PCI_CFG_RETRY_TIMEOUT, 0x00, 1); 7058 7059 if (!sc->sc_attached) 7060 return 0; 7061 7062 iwm_init_task(device_get_softc(dev)); 7063 7064 IWM_LOCK(sc); 7065 if (sc->sc_flags & IWM_FLAG_SCANNING) { 7066 sc->sc_flags &= ~IWM_FLAG_SCANNING; 7067 do_reinit = 1; 7068 } 7069 IWM_UNLOCK(sc); 7070 7071 if (do_reinit) 7072 ieee80211_resume_all(&sc->sc_ic); 7073 7074 return 0; 7075 } 7076 7077 static int 7078 iwm_suspend(device_t dev) 7079 { 7080 int do_stop = 0; 7081 struct iwm_softc *sc = device_get_softc(dev); 7082 7083 do_stop = !! (sc->sc_ic.ic_nrunning > 0); 7084 7085 if (!sc->sc_attached) 7086 return (0); 7087 7088 ieee80211_suspend_all(&sc->sc_ic); 7089 7090 if (do_stop) { 7091 IWM_LOCK(sc); 7092 iwm_stop(sc); 7093 sc->sc_flags |= IWM_FLAG_SCANNING; 7094 IWM_UNLOCK(sc); 7095 } 7096 7097 return (0); 7098 } 7099 7100 static int 7101 iwm_detach_local(struct iwm_softc *sc, int do_net80211) 7102 { 7103 struct iwm_fw_info *fw = &sc->sc_fw; 7104 device_t dev = sc->sc_dev; 7105 int i; 7106 7107 IWM_LOCK_ASSERT_UNLOCKED(sc); 7108 7109 IWM_LOCK(sc); 7110 if (!sc->sc_attached) { 7111 IWM_UNLOCK(sc); 7112 return 0; 7113 } 7114 sc->sc_attached = 0; 7115 sc->sc_flags |= IWM_FLAG_STOPPED; 7116 IWM_UNLOCK(sc); 7117 7118 if (do_net80211) { 7119 ieee80211_draintask(&sc->sc_ic, &sc->sc_es_task); 7120 } 7121 iwm_stop_device(sc); 7122 7123 while (taskqueue_cancel(sc->sc_tq, &sc->mac_ctxt_task, NULL) != 0) 7124 taskqueue_drain(sc->sc_tq, &sc->mac_ctxt_task); 7125 while (taskqueue_cancel(sc->sc_tq, &sc->phy_ctxt_task, NULL) != 0) 7126 taskqueue_drain(sc->sc_tq, &sc->phy_ctxt_task); 7127 7128 taskqueue_drain_all(sc->sc_tq); 7129 taskqueue_free(sc->sc_tq); 7130 sc->sc_tq = NULL; 7131 7132 if (do_net80211) { 7133 IWM_LOCK(sc); 7134 iwm_xmit_queue_drain(sc); 7135 IWM_UNLOCK(sc); 7136 ieee80211_ifdetach(&sc->sc_ic); 7137 } 7138 callout_drain(&sc->sc_led_blink_to); 7139 callout_drain(&sc->sc_watchdog_to); 7140 7141 iwm_phy_db_free(sc->sc_phy_db); 7142 sc->sc_phy_db = NULL; 7143 7144 iwm_free_nvm_data(sc->nvm_data); 7145 7146 /* Free descriptor rings */ 7147 iwm_free_rx_ring(sc, &sc->rxq); 7148 for (i = 0; i < nitems(sc->txq); i++) 7149 iwm_free_tx_ring(sc, &sc->txq[i]); 7150 7151 /* Free firmware */ 7152 if (fw->fw_fp != NULL) 7153 iwm_fw_info_free(fw); 7154 7155 /* Free scheduler */ 7156 iwm_dma_contig_free(&sc->sched_dma); 7157 iwm_dma_contig_free(&sc->ict_dma); 7158 iwm_dma_contig_free(&sc->kw_dma); 7159 iwm_dma_contig_free(&sc->fw_dma); 7160 7161 iwm_free_fw_paging(sc); 7162 7163 /* Finished with the hardware - detach things */ 7164 iwm_pci_detach(dev); 7165 7166 if (sc->sc_notif_wait != NULL) { 7167 iwm_notification_wait_free(sc->sc_notif_wait); 7168 sc->sc_notif_wait = NULL; 7169 } 7170 7171 IWM_LOCK_DESTROY(sc); 7172 7173 return (0); 7174 } 7175 7176 static int 7177 iwm_detach(device_t dev) 7178 { 7179 struct iwm_softc *sc = device_get_softc(dev); 7180 7181 return (iwm_detach_local(sc, 1)); 7182 } 7183 7184 static device_method_t iwm_pci_methods[] = { 7185 /* Device interface */ 7186 DEVMETHOD(device_probe, iwm_probe), 7187 DEVMETHOD(device_attach, iwm_attach), 7188 DEVMETHOD(device_detach, iwm_detach), 7189 DEVMETHOD(device_suspend, iwm_suspend), 7190 DEVMETHOD(device_resume, iwm_resume), 7191 7192 DEVMETHOD_END 7193 }; 7194 7195 static driver_t iwm_pci_driver = { 7196 "iwm", 7197 iwm_pci_methods, 7198 sizeof (struct iwm_softc) 7199 }; 7200 7201 DRIVER_MODULE(iwm, pci, iwm_pci_driver, NULL, NULL); 7202 MODULE_PNP_INFO("U16:device;P:#;T:vendor=0x8086", pci, iwm_pci_driver, 7203 iwm_devices, nitems(iwm_devices)); 7204 MODULE_DEPEND(iwm, firmware, 1, 1, 1); 7205 MODULE_DEPEND(iwm, pci, 1, 1, 1); 7206 MODULE_DEPEND(iwm, wlan, 1, 1, 1); 7207