1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2007-2015, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/debugfs.h> 10 #include <linux/sched.h> 11 #include <linux/bitops.h> 12 #include <linux/gfp.h> 13 #include <linux/vmalloc.h> 14 #include <linux/module.h> 15 #include <linux/wait.h> 16 #include <linux/seq_file.h> 17 #if defined(__FreeBSD__) 18 #include <sys/rman.h> 19 #include <linux/delay.h> 20 #endif 21 22 #include "iwl-drv.h" 23 #include "iwl-trans.h" 24 #include "iwl-csr.h" 25 #include "iwl-prph.h" 26 #include "iwl-scd.h" 27 #include "iwl-agn-hw.h" 28 #include "fw/error-dump.h" 29 #include "fw/dbg.h" 30 #include "fw/api/tx.h" 31 #include "mei/iwl-mei.h" 32 #include "internal.h" 33 #include "iwl-fh.h" 34 #include "iwl-context-info-gen3.h" 35 36 /* extended range in FW SRAM */ 37 #define IWL_FW_MEM_EXTENDED_START 0x40000 38 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 39 40 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 41 { 42 #define PCI_DUMP_SIZE 352 43 #define PCI_MEM_DUMP_SIZE 64 44 #define PCI_PARENT_DUMP_SIZE 524 45 #define PREFIX_LEN 32 46 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 47 struct pci_dev *pdev = trans_pcie->pci_dev; 48 u32 i, pos, alloc_size, *ptr, *buf; 49 char *prefix; 50 51 if (trans_pcie->pcie_dbg_dumped_once) 52 return; 53 54 /* Should be a multiple of 4 */ 55 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 56 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 57 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 58 59 /* Alloc a max size buffer */ 60 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 61 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 62 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 63 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 64 65 buf = kmalloc(alloc_size, GFP_ATOMIC); 66 if (!buf) 67 return; 68 prefix = (char *)buf + alloc_size - PREFIX_LEN; 69 70 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 71 72 /* Print wifi device registers */ 73 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 74 IWL_ERR(trans, "iwlwifi device config registers:\n"); 75 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 76 if (pci_read_config_dword(pdev, i, ptr)) 77 goto err_read; 78 #if defined(__linux__) 79 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 80 #elif defined(__FreeBSD__) 81 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 82 #endif 83 84 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 85 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 86 *ptr = iwl_read32(trans, i); 87 #if defined(__linux__) 88 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 89 #elif defined(__FreeBSD__) 90 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 91 #endif 92 93 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 94 if (pos) { 95 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 96 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 97 if (pci_read_config_dword(pdev, pos + i, ptr)) 98 goto err_read; 99 #if defined(__linux__) 100 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 101 32, 4, buf, i, 0); 102 #elif defined(__FreeBSD__) 103 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 104 #endif 105 } 106 107 /* Print parent device registers next */ 108 if (!pdev->bus->self) 109 goto out; 110 111 pdev = pdev->bus->self; 112 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 113 114 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 115 pci_name(pdev)); 116 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 117 if (pci_read_config_dword(pdev, i, ptr)) 118 goto err_read; 119 #if defined(__linux__) 120 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 121 #elif defined(__FreeBSD__) 122 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 123 #endif 124 125 /* Print root port AER registers */ 126 pos = 0; 127 pdev = pcie_find_root_port(pdev); 128 if (pdev) 129 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 130 if (pos) { 131 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 132 pci_name(pdev)); 133 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 134 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 135 if (pci_read_config_dword(pdev, pos + i, ptr)) 136 goto err_read; 137 #if defined(__linux__) 138 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 139 4, buf, i, 0); 140 #elif defined(__FreeBSD__) 141 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 142 #endif 143 } 144 goto out; 145 146 err_read: 147 #if defined(__linux__) 148 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 149 #elif defined(__FreeBSD__) 150 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 151 #endif 152 IWL_ERR(trans, "Read failed at 0x%X\n", i); 153 out: 154 trans_pcie->pcie_dbg_dumped_once = 1; 155 kfree(buf); 156 } 157 158 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership) 159 { 160 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 161 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 162 iwl_set_bit(trans, CSR_GP_CNTRL, 163 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 164 usleep_range(10000, 20000); 165 } else { 166 iwl_set_bit(trans, CSR_RESET, 167 CSR_RESET_REG_FLAG_SW_RESET); 168 usleep_range(5000, 6000); 169 } 170 171 if (retake_ownership) 172 return iwl_pcie_prepare_card_hw(trans); 173 174 return 0; 175 } 176 177 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 178 { 179 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 180 181 if (!fw_mon->size) 182 return; 183 184 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 185 fw_mon->physical); 186 187 fw_mon->block = NULL; 188 fw_mon->physical = 0; 189 fw_mon->size = 0; 190 } 191 192 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 193 u8 max_power) 194 { 195 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 196 void *block = NULL; 197 dma_addr_t physical = 0; 198 u32 size = 0; 199 u8 power; 200 201 if (fw_mon->size) { 202 memset(fw_mon->block, 0, fw_mon->size); 203 return; 204 } 205 206 /* need at least 2 KiB, so stop at 11 */ 207 for (power = max_power; power >= 11; power--) { 208 size = BIT(power); 209 block = dma_alloc_coherent(trans->dev, size, &physical, 210 GFP_KERNEL | __GFP_NOWARN); 211 if (!block) 212 continue; 213 214 IWL_INFO(trans, 215 "Allocated 0x%08x bytes for firmware monitor.\n", 216 size); 217 break; 218 } 219 220 if (WARN_ON_ONCE(!block)) 221 return; 222 223 if (power != max_power) 224 IWL_ERR(trans, 225 "Sorry - debug buffer is only %luK while you requested %luK\n", 226 (unsigned long)BIT(power - 10), 227 (unsigned long)BIT(max_power - 10)); 228 229 fw_mon->block = block; 230 fw_mon->physical = physical; 231 fw_mon->size = size; 232 } 233 234 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 235 { 236 if (!max_power) { 237 /* default max_power is maximum */ 238 max_power = 26; 239 } else { 240 max_power += 11; 241 } 242 243 if (WARN(max_power > 26, 244 "External buffer size for monitor is too big %d, check the FW TLV\n", 245 max_power)) 246 return; 247 248 iwl_pcie_alloc_fw_monitor_block(trans, max_power); 249 } 250 251 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 252 { 253 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 254 ((reg & 0x0000ffff) | (2 << 28))); 255 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 256 } 257 258 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 259 { 260 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 261 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 262 ((reg & 0x0000ffff) | (3 << 28))); 263 } 264 265 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 266 { 267 if (trans->cfg->apmg_not_supported) 268 return; 269 270 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 271 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 272 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 273 ~APMG_PS_CTRL_MSK_PWR_SRC); 274 else 275 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 276 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 277 ~APMG_PS_CTRL_MSK_PWR_SRC); 278 } 279 280 /* PCI registers */ 281 #define PCI_CFG_RETRY_TIMEOUT 0x041 282 283 void iwl_pcie_apm_config(struct iwl_trans *trans) 284 { 285 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 286 u16 lctl; 287 u16 cap; 288 289 /* 290 * L0S states have been found to be unstable with our devices 291 * and in newer hardware they are not officially supported at 292 * all, so we must always set the L0S_DISABLED bit. 293 */ 294 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 295 296 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 297 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 298 299 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 300 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 301 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 302 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 303 trans->ltr_enabled ? "En" : "Dis"); 304 } 305 306 /* 307 * Start up NIC's basic functionality after it has been reset 308 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 309 * NOTE: This does not load uCode nor start the embedded processor 310 */ 311 static int iwl_pcie_apm_init(struct iwl_trans *trans) 312 { 313 int ret; 314 315 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 316 317 /* 318 * Use "set_bit" below rather than "write", to preserve any hardware 319 * bits already set by default after reset. 320 */ 321 322 /* Disable L0S exit timer (platform NMI Work/Around) */ 323 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 324 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 325 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 326 327 /* 328 * Disable L0s without affecting L1; 329 * don't wait for ICH L0s (ICH bug W/A) 330 */ 331 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 332 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 333 334 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 335 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 336 337 /* 338 * Enable HAP INTA (interrupt from management bus) to 339 * wake device's PCI Express link L1a -> L0s 340 */ 341 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 342 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 343 344 iwl_pcie_apm_config(trans); 345 346 /* Configure analog phase-lock-loop before activating to D0A */ 347 if (trans->trans_cfg->base_params->pll_cfg) 348 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 349 350 ret = iwl_finish_nic_init(trans); 351 if (ret) 352 return ret; 353 354 if (trans->cfg->host_interrupt_operation_mode) { 355 /* 356 * This is a bit of an abuse - This is needed for 7260 / 3160 357 * only check host_interrupt_operation_mode even if this is 358 * not related to host_interrupt_operation_mode. 359 * 360 * Enable the oscillator to count wake up time for L1 exit. This 361 * consumes slightly more power (100uA) - but allows to be sure 362 * that we wake up from L1 on time. 363 * 364 * This looks weird: read twice the same register, discard the 365 * value, set a bit, and yet again, read that same register 366 * just to discard the value. But that's the way the hardware 367 * seems to like it. 368 */ 369 iwl_read_prph(trans, OSC_CLK); 370 iwl_read_prph(trans, OSC_CLK); 371 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 372 iwl_read_prph(trans, OSC_CLK); 373 iwl_read_prph(trans, OSC_CLK); 374 } 375 376 /* 377 * Enable DMA clock and wait for it to stabilize. 378 * 379 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 380 * bits do not disable clocks. This preserves any hardware 381 * bits already set by default in "CLK_CTRL_REG" after reset. 382 */ 383 if (!trans->cfg->apmg_not_supported) { 384 iwl_write_prph(trans, APMG_CLK_EN_REG, 385 APMG_CLK_VAL_DMA_CLK_RQT); 386 udelay(20); 387 388 /* Disable L1-Active */ 389 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 390 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 391 392 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 393 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 394 APMG_RTC_INT_STT_RFKILL); 395 } 396 397 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 398 399 return 0; 400 } 401 402 /* 403 * Enable LP XTAL to avoid HW bug where device may consume much power if 404 * FW is not loaded after device reset. LP XTAL is disabled by default 405 * after device HW reset. Do it only if XTAL is fed by internal source. 406 * Configure device's "persistence" mode to avoid resetting XTAL again when 407 * SHRD_HW_RST occurs in S3. 408 */ 409 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 410 { 411 int ret; 412 u32 apmg_gp1_reg; 413 u32 apmg_xtal_cfg_reg; 414 u32 dl_cfg_reg; 415 416 /* Force XTAL ON */ 417 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 418 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 419 420 ret = iwl_trans_pcie_sw_reset(trans, true); 421 422 if (!ret) 423 ret = iwl_finish_nic_init(trans); 424 425 if (WARN_ON(ret)) { 426 /* Release XTAL ON request */ 427 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 428 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 429 return; 430 } 431 432 /* 433 * Clear "disable persistence" to avoid LP XTAL resetting when 434 * SHRD_HW_RST is applied in S3. 435 */ 436 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 437 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 438 439 /* 440 * Force APMG XTAL to be active to prevent its disabling by HW 441 * caused by APMG idle state. 442 */ 443 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 444 SHR_APMG_XTAL_CFG_REG); 445 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 446 apmg_xtal_cfg_reg | 447 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 448 449 ret = iwl_trans_pcie_sw_reset(trans, true); 450 if (ret) 451 IWL_ERR(trans, 452 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 453 454 /* Enable LP XTAL by indirect access through CSR */ 455 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 456 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 457 SHR_APMG_GP1_WF_XTAL_LP_EN | 458 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 459 460 /* Clear delay line clock power up */ 461 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 462 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 463 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 464 465 /* 466 * Enable persistence mode to avoid LP XTAL resetting when 467 * SHRD_HW_RST is applied in S3. 468 */ 469 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 470 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 471 472 /* 473 * Clear "initialization complete" bit to move adapter from 474 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 475 */ 476 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 477 478 /* Activates XTAL resources monitor */ 479 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 480 CSR_MONITOR_XTAL_RESOURCES); 481 482 /* Release XTAL ON request */ 483 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 484 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 485 udelay(10); 486 487 /* Release APMG XTAL */ 488 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 489 apmg_xtal_cfg_reg & 490 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 491 } 492 493 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 494 { 495 int ret; 496 497 /* stop device's busmaster DMA activity */ 498 499 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 500 iwl_set_bit(trans, CSR_GP_CNTRL, 501 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 502 503 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 504 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 505 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 506 100); 507 usleep_range(10000, 20000); 508 } else { 509 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 510 511 ret = iwl_poll_bit(trans, CSR_RESET, 512 CSR_RESET_REG_FLAG_MASTER_DISABLED, 513 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 514 } 515 516 if (ret < 0) 517 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 518 519 IWL_DEBUG_INFO(trans, "stop master\n"); 520 } 521 522 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 523 { 524 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 525 526 if (op_mode_leave) { 527 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 528 iwl_pcie_apm_init(trans); 529 530 /* inform ME that we are leaving */ 531 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 532 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 533 APMG_PCIDEV_STT_VAL_WAKE_ME); 534 else if (trans->trans_cfg->device_family >= 535 IWL_DEVICE_FAMILY_8000) { 536 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 537 CSR_RESET_LINK_PWR_MGMT_DISABLED); 538 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 539 CSR_HW_IF_CONFIG_REG_PREPARE | 540 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 541 mdelay(1); 542 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 543 CSR_RESET_LINK_PWR_MGMT_DISABLED); 544 } 545 mdelay(5); 546 } 547 548 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 549 550 /* Stop device's DMA activity */ 551 iwl_pcie_apm_stop_master(trans); 552 553 if (trans->cfg->lp_xtal_workaround) { 554 iwl_pcie_apm_lp_xtal_enable(trans); 555 return; 556 } 557 558 iwl_trans_pcie_sw_reset(trans, false); 559 560 /* 561 * Clear "initialization complete" bit to move adapter from 562 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 563 */ 564 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 565 } 566 567 static int iwl_pcie_nic_init(struct iwl_trans *trans) 568 { 569 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 570 int ret; 571 572 /* nic_init */ 573 spin_lock_bh(&trans_pcie->irq_lock); 574 ret = iwl_pcie_apm_init(trans); 575 spin_unlock_bh(&trans_pcie->irq_lock); 576 577 if (ret) 578 return ret; 579 580 iwl_pcie_set_pwr(trans, false); 581 582 iwl_op_mode_nic_config(trans->op_mode); 583 584 /* Allocate the RX queue, or reset if it is already allocated */ 585 ret = iwl_pcie_rx_init(trans); 586 if (ret) 587 return ret; 588 589 /* Allocate or reset and init all Tx and Command queues */ 590 if (iwl_pcie_tx_init(trans)) { 591 iwl_pcie_rx_free(trans); 592 return -ENOMEM; 593 } 594 595 if (trans->trans_cfg->base_params->shadow_reg_enable) { 596 /* enable shadow regs in HW */ 597 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 598 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 599 } 600 601 return 0; 602 } 603 604 #define HW_READY_TIMEOUT (50) 605 606 /* Note: returns poll_bit return value, which is >= 0 if success */ 607 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 608 { 609 int ret; 610 611 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 612 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 613 614 /* See if we got it */ 615 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 616 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 617 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 618 HW_READY_TIMEOUT); 619 620 if (ret >= 0) 621 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 622 623 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 624 return ret; 625 } 626 627 /* Note: returns standard 0/-ERROR code */ 628 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 629 { 630 int ret; 631 int iter; 632 633 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 634 635 ret = iwl_pcie_set_hw_ready(trans); 636 /* If the card is ready, exit 0 */ 637 if (ret >= 0) { 638 trans->csme_own = false; 639 return 0; 640 } 641 642 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 643 CSR_RESET_LINK_PWR_MGMT_DISABLED); 644 usleep_range(1000, 2000); 645 646 for (iter = 0; iter < 10; iter++) { 647 int t = 0; 648 649 /* If HW is not ready, prepare the conditions to check again */ 650 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 651 CSR_HW_IF_CONFIG_REG_PREPARE); 652 653 do { 654 ret = iwl_pcie_set_hw_ready(trans); 655 if (ret >= 0) { 656 trans->csme_own = false; 657 return 0; 658 } 659 660 if (iwl_mei_is_connected()) { 661 IWL_DEBUG_INFO(trans, 662 "Couldn't prepare the card but SAP is connected\n"); 663 trans->csme_own = true; 664 if (trans->trans_cfg->device_family != 665 IWL_DEVICE_FAMILY_9000) 666 IWL_ERR(trans, 667 "SAP not supported for this NIC family\n"); 668 669 return -EBUSY; 670 } 671 672 usleep_range(200, 1000); 673 t += 200; 674 } while (t < 150000); 675 msleep(25); 676 } 677 678 IWL_ERR(trans, "Couldn't prepare the card\n"); 679 680 return ret; 681 } 682 683 /* 684 * ucode 685 */ 686 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 687 u32 dst_addr, dma_addr_t phy_addr, 688 u32 byte_cnt) 689 { 690 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 691 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 692 693 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 694 dst_addr); 695 696 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 697 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 698 699 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 700 (iwl_get_dma_hi_addr(phy_addr) 701 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 702 703 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 704 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 705 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 706 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 707 708 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 709 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 710 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 711 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 712 } 713 714 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 715 u32 dst_addr, dma_addr_t phy_addr, 716 u32 byte_cnt) 717 { 718 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 719 int ret; 720 721 trans_pcie->ucode_write_complete = false; 722 723 if (!iwl_trans_grab_nic_access(trans)) 724 return -EIO; 725 726 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 727 byte_cnt); 728 iwl_trans_release_nic_access(trans); 729 730 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 731 trans_pcie->ucode_write_complete, 5 * HZ); 732 if (!ret) { 733 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 734 iwl_trans_pcie_dump_regs(trans); 735 return -ETIMEDOUT; 736 } 737 738 return 0; 739 } 740 741 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 742 const struct fw_desc *section) 743 { 744 u8 *v_addr; 745 dma_addr_t p_addr; 746 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 747 int ret = 0; 748 749 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 750 section_num); 751 752 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 753 GFP_KERNEL | __GFP_NOWARN); 754 if (!v_addr) { 755 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 756 chunk_sz = PAGE_SIZE; 757 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 758 &p_addr, GFP_KERNEL); 759 if (!v_addr) 760 return -ENOMEM; 761 } 762 763 for (offset = 0; offset < section->len; offset += chunk_sz) { 764 u32 copy_size, dst_addr; 765 bool extended_addr = false; 766 767 copy_size = min_t(u32, chunk_sz, section->len - offset); 768 dst_addr = section->offset + offset; 769 770 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 771 dst_addr <= IWL_FW_MEM_EXTENDED_END) 772 extended_addr = true; 773 774 if (extended_addr) 775 iwl_set_bits_prph(trans, LMPM_CHICK, 776 LMPM_CHICK_EXTENDED_ADDR_SPACE); 777 778 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 779 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 780 copy_size); 781 782 if (extended_addr) 783 iwl_clear_bits_prph(trans, LMPM_CHICK, 784 LMPM_CHICK_EXTENDED_ADDR_SPACE); 785 786 if (ret) { 787 IWL_ERR(trans, 788 "Could not load the [%d] uCode section\n", 789 section_num); 790 break; 791 } 792 } 793 794 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 795 return ret; 796 } 797 798 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 799 const struct fw_img *image, 800 int cpu, 801 int *first_ucode_section) 802 { 803 int shift_param; 804 int i, ret = 0, sec_num = 0x1; 805 u32 val, last_read_idx = 0; 806 807 if (cpu == 1) { 808 shift_param = 0; 809 *first_ucode_section = 0; 810 } else { 811 shift_param = 16; 812 (*first_ucode_section)++; 813 } 814 815 for (i = *first_ucode_section; i < image->num_sec; i++) { 816 last_read_idx = i; 817 818 /* 819 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 820 * CPU1 to CPU2. 821 * PAGING_SEPARATOR_SECTION delimiter - separate between 822 * CPU2 non paged to CPU2 paging sec. 823 */ 824 if (!image->sec[i].data || 825 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 826 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 827 IWL_DEBUG_FW(trans, 828 "Break since Data not valid or Empty section, sec = %d\n", 829 i); 830 break; 831 } 832 833 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 834 if (ret) 835 return ret; 836 837 /* Notify ucode of loaded section number and status */ 838 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 839 val = val | (sec_num << shift_param); 840 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 841 842 sec_num = (sec_num << 1) | 0x1; 843 } 844 845 *first_ucode_section = last_read_idx; 846 847 iwl_enable_interrupts(trans); 848 849 if (trans->trans_cfg->gen2) { 850 if (cpu == 1) 851 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 852 0xFFFF); 853 else 854 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 855 0xFFFFFFFF); 856 } else { 857 if (cpu == 1) 858 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 859 0xFFFF); 860 else 861 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 862 0xFFFFFFFF); 863 } 864 865 return 0; 866 } 867 868 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 869 const struct fw_img *image, 870 int cpu, 871 int *first_ucode_section) 872 { 873 int i, ret = 0; 874 u32 last_read_idx = 0; 875 876 if (cpu == 1) 877 *first_ucode_section = 0; 878 else 879 (*first_ucode_section)++; 880 881 for (i = *first_ucode_section; i < image->num_sec; i++) { 882 last_read_idx = i; 883 884 /* 885 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 886 * CPU1 to CPU2. 887 * PAGING_SEPARATOR_SECTION delimiter - separate between 888 * CPU2 non paged to CPU2 paging sec. 889 */ 890 if (!image->sec[i].data || 891 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 892 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 893 IWL_DEBUG_FW(trans, 894 "Break since Data not valid or Empty section, sec = %d\n", 895 i); 896 break; 897 } 898 899 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 900 if (ret) 901 return ret; 902 } 903 904 *first_ucode_section = last_read_idx; 905 906 return 0; 907 } 908 909 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 910 { 911 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 912 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 913 &trans->dbg.fw_mon_cfg[alloc_id]; 914 struct iwl_dram_data *frag; 915 916 if (!iwl_trans_dbg_ini_valid(trans)) 917 return; 918 919 if (le32_to_cpu(fw_mon_cfg->buf_location) == 920 IWL_FW_INI_LOCATION_SRAM_PATH) { 921 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 922 /* set sram monitor by enabling bit 7 */ 923 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 924 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 925 926 return; 927 } 928 929 if (le32_to_cpu(fw_mon_cfg->buf_location) != 930 IWL_FW_INI_LOCATION_DRAM_PATH || 931 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 932 return; 933 934 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 935 936 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 937 alloc_id); 938 939 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 940 frag->physical >> MON_BUFF_SHIFT_VER2); 941 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 942 (frag->physical + frag->size - 256) >> 943 MON_BUFF_SHIFT_VER2); 944 } 945 946 void iwl_pcie_apply_destination(struct iwl_trans *trans) 947 { 948 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 949 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 950 int i; 951 952 if (iwl_trans_dbg_ini_valid(trans)) { 953 iwl_pcie_apply_destination_ini(trans); 954 return; 955 } 956 957 IWL_INFO(trans, "Applying debug destination %s\n", 958 get_fw_dbg_mode_string(dest->monitor_mode)); 959 960 if (dest->monitor_mode == EXTERNAL_MODE) 961 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 962 else 963 IWL_WARN(trans, "PCI should have external buffer debug\n"); 964 965 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 966 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 967 u32 val = le32_to_cpu(dest->reg_ops[i].val); 968 969 switch (dest->reg_ops[i].op) { 970 case CSR_ASSIGN: 971 iwl_write32(trans, addr, val); 972 break; 973 case CSR_SETBIT: 974 iwl_set_bit(trans, addr, BIT(val)); 975 break; 976 case CSR_CLEARBIT: 977 iwl_clear_bit(trans, addr, BIT(val)); 978 break; 979 case PRPH_ASSIGN: 980 iwl_write_prph(trans, addr, val); 981 break; 982 case PRPH_SETBIT: 983 iwl_set_bits_prph(trans, addr, BIT(val)); 984 break; 985 case PRPH_CLEARBIT: 986 iwl_clear_bits_prph(trans, addr, BIT(val)); 987 break; 988 case PRPH_BLOCKBIT: 989 if (iwl_read_prph(trans, addr) & BIT(val)) { 990 IWL_ERR(trans, 991 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 992 val, addr); 993 goto monitor; 994 } 995 break; 996 default: 997 IWL_ERR(trans, "FW debug - unknown OP %d\n", 998 dest->reg_ops[i].op); 999 break; 1000 } 1001 } 1002 1003 monitor: 1004 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 1005 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 1006 fw_mon->physical >> dest->base_shift); 1007 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1008 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 1009 (fw_mon->physical + fw_mon->size - 1010 256) >> dest->end_shift); 1011 else 1012 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 1013 (fw_mon->physical + fw_mon->size) >> 1014 dest->end_shift); 1015 } 1016 } 1017 1018 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 1019 const struct fw_img *image) 1020 { 1021 int ret = 0; 1022 int first_ucode_section; 1023 1024 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1025 image->is_dual_cpus ? "Dual" : "Single"); 1026 1027 /* load to FW the binary non secured sections of CPU1 */ 1028 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1029 if (ret) 1030 return ret; 1031 1032 if (image->is_dual_cpus) { 1033 /* set CPU2 header address */ 1034 iwl_write_prph(trans, 1035 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1036 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1037 1038 /* load to FW the binary sections of CPU2 */ 1039 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1040 &first_ucode_section); 1041 if (ret) 1042 return ret; 1043 } 1044 1045 if (iwl_pcie_dbg_on(trans)) 1046 iwl_pcie_apply_destination(trans); 1047 1048 iwl_enable_interrupts(trans); 1049 1050 /* release CPU reset */ 1051 iwl_write32(trans, CSR_RESET, 0); 1052 1053 return 0; 1054 } 1055 1056 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1057 const struct fw_img *image) 1058 { 1059 int ret = 0; 1060 int first_ucode_section; 1061 1062 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1063 image->is_dual_cpus ? "Dual" : "Single"); 1064 1065 if (iwl_pcie_dbg_on(trans)) 1066 iwl_pcie_apply_destination(trans); 1067 1068 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1069 iwl_read_prph(trans, WFPM_GP2)); 1070 1071 /* 1072 * Set default value. On resume reading the values that were 1073 * zeored can provide debug data on the resume flow. 1074 * This is for debugging only and has no functional impact. 1075 */ 1076 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1077 1078 /* configure the ucode to be ready to get the secured image */ 1079 /* release CPU reset */ 1080 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1081 1082 /* load to FW the binary Secured sections of CPU1 */ 1083 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1084 &first_ucode_section); 1085 if (ret) 1086 return ret; 1087 1088 /* load to FW the binary sections of CPU2 */ 1089 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1090 &first_ucode_section); 1091 } 1092 1093 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1094 { 1095 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1096 bool hw_rfkill = iwl_is_rfkill_set(trans); 1097 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1098 bool report; 1099 1100 if (hw_rfkill) { 1101 set_bit(STATUS_RFKILL_HW, &trans->status); 1102 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1103 } else { 1104 clear_bit(STATUS_RFKILL_HW, &trans->status); 1105 if (trans_pcie->opmode_down) 1106 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1107 } 1108 1109 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1110 1111 if (prev != report) 1112 iwl_trans_pcie_rf_kill(trans, report, false); 1113 1114 return hw_rfkill; 1115 } 1116 1117 struct iwl_causes_list { 1118 u16 mask_reg; 1119 u8 bit; 1120 u8 addr; 1121 }; 1122 1123 #define IWL_CAUSE(reg, mask) \ 1124 { \ 1125 .mask_reg = reg, \ 1126 .bit = ilog2(mask), \ 1127 .addr = ilog2(mask) + \ 1128 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1129 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1130 0xffff), /* causes overflow warning */ \ 1131 } 1132 1133 static const struct iwl_causes_list causes_list_common[] = { 1134 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 1135 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 1136 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 1137 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 1138 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 1139 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 1140 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 1141 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR), 1142 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 1143 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 1144 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 1145 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 1146 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 1147 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 1148 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 1149 }; 1150 1151 static const struct iwl_causes_list causes_list_pre_bz[] = { 1152 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1153 }; 1154 1155 static const struct iwl_causes_list causes_list_bz[] = { 1156 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1157 }; 1158 1159 static void iwl_pcie_map_list(struct iwl_trans *trans, 1160 const struct iwl_causes_list *causes, 1161 int arr_size, int val) 1162 { 1163 int i; 1164 1165 for (i = 0; i < arr_size; i++) { 1166 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1167 iwl_clear_bit(trans, causes[i].mask_reg, 1168 BIT(causes[i].bit)); 1169 } 1170 } 1171 1172 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1173 { 1174 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1175 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1176 /* 1177 * Access all non RX causes and map them to the default irq. 1178 * In case we are missing at least one interrupt vector, 1179 * the first interrupt vector will serve non-RX and FBQ causes. 1180 */ 1181 iwl_pcie_map_list(trans, causes_list_common, 1182 ARRAY_SIZE(causes_list_common), val); 1183 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1184 iwl_pcie_map_list(trans, causes_list_bz, 1185 ARRAY_SIZE(causes_list_bz), val); 1186 else 1187 iwl_pcie_map_list(trans, causes_list_pre_bz, 1188 ARRAY_SIZE(causes_list_pre_bz), val); 1189 } 1190 1191 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1192 { 1193 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1194 u32 offset = 1195 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1196 u32 val, idx; 1197 1198 /* 1199 * The first RX queue - fallback queue, which is designated for 1200 * management frame, command responses etc, is always mapped to the 1201 * first interrupt vector. The other RX queues are mapped to 1202 * the other (N - 2) interrupt vectors. 1203 */ 1204 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1205 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1206 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1207 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1208 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1209 } 1210 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1211 1212 val = MSIX_FH_INT_CAUSES_Q(0); 1213 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1214 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1215 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1216 1217 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1218 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1219 } 1220 1221 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1222 { 1223 struct iwl_trans *trans = trans_pcie->trans; 1224 1225 if (!trans_pcie->msix_enabled) { 1226 if (trans->trans_cfg->mq_rx_supported && 1227 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1228 iwl_write_umac_prph(trans, UREG_CHICK, 1229 UREG_CHICK_MSI_ENABLE); 1230 return; 1231 } 1232 /* 1233 * The IVAR table needs to be configured again after reset, 1234 * but if the device is disabled, we can't write to 1235 * prph. 1236 */ 1237 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1238 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1239 1240 /* 1241 * Each cause from the causes list above and the RX causes is 1242 * represented as a byte in the IVAR table. The first nibble 1243 * represents the bound interrupt vector of the cause, the second 1244 * represents no auto clear for this cause. This will be set if its 1245 * interrupt vector is bound to serve other causes. 1246 */ 1247 iwl_pcie_map_rx_causes(trans); 1248 1249 iwl_pcie_map_non_rx_causes(trans); 1250 } 1251 1252 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1253 { 1254 struct iwl_trans *trans = trans_pcie->trans; 1255 1256 iwl_pcie_conf_msix_hw(trans_pcie); 1257 1258 if (!trans_pcie->msix_enabled) 1259 return; 1260 1261 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1262 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1263 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1264 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1265 } 1266 1267 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq) 1268 { 1269 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1270 1271 lockdep_assert_held(&trans_pcie->mutex); 1272 1273 if (trans_pcie->is_down) 1274 return; 1275 1276 trans_pcie->is_down = true; 1277 1278 /* tell the device to stop sending interrupts */ 1279 iwl_disable_interrupts(trans); 1280 1281 /* device going down, Stop using ICT table */ 1282 iwl_pcie_disable_ict(trans); 1283 1284 /* 1285 * If a HW restart happens during firmware loading, 1286 * then the firmware loading might call this function 1287 * and later it might be called again due to the 1288 * restart. So don't process again if the device is 1289 * already dead. 1290 */ 1291 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1292 IWL_DEBUG_INFO(trans, 1293 "DEVICE_ENABLED bit was set and is now cleared\n"); 1294 if (!from_irq) 1295 iwl_pcie_synchronize_irqs(trans); 1296 iwl_pcie_rx_napi_sync(trans); 1297 iwl_pcie_tx_stop(trans); 1298 iwl_pcie_rx_stop(trans); 1299 1300 /* Power-down device's busmaster DMA clocks */ 1301 if (!trans->cfg->apmg_not_supported) { 1302 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1303 APMG_CLK_VAL_DMA_CLK_RQT); 1304 udelay(5); 1305 } 1306 } 1307 1308 /* Make sure (redundant) we've released our request to stay awake */ 1309 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1310 iwl_clear_bit(trans, CSR_GP_CNTRL, 1311 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1312 else 1313 iwl_clear_bit(trans, CSR_GP_CNTRL, 1314 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1315 1316 /* Stop the device, and put it in low power state */ 1317 iwl_pcie_apm_stop(trans, false); 1318 1319 /* re-take ownership to prevent other users from stealing the device */ 1320 iwl_trans_pcie_sw_reset(trans, true); 1321 1322 /* 1323 * Upon stop, the IVAR table gets erased, so msi-x won't 1324 * work. This causes a bug in RF-KILL flows, since the interrupt 1325 * that enables radio won't fire on the correct irq, and the 1326 * driver won't be able to handle the interrupt. 1327 * Configure the IVAR table again after reset. 1328 */ 1329 iwl_pcie_conf_msix_hw(trans_pcie); 1330 1331 /* 1332 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1333 * This is a bug in certain verions of the hardware. 1334 * Certain devices also keep sending HW RF kill interrupt all 1335 * the time, unless the interrupt is ACKed even if the interrupt 1336 * should be masked. Re-ACK all the interrupts here. 1337 */ 1338 iwl_disable_interrupts(trans); 1339 1340 /* clear all status bits */ 1341 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1342 clear_bit(STATUS_INT_ENABLED, &trans->status); 1343 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1344 1345 /* 1346 * Even if we stop the HW, we still want the RF kill 1347 * interrupt 1348 */ 1349 iwl_enable_rfkill_int(trans); 1350 } 1351 1352 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1353 { 1354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1355 1356 if (trans_pcie->msix_enabled) { 1357 int i; 1358 1359 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1360 synchronize_irq(trans_pcie->msix_entries[i].vector); 1361 } else { 1362 synchronize_irq(trans_pcie->pci_dev->irq); 1363 } 1364 } 1365 1366 int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1367 const struct fw_img *fw, bool run_in_rfkill) 1368 { 1369 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1370 bool hw_rfkill; 1371 int ret; 1372 1373 /* This may fail if AMT took ownership of the device */ 1374 if (iwl_pcie_prepare_card_hw(trans)) { 1375 IWL_WARN(trans, "Exit HW not ready\n"); 1376 return -EIO; 1377 } 1378 1379 iwl_enable_rfkill_int(trans); 1380 1381 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1382 1383 /* 1384 * We enabled the RF-Kill interrupt and the handler may very 1385 * well be running. Disable the interrupts to make sure no other 1386 * interrupt can be fired. 1387 */ 1388 iwl_disable_interrupts(trans); 1389 1390 /* Make sure it finished running */ 1391 iwl_pcie_synchronize_irqs(trans); 1392 1393 mutex_lock(&trans_pcie->mutex); 1394 1395 /* If platform's RF_KILL switch is NOT set to KILL */ 1396 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1397 if (hw_rfkill && !run_in_rfkill) { 1398 ret = -ERFKILL; 1399 goto out; 1400 } 1401 1402 /* Someone called stop_device, don't try to start_fw */ 1403 if (trans_pcie->is_down) { 1404 IWL_WARN(trans, 1405 "Can't start_fw since the HW hasn't been started\n"); 1406 ret = -EIO; 1407 goto out; 1408 } 1409 1410 /* make sure rfkill handshake bits are cleared */ 1411 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1412 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1413 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1414 1415 /* clear (again), then enable host interrupts */ 1416 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1417 1418 ret = iwl_pcie_nic_init(trans); 1419 if (ret) { 1420 IWL_ERR(trans, "Unable to init nic\n"); 1421 goto out; 1422 } 1423 1424 /* 1425 * Now, we load the firmware and don't want to be interrupted, even 1426 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1427 * FH_TX interrupt which is needed to load the firmware). If the 1428 * RF-Kill switch is toggled, we will find out after having loaded 1429 * the firmware and return the proper value to the caller. 1430 */ 1431 iwl_enable_fw_load_int(trans); 1432 1433 /* really make sure rfkill handshake bits are cleared */ 1434 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1435 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1436 1437 /* Load the given image to the HW */ 1438 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1439 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1440 else 1441 ret = iwl_pcie_load_given_ucode(trans, fw); 1442 1443 /* re-check RF-Kill state since we may have missed the interrupt */ 1444 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1445 if (hw_rfkill && !run_in_rfkill) 1446 ret = -ERFKILL; 1447 1448 out: 1449 mutex_unlock(&trans_pcie->mutex); 1450 return ret; 1451 } 1452 1453 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1454 { 1455 iwl_pcie_reset_ict(trans); 1456 iwl_pcie_tx_start(trans, scd_addr); 1457 } 1458 1459 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1460 bool was_in_rfkill) 1461 { 1462 bool hw_rfkill; 1463 1464 /* 1465 * Check again since the RF kill state may have changed while 1466 * all the interrupts were disabled, in this case we couldn't 1467 * receive the RF kill interrupt and update the state in the 1468 * op_mode. 1469 * Don't call the op_mode if the rkfill state hasn't changed. 1470 * This allows the op_mode to call stop_device from the rfkill 1471 * notification without endless recursion. Under very rare 1472 * circumstances, we might have a small recursion if the rfkill 1473 * state changed exactly now while we were called from stop_device. 1474 * This is very unlikely but can happen and is supported. 1475 */ 1476 hw_rfkill = iwl_is_rfkill_set(trans); 1477 if (hw_rfkill) { 1478 set_bit(STATUS_RFKILL_HW, &trans->status); 1479 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1480 } else { 1481 clear_bit(STATUS_RFKILL_HW, &trans->status); 1482 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1483 } 1484 if (hw_rfkill != was_in_rfkill) 1485 iwl_trans_pcie_rf_kill(trans, hw_rfkill, false); 1486 } 1487 1488 void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1489 { 1490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1491 bool was_in_rfkill; 1492 1493 iwl_op_mode_time_point(trans->op_mode, 1494 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1495 NULL); 1496 1497 mutex_lock(&trans_pcie->mutex); 1498 trans_pcie->opmode_down = true; 1499 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1500 _iwl_trans_pcie_stop_device(trans, false); 1501 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1502 mutex_unlock(&trans_pcie->mutex); 1503 } 1504 1505 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq) 1506 { 1507 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1508 IWL_TRANS_GET_PCIE_TRANS(trans); 1509 1510 lockdep_assert_held(&trans_pcie->mutex); 1511 1512 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1513 state ? "disabled" : "enabled"); 1514 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) && 1515 !WARN_ON(trans->trans_cfg->gen2)) 1516 _iwl_trans_pcie_stop_device(trans, from_irq); 1517 } 1518 1519 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1520 bool test, bool reset) 1521 { 1522 iwl_disable_interrupts(trans); 1523 1524 /* 1525 * in testing mode, the host stays awake and the 1526 * hardware won't be reset (not even partially) 1527 */ 1528 if (test) 1529 return; 1530 1531 iwl_pcie_disable_ict(trans); 1532 1533 iwl_pcie_synchronize_irqs(trans); 1534 1535 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1536 iwl_clear_bit(trans, CSR_GP_CNTRL, 1537 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1538 iwl_clear_bit(trans, CSR_GP_CNTRL, 1539 CSR_GP_CNTRL_REG_FLAG_MAC_INIT); 1540 } else { 1541 iwl_clear_bit(trans, CSR_GP_CNTRL, 1542 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1543 iwl_clear_bit(trans, CSR_GP_CNTRL, 1544 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1545 } 1546 1547 if (reset) { 1548 /* 1549 * reset TX queues -- some of their registers reset during S3 1550 * so if we don't reset everything here the D3 image would try 1551 * to execute some invalid memory upon resume 1552 */ 1553 iwl_trans_pcie_tx_reset(trans); 1554 } 1555 1556 iwl_pcie_set_pwr(trans, true); 1557 } 1558 1559 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1560 { 1561 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1562 int ret; 1563 1564 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 1565 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1566 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1567 UREG_DOORBELL_TO_ISR6_RESUME); 1568 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1569 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1570 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1571 CSR_IPC_SLEEP_CONTROL_RESUME); 1572 else 1573 return 0; 1574 1575 ret = wait_event_timeout(trans_pcie->sx_waitq, 1576 trans_pcie->sx_complete, 2 * HZ); 1577 1578 /* Invalidate it toward next suspend or resume */ 1579 trans_pcie->sx_complete = false; 1580 1581 if (!ret) { 1582 IWL_ERR(trans, "Timeout %s D3\n", 1583 suspend ? "entering" : "exiting"); 1584 return -ETIMEDOUT; 1585 } 1586 1587 return 0; 1588 } 1589 1590 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset) 1591 { 1592 int ret; 1593 1594 if (!reset) 1595 /* Enable persistence mode to avoid reset */ 1596 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1597 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1598 1599 ret = iwl_pcie_d3_handshake(trans, true); 1600 if (ret) 1601 return ret; 1602 1603 iwl_pcie_d3_complete_suspend(trans, test, reset); 1604 1605 return 0; 1606 } 1607 1608 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1609 enum iwl_d3_status *status, 1610 bool test, bool reset) 1611 { 1612 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1613 u32 val; 1614 int ret; 1615 1616 if (test) { 1617 iwl_enable_interrupts(trans); 1618 *status = IWL_D3_STATUS_ALIVE; 1619 ret = 0; 1620 goto out; 1621 } 1622 1623 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1624 iwl_set_bit(trans, CSR_GP_CNTRL, 1625 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1626 else 1627 iwl_set_bit(trans, CSR_GP_CNTRL, 1628 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1629 1630 ret = iwl_finish_nic_init(trans); 1631 if (ret) 1632 return ret; 1633 1634 /* 1635 * Reconfigure IVAR table in case of MSIX or reset ict table in 1636 * MSI mode since HW reset erased it. 1637 * Also enables interrupts - none will happen as 1638 * the device doesn't know we're waking it up, only when 1639 * the opmode actually tells it after this call. 1640 */ 1641 iwl_pcie_conf_msix_hw(trans_pcie); 1642 if (!trans_pcie->msix_enabled) 1643 iwl_pcie_reset_ict(trans); 1644 iwl_enable_interrupts(trans); 1645 1646 iwl_pcie_set_pwr(trans, false); 1647 1648 if (!reset) { 1649 iwl_clear_bit(trans, CSR_GP_CNTRL, 1650 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1651 } else { 1652 iwl_trans_pcie_tx_reset(trans); 1653 1654 ret = iwl_pcie_rx_init(trans); 1655 if (ret) { 1656 IWL_ERR(trans, 1657 "Failed to resume the device (RX reset)\n"); 1658 return ret; 1659 } 1660 } 1661 1662 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1663 iwl_read_umac_prph(trans, WFPM_GP2)); 1664 1665 val = iwl_read32(trans, CSR_RESET); 1666 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1667 *status = IWL_D3_STATUS_RESET; 1668 else 1669 *status = IWL_D3_STATUS_ALIVE; 1670 1671 out: 1672 if (*status == IWL_D3_STATUS_ALIVE) 1673 ret = iwl_pcie_d3_handshake(trans, false); 1674 1675 return ret; 1676 } 1677 1678 static void 1679 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1680 struct iwl_trans *trans, 1681 const struct iwl_cfg_trans_params *cfg_trans) 1682 { 1683 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1684 int max_irqs, num_irqs, i, ret; 1685 u16 pci_cmd; 1686 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1687 1688 if (!cfg_trans->mq_rx_supported) 1689 goto enable_msi; 1690 1691 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 1692 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1693 1694 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1695 for (i = 0; i < max_irqs; i++) 1696 trans_pcie->msix_entries[i].entry = i; 1697 1698 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1699 MSIX_MIN_INTERRUPT_VECTORS, 1700 max_irqs); 1701 if (num_irqs < 0) { 1702 IWL_DEBUG_INFO(trans, 1703 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1704 num_irqs); 1705 goto enable_msi; 1706 } 1707 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1708 1709 IWL_DEBUG_INFO(trans, 1710 "MSI-X enabled. %d interrupt vectors were allocated\n", 1711 num_irqs); 1712 1713 /* 1714 * In case the OS provides fewer interrupts than requested, different 1715 * causes will share the same interrupt vector as follows: 1716 * One interrupt less: non rx causes shared with FBQ. 1717 * Two interrupts less: non rx causes shared with FBQ and RSS. 1718 * More than two interrupts: we will use fewer RSS queues. 1719 */ 1720 if (num_irqs <= max_irqs - 2) { 1721 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1722 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1723 IWL_SHARED_IRQ_FIRST_RSS; 1724 } else if (num_irqs == max_irqs - 1) { 1725 trans_pcie->trans->num_rx_queues = num_irqs; 1726 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1727 } else { 1728 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1729 } 1730 1731 IWL_DEBUG_INFO(trans, 1732 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1733 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 1734 1735 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1736 1737 trans_pcie->alloc_vecs = num_irqs; 1738 trans_pcie->msix_enabled = true; 1739 return; 1740 1741 enable_msi: 1742 ret = pci_enable_msi(pdev); 1743 if (ret) { 1744 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1745 /* enable rfkill interrupt: hw bug w/a */ 1746 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1747 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1748 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1749 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1750 } 1751 } 1752 } 1753 1754 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1755 { 1756 #if defined(CONFIG_SMP) 1757 int iter_rx_q, i, ret, cpu, offset; 1758 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1759 1760 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1761 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1762 offset = 1 + i; 1763 for (; i < iter_rx_q ; i++) { 1764 /* 1765 * Get the cpu prior to the place to search 1766 * (i.e. return will be > i - 1). 1767 */ 1768 cpu = cpumask_next(i - offset, cpu_online_mask); 1769 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1770 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1771 &trans_pcie->affinity_mask[i]); 1772 if (ret) 1773 IWL_ERR(trans_pcie->trans, 1774 "Failed to set affinity mask for IRQ %d\n", 1775 trans_pcie->msix_entries[i].vector); 1776 } 1777 #endif 1778 } 1779 1780 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1781 struct iwl_trans_pcie *trans_pcie) 1782 { 1783 int i; 1784 1785 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1786 int ret; 1787 struct msix_entry *msix_entry; 1788 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1789 1790 if (!qname) 1791 return -ENOMEM; 1792 1793 msix_entry = &trans_pcie->msix_entries[i]; 1794 ret = devm_request_threaded_irq(&pdev->dev, 1795 msix_entry->vector, 1796 iwl_pcie_msix_isr, 1797 (i == trans_pcie->def_irq) ? 1798 iwl_pcie_irq_msix_handler : 1799 iwl_pcie_irq_rx_msix_handler, 1800 IRQF_SHARED, 1801 qname, 1802 msix_entry); 1803 if (ret) { 1804 IWL_ERR(trans_pcie->trans, 1805 "Error allocating IRQ %d\n", i); 1806 1807 return ret; 1808 } 1809 } 1810 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1811 1812 return 0; 1813 } 1814 1815 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1816 { 1817 u32 hpm, wprot; 1818 1819 switch (trans->trans_cfg->device_family) { 1820 case IWL_DEVICE_FAMILY_9000: 1821 wprot = PREG_PRPH_WPROT_9000; 1822 break; 1823 case IWL_DEVICE_FAMILY_22000: 1824 wprot = PREG_PRPH_WPROT_22000; 1825 break; 1826 default: 1827 return 0; 1828 } 1829 1830 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1831 if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) { 1832 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1833 1834 if (wprot_val & PREG_WFPM_ACCESS) { 1835 IWL_ERR(trans, 1836 "Error, can not clear persistence bit\n"); 1837 return -EPERM; 1838 } 1839 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1840 hpm & ~PERSISTENCE_BIT); 1841 } 1842 1843 return 0; 1844 } 1845 1846 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1847 { 1848 int ret; 1849 1850 ret = iwl_finish_nic_init(trans); 1851 if (ret < 0) 1852 return ret; 1853 1854 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1855 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1856 udelay(20); 1857 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1858 HPM_HIPM_GEN_CFG_CR_PG_EN | 1859 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1860 udelay(20); 1861 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1862 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1863 1864 return iwl_trans_pcie_sw_reset(trans, true); 1865 } 1866 1867 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1868 { 1869 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1870 int err; 1871 1872 lockdep_assert_held(&trans_pcie->mutex); 1873 1874 err = iwl_pcie_prepare_card_hw(trans); 1875 if (err) { 1876 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1877 return err; 1878 } 1879 1880 err = iwl_trans_pcie_clear_persistence_bit(trans); 1881 if (err) 1882 return err; 1883 1884 err = iwl_trans_pcie_sw_reset(trans, true); 1885 if (err) 1886 return err; 1887 1888 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1889 trans->trans_cfg->integrated) { 1890 err = iwl_pcie_gen2_force_power_gating(trans); 1891 if (err) 1892 return err; 1893 } 1894 1895 err = iwl_pcie_apm_init(trans); 1896 if (err) 1897 return err; 1898 1899 iwl_pcie_init_msix(trans_pcie); 1900 1901 /* From now on, the op_mode will be kept updated about RF kill state */ 1902 iwl_enable_rfkill_int(trans); 1903 1904 trans_pcie->opmode_down = false; 1905 1906 /* Set is_down to false here so that...*/ 1907 trans_pcie->is_down = false; 1908 1909 /* ...rfkill can call stop_device and set it false if needed */ 1910 iwl_pcie_check_hw_rf_kill(trans); 1911 1912 return 0; 1913 } 1914 1915 int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1916 { 1917 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1918 int ret; 1919 1920 mutex_lock(&trans_pcie->mutex); 1921 ret = _iwl_trans_pcie_start_hw(trans); 1922 mutex_unlock(&trans_pcie->mutex); 1923 1924 return ret; 1925 } 1926 1927 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1928 { 1929 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1930 1931 mutex_lock(&trans_pcie->mutex); 1932 1933 /* disable interrupts - don't enable HW RF kill interrupt */ 1934 iwl_disable_interrupts(trans); 1935 1936 iwl_pcie_apm_stop(trans, true); 1937 1938 iwl_disable_interrupts(trans); 1939 1940 iwl_pcie_disable_ict(trans); 1941 1942 mutex_unlock(&trans_pcie->mutex); 1943 1944 iwl_pcie_synchronize_irqs(trans); 1945 } 1946 1947 #if defined(__linux__) 1948 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1949 { 1950 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1951 } 1952 1953 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1954 { 1955 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1956 } 1957 1958 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1959 { 1960 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1961 } 1962 #elif defined(__FreeBSD__) 1963 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1964 { 1965 1966 IWL_DEBUG_PCI_RW(trans, "W1 %#010x %#04x\n", ofs, val); 1967 bus_write_1((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs, val); 1968 } 1969 1970 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1971 { 1972 1973 IWL_DEBUG_PCI_RW(trans, "W4 %#010x %#010x\n", ofs, val); 1974 bus_write_4((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs, val); 1975 } 1976 1977 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1978 { 1979 u32 v; 1980 1981 v = bus_read_4((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs); 1982 IWL_DEBUG_PCI_RW(trans, "R4 %#010x %#010x\n", ofs, v); 1983 return (v); 1984 } 1985 #endif 1986 1987 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1988 { 1989 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1990 return 0x00FFFFFF; 1991 else 1992 return 0x000FFFFF; 1993 } 1994 1995 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1996 { 1997 u32 mask = iwl_trans_pcie_prph_msk(trans); 1998 1999 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 2000 ((reg & mask) | (3 << 24))); 2001 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 2002 } 2003 2004 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val) 2005 { 2006 u32 mask = iwl_trans_pcie_prph_msk(trans); 2007 2008 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 2009 ((addr & mask) | (3 << 24))); 2010 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 2011 } 2012 2013 void iwl_trans_pcie_configure(struct iwl_trans *trans, 2014 const struct iwl_trans_config *trans_cfg) 2015 { 2016 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2017 2018 /* free all first - we might be reconfigured for a different size */ 2019 iwl_pcie_free_rbs_pool(trans); 2020 2021 trans_pcie->txqs.cmd.q_id = trans_cfg->cmd_queue; 2022 trans_pcie->txqs.cmd.fifo = trans_cfg->cmd_fifo; 2023 trans_pcie->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 2024 trans_pcie->txqs.page_offs = trans_cfg->cb_data_offs; 2025 trans_pcie->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 2026 trans_pcie->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; 2027 2028 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 2029 trans_pcie->n_no_reclaim_cmds = 0; 2030 else 2031 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 2032 if (trans_pcie->n_no_reclaim_cmds) 2033 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 2034 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 2035 2036 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 2037 trans_pcie->rx_page_order = 2038 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 2039 trans_pcie->rx_buf_bytes = 2040 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 2041 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 2042 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 2043 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 2044 2045 trans_pcie->txqs.bc_table_dword = trans_cfg->bc_table_dword; 2046 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 2047 2048 trans->command_groups = trans_cfg->command_groups; 2049 trans->command_groups_size = trans_cfg->command_groups_size; 2050 2051 2052 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 2053 } 2054 2055 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions, 2056 struct device *dev) 2057 { 2058 u8 i; 2059 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 2060 2061 /* free DRAM payloads */ 2062 for (i = 0; i < dram_regions->n_regions; i++) { 2063 dma_free_coherent(dev, dram_regions->drams[i].size, 2064 dram_regions->drams[i].block, 2065 dram_regions->drams[i].physical); 2066 } 2067 dram_regions->n_regions = 0; 2068 2069 /* free DRAM addresses array */ 2070 if (desc_dram->block) { 2071 dma_free_coherent(dev, desc_dram->size, 2072 desc_dram->block, 2073 desc_dram->physical); 2074 } 2075 memset(desc_dram, 0, sizeof(*desc_dram)); 2076 } 2077 2078 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans) 2079 { 2080 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd); 2081 } 2082 2083 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans) 2084 { 2085 struct iwl_cmd_header_wide bad_cmd = { 2086 .cmd = INVALID_WR_PTR_CMD, 2087 .group_id = DEBUG_GROUP, 2088 .sequence = cpu_to_le16(0xffff), 2089 .length = cpu_to_le16(0), 2090 .version = 0, 2091 }; 2092 int ret; 2093 2094 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd, 2095 sizeof(bad_cmd)); 2096 if (ret) 2097 return ret; 2098 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); 2099 return 0; 2100 } 2101 2102 void iwl_trans_pcie_free(struct iwl_trans *trans) 2103 { 2104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2105 int i; 2106 2107 iwl_pcie_synchronize_irqs(trans); 2108 2109 if (trans->trans_cfg->gen2) 2110 iwl_txq_gen2_tx_free(trans); 2111 else 2112 iwl_pcie_tx_free(trans); 2113 iwl_pcie_rx_free(trans); 2114 2115 if (trans_pcie->rba.alloc_wq) { 2116 destroy_workqueue(trans_pcie->rba.alloc_wq); 2117 trans_pcie->rba.alloc_wq = NULL; 2118 } 2119 2120 if (trans_pcie->msix_enabled) { 2121 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 2122 irq_set_affinity_hint( 2123 trans_pcie->msix_entries[i].vector, 2124 NULL); 2125 } 2126 2127 trans_pcie->msix_enabled = false; 2128 } else { 2129 iwl_pcie_free_ict(trans); 2130 } 2131 2132 free_netdev(trans_pcie->napi_dev); 2133 2134 iwl_pcie_free_invalid_tx_cmd(trans); 2135 2136 iwl_pcie_free_fw_monitor(trans); 2137 2138 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, 2139 trans->dev); 2140 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data, 2141 trans->dev); 2142 2143 mutex_destroy(&trans_pcie->mutex); 2144 2145 #ifdef CONFIG_INET 2146 if (trans_pcie->txqs.tso_hdr_page) { 2147 for_each_possible_cpu(i) { 2148 struct iwl_tso_hdr_page *p = 2149 per_cpu_ptr(trans_pcie->txqs.tso_hdr_page, i); 2150 2151 if (p && p->page) 2152 __free_page(p->page); 2153 } 2154 2155 free_percpu(trans_pcie->txqs.tso_hdr_page); 2156 } 2157 #endif 2158 2159 iwl_trans_free(trans); 2160 } 2161 2162 struct iwl_trans_pcie_removal { 2163 struct pci_dev *pdev; 2164 struct work_struct work; 2165 bool rescan; 2166 }; 2167 2168 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2169 { 2170 struct iwl_trans_pcie_removal *removal = 2171 container_of(wk, struct iwl_trans_pcie_removal, work); 2172 struct pci_dev *pdev = removal->pdev; 2173 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2174 struct pci_bus *bus; 2175 2176 pci_lock_rescan_remove(); 2177 2178 bus = pdev->bus; 2179 /* in this case, something else already removed the device */ 2180 if (!bus) 2181 goto out; 2182 2183 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 2184 2185 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2186 2187 pci_stop_and_remove_bus_device(pdev); 2188 pci_dev_put(pdev); 2189 2190 if (removal->rescan) { 2191 #if defined(__linux__) 2192 if (bus->parent) 2193 bus = bus->parent; 2194 #endif 2195 pci_rescan_bus(bus); 2196 } 2197 2198 out: 2199 pci_unlock_rescan_remove(); 2200 2201 kfree(removal); 2202 module_put(THIS_MODULE); 2203 } 2204 2205 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan) 2206 { 2207 struct iwl_trans_pcie_removal *removal; 2208 2209 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2210 return; 2211 2212 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2213 iwl_pcie_dump_csr(trans); 2214 2215 /* 2216 * get a module reference to avoid doing this 2217 * while unloading anyway and to avoid 2218 * scheduling a work with code that's being 2219 * removed. 2220 */ 2221 if (!try_module_get(THIS_MODULE)) { 2222 IWL_ERR(trans, 2223 "Module is being unloaded - abort\n"); 2224 return; 2225 } 2226 2227 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2228 if (!removal) { 2229 module_put(THIS_MODULE); 2230 return; 2231 } 2232 /* 2233 * we don't need to clear this flag, because 2234 * the trans will be freed and reallocated. 2235 */ 2236 set_bit(STATUS_TRANS_DEAD, &trans->status); 2237 2238 removal->pdev = to_pci_dev(trans->dev); 2239 removal->rescan = rescan; 2240 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2241 pci_dev_get(removal->pdev); 2242 schedule_work(&removal->work); 2243 } 2244 EXPORT_SYMBOL(iwl_trans_pcie_remove); 2245 2246 /* 2247 * This version doesn't disable BHs but rather assumes they're 2248 * already disabled. 2249 */ 2250 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2251 { 2252 int ret; 2253 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2254 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2255 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2256 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2257 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2258 2259 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2260 return false; 2261 2262 spin_lock(&trans_pcie->reg_lock); 2263 2264 if (trans_pcie->cmd_hold_nic_awake) 2265 goto out; 2266 2267 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2268 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2269 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2270 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2271 } 2272 2273 /* this bit wakes up the NIC */ 2274 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2275 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2276 udelay(2); 2277 2278 /* 2279 * These bits say the device is running, and should keep running for 2280 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2281 * but they do not indicate that embedded SRAM is restored yet; 2282 * HW with volatile SRAM must save/restore contents to/from 2283 * host DRAM when sleeping/waking for power-saving. 2284 * Each direction takes approximately 1/4 millisecond; with this 2285 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2286 * series of register accesses are expected (e.g. reading Event Log), 2287 * to keep device from sleeping. 2288 * 2289 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2290 * SRAM is okay/restored. We don't check that here because this call 2291 * is just for hardware register access; but GP1 MAC_SLEEP 2292 * check is a good idea before accessing the SRAM of HW with 2293 * volatile SRAM (e.g. reading Event Log). 2294 * 2295 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2296 * and do not save/restore SRAM when power cycling. 2297 */ 2298 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2299 if (unlikely(ret < 0)) { 2300 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2301 2302 WARN_ONCE(1, 2303 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2304 cntrl); 2305 2306 iwl_trans_pcie_dump_regs(trans); 2307 2308 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2309 iwl_trans_pcie_remove(trans, false); 2310 else 2311 iwl_write32(trans, CSR_RESET, 2312 CSR_RESET_REG_FLAG_FORCE_NMI); 2313 2314 spin_unlock(&trans_pcie->reg_lock); 2315 return false; 2316 } 2317 2318 out: 2319 /* 2320 * Fool sparse by faking we release the lock - sparse will 2321 * track nic_access anyway. 2322 */ 2323 __release(&trans_pcie->reg_lock); 2324 return true; 2325 } 2326 2327 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2328 { 2329 bool ret; 2330 2331 local_bh_disable(); 2332 ret = __iwl_trans_pcie_grab_nic_access(trans); 2333 if (ret) { 2334 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2335 return ret; 2336 } 2337 local_bh_enable(); 2338 return false; 2339 } 2340 2341 void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2342 { 2343 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2344 2345 lockdep_assert_held(&trans_pcie->reg_lock); 2346 2347 /* 2348 * Fool sparse by faking we acquiring the lock - sparse will 2349 * track nic_access anyway. 2350 */ 2351 __acquire(&trans_pcie->reg_lock); 2352 2353 if (trans_pcie->cmd_hold_nic_awake) 2354 goto out; 2355 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2356 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2357 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2358 else 2359 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2360 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2361 /* 2362 * Above we read the CSR_GP_CNTRL register, which will flush 2363 * any previous writes, but we need the write that clears the 2364 * MAC_ACCESS_REQ bit to be performed before any other writes 2365 * scheduled on different CPUs (after we drop reg_lock). 2366 */ 2367 out: 2368 spin_unlock_bh(&trans_pcie->reg_lock); 2369 } 2370 2371 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2372 void *buf, int dwords) 2373 { 2374 #define IWL_MAX_HW_ERRS 5 2375 unsigned int num_consec_hw_errors = 0; 2376 int offs = 0; 2377 u32 *vals = buf; 2378 2379 while (offs < dwords) { 2380 /* limit the time we spin here under lock to 1/2s */ 2381 unsigned long end = jiffies + HZ / 2; 2382 bool resched = false; 2383 2384 if (iwl_trans_grab_nic_access(trans)) { 2385 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2386 addr + 4 * offs); 2387 2388 while (offs < dwords) { 2389 vals[offs] = iwl_read32(trans, 2390 HBUS_TARG_MEM_RDAT); 2391 2392 if (iwl_trans_is_hw_error_value(vals[offs])) 2393 num_consec_hw_errors++; 2394 else 2395 num_consec_hw_errors = 0; 2396 2397 if (num_consec_hw_errors >= IWL_MAX_HW_ERRS) { 2398 iwl_trans_release_nic_access(trans); 2399 return -EIO; 2400 } 2401 2402 offs++; 2403 2404 if (time_after(jiffies, end)) { 2405 resched = true; 2406 break; 2407 } 2408 } 2409 iwl_trans_release_nic_access(trans); 2410 2411 if (resched) 2412 cond_resched(); 2413 } else { 2414 return -EBUSY; 2415 } 2416 } 2417 2418 return 0; 2419 } 2420 2421 int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2422 const void *buf, int dwords) 2423 { 2424 int offs, ret = 0; 2425 const u32 *vals = buf; 2426 2427 if (iwl_trans_grab_nic_access(trans)) { 2428 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2429 for (offs = 0; offs < dwords; offs++) 2430 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2431 vals ? vals[offs] : 0); 2432 iwl_trans_release_nic_access(trans); 2433 } else { 2434 ret = -EBUSY; 2435 } 2436 return ret; 2437 } 2438 2439 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2440 u32 *val) 2441 { 2442 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2443 ofs, val); 2444 } 2445 2446 #define IWL_FLUSH_WAIT_MS 2000 2447 2448 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2449 struct iwl_trans_rxq_dma_data *data) 2450 { 2451 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2452 2453 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2454 return -EINVAL; 2455 2456 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2457 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2458 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2459 data->fr_bd_wid = 0; 2460 2461 return 0; 2462 } 2463 2464 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2465 { 2466 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2467 struct iwl_txq *txq; 2468 unsigned long now = jiffies; 2469 bool overflow_tx; 2470 u8 wr_ptr; 2471 2472 /* Make sure the NIC is still alive in the bus */ 2473 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2474 return -ENODEV; 2475 2476 if (!test_bit(txq_idx, trans_pcie->txqs.queue_used)) 2477 return -EINVAL; 2478 2479 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2480 txq = trans_pcie->txqs.txq[txq_idx]; 2481 2482 spin_lock_bh(&txq->lock); 2483 overflow_tx = txq->overflow_tx || 2484 !skb_queue_empty(&txq->overflow_q); 2485 spin_unlock_bh(&txq->lock); 2486 2487 wr_ptr = READ_ONCE(txq->write_ptr); 2488 2489 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2490 overflow_tx) && 2491 !time_after(jiffies, 2492 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2493 u8 write_ptr = READ_ONCE(txq->write_ptr); 2494 2495 /* 2496 * If write pointer moved during the wait, warn only 2497 * if the TX came from op mode. In case TX came from 2498 * trans layer (overflow TX) don't warn. 2499 */ 2500 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2501 "WR pointer moved while flushing %d -> %d\n", 2502 wr_ptr, write_ptr)) 2503 return -ETIMEDOUT; 2504 wr_ptr = write_ptr; 2505 2506 usleep_range(1000, 2000); 2507 2508 spin_lock_bh(&txq->lock); 2509 overflow_tx = txq->overflow_tx || 2510 !skb_queue_empty(&txq->overflow_q); 2511 spin_unlock_bh(&txq->lock); 2512 } 2513 2514 if (txq->read_ptr != txq->write_ptr) { 2515 IWL_ERR(trans, 2516 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2517 iwl_txq_log_scd_error(trans, txq); 2518 return -ETIMEDOUT; 2519 } 2520 2521 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2522 2523 return 0; 2524 } 2525 2526 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2527 { 2528 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2529 int cnt; 2530 int ret = 0; 2531 2532 /* waiting for all the tx frames complete might take a while */ 2533 for (cnt = 0; 2534 cnt < trans->trans_cfg->base_params->num_of_queues; 2535 cnt++) { 2536 2537 if (cnt == trans_pcie->txqs.cmd.q_id) 2538 continue; 2539 if (!test_bit(cnt, trans_pcie->txqs.queue_used)) 2540 continue; 2541 if (!(BIT(cnt) & txq_bm)) 2542 continue; 2543 2544 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2545 if (ret) 2546 break; 2547 } 2548 2549 return ret; 2550 } 2551 2552 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2553 u32 mask, u32 value) 2554 { 2555 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2556 2557 spin_lock_bh(&trans_pcie->reg_lock); 2558 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2559 spin_unlock_bh(&trans_pcie->reg_lock); 2560 } 2561 2562 static const char *get_csr_string(int cmd) 2563 { 2564 #define IWL_CMD(x) case x: return #x 2565 switch (cmd) { 2566 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2567 IWL_CMD(CSR_INT_COALESCING); 2568 IWL_CMD(CSR_INT); 2569 IWL_CMD(CSR_INT_MASK); 2570 IWL_CMD(CSR_FH_INT_STATUS); 2571 IWL_CMD(CSR_GPIO_IN); 2572 IWL_CMD(CSR_RESET); 2573 IWL_CMD(CSR_GP_CNTRL); 2574 IWL_CMD(CSR_HW_REV); 2575 IWL_CMD(CSR_EEPROM_REG); 2576 IWL_CMD(CSR_EEPROM_GP); 2577 IWL_CMD(CSR_OTP_GP_REG); 2578 IWL_CMD(CSR_GIO_REG); 2579 IWL_CMD(CSR_GP_UCODE_REG); 2580 IWL_CMD(CSR_GP_DRIVER_REG); 2581 IWL_CMD(CSR_UCODE_DRV_GP1); 2582 IWL_CMD(CSR_UCODE_DRV_GP2); 2583 IWL_CMD(CSR_LED_REG); 2584 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2585 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2586 IWL_CMD(CSR_ANA_PLL_CFG); 2587 IWL_CMD(CSR_HW_REV_WA_REG); 2588 IWL_CMD(CSR_MONITOR_STATUS_REG); 2589 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2590 default: 2591 return "UNKNOWN"; 2592 } 2593 #undef IWL_CMD 2594 } 2595 2596 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2597 { 2598 int i; 2599 static const u32 csr_tbl[] = { 2600 CSR_HW_IF_CONFIG_REG, 2601 CSR_INT_COALESCING, 2602 CSR_INT, 2603 CSR_INT_MASK, 2604 CSR_FH_INT_STATUS, 2605 CSR_GPIO_IN, 2606 CSR_RESET, 2607 CSR_GP_CNTRL, 2608 CSR_HW_REV, 2609 CSR_EEPROM_REG, 2610 CSR_EEPROM_GP, 2611 CSR_OTP_GP_REG, 2612 CSR_GIO_REG, 2613 CSR_GP_UCODE_REG, 2614 CSR_GP_DRIVER_REG, 2615 CSR_UCODE_DRV_GP1, 2616 CSR_UCODE_DRV_GP2, 2617 CSR_LED_REG, 2618 CSR_DRAM_INT_TBL_REG, 2619 CSR_GIO_CHICKEN_BITS, 2620 CSR_ANA_PLL_CFG, 2621 CSR_MONITOR_STATUS_REG, 2622 CSR_HW_REV_WA_REG, 2623 CSR_DBG_HPET_MEM_REG 2624 }; 2625 IWL_ERR(trans, "CSR values:\n"); 2626 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2627 "CSR_INT_PERIODIC_REG)\n"); 2628 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2629 IWL_ERR(trans, " %25s: 0X%08x\n", 2630 get_csr_string(csr_tbl[i]), 2631 iwl_read32(trans, csr_tbl[i])); 2632 } 2633 } 2634 2635 #ifdef CONFIG_IWLWIFI_DEBUGFS 2636 /* create and remove of files */ 2637 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2638 debugfs_create_file(#name, mode, parent, trans, \ 2639 &iwl_dbgfs_##name##_ops); \ 2640 } while (0) 2641 2642 /* file operation */ 2643 #define DEBUGFS_READ_FILE_OPS(name) \ 2644 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2645 .read = iwl_dbgfs_##name##_read, \ 2646 .open = simple_open, \ 2647 .llseek = generic_file_llseek, \ 2648 }; 2649 2650 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2651 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2652 .write = iwl_dbgfs_##name##_write, \ 2653 .open = simple_open, \ 2654 .llseek = generic_file_llseek, \ 2655 }; 2656 2657 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2658 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2659 .write = iwl_dbgfs_##name##_write, \ 2660 .read = iwl_dbgfs_##name##_read, \ 2661 .open = simple_open, \ 2662 .llseek = generic_file_llseek, \ 2663 }; 2664 2665 struct iwl_dbgfs_tx_queue_priv { 2666 struct iwl_trans *trans; 2667 }; 2668 2669 struct iwl_dbgfs_tx_queue_state { 2670 loff_t pos; 2671 }; 2672 2673 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2674 { 2675 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2676 struct iwl_dbgfs_tx_queue_state *state; 2677 2678 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2679 return NULL; 2680 2681 state = kmalloc(sizeof(*state), GFP_KERNEL); 2682 if (!state) 2683 return NULL; 2684 state->pos = *pos; 2685 return state; 2686 } 2687 2688 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2689 void *v, loff_t *pos) 2690 { 2691 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2692 struct iwl_dbgfs_tx_queue_state *state = v; 2693 2694 *pos = ++state->pos; 2695 2696 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2697 return NULL; 2698 2699 return state; 2700 } 2701 2702 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2703 { 2704 kfree(v); 2705 } 2706 2707 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2708 { 2709 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2710 struct iwl_dbgfs_tx_queue_state *state = v; 2711 struct iwl_trans *trans = priv->trans; 2712 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2713 struct iwl_txq *txq = trans_pcie->txqs.txq[state->pos]; 2714 2715 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2716 (unsigned int)state->pos, 2717 !!test_bit(state->pos, trans_pcie->txqs.queue_used), 2718 !!test_bit(state->pos, trans_pcie->txqs.queue_stopped)); 2719 if (txq) 2720 seq_printf(seq, 2721 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2722 txq->read_ptr, txq->write_ptr, 2723 txq->need_update, txq->frozen, 2724 txq->n_window, txq->ampdu); 2725 else 2726 seq_puts(seq, "(unallocated)"); 2727 2728 if (state->pos == trans_pcie->txqs.cmd.q_id) 2729 seq_puts(seq, " (HCMD)"); 2730 seq_puts(seq, "\n"); 2731 2732 return 0; 2733 } 2734 2735 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2736 .start = iwl_dbgfs_tx_queue_seq_start, 2737 .next = iwl_dbgfs_tx_queue_seq_next, 2738 .stop = iwl_dbgfs_tx_queue_seq_stop, 2739 .show = iwl_dbgfs_tx_queue_seq_show, 2740 }; 2741 2742 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2743 { 2744 struct iwl_dbgfs_tx_queue_priv *priv; 2745 2746 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2747 sizeof(*priv)); 2748 2749 if (!priv) 2750 return -ENOMEM; 2751 2752 priv->trans = inode->i_private; 2753 return 0; 2754 } 2755 2756 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2757 char __user *user_buf, 2758 size_t count, loff_t *ppos) 2759 { 2760 struct iwl_trans *trans = file->private_data; 2761 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2762 char *buf; 2763 int pos = 0, i, ret; 2764 size_t bufsz; 2765 2766 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2767 2768 if (!trans_pcie->rxq) 2769 return -EAGAIN; 2770 2771 buf = kzalloc(bufsz, GFP_KERNEL); 2772 if (!buf) 2773 return -ENOMEM; 2774 2775 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2776 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2777 2778 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2779 i); 2780 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2781 rxq->read); 2782 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2783 rxq->write); 2784 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2785 rxq->write_actual); 2786 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2787 rxq->need_update); 2788 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2789 rxq->free_count); 2790 if (rxq->rb_stts) { 2791 u32 r = iwl_get_closed_rb_stts(trans, rxq); 2792 pos += scnprintf(buf + pos, bufsz - pos, 2793 "\tclosed_rb_num: %u\n", r); 2794 } else { 2795 pos += scnprintf(buf + pos, bufsz - pos, 2796 "\tclosed_rb_num: Not Allocated\n"); 2797 } 2798 } 2799 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2800 kfree(buf); 2801 2802 return ret; 2803 } 2804 2805 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2806 char __user *user_buf, 2807 size_t count, loff_t *ppos) 2808 { 2809 struct iwl_trans *trans = file->private_data; 2810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2811 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2812 2813 int pos = 0; 2814 char *buf; 2815 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2816 ssize_t ret; 2817 2818 buf = kzalloc(bufsz, GFP_KERNEL); 2819 if (!buf) 2820 return -ENOMEM; 2821 2822 pos += scnprintf(buf + pos, bufsz - pos, 2823 "Interrupt Statistics Report:\n"); 2824 2825 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2826 isr_stats->hw); 2827 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2828 isr_stats->sw); 2829 if (isr_stats->sw || isr_stats->hw) { 2830 pos += scnprintf(buf + pos, bufsz - pos, 2831 "\tLast Restarting Code: 0x%X\n", 2832 isr_stats->err_code); 2833 } 2834 #ifdef CONFIG_IWLWIFI_DEBUG 2835 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2836 isr_stats->sch); 2837 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2838 isr_stats->alive); 2839 #endif 2840 pos += scnprintf(buf + pos, bufsz - pos, 2841 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2842 2843 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2844 isr_stats->ctkill); 2845 2846 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2847 isr_stats->wakeup); 2848 2849 pos += scnprintf(buf + pos, bufsz - pos, 2850 "Rx command responses:\t\t %u\n", isr_stats->rx); 2851 2852 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2853 isr_stats->tx); 2854 2855 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2856 isr_stats->unhandled); 2857 2858 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2859 kfree(buf); 2860 return ret; 2861 } 2862 2863 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2864 const char __user *user_buf, 2865 size_t count, loff_t *ppos) 2866 { 2867 struct iwl_trans *trans = file->private_data; 2868 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2869 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2870 u32 reset_flag; 2871 int ret; 2872 2873 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2874 if (ret) 2875 return ret; 2876 if (reset_flag == 0) 2877 memset(isr_stats, 0, sizeof(*isr_stats)); 2878 2879 return count; 2880 } 2881 2882 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2883 const char __user *user_buf, 2884 size_t count, loff_t *ppos) 2885 { 2886 struct iwl_trans *trans = file->private_data; 2887 2888 iwl_pcie_dump_csr(trans); 2889 2890 return count; 2891 } 2892 2893 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2894 char __user *user_buf, 2895 size_t count, loff_t *ppos) 2896 { 2897 struct iwl_trans *trans = file->private_data; 2898 char *buf = NULL; 2899 ssize_t ret; 2900 2901 ret = iwl_dump_fh(trans, &buf); 2902 if (ret < 0) 2903 return ret; 2904 if (!buf) 2905 return -EINVAL; 2906 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2907 kfree(buf); 2908 return ret; 2909 } 2910 2911 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2912 char __user *user_buf, 2913 size_t count, loff_t *ppos) 2914 { 2915 struct iwl_trans *trans = file->private_data; 2916 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2917 char buf[100]; 2918 int pos; 2919 2920 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2921 trans_pcie->debug_rfkill, 2922 !(iwl_read32(trans, CSR_GP_CNTRL) & 2923 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2924 2925 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2926 } 2927 2928 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2929 const char __user *user_buf, 2930 size_t count, loff_t *ppos) 2931 { 2932 struct iwl_trans *trans = file->private_data; 2933 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2934 bool new_value; 2935 int ret; 2936 2937 ret = kstrtobool_from_user(user_buf, count, &new_value); 2938 if (ret) 2939 return ret; 2940 if (new_value == trans_pcie->debug_rfkill) 2941 return count; 2942 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2943 trans_pcie->debug_rfkill, new_value); 2944 trans_pcie->debug_rfkill = new_value; 2945 iwl_pcie_handle_rfkill_irq(trans, false); 2946 2947 return count; 2948 } 2949 2950 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2951 struct file *file) 2952 { 2953 struct iwl_trans *trans = inode->i_private; 2954 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2955 2956 if (!trans->dbg.dest_tlv || 2957 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2958 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2959 return -ENOENT; 2960 } 2961 2962 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2963 return -EBUSY; 2964 2965 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2966 return simple_open(inode, file); 2967 } 2968 2969 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2970 struct file *file) 2971 { 2972 struct iwl_trans_pcie *trans_pcie = 2973 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2974 2975 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2976 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2977 return 0; 2978 } 2979 2980 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2981 void *buf, ssize_t *size, 2982 ssize_t *bytes_copied) 2983 { 2984 ssize_t buf_size_left = count - *bytes_copied; 2985 2986 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2987 if (*size > buf_size_left) 2988 *size = buf_size_left; 2989 2990 *size -= copy_to_user(user_buf, buf, *size); 2991 *bytes_copied += *size; 2992 2993 if (buf_size_left == *size) 2994 return true; 2995 return false; 2996 } 2997 2998 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2999 char __user *user_buf, 3000 size_t count, loff_t *ppos) 3001 { 3002 struct iwl_trans *trans = file->private_data; 3003 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3004 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 3005 struct cont_rec *data = &trans_pcie->fw_mon_data; 3006 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 3007 ssize_t size, bytes_copied = 0; 3008 bool b_full; 3009 3010 if (trans->dbg.dest_tlv) { 3011 write_ptr_addr = 3012 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3013 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3014 } else { 3015 write_ptr_addr = MON_BUFF_WRPTR; 3016 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 3017 } 3018 3019 if (unlikely(!trans->dbg.rec_on)) 3020 return 0; 3021 3022 mutex_lock(&data->mutex); 3023 if (data->state == 3024 IWL_FW_MON_DBGFS_STATE_DISABLED) { 3025 mutex_unlock(&data->mutex); 3026 return 0; 3027 } 3028 3029 /* write_ptr position in bytes rather then DW */ 3030 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 3031 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 3032 3033 if (data->prev_wrap_cnt == wrap_cnt) { 3034 size = write_ptr - data->prev_wr_ptr; 3035 curr_buf = cpu_addr + data->prev_wr_ptr; 3036 b_full = iwl_write_to_user_buf(user_buf, count, 3037 curr_buf, &size, 3038 &bytes_copied); 3039 data->prev_wr_ptr += size; 3040 3041 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 3042 write_ptr < data->prev_wr_ptr) { 3043 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 3044 curr_buf = cpu_addr + data->prev_wr_ptr; 3045 b_full = iwl_write_to_user_buf(user_buf, count, 3046 curr_buf, &size, 3047 &bytes_copied); 3048 data->prev_wr_ptr += size; 3049 3050 if (!b_full) { 3051 size = write_ptr; 3052 b_full = iwl_write_to_user_buf(user_buf, count, 3053 cpu_addr, &size, 3054 &bytes_copied); 3055 data->prev_wr_ptr = size; 3056 data->prev_wrap_cnt++; 3057 } 3058 } else { 3059 if (data->prev_wrap_cnt == wrap_cnt - 1 && 3060 write_ptr > data->prev_wr_ptr) 3061 IWL_WARN(trans, 3062 "write pointer passed previous write pointer, start copying from the beginning\n"); 3063 else if (!unlikely(data->prev_wrap_cnt == 0 && 3064 data->prev_wr_ptr == 0)) 3065 IWL_WARN(trans, 3066 "monitor data is out of sync, start copying from the beginning\n"); 3067 3068 size = write_ptr; 3069 b_full = iwl_write_to_user_buf(user_buf, count, 3070 cpu_addr, &size, 3071 &bytes_copied); 3072 data->prev_wr_ptr = size; 3073 data->prev_wrap_cnt = wrap_cnt; 3074 } 3075 3076 mutex_unlock(&data->mutex); 3077 3078 return bytes_copied; 3079 } 3080 3081 static ssize_t iwl_dbgfs_rf_read(struct file *file, 3082 char __user *user_buf, 3083 size_t count, loff_t *ppos) 3084 { 3085 struct iwl_trans *trans = file->private_data; 3086 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3087 3088 if (!trans_pcie->rf_name[0]) 3089 return -ENODEV; 3090 3091 return simple_read_from_buffer(user_buf, count, ppos, 3092 trans_pcie->rf_name, 3093 strlen(trans_pcie->rf_name)); 3094 } 3095 3096 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 3097 DEBUGFS_READ_FILE_OPS(fh_reg); 3098 DEBUGFS_READ_FILE_OPS(rx_queue); 3099 DEBUGFS_WRITE_FILE_OPS(csr); 3100 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 3101 DEBUGFS_READ_FILE_OPS(rf); 3102 3103 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 3104 .owner = THIS_MODULE, 3105 .open = iwl_dbgfs_tx_queue_open, 3106 .read = seq_read, 3107 .llseek = seq_lseek, 3108 .release = seq_release_private, 3109 }; 3110 3111 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 3112 .read = iwl_dbgfs_monitor_data_read, 3113 .open = iwl_dbgfs_monitor_data_open, 3114 .release = iwl_dbgfs_monitor_data_release, 3115 }; 3116 3117 /* Create the debugfs files and directories */ 3118 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3119 { 3120 struct dentry *dir = trans->dbgfs_dir; 3121 3122 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 3123 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 3124 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 3125 DEBUGFS_ADD_FILE(csr, dir, 0200); 3126 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 3127 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3128 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3129 DEBUGFS_ADD_FILE(rf, dir, 0400); 3130 } 3131 3132 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3133 { 3134 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3135 struct cont_rec *data = &trans_pcie->fw_mon_data; 3136 3137 mutex_lock(&data->mutex); 3138 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3139 mutex_unlock(&data->mutex); 3140 } 3141 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3142 3143 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3144 { 3145 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3146 u32 cmdlen = 0; 3147 int i; 3148 3149 for (i = 0; i < trans_pcie->txqs.tfd.max_tbs; i++) 3150 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3151 3152 return cmdlen; 3153 } 3154 3155 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3156 struct iwl_fw_error_dump_data **data, 3157 int allocated_rb_nums) 3158 { 3159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3160 int max_len = trans_pcie->rx_buf_bytes; 3161 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3162 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3163 u32 i, r, j, rb_len = 0; 3164 3165 spin_lock_bh(&rxq->lock); 3166 3167 r = iwl_get_closed_rb_stts(trans, rxq); 3168 3169 for (i = rxq->read, j = 0; 3170 i != r && j < allocated_rb_nums; 3171 i = (i + 1) & RX_QUEUE_MASK, j++) { 3172 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3173 struct iwl_fw_error_dump_rb *rb; 3174 3175 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3176 max_len, DMA_FROM_DEVICE); 3177 3178 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3179 3180 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3181 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3182 rb = (void *)(*data)->data; 3183 rb->index = cpu_to_le32(i); 3184 memcpy(rb->data, page_address(rxb->page), max_len); 3185 3186 *data = iwl_fw_error_next_data(*data); 3187 } 3188 3189 spin_unlock_bh(&rxq->lock); 3190 3191 return rb_len; 3192 } 3193 #define IWL_CSR_TO_DUMP (0x250) 3194 3195 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3196 struct iwl_fw_error_dump_data **data) 3197 { 3198 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3199 __le32 *val; 3200 int i; 3201 3202 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3203 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3204 val = (void *)(*data)->data; 3205 3206 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3207 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3208 3209 *data = iwl_fw_error_next_data(*data); 3210 3211 return csr_len; 3212 } 3213 3214 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3215 struct iwl_fw_error_dump_data **data) 3216 { 3217 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3218 __le32 *val; 3219 int i; 3220 3221 if (!iwl_trans_grab_nic_access(trans)) 3222 return 0; 3223 3224 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3225 (*data)->len = cpu_to_le32(fh_regs_len); 3226 val = (void *)(*data)->data; 3227 3228 if (!trans->trans_cfg->gen2) 3229 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3230 i += sizeof(u32)) 3231 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3232 else 3233 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3234 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3235 i += sizeof(u32)) 3236 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3237 i)); 3238 3239 iwl_trans_release_nic_access(trans); 3240 3241 *data = iwl_fw_error_next_data(*data); 3242 3243 return sizeof(**data) + fh_regs_len; 3244 } 3245 3246 static u32 3247 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3248 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3249 u32 monitor_len) 3250 { 3251 u32 buf_size_in_dwords = (monitor_len >> 2); 3252 u32 *buffer = (u32 *)fw_mon_data->data; 3253 u32 i; 3254 3255 if (!iwl_trans_grab_nic_access(trans)) 3256 return 0; 3257 3258 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3259 for (i = 0; i < buf_size_in_dwords; i++) 3260 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3261 MON_DMARB_RD_DATA_ADDR); 3262 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3263 3264 iwl_trans_release_nic_access(trans); 3265 3266 return monitor_len; 3267 } 3268 3269 static void 3270 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3271 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3272 { 3273 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3274 3275 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3276 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3277 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3278 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3279 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3280 } else if (trans->dbg.dest_tlv) { 3281 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3282 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3283 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3284 } else { 3285 base = MON_BUFF_BASE_ADDR; 3286 write_ptr = MON_BUFF_WRPTR; 3287 wrap_cnt = MON_BUFF_CYCLE_CNT; 3288 } 3289 3290 write_ptr_val = iwl_read_prph(trans, write_ptr); 3291 fw_mon_data->fw_mon_cycle_cnt = 3292 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3293 fw_mon_data->fw_mon_base_ptr = 3294 cpu_to_le32(iwl_read_prph(trans, base)); 3295 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3296 fw_mon_data->fw_mon_base_high_ptr = 3297 cpu_to_le32(iwl_read_prph(trans, base_high)); 3298 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3299 /* convert wrtPtr to DWs, to align with all HWs */ 3300 write_ptr_val >>= 2; 3301 } 3302 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3303 } 3304 3305 static u32 3306 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3307 struct iwl_fw_error_dump_data **data, 3308 u32 monitor_len) 3309 { 3310 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3311 u32 len = 0; 3312 3313 if (trans->dbg.dest_tlv || 3314 (fw_mon->size && 3315 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3316 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3317 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3318 3319 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3320 fw_mon_data = (void *)(*data)->data; 3321 3322 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3323 3324 len += sizeof(**data) + sizeof(*fw_mon_data); 3325 if (fw_mon->size) { 3326 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3327 monitor_len = fw_mon->size; 3328 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3329 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3330 /* 3331 * Update pointers to reflect actual values after 3332 * shifting 3333 */ 3334 if (trans->dbg.dest_tlv->version) { 3335 base = (iwl_read_prph(trans, base) & 3336 IWL_LDBG_M2S_BUF_BA_MSK) << 3337 trans->dbg.dest_tlv->base_shift; 3338 base *= IWL_M2S_UNIT_SIZE; 3339 base += trans->cfg->smem_offset; 3340 } else { 3341 base = iwl_read_prph(trans, base) << 3342 trans->dbg.dest_tlv->base_shift; 3343 } 3344 3345 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3346 monitor_len / sizeof(u32)); 3347 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3348 monitor_len = 3349 iwl_trans_pci_dump_marbh_monitor(trans, 3350 fw_mon_data, 3351 monitor_len); 3352 } else { 3353 /* Didn't match anything - output no monitor data */ 3354 monitor_len = 0; 3355 } 3356 3357 len += monitor_len; 3358 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3359 } 3360 3361 return len; 3362 } 3363 3364 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3365 { 3366 if (trans->dbg.fw_mon.size) { 3367 *len += sizeof(struct iwl_fw_error_dump_data) + 3368 sizeof(struct iwl_fw_error_dump_fw_mon) + 3369 trans->dbg.fw_mon.size; 3370 return trans->dbg.fw_mon.size; 3371 } else if (trans->dbg.dest_tlv) { 3372 u32 base, end, cfg_reg, monitor_len; 3373 3374 if (trans->dbg.dest_tlv->version == 1) { 3375 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3376 cfg_reg = iwl_read_prph(trans, cfg_reg); 3377 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3378 trans->dbg.dest_tlv->base_shift; 3379 base *= IWL_M2S_UNIT_SIZE; 3380 base += trans->cfg->smem_offset; 3381 3382 monitor_len = 3383 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3384 trans->dbg.dest_tlv->end_shift; 3385 monitor_len *= IWL_M2S_UNIT_SIZE; 3386 } else { 3387 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3388 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3389 3390 base = iwl_read_prph(trans, base) << 3391 trans->dbg.dest_tlv->base_shift; 3392 end = iwl_read_prph(trans, end) << 3393 trans->dbg.dest_tlv->end_shift; 3394 3395 /* Make "end" point to the actual end */ 3396 if (trans->trans_cfg->device_family >= 3397 IWL_DEVICE_FAMILY_8000 || 3398 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3399 end += (1 << trans->dbg.dest_tlv->end_shift); 3400 monitor_len = end - base; 3401 } 3402 *len += sizeof(struct iwl_fw_error_dump_data) + 3403 sizeof(struct iwl_fw_error_dump_fw_mon) + 3404 monitor_len; 3405 return monitor_len; 3406 } 3407 return 0; 3408 } 3409 3410 struct iwl_trans_dump_data * 3411 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask, 3412 const struct iwl_dump_sanitize_ops *sanitize_ops, 3413 void *sanitize_ctx) 3414 { 3415 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3416 struct iwl_fw_error_dump_data *data; 3417 struct iwl_txq *cmdq = trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id]; 3418 struct iwl_fw_error_dump_txcmd *txcmd; 3419 struct iwl_trans_dump_data *dump_data; 3420 u32 len, num_rbs = 0, monitor_len = 0; 3421 int i, ptr; 3422 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3423 !trans->trans_cfg->mq_rx_supported && 3424 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3425 3426 if (!dump_mask) 3427 return NULL; 3428 3429 /* transport dump header */ 3430 len = sizeof(*dump_data); 3431 3432 /* host commands */ 3433 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3434 len += sizeof(*data) + 3435 cmdq->n_window * (sizeof(*txcmd) + 3436 TFD_MAX_PAYLOAD_SIZE); 3437 3438 /* FW monitor */ 3439 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3440 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3441 3442 /* CSR registers */ 3443 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3444 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3445 3446 /* FH registers */ 3447 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3448 if (trans->trans_cfg->gen2) 3449 len += sizeof(*data) + 3450 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3451 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3452 else 3453 len += sizeof(*data) + 3454 (FH_MEM_UPPER_BOUND - 3455 FH_MEM_LOWER_BOUND); 3456 } 3457 3458 if (dump_rbs) { 3459 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3460 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3461 /* RBs */ 3462 num_rbs = iwl_get_closed_rb_stts(trans, rxq); 3463 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3464 len += num_rbs * (sizeof(*data) + 3465 sizeof(struct iwl_fw_error_dump_rb) + 3466 (PAGE_SIZE << trans_pcie->rx_page_order)); 3467 } 3468 3469 /* Paged memory for gen2 HW */ 3470 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3471 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3472 len += sizeof(*data) + 3473 sizeof(struct iwl_fw_error_dump_paging) + 3474 trans->init_dram.paging[i].size; 3475 3476 dump_data = vzalloc(len); 3477 if (!dump_data) 3478 return NULL; 3479 3480 len = 0; 3481 data = (void *)dump_data->data; 3482 3483 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3484 u16 tfd_size = trans_pcie->txqs.tfd.size; 3485 3486 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3487 txcmd = (void *)data->data; 3488 spin_lock_bh(&cmdq->lock); 3489 ptr = cmdq->write_ptr; 3490 for (i = 0; i < cmdq->n_window; i++) { 3491 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3492 u8 tfdidx; 3493 u32 caplen, cmdlen; 3494 3495 if (trans->trans_cfg->gen2) 3496 tfdidx = idx; 3497 else 3498 tfdidx = ptr; 3499 3500 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3501 (u8 *)cmdq->tfds + 3502 tfd_size * tfdidx); 3503 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3504 3505 if (cmdlen) { 3506 len += sizeof(*txcmd) + caplen; 3507 txcmd->cmdlen = cpu_to_le32(cmdlen); 3508 txcmd->caplen = cpu_to_le32(caplen); 3509 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3510 caplen); 3511 if (sanitize_ops && sanitize_ops->frob_hcmd) 3512 sanitize_ops->frob_hcmd(sanitize_ctx, 3513 txcmd->data, 3514 caplen); 3515 txcmd = (void *)((u8 *)txcmd->data + caplen); 3516 } 3517 3518 ptr = iwl_txq_dec_wrap(trans, ptr); 3519 } 3520 spin_unlock_bh(&cmdq->lock); 3521 3522 data->len = cpu_to_le32(len); 3523 len += sizeof(*data); 3524 data = iwl_fw_error_next_data(data); 3525 } 3526 3527 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3528 len += iwl_trans_pcie_dump_csr(trans, &data); 3529 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3530 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3531 if (dump_rbs) 3532 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3533 3534 /* Paged memory for gen2 HW */ 3535 if (trans->trans_cfg->gen2 && 3536 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3537 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3538 struct iwl_fw_error_dump_paging *paging; 3539 u32 page_len = trans->init_dram.paging[i].size; 3540 3541 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3542 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3543 paging = (void *)data->data; 3544 paging->index = cpu_to_le32(i); 3545 memcpy(paging->data, 3546 trans->init_dram.paging[i].block, page_len); 3547 data = iwl_fw_error_next_data(data); 3548 3549 len += sizeof(*data) + sizeof(*paging) + page_len; 3550 } 3551 } 3552 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3553 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3554 3555 dump_data->len = len; 3556 3557 return dump_data; 3558 } 3559 3560 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3561 { 3562 if (enable) 3563 iwl_enable_interrupts(trans); 3564 else 3565 iwl_disable_interrupts(trans); 3566 } 3567 3568 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3569 { 3570 u32 inta_addr, sw_err_bit; 3571 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3572 3573 if (trans_pcie->msix_enabled) { 3574 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3575 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3576 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3577 else 3578 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3579 } else { 3580 inta_addr = CSR_INT; 3581 sw_err_bit = CSR_INT_BIT_SW_ERR; 3582 } 3583 3584 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3585 } 3586 3587 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3588 const struct pci_device_id *ent, 3589 const struct iwl_cfg_trans_params *cfg_trans) 3590 { 3591 struct iwl_trans_pcie *trans_pcie, **priv; 3592 struct iwl_trans *trans; 3593 int ret, addr_size; 3594 void __iomem * const *table; 3595 u32 bar0; 3596 3597 /* reassign our BAR 0 if invalid due to possible runtime PM races */ 3598 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0); 3599 if (bar0 == PCI_BASE_ADDRESS_MEM_TYPE_64) { 3600 ret = pci_assign_resource(pdev, 0); 3601 if (ret) 3602 return ERR_PTR(ret); 3603 } 3604 3605 ret = pcim_enable_device(pdev); 3606 if (ret) 3607 return ERR_PTR(ret); 3608 3609 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, 3610 cfg_trans); 3611 if (!trans) 3612 return ERR_PTR(-ENOMEM); 3613 3614 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3615 3616 if (trans->trans_cfg->gen2) { 3617 trans_pcie->txqs.tfd.addr_size = 64; 3618 trans_pcie->txqs.tfd.max_tbs = IWL_TFH_NUM_TBS; 3619 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfh_tfd); 3620 } else { 3621 trans_pcie->txqs.tfd.addr_size = 36; 3622 trans_pcie->txqs.tfd.max_tbs = IWL_NUM_OF_TBS; 3623 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfd); 3624 } 3625 trans->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie); 3626 3627 #ifdef CONFIG_INET 3628 trans_pcie->txqs.tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3629 if (!trans_pcie->txqs.tso_hdr_page) { 3630 ret = -ENOMEM; 3631 goto out_free_trans; 3632 } 3633 #endif 3634 3635 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3636 trans_pcie->txqs.bc_tbl_size = 3637 sizeof(struct iwl_gen3_bc_tbl_entry) * TFD_QUEUE_BC_SIZE_GEN3_BZ; 3638 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 3639 trans_pcie->txqs.bc_tbl_size = 3640 sizeof(struct iwl_gen3_bc_tbl_entry) * TFD_QUEUE_BC_SIZE_GEN3_AX210; 3641 else 3642 trans_pcie->txqs.bc_tbl_size = sizeof(struct iwlagn_scd_bc_tbl); 3643 /* 3644 * For gen2 devices, we use a single allocation for each byte-count 3645 * table, but they're pretty small (1k) so use a DMA pool that we 3646 * allocate here. 3647 */ 3648 if (trans->trans_cfg->gen2) { 3649 trans_pcie->txqs.bc_pool = 3650 dmam_pool_create("iwlwifi:bc", trans->dev, 3651 trans_pcie->txqs.bc_tbl_size, 3652 256, 0); 3653 if (!trans_pcie->txqs.bc_pool) { 3654 ret = -ENOMEM; 3655 goto out_free_tso; 3656 } 3657 } 3658 3659 /* Some things must not change even if the config does */ 3660 WARN_ON(trans_pcie->txqs.tfd.addr_size != 3661 (trans->trans_cfg->gen2 ? 64 : 36)); 3662 3663 /* Initialize NAPI here - it should be before registering to mac80211 3664 * in the opmode but after the HW struct is allocated. 3665 */ 3666 trans_pcie->napi_dev = alloc_netdev_dummy(sizeof(struct iwl_trans_pcie *)); 3667 if (!trans_pcie->napi_dev) { 3668 ret = -ENOMEM; 3669 goto out_free_tso; 3670 } 3671 /* The private struct in netdev is a pointer to struct iwl_trans_pcie */ 3672 priv = netdev_priv(trans_pcie->napi_dev); 3673 *priv = trans_pcie; 3674 3675 trans_pcie->trans = trans; 3676 trans_pcie->opmode_down = true; 3677 spin_lock_init(&trans_pcie->irq_lock); 3678 spin_lock_init(&trans_pcie->reg_lock); 3679 spin_lock_init(&trans_pcie->alloc_page_lock); 3680 mutex_init(&trans_pcie->mutex); 3681 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3682 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3683 init_waitqueue_head(&trans_pcie->imr_waitq); 3684 3685 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3686 WQ_HIGHPRI | WQ_UNBOUND, 0); 3687 if (!trans_pcie->rba.alloc_wq) { 3688 ret = -ENOMEM; 3689 goto out_free_ndev; 3690 } 3691 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3692 3693 trans_pcie->debug_rfkill = -1; 3694 3695 if (!cfg_trans->base_params->pcie_l1_allowed) { 3696 /* 3697 * W/A - seems to solve weird behavior. We need to remove this 3698 * if we don't want to stay in L1 all the time. This wastes a 3699 * lot of power. 3700 */ 3701 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3702 PCIE_LINK_STATE_L1 | 3703 PCIE_LINK_STATE_CLKPM); 3704 } 3705 3706 pci_set_master(pdev); 3707 3708 addr_size = trans_pcie->txqs.tfd.addr_size; 3709 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3710 if (ret) { 3711 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3712 /* both attempts failed: */ 3713 if (ret) { 3714 dev_err(&pdev->dev, "No suitable DMA available\n"); 3715 goto out_no_pci; 3716 } 3717 } 3718 3719 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3720 if (ret) { 3721 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3722 goto out_no_pci; 3723 } 3724 3725 #if defined(__FreeBSD__) 3726 linuxkpi_pcim_want_to_use_bus_functions(pdev); 3727 #endif 3728 table = pcim_iomap_table(pdev); 3729 if (!table) { 3730 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3731 ret = -ENOMEM; 3732 goto out_no_pci; 3733 } 3734 3735 trans_pcie->hw_base = table[0]; 3736 if (!trans_pcie->hw_base) { 3737 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3738 ret = -ENODEV; 3739 goto out_no_pci; 3740 } 3741 3742 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3743 * PCI Tx retries from interfering with C3 CPU state */ 3744 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3745 3746 trans_pcie->pci_dev = pdev; 3747 iwl_disable_interrupts(trans); 3748 3749 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3750 if (trans->hw_rev == 0xffffffff) { 3751 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3752 ret = -EIO; 3753 goto out_no_pci; 3754 } 3755 3756 /* 3757 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3758 * changed, and now the revision step also includes bit 0-1 (no more 3759 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3760 * in the old format. 3761 */ 3762 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3763 trans->hw_rev_step = trans->hw_rev & 0xF; 3764 else 3765 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3766 3767 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3768 3769 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3770 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3771 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3772 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3773 3774 init_waitqueue_head(&trans_pcie->sx_waitq); 3775 3776 ret = iwl_pcie_alloc_invalid_tx_cmd(trans); 3777 if (ret) 3778 goto out_no_pci; 3779 3780 if (trans_pcie->msix_enabled) { 3781 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3782 if (ret) 3783 goto out_no_pci; 3784 } else { 3785 ret = iwl_pcie_alloc_ict(trans); 3786 if (ret) 3787 goto out_no_pci; 3788 3789 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3790 iwl_pcie_isr, 3791 iwl_pcie_irq_handler, 3792 IRQF_SHARED, DRV_NAME, trans); 3793 if (ret) { 3794 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3795 goto out_free_ict; 3796 } 3797 } 3798 3799 #ifdef CONFIG_IWLWIFI_DEBUGFS 3800 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3801 mutex_init(&trans_pcie->fw_mon_data.mutex); 3802 #endif 3803 3804 iwl_dbg_tlv_init(trans); 3805 3806 return trans; 3807 3808 out_free_ict: 3809 iwl_pcie_free_ict(trans); 3810 out_no_pci: 3811 destroy_workqueue(trans_pcie->rba.alloc_wq); 3812 out_free_ndev: 3813 free_netdev(trans_pcie->napi_dev); 3814 out_free_tso: 3815 #ifdef CONFIG_INET 3816 free_percpu(trans_pcie->txqs.tso_hdr_page); 3817 out_free_trans: 3818 #endif 3819 iwl_trans_free(trans); 3820 return ERR_PTR(ret); 3821 } 3822 3823 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3824 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3825 { 3826 iwl_write_prph(trans, IMR_UREG_CHICK, 3827 iwl_read_prph(trans, IMR_UREG_CHICK) | 3828 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3829 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3830 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3831 (u32)(src_addr & 0xFFFFFFFF)); 3832 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3833 iwl_get_dma_hi_addr(src_addr)); 3834 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3835 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3836 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3837 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3838 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3839 } 3840 3841 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3842 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3843 { 3844 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3845 int ret = -1; 3846 3847 trans_pcie->imr_status = IMR_D2S_REQUESTED; 3848 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3849 ret = wait_event_timeout(trans_pcie->imr_waitq, 3850 trans_pcie->imr_status != 3851 IMR_D2S_REQUESTED, 5 * HZ); 3852 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3853 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3854 iwl_trans_pcie_dump_regs(trans); 3855 return -ETIMEDOUT; 3856 } 3857 trans_pcie->imr_status = IMR_D2S_IDLE; 3858 return 0; 3859 } 3860