1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2025 Intel Corporation
5 */
6 #include "iwl-trans.h"
7 #include "iwl-prph.h"
8 #include "iwl-context-info.h"
9 #include "iwl-context-info-v2.h"
10 #include "internal.h"
11 #include "fw/dbg.h"
12
13 #define FW_RESET_TIMEOUT (HZ / 5)
14
15 /*
16 * Start up NIC's basic functionality after it has been reset
17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
18 * NOTE: This does not load uCode nor start the embedded processor
19 */
iwl_pcie_gen2_apm_init(struct iwl_trans * trans)20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
21 {
22 int ret = 0;
23
24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
25
26 /*
27 * Use "set_bit" below rather than "write", to preserve any hardware
28 * bits already set by default after reset.
29 */
30
31 /*
32 * Disable L0s without affecting L1;
33 * don't wait for ICH L0s (ICH bug W/A)
34 */
35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
37
38 /* Set FH wait threshold to maximum (HW error during stress W/A) */
39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
40
41 /*
42 * Enable HAP INTA (interrupt from management bus) to
43 * wake device's PCI Express link L1a -> L0s
44 */
45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
46 CSR_HW_IF_CONFIG_REG_HAP_WAKE);
47
48 iwl_pcie_apm_config(trans);
49
50 ret = iwl_finish_nic_init(trans);
51 if (ret)
52 return ret;
53
54 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
55
56 return 0;
57 }
58
iwl_pcie_gen2_apm_stop(struct iwl_trans * trans,bool op_mode_leave)59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
60 {
61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
62
63 if (op_mode_leave) {
64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
65 iwl_pcie_gen2_apm_init(trans);
66
67 /* inform ME that we are leaving */
68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
69 CSR_RESET_LINK_PWR_MGMT_DISABLED);
70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
71 CSR_HW_IF_CONFIG_REG_WAKE_ME |
72 CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN);
73 mdelay(1);
74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
75 CSR_RESET_LINK_PWR_MGMT_DISABLED);
76 mdelay(5);
77 }
78
79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
80
81 /* Stop device's DMA activity */
82 iwl_pcie_apm_stop_master(trans);
83
84 iwl_trans_pcie_sw_reset(trans, false);
85
86 /*
87 * Clear "initialization complete" bit to move adapter from
88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
89 */
90 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
91 iwl_clear_bit(trans, CSR_GP_CNTRL,
92 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
93 else
94 iwl_clear_bit(trans, CSR_GP_CNTRL,
95 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
96 }
97
iwl_trans_pcie_fw_reset_handshake(struct iwl_trans * trans)98 void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
99 {
100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 int ret;
102
103 trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
104
105 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
106 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
107 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
108 else if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
109 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
110 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
111 else
112 iwl_write32(trans, CSR_DOORBELL_VECTOR,
113 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
114
115 /* wait 200ms */
116 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
117 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
118 FW_RESET_TIMEOUT);
119 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
120 bool reset_done;
121 u32 inta_hw;
122
123 if (trans_pcie->msix_enabled) {
124 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
125 reset_done =
126 inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE;
127 } else {
128 inta_hw = iwl_read32(trans, CSR_INT);
129 reset_done = inta_hw & CSR_INT_BIT_RESET_DONE;
130 }
131
132 IWL_ERR(trans,
133 "timeout waiting for FW reset ACK (inta_hw=0x%x, reset_done %d)\n",
134 inta_hw, reset_done);
135
136 if (!reset_done) {
137 struct iwl_fw_error_dump_mode mode = {
138 .type = IWL_ERR_TYPE_RESET_HS_TIMEOUT,
139 .context = IWL_ERR_CONTEXT_FROM_OPMODE,
140 };
141 iwl_op_mode_nic_error(trans->op_mode,
142 IWL_ERR_TYPE_RESET_HS_TIMEOUT);
143 iwl_op_mode_dump_error(trans->op_mode, &mode);
144 }
145 }
146
147 trans_pcie->fw_reset_state = FW_RESET_IDLE;
148 }
149
_iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)150 static void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
151 {
152 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
153
154 lockdep_assert_held(&trans_pcie->mutex);
155
156 if (trans_pcie->is_down)
157 return;
158
159 if (trans->state >= IWL_TRANS_FW_STARTED &&
160 trans->conf.fw_reset_handshake) {
161 /*
162 * Reset handshake can dump firmware on timeout, but that
163 * should assume that the firmware is already dead.
164 */
165 trans->state = IWL_TRANS_NO_FW;
166 iwl_trans_pcie_fw_reset_handshake(trans);
167 }
168
169 trans_pcie->is_down = true;
170
171 /* tell the device to stop sending interrupts */
172 iwl_disable_interrupts(trans);
173
174 /* device going down, Stop using ICT table */
175 iwl_pcie_disable_ict(trans);
176
177 /*
178 * If a HW restart happens during firmware loading,
179 * then the firmware loading might call this function
180 * and later it might be called again due to the
181 * restart. So don't process again if the device is
182 * already dead.
183 */
184 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
185 IWL_DEBUG_INFO(trans,
186 "DEVICE_ENABLED bit was set and is now cleared\n");
187 iwl_pcie_synchronize_irqs(trans);
188 iwl_pcie_rx_napi_sync(trans);
189 iwl_txq_gen2_tx_free(trans);
190 iwl_pcie_rx_stop(trans);
191 }
192
193 iwl_pcie_ctxt_info_free_paging(trans);
194 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
195 iwl_pcie_ctxt_info_v2_free(trans, false);
196 else
197 iwl_pcie_ctxt_info_free(trans);
198
199 /* Stop the device, and put it in low power state */
200 iwl_pcie_gen2_apm_stop(trans, false);
201
202 /* re-take ownership to prevent other users from stealing the device */
203 iwl_trans_pcie_sw_reset(trans, true);
204
205 /*
206 * Upon stop, the IVAR table gets erased, so msi-x won't
207 * work. This causes a bug in RF-KILL flows, since the interrupt
208 * that enables radio won't fire on the correct irq, and the
209 * driver won't be able to handle the interrupt.
210 * Configure the IVAR table again after reset.
211 */
212 iwl_pcie_conf_msix_hw(trans_pcie);
213
214 /*
215 * Upon stop, the APM issues an interrupt if HW RF kill is set.
216 * This is a bug in certain verions of the hardware.
217 * Certain devices also keep sending HW RF kill interrupt all
218 * the time, unless the interrupt is ACKed even if the interrupt
219 * should be masked. Re-ACK all the interrupts here.
220 */
221 iwl_disable_interrupts(trans);
222
223 /* clear all status bits */
224 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
225 clear_bit(STATUS_INT_ENABLED, &trans->status);
226 clear_bit(STATUS_TPOWER_PMI, &trans->status);
227
228 /*
229 * Even if we stop the HW, we still want the RF kill
230 * interrupt
231 */
232 iwl_enable_rfkill_int(trans);
233 }
234
iwl_trans_pcie_gen2_stop_device(struct iwl_trans * trans)235 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
236 {
237 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
238 bool was_in_rfkill;
239
240 iwl_op_mode_time_point(trans->op_mode,
241 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
242 NULL);
243
244 mutex_lock(&trans_pcie->mutex);
245 trans_pcie->opmode_down = true;
246 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
247 _iwl_trans_pcie_gen2_stop_device(trans);
248 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
249 mutex_unlock(&trans_pcie->mutex);
250 }
251
iwl_pcie_gen2_nic_init(struct iwl_trans * trans)252 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
253 {
254 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
255 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
256 trans->mac_cfg->base->min_txq_size);
257 int ret;
258
259 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
260 spin_lock_bh(&trans_pcie->irq_lock);
261 ret = iwl_pcie_gen2_apm_init(trans);
262 spin_unlock_bh(&trans_pcie->irq_lock);
263 if (ret)
264 return ret;
265
266 iwl_op_mode_nic_config(trans->op_mode);
267
268 /* Allocate the RX queue, or reset if it is already allocated */
269 if (iwl_pcie_gen2_rx_init(trans))
270 return -ENOMEM;
271
272 /* Allocate or reset and init all Tx and Command queues */
273 if (iwl_txq_gen2_init(trans, trans->conf.cmd_queue, queue_size))
274 return -ENOMEM;
275
276 /* enable shadow regs in HW */
277 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
278 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
279
280 return 0;
281 }
282
iwl_pcie_get_rf_name(struct iwl_trans * trans)283 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
284 {
285 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
286 char *buf = trans_pcie->rf_name;
287 size_t buflen = sizeof(trans_pcie->rf_name);
288 size_t pos;
289 u32 version;
290
291 if (buf[0])
292 return;
293
294 switch (CSR_HW_RFID_TYPE(trans->info.hw_rf_id)) {
295 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
296 pos = scnprintf(buf, buflen, "JF");
297 break;
298 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
299 pos = scnprintf(buf, buflen, "GF");
300 break;
301 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
302 pos = scnprintf(buf, buflen, "GF4");
303 break;
304 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
305 pos = scnprintf(buf, buflen, "HR");
306 break;
307 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
308 pos = scnprintf(buf, buflen, "HR1");
309 break;
310 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
311 pos = scnprintf(buf, buflen, "HRCDB");
312 break;
313 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_FM):
314 pos = scnprintf(buf, buflen, "FM");
315 break;
316 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_WP):
317 if (SILICON_Z_STEP ==
318 CSR_HW_RFID_STEP(trans->info.hw_rf_id))
319 pos = scnprintf(buf, buflen, "WHTC");
320 else
321 pos = scnprintf(buf, buflen, "WH");
322 break;
323 default:
324 return;
325 }
326
327 switch (CSR_HW_RFID_TYPE(trans->info.hw_rf_id)) {
328 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
329 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
330 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
331 version = iwl_read_prph(trans, CNVI_MBOX_C);
332 switch (version) {
333 case 0x20000:
334 pos += scnprintf(buf + pos, buflen - pos, " B3");
335 break;
336 case 0x120000:
337 pos += scnprintf(buf + pos, buflen - pos, " B5");
338 break;
339 default:
340 pos += scnprintf(buf + pos, buflen - pos,
341 " (0x%x)", version);
342 break;
343 }
344 break;
345 default:
346 break;
347 }
348
349 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
350 trans->info.hw_rf_id);
351
352 IWL_INFO(trans, "Detected RF %s\n", buf);
353
354 /*
355 * also add a \n for debugfs - need to do it after printing
356 * since our IWL_INFO machinery wants to see a static \n at
357 * the end of the string
358 */
359 pos += scnprintf(buf + pos, buflen - pos, "\n");
360 }
361
iwl_trans_pcie_gen2_fw_alive(struct iwl_trans * trans)362 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans)
363 {
364 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
365
366 iwl_pcie_reset_ict(trans);
367
368 /* make sure all queue are not stopped/used */
369 memset(trans_pcie->txqs.queue_stopped, 0,
370 sizeof(trans_pcie->txqs.queue_stopped));
371 memset(trans_pcie->txqs.queue_used, 0,
372 sizeof(trans_pcie->txqs.queue_used));
373
374 /* now that we got alive we can free the fw image & the context info.
375 * paging memory cannot be freed included since FW will still use it
376 */
377 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
378 iwl_pcie_ctxt_info_v2_free(trans, true);
379 else
380 iwl_pcie_ctxt_info_free(trans);
381
382 /*
383 * Re-enable all the interrupts, including the RF-Kill one, now that
384 * the firmware is alive.
385 */
386 iwl_enable_interrupts(trans);
387 mutex_lock(&trans_pcie->mutex);
388 iwl_pcie_check_hw_rf_kill(trans);
389
390 iwl_pcie_get_rf_name(trans);
391 mutex_unlock(&trans_pcie->mutex);
392
393 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
394 trans->step_urm = !!(iwl_read_umac_prph(trans,
395 CNVI_PMU_STEP_FLOW) &
396 CNVI_PMU_STEP_FLOW_FORCE_URM);
397 }
398
iwl_pcie_set_ltr(struct iwl_trans * trans)399 static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
400 {
401 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
402 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
403 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
404 u32_encode_bits(250,
405 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
406 CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
407 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
408 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
409 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
410
411 /*
412 * To workaround hardware latency issues during the boot process,
413 * initialize the LTR to ~250 usec (see ltr_val above).
414 * The firmware initializes this again later (to a smaller value).
415 */
416 if ((trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
417 trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
418 !trans->mac_cfg->integrated) {
419 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
420 return true;
421 }
422
423 if (trans->mac_cfg->integrated &&
424 trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
425 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
426 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
427 return true;
428 }
429
430 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
431 /* First clear the interrupt, just in case */
432 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
433 MSIX_HW_INT_CAUSES_REG_IML);
434 /* In this case, unfortunately the same ROM bug exists in the
435 * device (not setting LTR correctly), but we don't have control
436 * over the settings from the host due to some hardware security
437 * features. The only workaround we've been able to come up with
438 * so far is to try to keep the CPU and device busy by polling
439 * it and the IML (image loader) completed interrupt.
440 */
441 return false;
442 }
443
444 /* nothing needs to be done on other devices */
445 return true;
446 }
447
iwl_pcie_spin_for_iml(struct iwl_trans * trans)448 static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
449 {
450 /* in practice, this seems to complete in around 20-30ms at most, wait 100 */
451 #define IML_WAIT_TIMEOUT (HZ / 10)
452 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
453 unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;
454 u32 value, loops = 0;
455 bool irq = false;
456
457 if (WARN_ON(!trans_pcie->iml))
458 return;
459
460 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
461 IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
462 value);
463
464 while (time_before(jiffies, end_time)) {
465 if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
466 MSIX_HW_INT_CAUSES_REG_IML) {
467 irq = true;
468 break;
469 }
470 /* Keep the CPU and device busy. */
471 value = iwl_read32(trans, CSR_LTR_LAST_MSG);
472 loops++;
473 }
474
475 IWL_DEBUG_INFO(trans,
476 "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",
477 irq, loops, value);
478
479 /* We don't fail here even if we timed out - maybe we get lucky and the
480 * interrupt comes in later (and we get alive from firmware) and then
481 * we're all happy - but if not we'll fail on alive timeout or get some
482 * other error out.
483 */
484 }
485
iwl_trans_pcie_gen2_start_fw(struct iwl_trans * trans,const struct iwl_fw * fw,const struct fw_img * img,bool run_in_rfkill)486 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
487 const struct iwl_fw *fw,
488 const struct fw_img *img,
489 bool run_in_rfkill)
490 {
491 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
492 bool hw_rfkill, keep_ram_busy;
493 bool top_reset_done = false;
494 int ret;
495
496 mutex_lock(&trans_pcie->mutex);
497 again:
498 /* This may fail if AMT took ownership of the device */
499 if (iwl_pcie_prepare_card_hw(trans)) {
500 IWL_WARN(trans, "Exit HW not ready\n");
501 ret = -EIO;
502 goto out;
503 }
504
505 iwl_enable_rfkill_int(trans);
506
507 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
508
509 /*
510 * We enabled the RF-Kill interrupt and the handler may very
511 * well be running. Disable the interrupts to make sure no other
512 * interrupt can be fired.
513 */
514 iwl_disable_interrupts(trans);
515
516 /* Make sure it finished running */
517 iwl_pcie_synchronize_irqs(trans);
518
519 /* If platform's RF_KILL switch is NOT set to KILL */
520 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
521 if (hw_rfkill && !run_in_rfkill) {
522 ret = -ERFKILL;
523 goto out;
524 }
525
526 /* Someone called stop_device, don't try to start_fw */
527 if (trans_pcie->is_down) {
528 IWL_WARN(trans,
529 "Can't start_fw since the HW hasn't been started\n");
530 ret = -EIO;
531 goto out;
532 }
533
534 /* make sure rfkill handshake bits are cleared */
535 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
536 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
537 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
538
539 /* clear (again), then enable host interrupts */
540 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
541
542 ret = iwl_pcie_gen2_nic_init(trans);
543 if (ret) {
544 IWL_ERR(trans, "Unable to init nic\n");
545 goto out;
546 }
547
548 if (WARN_ON(trans->do_top_reset &&
549 trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_SC))
550 return -EINVAL;
551
552 /* we need to wait later - set state */
553 if (trans->do_top_reset)
554 trans_pcie->fw_reset_state = FW_RESET_TOP_REQUESTED;
555
556 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
557 if (!top_reset_done) {
558 ret = iwl_pcie_ctxt_info_v2_alloc(trans, fw, img);
559 if (ret)
560 goto out;
561 }
562
563 iwl_pcie_ctxt_info_v2_kick(trans);
564 } else {
565 ret = iwl_pcie_ctxt_info_init(trans, img);
566 if (ret)
567 goto out;
568 }
569
570 keep_ram_busy = !iwl_pcie_set_ltr(trans);
571
572 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
573 IWL_DEBUG_POWER(trans, "function scratch register value is 0x%08x\n",
574 iwl_read32(trans, CSR_FUNC_SCRATCH));
575 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
576 iwl_set_bit(trans, CSR_GP_CNTRL,
577 CSR_GP_CNTRL_REG_FLAG_ROM_START);
578 } else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
579 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
580 } else {
581 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
582 }
583
584 if (keep_ram_busy)
585 iwl_pcie_spin_for_iml(trans);
586
587 if (trans->do_top_reset) {
588 trans->do_top_reset = 0;
589
590 #define FW_TOP_RESET_TIMEOUT (HZ / 4)
591 ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
592 trans_pcie->fw_reset_state != FW_RESET_TOP_REQUESTED,
593 FW_TOP_RESET_TIMEOUT);
594
595 if (trans_pcie->fw_reset_state != FW_RESET_OK) {
596 if (trans_pcie->fw_reset_state != FW_RESET_TOP_REQUESTED)
597 IWL_ERR(trans,
598 "TOP reset interrupted by error (state %d)!\n",
599 trans_pcie->fw_reset_state);
600 else
601 IWL_ERR(trans, "TOP reset timed out!\n");
602 iwl_op_mode_nic_error(trans->op_mode,
603 IWL_ERR_TYPE_TOP_RESET_FAILED);
604 iwl_trans_schedule_reset(trans,
605 IWL_ERR_TYPE_TOP_RESET_FAILED);
606 ret = -EIO;
607 goto out;
608 }
609
610 msleep(10);
611 IWL_INFO(trans, "TOP reset successful, reinit now\n");
612 /* now load the firmware again properly */
613 trans_pcie->prph_scratch->ctrl_cfg.control.control_flags &=
614 ~cpu_to_le32(IWL_PRPH_SCRATCH_TOP_RESET);
615 top_reset_done = true;
616 goto again;
617 }
618
619 /* re-check RF-Kill state since we may have missed the interrupt */
620 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
621 if (hw_rfkill && !run_in_rfkill)
622 ret = -ERFKILL;
623
624 out:
625 mutex_unlock(&trans_pcie->mutex);
626 return ret;
627 }
628