xref: /freebsd/sys/contrib/dev/iwlwifi/pcie/tx.c (revision a4128aad8503277614f2d214011ef60a19447b83)
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2003-2014, 2018-2021, 2023-2024 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
6  */
7 #include <linux/etherdevice.h>
8 #include <linux/ieee80211.h>
9 #include <linux/dmapool.h>
10 #include <linux/slab.h>
11 #include <linux/sched.h>
12 #include <linux/tcp.h>
13 #ifdef CONFIG_INET
14 #include <net/ip6_checksum.h>
15 #include <net/tso.h>
16 #endif
17 #if defined(__FreeBSD__)
18 #include <net/mac80211.h>
19 #endif
20 
21 #include "fw/api/commands.h"
22 #include "fw/api/datapath.h"
23 #include "fw/api/debug.h"
24 #include "iwl-fh.h"
25 #include "iwl-debug.h"
26 #include "iwl-csr.h"
27 #include "iwl-prph.h"
28 #include "iwl-io.h"
29 #include "iwl-scd.h"
30 #include "iwl-op-mode.h"
31 #include "internal.h"
32 #include "fw/api/tx.h"
33 
34 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
35  * DMA services
36  *
37  * Theory of operation
38  *
39  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
40  * of buffer descriptors, each of which points to one or more data buffers for
41  * the device to read from or fill.  Driver and device exchange status of each
42  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
43  * entries in each circular buffer, to protect against confusing empty and full
44  * queue states.
45  *
46  * The device reads or writes the data in the queues via the device's several
47  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
48  *
49  * For Tx queue, there are low mark and high mark limits. If, after queuing
50  * the packet for Tx, free space become < low mark, Tx queue stopped. When
51  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
52  * Tx queue resumed.
53  *
54  ***************************************************/
55 
56 
57 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
58 			   struct iwl_dma_ptr *ptr, size_t size)
59 {
60 	if (WARN_ON(ptr->addr))
61 		return -EINVAL;
62 
63 	ptr->addr = dma_alloc_coherent(trans->dev, size,
64 				       &ptr->dma, GFP_KERNEL);
65 	if (!ptr->addr)
66 		return -ENOMEM;
67 	ptr->size = size;
68 	return 0;
69 }
70 
71 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
72 {
73 	if (unlikely(!ptr->addr))
74 		return;
75 
76 	dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
77 	memset(ptr, 0, sizeof(*ptr));
78 }
79 
80 /*
81  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
82  */
83 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
84 				    struct iwl_txq *txq)
85 {
86 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
87 	u32 reg = 0;
88 	int txq_id = txq->id;
89 
90 	lockdep_assert_held(&txq->lock);
91 
92 	/*
93 	 * explicitly wake up the NIC if:
94 	 * 1. shadow registers aren't enabled
95 	 * 2. NIC is woken up for CMD regardless of shadow outside this function
96 	 * 3. there is a chance that the NIC is asleep
97 	 */
98 	if (!trans->trans_cfg->base_params->shadow_reg_enable &&
99 	    txq_id != trans_pcie->txqs.cmd.q_id &&
100 	    test_bit(STATUS_TPOWER_PMI, &trans->status)) {
101 		/*
102 		 * wake up nic if it's powered down ...
103 		 * uCode will wake up, and interrupt us again, so next
104 		 * time we'll skip this part.
105 		 */
106 		reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
107 
108 		if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
109 			IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
110 				       txq_id, reg);
111 			iwl_set_bit(trans, CSR_GP_CNTRL,
112 				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
113 			txq->need_update = true;
114 			return;
115 		}
116 	}
117 
118 	/*
119 	 * if not in power-save mode, uCode will never sleep when we're
120 	 * trying to tx (during RFKILL, we're not trying to tx).
121 	 */
122 	IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
123 	if (!txq->block)
124 		iwl_write32(trans, HBUS_TARG_WRPTR,
125 			    txq->write_ptr | (txq_id << 8));
126 }
127 
128 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
129 {
130 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
131 	int i;
132 
133 	for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
134 		struct iwl_txq *txq = trans_pcie->txqs.txq[i];
135 
136 		if (!test_bit(i, trans_pcie->txqs.queue_used))
137 			continue;
138 
139 		spin_lock_bh(&txq->lock);
140 		if (txq->need_update) {
141 			iwl_pcie_txq_inc_wr_ptr(trans, txq);
142 			txq->need_update = false;
143 		}
144 		spin_unlock_bh(&txq->lock);
145 	}
146 }
147 
148 static inline void iwl_pcie_gen1_tfd_set_tb(struct iwl_tfd *tfd,
149 					    u8 idx, dma_addr_t addr, u16 len)
150 {
151 	struct iwl_tfd_tb *tb = &tfd->tbs[idx];
152 	u16 hi_n_len = len << 4;
153 
154 	put_unaligned_le32(addr, &tb->lo);
155 	hi_n_len |= iwl_get_dma_hi_addr(addr);
156 
157 	tb->hi_n_len = cpu_to_le16(hi_n_len);
158 
159 	tfd->num_tbs = idx + 1;
160 }
161 
162 static inline u8 iwl_txq_gen1_tfd_get_num_tbs(struct iwl_tfd *tfd)
163 {
164 	return tfd->num_tbs & 0x1f;
165 }
166 
167 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
168 				  dma_addr_t addr, u16 len, bool reset)
169 {
170 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
171 	void *tfd;
172 	u32 num_tbs;
173 
174 	tfd = (u8 *)txq->tfds + trans_pcie->txqs.tfd.size * txq->write_ptr;
175 
176 	if (reset)
177 		memset(tfd, 0, trans_pcie->txqs.tfd.size);
178 
179 	num_tbs = iwl_txq_gen1_tfd_get_num_tbs(tfd);
180 
181 	/* Each TFD can point to a maximum max_tbs Tx buffers */
182 	if (num_tbs >= trans_pcie->txqs.tfd.max_tbs) {
183 		IWL_ERR(trans, "Error can not send more than %d chunks\n",
184 			trans_pcie->txqs.tfd.max_tbs);
185 		return -EINVAL;
186 	}
187 
188 	if (WARN(addr & ~IWL_TX_DMA_MASK,
189 		 "Unaligned address = %llx\n", (unsigned long long)addr))
190 		return -EINVAL;
191 
192 	iwl_pcie_gen1_tfd_set_tb(tfd, num_tbs, addr, len);
193 
194 	return num_tbs;
195 }
196 
197 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
198 {
199 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
200 
201 	if (!trans->trans_cfg->base_params->apmg_wake_up_wa)
202 		return;
203 
204 	spin_lock(&trans_pcie->reg_lock);
205 
206 	if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) {
207 		spin_unlock(&trans_pcie->reg_lock);
208 		return;
209 	}
210 
211 	trans_pcie->cmd_hold_nic_awake = false;
212 	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
213 				   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
214 	spin_unlock(&trans_pcie->reg_lock);
215 }
216 
217 static void iwl_pcie_free_and_unmap_tso_page(struct iwl_trans *trans,
218 					     struct page *page)
219 {
220 	struct iwl_tso_page_info *info = IWL_TSO_PAGE_INFO(page_address(page));
221 
222 	/* Decrease internal use count and unmap/free page if needed */
223 	if (refcount_dec_and_test(&info->use_count)) {
224 		dma_unmap_page(trans->dev, info->dma_addr, PAGE_SIZE,
225 			       DMA_TO_DEVICE);
226 
227 		__free_page(page);
228 	}
229 }
230 
231 void iwl_pcie_free_tso_pages(struct iwl_trans *trans, struct sk_buff *skb,
232 			     struct iwl_cmd_meta *cmd_meta)
233 {
234 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
235 	struct page **page_ptr;
236 	struct page *next;
237 
238 	page_ptr = (void *)((u8 *)skb->cb + trans_pcie->txqs.page_offs);
239 	next = *page_ptr;
240 	*page_ptr = NULL;
241 
242 	while (next) {
243 		struct iwl_tso_page_info *info;
244 		struct page *tmp = next;
245 
246 		info = IWL_TSO_PAGE_INFO(page_address(next));
247 		next = info->next;
248 
249 		/* Unmap the scatter gather list that is on the last page */
250 		if (!next && cmd_meta->sg_offset) {
251 			struct sg_table *sgt;
252 
253 			sgt = (void *)((u8 *)page_address(tmp) +
254 				       cmd_meta->sg_offset);
255 
256 			dma_unmap_sgtable(trans->dev, sgt, DMA_TO_DEVICE, 0);
257 		}
258 
259 		iwl_pcie_free_and_unmap_tso_page(trans, tmp);
260 	}
261 }
262 
263 static inline dma_addr_t
264 iwl_txq_gen1_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
265 {
266 	struct iwl_tfd_tb *tb = &tfd->tbs[idx];
267 	dma_addr_t addr;
268 	dma_addr_t hi_len;
269 
270 	addr = get_unaligned_le32(&tb->lo);
271 
272 	if (sizeof(dma_addr_t) <= sizeof(u32))
273 		return addr;
274 
275 	hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
276 
277 	/*
278 	 * shift by 16 twice to avoid warnings on 32-bit
279 	 * (where this code never runs anyway due to the
280 	 * if statement above)
281 	 */
282 	return addr | ((hi_len << 16) << 16);
283 }
284 
285 static void iwl_txq_set_tfd_invalid_gen1(struct iwl_trans *trans,
286 					 struct iwl_tfd *tfd)
287 {
288 	tfd->num_tbs = 0;
289 
290 	iwl_pcie_gen1_tfd_set_tb(tfd, 0, trans->invalid_tx_cmd.dma,
291 				 trans->invalid_tx_cmd.size);
292 }
293 
294 static void iwl_txq_gen1_tfd_unmap(struct iwl_trans *trans,
295 				   struct iwl_cmd_meta *meta,
296 				   struct iwl_txq *txq, int index)
297 {
298 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
299 	int i, num_tbs;
300 	struct iwl_tfd *tfd = iwl_txq_get_tfd(trans, txq, index);
301 
302 	/* Sanity check on number of chunks */
303 	num_tbs = iwl_txq_gen1_tfd_get_num_tbs(tfd);
304 
305 	if (num_tbs > trans_pcie->txqs.tfd.max_tbs) {
306 		IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
307 		/* @todo issue fatal error, it is quite serious situation */
308 		return;
309 	}
310 
311 	/* TB1 is mapped directly, the rest is the TSO page and SG list. */
312 	if (meta->sg_offset)
313 		num_tbs = 2;
314 
315 	/* first TB is never freed - it's the bidirectional DMA data */
316 
317 	for (i = 1; i < num_tbs; i++) {
318 		if (meta->tbs & BIT(i))
319 			dma_unmap_page(trans->dev,
320 				       iwl_txq_gen1_tfd_tb_get_addr(tfd, i),
321 				       iwl_txq_gen1_tfd_tb_get_len(trans,
322 								   tfd, i),
323 				       DMA_TO_DEVICE);
324 		else
325 			dma_unmap_single(trans->dev,
326 					 iwl_txq_gen1_tfd_tb_get_addr(tfd, i),
327 					 iwl_txq_gen1_tfd_tb_get_len(trans,
328 								     tfd, i),
329 					 DMA_TO_DEVICE);
330 	}
331 
332 	meta->tbs = 0;
333 
334 	iwl_txq_set_tfd_invalid_gen1(trans, tfd);
335 }
336 
337 /**
338  * iwl_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
339  * @trans: transport private data
340  * @txq: tx queue
341  * @read_ptr: the TXQ read_ptr to free
342  *
343  * Does NOT advance any TFD circular buffer read/write indexes
344  * Does NOT free the TFD itself (which is within circular buffer)
345  */
346 static void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
347 			     int read_ptr)
348 {
349 	/* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
350 	 * idx is bounded by n_window
351 	 */
352 	int idx = iwl_txq_get_cmd_index(txq, read_ptr);
353 	struct sk_buff *skb;
354 
355 	lockdep_assert_held(&txq->reclaim_lock);
356 
357 	if (!txq->entries)
358 		return;
359 
360 	/* We have only q->n_window txq->entries, but we use
361 	 * TFD_QUEUE_SIZE_MAX tfds
362 	 */
363 	if (trans->trans_cfg->gen2)
364 		iwl_txq_gen2_tfd_unmap(trans, &txq->entries[idx].meta,
365 				       iwl_txq_get_tfd(trans, txq, read_ptr));
366 	else
367 		iwl_txq_gen1_tfd_unmap(trans, &txq->entries[idx].meta,
368 				       txq, read_ptr);
369 
370 	/* free SKB */
371 	skb = txq->entries[idx].skb;
372 
373 	/* Can be called from irqs-disabled context
374 	 * If skb is not NULL, it means that the whole queue is being
375 	 * freed and that the queue is not empty - free the skb
376 	 */
377 	if (skb) {
378 		iwl_op_mode_free_skb(trans->op_mode, skb);
379 		txq->entries[idx].skb = NULL;
380 	}
381 }
382 
383 /*
384  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
385  */
386 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
387 {
388 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
389 	struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
390 
391 	if (!txq) {
392 		IWL_ERR(trans, "Trying to free a queue that wasn't allocated?\n");
393 		return;
394 	}
395 
396 	spin_lock_bh(&txq->reclaim_lock);
397 	spin_lock(&txq->lock);
398 	while (txq->write_ptr != txq->read_ptr) {
399 		IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
400 				   txq_id, txq->read_ptr);
401 
402 		if (txq_id != trans_pcie->txqs.cmd.q_id) {
403 			struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
404 			struct iwl_cmd_meta *cmd_meta =
405 				&txq->entries[txq->read_ptr].meta;
406 
407 			if (WARN_ON_ONCE(!skb))
408 				continue;
409 
410 			iwl_pcie_free_tso_pages(trans, skb, cmd_meta);
411 		}
412 		iwl_txq_free_tfd(trans, txq, txq->read_ptr);
413 		txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr);
414 
415 		if (txq->read_ptr == txq->write_ptr &&
416 		    txq_id == trans_pcie->txqs.cmd.q_id)
417 			iwl_pcie_clear_cmd_in_flight(trans);
418 	}
419 
420 	while (!skb_queue_empty(&txq->overflow_q)) {
421 		struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
422 
423 		iwl_op_mode_free_skb(trans->op_mode, skb);
424 	}
425 
426 	spin_unlock(&txq->lock);
427 	spin_unlock_bh(&txq->reclaim_lock);
428 
429 	/* just in case - this queue may have been stopped */
430 	iwl_trans_pcie_wake_queue(trans, txq);
431 }
432 
433 /*
434  * iwl_pcie_txq_free - Deallocate DMA queue.
435  * @txq: Transmit queue to deallocate.
436  *
437  * Empty queue by removing and destroying all BD's.
438  * Free all buffers.
439  * 0-fill, but do not free "txq" descriptor structure.
440  */
441 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
442 {
443 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
444 	struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
445 	struct device *dev = trans->dev;
446 	int i;
447 
448 	if (WARN_ON(!txq))
449 		return;
450 
451 	iwl_pcie_txq_unmap(trans, txq_id);
452 
453 	/* De-alloc array of command/tx buffers */
454 	if (txq_id == trans_pcie->txqs.cmd.q_id)
455 		for (i = 0; i < txq->n_window; i++) {
456 			kfree_sensitive(txq->entries[i].cmd);
457 			kfree_sensitive(txq->entries[i].free_buf);
458 		}
459 
460 	/* De-alloc circular buffer of TFDs */
461 	if (txq->tfds) {
462 		dma_free_coherent(dev,
463 				  trans_pcie->txqs.tfd.size *
464 				  trans->trans_cfg->base_params->max_tfd_queue_size,
465 				  txq->tfds, txq->dma_addr);
466 		txq->dma_addr = 0;
467 		txq->tfds = NULL;
468 
469 		dma_free_coherent(dev,
470 				  sizeof(*txq->first_tb_bufs) * txq->n_window,
471 				  txq->first_tb_bufs, txq->first_tb_dma);
472 	}
473 
474 	kfree(txq->entries);
475 	txq->entries = NULL;
476 
477 	del_timer_sync(&txq->stuck_timer);
478 
479 	/* 0-fill queue descriptor structure */
480 	memset(txq, 0, sizeof(*txq));
481 }
482 
483 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
484 {
485 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
486 	int nq = trans->trans_cfg->base_params->num_of_queues;
487 	int chan;
488 	u32 reg_val;
489 	int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
490 				SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
491 
492 	/* make sure all queue are not stopped/used */
493 	memset(trans_pcie->txqs.queue_stopped, 0,
494 	       sizeof(trans_pcie->txqs.queue_stopped));
495 	memset(trans_pcie->txqs.queue_used, 0,
496 	       sizeof(trans_pcie->txqs.queue_used));
497 
498 	trans_pcie->scd_base_addr =
499 		iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
500 
501 	WARN_ON(scd_base_addr != 0 &&
502 		scd_base_addr != trans_pcie->scd_base_addr);
503 
504 	/* reset context data, TX status and translation data */
505 	iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
506 				   SCD_CONTEXT_MEM_LOWER_BOUND,
507 			    NULL, clear_dwords);
508 
509 	iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
510 		       trans_pcie->txqs.scd_bc_tbls.dma >> 10);
511 
512 	/* The chain extension of the SCD doesn't work well. This feature is
513 	 * enabled by default by the HW, so we need to disable it manually.
514 	 */
515 	if (trans->trans_cfg->base_params->scd_chain_ext_wa)
516 		iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
517 
518 	iwl_trans_ac_txq_enable(trans, trans_pcie->txqs.cmd.q_id,
519 				trans_pcie->txqs.cmd.fifo,
520 				trans_pcie->txqs.cmd.wdg_timeout);
521 
522 	/* Activate all Tx DMA/FIFO channels */
523 	iwl_scd_activate_fifos(trans);
524 
525 	/* Enable DMA channel */
526 	for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
527 		iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
528 				   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
529 				   FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
530 
531 	/* Update FH chicken bits */
532 	reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
533 	iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
534 			   reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
535 
536 	/* Enable L1-Active */
537 	if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
538 		iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
539 				    APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
540 }
541 
542 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
543 {
544 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
545 	int txq_id;
546 
547 	/*
548 	 * we should never get here in gen2 trans mode return early to avoid
549 	 * having invalid accesses
550 	 */
551 	if (WARN_ON_ONCE(trans->trans_cfg->gen2))
552 		return;
553 
554 	for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
555 	     txq_id++) {
556 		struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
557 		if (trans->trans_cfg->gen2)
558 			iwl_write_direct64(trans,
559 					   FH_MEM_CBBC_QUEUE(trans, txq_id),
560 					   txq->dma_addr);
561 		else
562 			iwl_write_direct32(trans,
563 					   FH_MEM_CBBC_QUEUE(trans, txq_id),
564 					   txq->dma_addr >> 8);
565 		iwl_pcie_txq_unmap(trans, txq_id);
566 		txq->read_ptr = 0;
567 		txq->write_ptr = 0;
568 	}
569 
570 	/* Tell NIC where to find the "keep warm" buffer */
571 	iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
572 			   trans_pcie->kw.dma >> 4);
573 
574 	/*
575 	 * Send 0 as the scd_base_addr since the device may have be reset
576 	 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
577 	 * contain garbage.
578 	 */
579 	iwl_pcie_tx_start(trans, 0);
580 }
581 
582 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
583 {
584 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
585 	int ch, ret;
586 	u32 mask = 0;
587 
588 	spin_lock_bh(&trans_pcie->irq_lock);
589 
590 	if (!iwl_trans_grab_nic_access(trans))
591 		goto out;
592 
593 	/* Stop each Tx DMA channel */
594 	for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
595 		iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
596 		mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
597 	}
598 
599 	/* Wait for DMA channels to be idle */
600 	ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
601 	if (ret < 0)
602 		IWL_ERR(trans,
603 			"Failing on timeout while stopping DMA channel %d [0x%08x]\n",
604 			ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
605 
606 	iwl_trans_release_nic_access(trans);
607 
608 out:
609 	spin_unlock_bh(&trans_pcie->irq_lock);
610 }
611 
612 /*
613  * iwl_pcie_tx_stop - Stop all Tx DMA channels
614  */
615 int iwl_pcie_tx_stop(struct iwl_trans *trans)
616 {
617 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
618 	int txq_id;
619 
620 	/* Turn off all Tx DMA fifos */
621 	iwl_scd_deactivate_fifos(trans);
622 
623 	/* Turn off all Tx DMA channels */
624 	iwl_pcie_tx_stop_fh(trans);
625 
626 	/*
627 	 * This function can be called before the op_mode disabled the
628 	 * queues. This happens when we have an rfkill interrupt.
629 	 * Since we stop Tx altogether - mark the queues as stopped.
630 	 */
631 	memset(trans_pcie->txqs.queue_stopped, 0,
632 	       sizeof(trans_pcie->txqs.queue_stopped));
633 	memset(trans_pcie->txqs.queue_used, 0,
634 	       sizeof(trans_pcie->txqs.queue_used));
635 
636 	/* This can happen: start_hw, stop_device */
637 	if (!trans_pcie->txq_memory)
638 		return 0;
639 
640 	/* Unmap DMA from host system and free skb's */
641 	for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
642 	     txq_id++)
643 		iwl_pcie_txq_unmap(trans, txq_id);
644 
645 	return 0;
646 }
647 
648 /*
649  * iwl_trans_tx_free - Free TXQ Context
650  *
651  * Destroy all TX DMA queues and structures
652  */
653 void iwl_pcie_tx_free(struct iwl_trans *trans)
654 {
655 	int txq_id;
656 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
657 
658 	memset(trans_pcie->txqs.queue_used, 0,
659 	       sizeof(trans_pcie->txqs.queue_used));
660 
661 	/* Tx queues */
662 	if (trans_pcie->txq_memory) {
663 		for (txq_id = 0;
664 		     txq_id < trans->trans_cfg->base_params->num_of_queues;
665 		     txq_id++) {
666 			iwl_pcie_txq_free(trans, txq_id);
667 			trans_pcie->txqs.txq[txq_id] = NULL;
668 		}
669 	}
670 
671 	kfree(trans_pcie->txq_memory);
672 	trans_pcie->txq_memory = NULL;
673 
674 	iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
675 
676 	iwl_pcie_free_dma_ptr(trans, &trans_pcie->txqs.scd_bc_tbls);
677 }
678 
679 void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
680 {
681 	u32 txq_id = txq->id;
682 	u32 status;
683 	bool active;
684 	u8 fifo;
685 
686 	if (trans->trans_cfg->gen2) {
687 		IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
688 			txq->read_ptr, txq->write_ptr);
689 		/* TODO: access new SCD registers and dump them */
690 		return;
691 	}
692 
693 	status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
694 	fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
695 	active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
696 
697 	IWL_ERR(trans,
698 		"Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
699 		txq_id, active ? "" : "in", fifo,
700 		jiffies_to_msecs(txq->wd_timeout),
701 		txq->read_ptr, txq->write_ptr,
702 		iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
703 			(trans->trans_cfg->base_params->max_tfd_queue_size - 1),
704 			iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
705 			(trans->trans_cfg->base_params->max_tfd_queue_size - 1),
706 			iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
707 }
708 
709 static void iwl_txq_stuck_timer(struct timer_list *t)
710 {
711 	struct iwl_txq *txq = from_timer(txq, t, stuck_timer);
712 	struct iwl_trans *trans = txq->trans;
713 
714 	spin_lock(&txq->lock);
715 	/* check if triggered erroneously */
716 	if (txq->read_ptr == txq->write_ptr) {
717 		spin_unlock(&txq->lock);
718 		return;
719 	}
720 	spin_unlock(&txq->lock);
721 
722 	iwl_txq_log_scd_error(trans, txq);
723 
724 	iwl_force_nmi(trans);
725 }
726 
727 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
728 		       int slots_num, bool cmd_queue)
729 {
730 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
731 	size_t num_entries = trans->trans_cfg->gen2 ?
732 		slots_num : trans->trans_cfg->base_params->max_tfd_queue_size;
733 	size_t tfd_sz;
734 	size_t tb0_buf_sz;
735 	int i;
736 
737 	if (WARN_ONCE(slots_num <= 0, "Invalid slots num:%d\n", slots_num))
738 		return -EINVAL;
739 
740 	if (WARN_ON(txq->entries || txq->tfds))
741 		return -EINVAL;
742 
743 	tfd_sz = trans_pcie->txqs.tfd.size * num_entries;
744 
745 	timer_setup(&txq->stuck_timer, iwl_txq_stuck_timer, 0);
746 	txq->trans = trans;
747 
748 	txq->n_window = slots_num;
749 
750 	txq->entries = kcalloc(slots_num,
751 			       sizeof(struct iwl_pcie_txq_entry),
752 			       GFP_KERNEL);
753 
754 	if (!txq->entries)
755 		goto error;
756 
757 	if (cmd_queue)
758 		for (i = 0; i < slots_num; i++) {
759 			txq->entries[i].cmd =
760 				kmalloc(sizeof(struct iwl_device_cmd),
761 					GFP_KERNEL);
762 			if (!txq->entries[i].cmd)
763 				goto error;
764 		}
765 
766 	/* Circular buffer of transmit frame descriptors (TFDs),
767 	 * shared with device
768 	 */
769 	txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
770 				       &txq->dma_addr, GFP_KERNEL);
771 	if (!txq->tfds)
772 		goto error;
773 
774 	BUILD_BUG_ON(sizeof(*txq->first_tb_bufs) != IWL_FIRST_TB_SIZE_ALIGN);
775 
776 	tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
777 
778 	txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
779 						&txq->first_tb_dma,
780 						GFP_KERNEL);
781 	if (!txq->first_tb_bufs)
782 		goto err_free_tfds;
783 
784 	for (i = 0; i < num_entries; i++) {
785 		void *tfd = iwl_txq_get_tfd(trans, txq, i);
786 
787 		if (trans->trans_cfg->gen2)
788 			iwl_txq_set_tfd_invalid_gen2(trans, tfd);
789 		else
790 			iwl_txq_set_tfd_invalid_gen1(trans, tfd);
791 	}
792 
793 	return 0;
794 err_free_tfds:
795 	dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
796 	txq->tfds = NULL;
797 error:
798 	if (txq->entries && cmd_queue)
799 		for (i = 0; i < slots_num; i++)
800 			kfree(txq->entries[i].cmd);
801 	kfree(txq->entries);
802 	txq->entries = NULL;
803 
804 	return -ENOMEM;
805 }
806 
807 /*
808  * iwl_pcie_tx_alloc - allocate TX context
809  * Allocate all Tx DMA structures and initialize them
810  */
811 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
812 {
813 	int ret;
814 	int txq_id, slots_num;
815 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
816 	u16 bc_tbls_size = trans->trans_cfg->base_params->num_of_queues;
817 
818 	if (WARN_ON(trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))
819 		return -EINVAL;
820 
821 	bc_tbls_size *= sizeof(struct iwlagn_scd_bc_tbl);
822 
823 	/*It is not allowed to alloc twice, so warn when this happens.
824 	 * We cannot rely on the previous allocation, so free and fail */
825 	if (WARN_ON(trans_pcie->txq_memory)) {
826 		ret = -EINVAL;
827 		goto error;
828 	}
829 
830 	ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->txqs.scd_bc_tbls,
831 				     bc_tbls_size);
832 	if (ret) {
833 		IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
834 		goto error;
835 	}
836 
837 	/* Alloc keep-warm buffer */
838 	ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
839 	if (ret) {
840 		IWL_ERR(trans, "Keep Warm allocation failed\n");
841 		goto error;
842 	}
843 
844 	trans_pcie->txq_memory =
845 		kcalloc(trans->trans_cfg->base_params->num_of_queues,
846 			sizeof(struct iwl_txq), GFP_KERNEL);
847 	if (!trans_pcie->txq_memory) {
848 		IWL_ERR(trans, "Not enough memory for txq\n");
849 		ret = -ENOMEM;
850 		goto error;
851 	}
852 
853 	/* Alloc and init all Tx queues, including the command queue (#4/#9) */
854 	for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
855 	     txq_id++) {
856 		bool cmd_queue = (txq_id == trans_pcie->txqs.cmd.q_id);
857 
858 		if (cmd_queue)
859 			slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
860 					  trans->cfg->min_txq_size);
861 		else
862 			slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
863 					  trans->cfg->min_ba_txq_size);
864 		trans_pcie->txqs.txq[txq_id] = &trans_pcie->txq_memory[txq_id];
865 		ret = iwl_pcie_txq_alloc(trans, trans_pcie->txqs.txq[txq_id],
866 					 slots_num, cmd_queue);
867 		if (ret) {
868 			IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
869 			goto error;
870 		}
871 		trans_pcie->txqs.txq[txq_id]->id = txq_id;
872 	}
873 
874 	return 0;
875 
876 error:
877 	iwl_pcie_tx_free(trans);
878 
879 	return ret;
880 }
881 
882 /*
883  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
884  */
885 static int iwl_queue_init(struct iwl_txq *q, int slots_num)
886 {
887 	q->n_window = slots_num;
888 
889 	/* slots_num must be power-of-two size, otherwise
890 	 * iwl_txq_get_cmd_index is broken.
891 	 */
892 	if (WARN_ON(!is_power_of_2(slots_num)))
893 		return -EINVAL;
894 
895 	q->low_mark = q->n_window / 4;
896 	if (q->low_mark < 4)
897 		q->low_mark = 4;
898 
899 	q->high_mark = q->n_window / 8;
900 	if (q->high_mark < 2)
901 		q->high_mark = 2;
902 
903 	q->write_ptr = 0;
904 	q->read_ptr = 0;
905 
906 	return 0;
907 }
908 
909 int iwl_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
910 		 int slots_num, bool cmd_queue)
911 {
912 	u32 tfd_queue_max_size =
913 		trans->trans_cfg->base_params->max_tfd_queue_size;
914 	int ret;
915 
916 	txq->need_update = false;
917 
918 	/* max_tfd_queue_size must be power-of-two size, otherwise
919 	 * iwl_txq_inc_wrap and iwl_txq_dec_wrap are broken.
920 	 */
921 	if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1),
922 		      "Max tfd queue size must be a power of two, but is %d",
923 		      tfd_queue_max_size))
924 		return -EINVAL;
925 
926 	/* Initialize queue's high/low-water marks, and head/tail indexes */
927 	ret = iwl_queue_init(txq, slots_num);
928 	if (ret)
929 		return ret;
930 
931 	spin_lock_init(&txq->lock);
932 	spin_lock_init(&txq->reclaim_lock);
933 
934 	if (cmd_queue) {
935 #if defined(__linux__)
936 		static struct lock_class_key iwl_txq_cmd_queue_lock_class;
937 
938 		lockdep_set_class(&txq->lock, &iwl_txq_cmd_queue_lock_class);
939 #endif
940 	}
941 
942 	__skb_queue_head_init(&txq->overflow_q);
943 
944 	return 0;
945 }
946 
947 int iwl_pcie_tx_init(struct iwl_trans *trans)
948 {
949 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
950 	int ret;
951 	int txq_id, slots_num;
952 	bool alloc = false;
953 
954 	if (!trans_pcie->txq_memory) {
955 		ret = iwl_pcie_tx_alloc(trans);
956 		if (ret)
957 			goto error;
958 		alloc = true;
959 	}
960 
961 	spin_lock_bh(&trans_pcie->irq_lock);
962 
963 	/* Turn off all Tx DMA fifos */
964 	iwl_scd_deactivate_fifos(trans);
965 
966 	/* Tell NIC where to find the "keep warm" buffer */
967 	iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
968 			   trans_pcie->kw.dma >> 4);
969 
970 	spin_unlock_bh(&trans_pcie->irq_lock);
971 
972 	/* Alloc and init all Tx queues, including the command queue (#4/#9) */
973 	for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
974 	     txq_id++) {
975 		bool cmd_queue = (txq_id == trans_pcie->txqs.cmd.q_id);
976 
977 		if (cmd_queue)
978 			slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
979 					  trans->cfg->min_txq_size);
980 		else
981 			slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
982 					  trans->cfg->min_ba_txq_size);
983 		ret = iwl_txq_init(trans, trans_pcie->txqs.txq[txq_id], slots_num,
984 				   cmd_queue);
985 		if (ret) {
986 			IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
987 			goto error;
988 		}
989 
990 		/*
991 		 * Tell nic where to find circular buffer of TFDs for a
992 		 * given Tx queue, and enable the DMA channel used for that
993 		 * queue.
994 		 * Circular buffer (TFD queue in DRAM) physical base address
995 		 */
996 		iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
997 				   trans_pcie->txqs.txq[txq_id]->dma_addr >> 8);
998 	}
999 
1000 	iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1001 	if (trans->trans_cfg->base_params->num_of_queues > 20)
1002 		iwl_set_bits_prph(trans, SCD_GP_CTRL,
1003 				  SCD_GP_CTRL_ENABLE_31_QUEUES);
1004 
1005 	return 0;
1006 error:
1007 	/*Upon error, free only if we allocated something */
1008 	if (alloc)
1009 		iwl_pcie_tx_free(trans);
1010 	return ret;
1011 }
1012 
1013 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1014 				      const struct iwl_host_cmd *cmd)
1015 {
1016 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1017 
1018 	/* Make sure the NIC is still alive in the bus */
1019 	if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1020 		return -ENODEV;
1021 
1022 	if (!trans->trans_cfg->base_params->apmg_wake_up_wa)
1023 		return 0;
1024 
1025 	/*
1026 	 * wake up the NIC to make sure that the firmware will see the host
1027 	 * command - we will let the NIC sleep once all the host commands
1028 	 * returned. This needs to be done only on NICs that have
1029 	 * apmg_wake_up_wa set (see above.)
1030 	 */
1031 	if (!_iwl_trans_pcie_grab_nic_access(trans))
1032 		return -EIO;
1033 
1034 	/*
1035 	 * In iwl_trans_grab_nic_access(), we've acquired the reg_lock.
1036 	 * There, we also returned immediately if cmd_hold_nic_awake is
1037 	 * already true, so it's OK to unconditionally set it to true.
1038 	 */
1039 	trans_pcie->cmd_hold_nic_awake = true;
1040 	spin_unlock(&trans_pcie->reg_lock);
1041 
1042 	return 0;
1043 }
1044 
1045 static void iwl_txq_progress(struct iwl_txq *txq)
1046 {
1047 	lockdep_assert_held(&txq->lock);
1048 
1049 	if (!txq->wd_timeout)
1050 		return;
1051 
1052 	/*
1053 	 * station is asleep and we send data - that must
1054 	 * be uAPSD or PS-Poll. Don't rearm the timer.
1055 	 */
1056 	if (txq->frozen)
1057 		return;
1058 
1059 	/*
1060 	 * if empty delete timer, otherwise move timer forward
1061 	 * since we're making progress on this queue
1062 	 */
1063 	if (txq->read_ptr == txq->write_ptr)
1064 		del_timer(&txq->stuck_timer);
1065 	else
1066 		mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1067 }
1068 
1069 static inline bool iwl_txq_used(const struct iwl_txq *q, int i,
1070 				int read_ptr, int write_ptr)
1071 {
1072 	int index = iwl_txq_get_cmd_index(q, i);
1073 	int r = iwl_txq_get_cmd_index(q, read_ptr);
1074 	int w = iwl_txq_get_cmd_index(q, write_ptr);
1075 
1076 	return w >= r ?
1077 		(index >= r && index < w) :
1078 		!(index < r && index >= w);
1079 }
1080 
1081 /*
1082  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1083  *
1084  * When FW advances 'R' index, all entries between old and new 'R' index
1085  * need to be reclaimed. As result, some free space forms.  If there is
1086  * enough free space (> low mark), wake the stack that feeds us.
1087  */
1088 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1089 {
1090 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1091 	struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
1092 	int nfreed = 0;
1093 	u16 r;
1094 
1095 	lockdep_assert_held(&txq->lock);
1096 
1097 	idx = iwl_txq_get_cmd_index(txq, idx);
1098 	r = iwl_txq_get_cmd_index(txq, txq->read_ptr);
1099 
1100 	if (idx >= trans->trans_cfg->base_params->max_tfd_queue_size ||
1101 	    (!iwl_txq_used(txq, idx, txq->read_ptr, txq->write_ptr))) {
1102 		WARN_ONCE(test_bit(txq_id, trans_pcie->txqs.queue_used),
1103 			  "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1104 			  __func__, txq_id, idx,
1105 			  trans->trans_cfg->base_params->max_tfd_queue_size,
1106 			  txq->write_ptr, txq->read_ptr);
1107 		return;
1108 	}
1109 
1110 	for (idx = iwl_txq_inc_wrap(trans, idx); r != idx;
1111 	     r = iwl_txq_inc_wrap(trans, r)) {
1112 		txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr);
1113 
1114 		if (nfreed++ > 0) {
1115 			IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1116 				idx, txq->write_ptr, r);
1117 			iwl_force_nmi(trans);
1118 		}
1119 	}
1120 
1121 	if (txq->read_ptr == txq->write_ptr)
1122 		iwl_pcie_clear_cmd_in_flight(trans);
1123 
1124 	iwl_txq_progress(txq);
1125 }
1126 
1127 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1128 				 u16 txq_id)
1129 {
1130 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1131 	u32 tbl_dw_addr;
1132 	u32 tbl_dw;
1133 	u16 scd_q2ratid;
1134 
1135 	scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1136 
1137 	tbl_dw_addr = trans_pcie->scd_base_addr +
1138 			SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1139 
1140 	tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1141 
1142 	if (txq_id & 0x1)
1143 		tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1144 	else
1145 		tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1146 
1147 	iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1148 
1149 	return 0;
1150 }
1151 
1152 /* Receiver address (actually, Rx station's index into station table),
1153  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1154 #define BUILD_RAxTID(sta_id, tid)	(((sta_id) << 4) + (tid))
1155 
1156 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1157 			       const struct iwl_trans_txq_scd_cfg *cfg,
1158 			       unsigned int wdg_timeout)
1159 {
1160 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1161 	struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
1162 	int fifo = -1;
1163 	bool scd_bug = false;
1164 
1165 	if (test_and_set_bit(txq_id, trans_pcie->txqs.queue_used))
1166 		WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1167 
1168 	txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1169 
1170 	if (cfg) {
1171 		fifo = cfg->fifo;
1172 
1173 		/* Disable the scheduler prior configuring the cmd queue */
1174 		if (txq_id == trans_pcie->txqs.cmd.q_id &&
1175 		    trans_pcie->scd_set_active)
1176 			iwl_scd_enable_set_active(trans, 0);
1177 
1178 		/* Stop this Tx queue before configuring it */
1179 		iwl_scd_txq_set_inactive(trans, txq_id);
1180 
1181 		/* Set this queue as a chain-building queue unless it is CMD */
1182 		if (txq_id != trans_pcie->txqs.cmd.q_id)
1183 			iwl_scd_txq_set_chain(trans, txq_id);
1184 
1185 		if (cfg->aggregate) {
1186 			u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1187 
1188 			/* Map receiver-address / traffic-ID to this queue */
1189 			iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1190 
1191 			/* enable aggregations for the queue */
1192 			iwl_scd_txq_enable_agg(trans, txq_id);
1193 			txq->ampdu = true;
1194 		} else {
1195 			/*
1196 			 * disable aggregations for the queue, this will also
1197 			 * make the ra_tid mapping configuration irrelevant
1198 			 * since it is now a non-AGG queue.
1199 			 */
1200 			iwl_scd_txq_disable_agg(trans, txq_id);
1201 
1202 			ssn = txq->read_ptr;
1203 		}
1204 	} else {
1205 		/*
1206 		 * If we need to move the SCD write pointer by steps of
1207 		 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
1208 		 * the op_mode know by returning true later.
1209 		 * Do this only in case cfg is NULL since this trick can
1210 		 * be done only if we have DQA enabled which is true for mvm
1211 		 * only. And mvm never sets a cfg pointer.
1212 		 * This is really ugly, but this is the easiest way out for
1213 		 * this sad hardware issue.
1214 		 * This bug has been fixed on devices 9000 and up.
1215 		 */
1216 		scd_bug = !trans->trans_cfg->mq_rx_supported &&
1217 			!((ssn - txq->write_ptr) & 0x3f) &&
1218 			(ssn != txq->write_ptr);
1219 		if (scd_bug)
1220 			ssn++;
1221 	}
1222 
1223 	/* Place first TFD at index corresponding to start sequence number.
1224 	 * Assumes that ssn_idx is valid (!= 0xFFF) */
1225 	txq->read_ptr = (ssn & 0xff);
1226 	txq->write_ptr = (ssn & 0xff);
1227 	iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1228 			   (ssn & 0xff) | (txq_id << 8));
1229 
1230 	if (cfg) {
1231 		u8 frame_limit = cfg->frame_limit;
1232 
1233 		iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1234 
1235 		/* Set up Tx window size and frame limit for this queue */
1236 		iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1237 				SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1238 		iwl_trans_write_mem32(trans,
1239 			trans_pcie->scd_base_addr +
1240 			SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1241 			SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1242 			SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1243 
1244 		/* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1245 		iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1246 			       (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1247 			       (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1248 			       (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1249 			       SCD_QUEUE_STTS_REG_MSK);
1250 
1251 		/* enable the scheduler for this queue (only) */
1252 		if (txq_id == trans_pcie->txqs.cmd.q_id &&
1253 		    trans_pcie->scd_set_active)
1254 			iwl_scd_enable_set_active(trans, BIT(txq_id));
1255 
1256 		IWL_DEBUG_TX_QUEUES(trans,
1257 				    "Activate queue %d on FIFO %d WrPtr: %d\n",
1258 				    txq_id, fifo, ssn & 0xff);
1259 	} else {
1260 		IWL_DEBUG_TX_QUEUES(trans,
1261 				    "Activate queue %d WrPtr: %d\n",
1262 				    txq_id, ssn & 0xff);
1263 	}
1264 
1265 	return scd_bug;
1266 }
1267 
1268 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1269 					bool shared_mode)
1270 {
1271 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1272 	struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
1273 
1274 	txq->ampdu = !shared_mode;
1275 }
1276 
1277 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1278 				bool configure_scd)
1279 {
1280 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1281 	u32 stts_addr = trans_pcie->scd_base_addr +
1282 			SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1283 	static const u32 zero_val[4] = {};
1284 
1285 	trans_pcie->txqs.txq[txq_id]->frozen_expiry_remainder = 0;
1286 	trans_pcie->txqs.txq[txq_id]->frozen = false;
1287 
1288 	/*
1289 	 * Upon HW Rfkill - we stop the device, and then stop the queues
1290 	 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1291 	 * allow the op_mode to call txq_disable after it already called
1292 	 * stop_device.
1293 	 */
1294 	if (!test_and_clear_bit(txq_id, trans_pcie->txqs.queue_used)) {
1295 		WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1296 			  "queue %d not used", txq_id);
1297 		return;
1298 	}
1299 
1300 	if (configure_scd) {
1301 		iwl_scd_txq_set_inactive(trans, txq_id);
1302 
1303 		iwl_trans_write_mem(trans, stts_addr, (const void *)zero_val,
1304 				    ARRAY_SIZE(zero_val));
1305 	}
1306 
1307 	iwl_pcie_txq_unmap(trans, txq_id);
1308 	trans_pcie->txqs.txq[txq_id]->ampdu = false;
1309 
1310 	IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1311 }
1312 
1313 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1314 
1315 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1316 {
1317 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1318 	int i;
1319 
1320 	for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
1321 		struct iwl_txq *txq = trans_pcie->txqs.txq[i];
1322 
1323 		if (i == trans_pcie->txqs.cmd.q_id)
1324 			continue;
1325 
1326 		/* we skip the command queue (obviously) so it's OK to nest */
1327 		spin_lock_nested(&txq->lock, 1);
1328 
1329 		if (!block && !(WARN_ON_ONCE(!txq->block))) {
1330 			txq->block--;
1331 			if (!txq->block) {
1332 				iwl_write32(trans, HBUS_TARG_WRPTR,
1333 					    txq->write_ptr | (i << 8));
1334 			}
1335 		} else if (block) {
1336 			txq->block++;
1337 		}
1338 
1339 		spin_unlock(&txq->lock);
1340 	}
1341 }
1342 
1343 /*
1344  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1345  * @priv: device private data point
1346  * @cmd: a pointer to the ucode command structure
1347  *
1348  * The function returns < 0 values to indicate the operation
1349  * failed. On success, it returns the index (>= 0) of command in the
1350  * command queue.
1351  */
1352 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1353 			  struct iwl_host_cmd *cmd)
1354 {
1355 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1356 	struct iwl_txq *txq = trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id];
1357 	struct iwl_device_cmd *out_cmd;
1358 	struct iwl_cmd_meta *out_meta;
1359 	void *dup_buf = NULL;
1360 	dma_addr_t phys_addr;
1361 	int idx;
1362 	u16 copy_size, cmd_size, tb0_size;
1363 	bool had_nocopy = false;
1364 	u8 group_id = iwl_cmd_groupid(cmd->id);
1365 	int i, ret;
1366 	u32 cmd_pos;
1367 	const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1368 	u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1369 	unsigned long flags;
1370 
1371 	if (WARN(!trans->wide_cmd_header &&
1372 		 group_id > IWL_ALWAYS_LONG_GROUP,
1373 		 "unsupported wide command %#x\n", cmd->id))
1374 		return -EINVAL;
1375 
1376 	if (group_id != 0) {
1377 		copy_size = sizeof(struct iwl_cmd_header_wide);
1378 		cmd_size = sizeof(struct iwl_cmd_header_wide);
1379 	} else {
1380 		copy_size = sizeof(struct iwl_cmd_header);
1381 		cmd_size = sizeof(struct iwl_cmd_header);
1382 	}
1383 
1384 	/* need one for the header if the first is NOCOPY */
1385 	BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1386 
1387 	for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1388 		cmddata[i] = cmd->data[i];
1389 		cmdlen[i] = cmd->len[i];
1390 
1391 		if (!cmd->len[i])
1392 			continue;
1393 
1394 		/* need at least IWL_FIRST_TB_SIZE copied */
1395 		if (copy_size < IWL_FIRST_TB_SIZE) {
1396 			int copy = IWL_FIRST_TB_SIZE - copy_size;
1397 
1398 			if (copy > cmdlen[i])
1399 				copy = cmdlen[i];
1400 			cmdlen[i] -= copy;
1401 			cmddata[i] += copy;
1402 			copy_size += copy;
1403 		}
1404 
1405 		if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1406 			had_nocopy = true;
1407 			if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1408 				idx = -EINVAL;
1409 				goto free_dup_buf;
1410 			}
1411 		} else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1412 			/*
1413 			 * This is also a chunk that isn't copied
1414 			 * to the static buffer so set had_nocopy.
1415 			 */
1416 			had_nocopy = true;
1417 
1418 			/* only allowed once */
1419 			if (WARN_ON(dup_buf)) {
1420 				idx = -EINVAL;
1421 				goto free_dup_buf;
1422 			}
1423 
1424 			dup_buf = kmemdup(cmddata[i], cmdlen[i],
1425 					  GFP_ATOMIC);
1426 			if (!dup_buf)
1427 				return -ENOMEM;
1428 		} else {
1429 			/* NOCOPY must not be followed by normal! */
1430 			if (WARN_ON(had_nocopy)) {
1431 				idx = -EINVAL;
1432 				goto free_dup_buf;
1433 			}
1434 			copy_size += cmdlen[i];
1435 		}
1436 		cmd_size += cmd->len[i];
1437 	}
1438 
1439 	/*
1440 	 * If any of the command structures end up being larger than
1441 	 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1442 	 * allocated into separate TFDs, then we will need to
1443 	 * increase the size of the buffers.
1444 	 */
1445 	if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1446 		 "Command %s (%#x) is too large (%d bytes)\n",
1447 		 iwl_get_cmd_string(trans, cmd->id),
1448 		 cmd->id, copy_size)) {
1449 		idx = -EINVAL;
1450 		goto free_dup_buf;
1451 	}
1452 
1453 	spin_lock_irqsave(&txq->lock, flags);
1454 
1455 	if (iwl_txq_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1456 		spin_unlock_irqrestore(&txq->lock, flags);
1457 
1458 		IWL_ERR(trans, "No space in command queue\n");
1459 		iwl_op_mode_cmd_queue_full(trans->op_mode);
1460 		idx = -ENOSPC;
1461 		goto free_dup_buf;
1462 	}
1463 
1464 	idx = iwl_txq_get_cmd_index(txq, txq->write_ptr);
1465 	out_cmd = txq->entries[idx].cmd;
1466 	out_meta = &txq->entries[idx].meta;
1467 
1468 	/* re-initialize, this also marks the SG list as unused */
1469 	memset(out_meta, 0, sizeof(*out_meta));
1470 	if (cmd->flags & CMD_WANT_SKB)
1471 		out_meta->source = cmd;
1472 
1473 	/* set up the header */
1474 	if (group_id != 0) {
1475 		out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1476 		out_cmd->hdr_wide.group_id = group_id;
1477 		out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1478 		out_cmd->hdr_wide.length =
1479 			cpu_to_le16(cmd_size -
1480 				    sizeof(struct iwl_cmd_header_wide));
1481 		out_cmd->hdr_wide.reserved = 0;
1482 		out_cmd->hdr_wide.sequence =
1483 			cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->txqs.cmd.q_id) |
1484 						 INDEX_TO_SEQ(txq->write_ptr));
1485 
1486 		cmd_pos = sizeof(struct iwl_cmd_header_wide);
1487 		copy_size = sizeof(struct iwl_cmd_header_wide);
1488 	} else {
1489 		out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1490 		out_cmd->hdr.sequence =
1491 			cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->txqs.cmd.q_id) |
1492 						 INDEX_TO_SEQ(txq->write_ptr));
1493 		out_cmd->hdr.group_id = 0;
1494 
1495 		cmd_pos = sizeof(struct iwl_cmd_header);
1496 		copy_size = sizeof(struct iwl_cmd_header);
1497 	}
1498 
1499 	/* and copy the data that needs to be copied */
1500 	for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1501 		int copy;
1502 
1503 		if (!cmd->len[i])
1504 			continue;
1505 
1506 		/* copy everything if not nocopy/dup */
1507 		if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1508 					   IWL_HCMD_DFL_DUP))) {
1509 			copy = cmd->len[i];
1510 
1511 			memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1512 			cmd_pos += copy;
1513 			copy_size += copy;
1514 			continue;
1515 		}
1516 
1517 		/*
1518 		 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1519 		 * in total (for bi-directional DMA), but copy up to what
1520 		 * we can fit into the payload for debug dump purposes.
1521 		 */
1522 		copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1523 
1524 		memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1525 		cmd_pos += copy;
1526 
1527 		/* However, treat copy_size the proper way, we need it below */
1528 		if (copy_size < IWL_FIRST_TB_SIZE) {
1529 			copy = IWL_FIRST_TB_SIZE - copy_size;
1530 
1531 			if (copy > cmd->len[i])
1532 				copy = cmd->len[i];
1533 			copy_size += copy;
1534 		}
1535 	}
1536 
1537 	IWL_DEBUG_HC(trans,
1538 		     "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1539 		     iwl_get_cmd_string(trans, cmd->id),
1540 		     group_id, out_cmd->hdr.cmd,
1541 		     le16_to_cpu(out_cmd->hdr.sequence),
1542 		     cmd_size, txq->write_ptr, idx, trans_pcie->txqs.cmd.q_id);
1543 
1544 	/* start the TFD with the minimum copy bytes */
1545 	tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1546 	memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1547 	iwl_pcie_txq_build_tfd(trans, txq,
1548 			       iwl_txq_get_first_tb_dma(txq, idx),
1549 			       tb0_size, true);
1550 
1551 	/* map first command fragment, if any remains */
1552 	if (copy_size > tb0_size) {
1553 		phys_addr = dma_map_single(trans->dev,
1554 					   ((u8 *)&out_cmd->hdr) + tb0_size,
1555 					   copy_size - tb0_size,
1556 					   DMA_TO_DEVICE);
1557 		if (dma_mapping_error(trans->dev, phys_addr)) {
1558 			iwl_txq_gen1_tfd_unmap(trans, out_meta, txq,
1559 					       txq->write_ptr);
1560 			idx = -ENOMEM;
1561 			goto out;
1562 		}
1563 
1564 		iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1565 				       copy_size - tb0_size, false);
1566 	}
1567 
1568 	/* map the remaining (adjusted) nocopy/dup fragments */
1569 	for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1570 		void *data = (void *)(uintptr_t)cmddata[i];
1571 
1572 		if (!cmdlen[i])
1573 			continue;
1574 		if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1575 					   IWL_HCMD_DFL_DUP)))
1576 			continue;
1577 		if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1578 			data = dup_buf;
1579 		phys_addr = dma_map_single(trans->dev, data,
1580 					   cmdlen[i], DMA_TO_DEVICE);
1581 		if (dma_mapping_error(trans->dev, phys_addr)) {
1582 			iwl_txq_gen1_tfd_unmap(trans, out_meta, txq,
1583 					       txq->write_ptr);
1584 			idx = -ENOMEM;
1585 			goto out;
1586 		}
1587 
1588 		iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1589 	}
1590 
1591 	BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1592 	out_meta->flags = cmd->flags;
1593 	if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1594 		kfree_sensitive(txq->entries[idx].free_buf);
1595 	txq->entries[idx].free_buf = dup_buf;
1596 
1597 	trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1598 
1599 	/* start timer if queue currently empty */
1600 	if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1601 		mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1602 
1603 	ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1604 	if (ret < 0) {
1605 		idx = ret;
1606 		goto out;
1607 	}
1608 
1609 	if (cmd->flags & CMD_BLOCK_TXQS)
1610 		iwl_trans_pcie_block_txq_ptrs(trans, true);
1611 
1612 	/* Increment and update queue's write index */
1613 	txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr);
1614 	iwl_pcie_txq_inc_wr_ptr(trans, txq);
1615 
1616  out:
1617 	spin_unlock_irqrestore(&txq->lock, flags);
1618  free_dup_buf:
1619 	if (idx < 0)
1620 		kfree(dup_buf);
1621 	return idx;
1622 }
1623 
1624 /*
1625  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1626  * @rxb: Rx buffer to reclaim
1627  */
1628 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1629 			    struct iwl_rx_cmd_buffer *rxb)
1630 {
1631 	struct iwl_rx_packet *pkt = rxb_addr(rxb);
1632 	u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1633 	u8 group_id;
1634 	u32 cmd_id;
1635 	int txq_id = SEQ_TO_QUEUE(sequence);
1636 	int index = SEQ_TO_INDEX(sequence);
1637 	int cmd_index;
1638 	struct iwl_device_cmd *cmd;
1639 	struct iwl_cmd_meta *meta;
1640 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1641 	struct iwl_txq *txq = trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id];
1642 
1643 	/* If a Tx command is being handled and it isn't in the actual
1644 	 * command queue then there a command routing bug has been introduced
1645 	 * in the queue management code. */
1646 	if (WARN(txq_id != trans_pcie->txqs.cmd.q_id,
1647 		 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1648 		 txq_id, trans_pcie->txqs.cmd.q_id, sequence, txq->read_ptr,
1649 		 txq->write_ptr)) {
1650 		iwl_print_hex_error(trans, pkt, 32);
1651 		return;
1652 	}
1653 
1654 	spin_lock_bh(&txq->lock);
1655 
1656 	cmd_index = iwl_txq_get_cmd_index(txq, index);
1657 	cmd = txq->entries[cmd_index].cmd;
1658 	meta = &txq->entries[cmd_index].meta;
1659 	group_id = cmd->hdr.group_id;
1660 	cmd_id = WIDE_ID(group_id, cmd->hdr.cmd);
1661 
1662 	if (trans->trans_cfg->gen2)
1663 		iwl_txq_gen2_tfd_unmap(trans, meta,
1664 				       iwl_txq_get_tfd(trans, txq, index));
1665 	else
1666 		iwl_txq_gen1_tfd_unmap(trans, meta, txq, index);
1667 
1668 	/* Input error checking is done when commands are added to queue. */
1669 	if (meta->flags & CMD_WANT_SKB) {
1670 		struct page *p = rxb_steal_page(rxb);
1671 
1672 		meta->source->resp_pkt = pkt;
1673 #if defined(__linux__)
1674 		meta->source->_rx_page_addr = (unsigned long)page_address(p);
1675 #elif defined(__FreeBSD__)
1676 		meta->source->_page = p;
1677 #endif
1678 		meta->source->_rx_page_order = trans_pcie->rx_page_order;
1679 	}
1680 
1681 	if (meta->flags & CMD_BLOCK_TXQS)
1682 		iwl_trans_pcie_block_txq_ptrs(trans, false);
1683 
1684 	iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1685 
1686 	if (!(meta->flags & CMD_ASYNC)) {
1687 		if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1688 			IWL_WARN(trans,
1689 				 "HCMD_ACTIVE already clear for command %s\n",
1690 				 iwl_get_cmd_string(trans, cmd_id));
1691 		}
1692 		clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1693 		IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1694 			       iwl_get_cmd_string(trans, cmd_id));
1695 		wake_up(&trans->wait_command_queue);
1696 	}
1697 
1698 	meta->flags = 0;
1699 
1700 	spin_unlock_bh(&txq->lock);
1701 }
1702 
1703 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1704 			     struct iwl_txq *txq, u8 hdr_len,
1705 			     struct iwl_cmd_meta *out_meta)
1706 {
1707 	u16 head_tb_len;
1708 	int i;
1709 
1710 	/*
1711 	 * Set up TFD's third entry to point directly to remainder
1712 	 * of skb's head, if any
1713 	 */
1714 	head_tb_len = skb_headlen(skb) - hdr_len;
1715 
1716 	if (head_tb_len > 0) {
1717 		dma_addr_t tb_phys = dma_map_single(trans->dev,
1718 						    skb->data + hdr_len,
1719 						    head_tb_len, DMA_TO_DEVICE);
1720 		if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
1721 			return -EINVAL;
1722 		trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb->data + hdr_len,
1723 					tb_phys, head_tb_len);
1724 		iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false);
1725 	}
1726 
1727 	/* set up the remaining entries to point to the data */
1728 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1729 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1730 		dma_addr_t tb_phys;
1731 		int tb_idx;
1732 
1733 		if (!skb_frag_size(frag))
1734 			continue;
1735 
1736 		tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1737 					   skb_frag_size(frag), DMA_TO_DEVICE);
1738 
1739 		if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
1740 			return -EINVAL;
1741 		trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb_frag_address(frag),
1742 					tb_phys, skb_frag_size(frag));
1743 		tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1744 						skb_frag_size(frag), false);
1745 		if (tb_idx < 0)
1746 			return tb_idx;
1747 
1748 		out_meta->tbs |= BIT(tb_idx);
1749 	}
1750 
1751 	return 0;
1752 }
1753 
1754 #ifdef CONFIG_INET
1755 static void *iwl_pcie_get_page_hdr(struct iwl_trans *trans,
1756 				   size_t len, struct sk_buff *skb)
1757 {
1758 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1759 	struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->txqs.tso_hdr_page);
1760 	struct iwl_tso_page_info *info;
1761 	struct page **page_ptr;
1762 	dma_addr_t phys;
1763 	void *ret;
1764 
1765 	page_ptr = (void *)((u8 *)skb->cb + trans_pcie->txqs.page_offs);
1766 
1767 	if (WARN_ON(*page_ptr))
1768 		return NULL;
1769 
1770 	if (!p->page)
1771 		goto alloc;
1772 
1773 	/*
1774 	 * Check if there's enough room on this page
1775 	 *
1776 	 * Note that we put a page chaining pointer *last* in the
1777 	 * page - we need it somewhere, and if it's there then we
1778 	 * avoid DMA mapping the last bits of the page which may
1779 	 * trigger the 32-bit boundary hardware bug.
1780 	 *
1781 	 * (see also get_workaround_page() in tx-gen2.c)
1782 	 */
1783 	if (((unsigned long)p->pos & ~PAGE_MASK) + len < IWL_TSO_PAGE_DATA_SIZE) {
1784 		info = IWL_TSO_PAGE_INFO(page_address(p->page));
1785 		goto out;
1786 	}
1787 
1788 	/* We don't have enough room on this page, get a new one. */
1789 	iwl_pcie_free_and_unmap_tso_page(trans, p->page);
1790 
1791 alloc:
1792 	p->page = alloc_page(GFP_ATOMIC);
1793 	if (!p->page)
1794 		return NULL;
1795 	p->pos = page_address(p->page);
1796 
1797 	info = IWL_TSO_PAGE_INFO(page_address(p->page));
1798 
1799 	/* set the chaining pointer to NULL */
1800 	info->next = NULL;
1801 
1802 	/* Create a DMA mapping for the page */
1803 	phys = dma_map_page_attrs(trans->dev, p->page, 0, PAGE_SIZE,
1804 				  DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
1805 	if (unlikely(dma_mapping_error(trans->dev, phys))) {
1806 		__free_page(p->page);
1807 		p->page = NULL;
1808 
1809 		return NULL;
1810 	}
1811 
1812 	/* Store physical address and set use count */
1813 	info->dma_addr = phys;
1814 	refcount_set(&info->use_count, 1);
1815 out:
1816 	*page_ptr = p->page;
1817 	/* Return an internal reference for the caller */
1818 	refcount_inc(&info->use_count);
1819 	ret = p->pos;
1820 	p->pos += len;
1821 
1822 	return ret;
1823 }
1824 
1825 /**
1826  * iwl_pcie_get_sgt_tb_phys - Find TB address in mapped SG list
1827  * @sgt: scatter gather table
1828  * @offset: Offset into the mapped memory (i.e. SKB payload data)
1829  * @len: Length of the area
1830  *
1831  * Find the DMA address that corresponds to the SKB payload data at the
1832  * position given by @offset.
1833  *
1834  * Returns: Address for TB entry
1835  */
1836 dma_addr_t iwl_pcie_get_sgt_tb_phys(struct sg_table *sgt, unsigned int offset,
1837 				    unsigned int len)
1838 {
1839 	struct scatterlist *sg;
1840 	unsigned int sg_offset = 0;
1841 	int i;
1842 
1843 	/*
1844 	 * Search the mapped DMA areas in the SG for the area that contains the
1845 	 * data at offset with the given length.
1846 	 */
1847 	for_each_sgtable_dma_sg(sgt, sg, i) {
1848 		if (offset >= sg_offset &&
1849 		    offset + len <= sg_offset + sg_dma_len(sg))
1850 			return sg_dma_address(sg) + offset - sg_offset;
1851 
1852 		sg_offset += sg_dma_len(sg);
1853 	}
1854 
1855 	WARN_ON_ONCE(1);
1856 
1857 	return DMA_MAPPING_ERROR;
1858 }
1859 
1860 /**
1861  * iwl_pcie_prep_tso - Prepare TSO page and SKB for sending
1862  * @trans: transport private data
1863  * @skb: the SKB to map
1864  * @cmd_meta: command meta to store the scatter list information for unmapping
1865  * @hdr: output argument for TSO headers
1866  * @hdr_room: requested length for TSO headers
1867  *
1868  * Allocate space for a scatter gather list and TSO headers and map the SKB
1869  * using the scatter gather list. The SKB is unmapped again when the page is
1870  * free'ed again at the end of the operation.
1871  *
1872  * Returns: newly allocated and mapped scatter gather table with list
1873  */
1874 struct sg_table *iwl_pcie_prep_tso(struct iwl_trans *trans, struct sk_buff *skb,
1875 				   struct iwl_cmd_meta *cmd_meta,
1876 				   u8 **hdr, unsigned int hdr_room)
1877 {
1878 	struct sg_table *sgt;
1879 
1880 	if (WARN_ON_ONCE(skb_has_frag_list(skb)))
1881 		return NULL;
1882 
1883 	*hdr = iwl_pcie_get_page_hdr(trans,
1884 				     hdr_room + __alignof__(struct sg_table) +
1885 				     sizeof(struct sg_table) +
1886 				     (skb_shinfo(skb)->nr_frags + 1) *
1887 				     sizeof(struct scatterlist),
1888 				     skb);
1889 	if (!*hdr)
1890 		return NULL;
1891 
1892 	sgt = (void *)PTR_ALIGN(*hdr + hdr_room, __alignof__(struct sg_table));
1893 	sgt->sgl = (void *)(sgt + 1);
1894 
1895 	sg_init_table(sgt->sgl, skb_shinfo(skb)->nr_frags + 1);
1896 
1897 	/* Only map the data, not the header (it is copied to the TSO page) */
1898 	sgt->orig_nents = skb_to_sgvec(skb, sgt->sgl, skb_headlen(skb),
1899 				       skb->data_len);
1900 	if (WARN_ON_ONCE(sgt->orig_nents <= 0))
1901 		return NULL;
1902 
1903 	/* And map the entire SKB */
1904 	if (dma_map_sgtable(trans->dev, sgt, DMA_TO_DEVICE, 0) < 0)
1905 		return NULL;
1906 
1907 	/* Store non-zero (i.e. valid) offset for unmapping */
1908 	cmd_meta->sg_offset = (unsigned long) sgt & ~PAGE_MASK;
1909 
1910 	return sgt;
1911 }
1912 
1913 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
1914 				   struct iwl_txq *txq, u8 hdr_len,
1915 				   struct iwl_cmd_meta *out_meta,
1916 				   struct iwl_device_tx_cmd *dev_cmd,
1917 				   u16 tb1_len)
1918 {
1919 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1920 	struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
1921 	struct ieee80211_hdr *hdr = (void *)skb->data;
1922 	unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
1923 	unsigned int mss = skb_shinfo(skb)->gso_size;
1924 	unsigned int data_offset = 0;
1925 	u16 length, iv_len, amsdu_pad;
1926 	dma_addr_t start_hdr_phys;
1927 	u8 *start_hdr, *pos_hdr;
1928 	struct sg_table *sgt;
1929 	struct tso_t tso;
1930 
1931 	/* if the packet is protected, then it must be CCMP or GCMP */
1932 	BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
1933 	iv_len = ieee80211_has_protected(hdr->frame_control) ?
1934 		IEEE80211_CCMP_HDR_LEN : 0;
1935 
1936 	trace_iwlwifi_dev_tx(trans->dev, skb,
1937 			     iwl_txq_get_tfd(trans, txq, txq->write_ptr),
1938 			     trans_pcie->txqs.tfd.size,
1939 			     &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
1940 
1941 	ip_hdrlen = skb_network_header_len(skb);
1942 	snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
1943 	total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
1944 	amsdu_pad = 0;
1945 
1946 	/* total amount of header we may need for this A-MSDU */
1947 	hdr_room = DIV_ROUND_UP(total_len, mss) *
1948 		(3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
1949 
1950 	/* Our device supports 9 segments at most, it will fit in 1 page */
1951 	sgt = iwl_pcie_prep_tso(trans, skb, out_meta, &start_hdr, hdr_room);
1952 	if (!sgt)
1953 		return -ENOMEM;
1954 
1955 	start_hdr_phys = iwl_pcie_get_tso_page_phys(start_hdr);
1956 	pos_hdr = start_hdr;
1957 	memcpy(pos_hdr, skb->data + hdr_len, iv_len);
1958 	pos_hdr += iv_len;
1959 
1960 	/*
1961 	 * Pull the ieee80211 header + IV to be able to use TSO core,
1962 	 * we will restore it for the tx_status flow.
1963 	 */
1964 	skb_pull(skb, hdr_len + iv_len);
1965 
1966 	/*
1967 	 * Remove the length of all the headers that we don't actually
1968 	 * have in the MPDU by themselves, but that we duplicate into
1969 	 * all the different MSDUs inside the A-MSDU.
1970 	 */
1971 	le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
1972 
1973 	tso_start(skb, &tso);
1974 
1975 	while (total_len) {
1976 		/* this is the data left for this subframe */
1977 		unsigned int data_left =
1978 			min_t(unsigned int, mss, total_len);
1979 		unsigned int hdr_tb_len;
1980 		dma_addr_t hdr_tb_phys;
1981 		u8 *subf_hdrs_start = pos_hdr;
1982 
1983 		total_len -= data_left;
1984 
1985 		memset(pos_hdr, 0, amsdu_pad);
1986 		pos_hdr += amsdu_pad;
1987 		amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
1988 				  data_left)) & 0x3;
1989 		ether_addr_copy(pos_hdr, ieee80211_get_DA(hdr));
1990 		pos_hdr += ETH_ALEN;
1991 		ether_addr_copy(pos_hdr, ieee80211_get_SA(hdr));
1992 		pos_hdr += ETH_ALEN;
1993 
1994 		length = snap_ip_tcp_hdrlen + data_left;
1995 		*((__be16 *)pos_hdr) = cpu_to_be16(length);
1996 		pos_hdr += sizeof(length);
1997 
1998 		/*
1999 		 * This will copy the SNAP as well which will be considered
2000 		 * as MAC header.
2001 		 */
2002 		tso_build_hdr(skb, pos_hdr, &tso, data_left, !total_len);
2003 
2004 		pos_hdr += snap_ip_tcp_hdrlen;
2005 
2006 		hdr_tb_len = pos_hdr - start_hdr;
2007 		hdr_tb_phys = iwl_pcie_get_tso_page_phys(start_hdr);
2008 
2009 		iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2010 				       hdr_tb_len, false);
2011 		trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
2012 					hdr_tb_phys, hdr_tb_len);
2013 		/* add this subframe's headers' length to the tx_cmd */
2014 		le16_add_cpu(&tx_cmd->len, pos_hdr - subf_hdrs_start);
2015 
2016 		/* prepare the start_hdr for the next subframe */
2017 		start_hdr = pos_hdr;
2018 
2019 		/* put the payload */
2020 		while (data_left) {
2021 			unsigned int size = min_t(unsigned int, tso.size,
2022 						  data_left);
2023 			dma_addr_t tb_phys;
2024 
2025 			tb_phys = iwl_pcie_get_sgt_tb_phys(sgt, data_offset, size);
2026 			/* Not a real mapping error, use direct comparison */
2027 			if (unlikely(tb_phys == DMA_MAPPING_ERROR))
2028 				return -EINVAL;
2029 
2030 			iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2031 					       size, false);
2032 			trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
2033 						tb_phys, size);
2034 
2035 			data_left -= size;
2036 			data_offset += size;
2037 			tso_build_data(skb, &tso, size);
2038 		}
2039 	}
2040 
2041 	dma_sync_single_for_device(trans->dev, start_hdr_phys, hdr_room,
2042 				   DMA_TO_DEVICE);
2043 
2044 	/* re -add the WiFi header and IV */
2045 	skb_push(skb, hdr_len + iv_len);
2046 
2047 	return 0;
2048 }
2049 #else /* CONFIG_INET */
2050 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2051 				   struct iwl_txq *txq, u8 hdr_len,
2052 				   struct iwl_cmd_meta *out_meta,
2053 				   struct iwl_device_tx_cmd *dev_cmd,
2054 				   u16 tb1_len)
2055 {
2056 	/* No A-MSDU without CONFIG_INET */
2057 	WARN_ON(1);
2058 
2059 	return -1;
2060 }
2061 #endif /* CONFIG_INET */
2062 
2063 #define IWL_TX_CRC_SIZE 4
2064 #define IWL_TX_DELIMITER_SIZE 4
2065 
2066 /*
2067  * iwl_txq_gen1_update_byte_cnt_tbl - Set up entry in Tx byte-count array
2068  */
2069 static void iwl_txq_gen1_update_byte_cnt_tbl(struct iwl_trans *trans,
2070 					     struct iwl_txq *txq, u16 byte_cnt,
2071 					     int num_tbs)
2072 {
2073 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2074 	struct iwlagn_scd_bc_tbl *scd_bc_tbl;
2075 	int write_ptr = txq->write_ptr;
2076 	int txq_id = txq->id;
2077 	u8 sec_ctl = 0;
2078 	u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2079 	__le16 bc_ent;
2080 	struct iwl_device_tx_cmd *dev_cmd = txq->entries[txq->write_ptr].cmd;
2081 	struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2082 	u8 sta_id = tx_cmd->sta_id;
2083 
2084 	scd_bc_tbl = trans_pcie->txqs.scd_bc_tbls.addr;
2085 
2086 	sec_ctl = tx_cmd->sec_ctl;
2087 
2088 	switch (sec_ctl & TX_CMD_SEC_MSK) {
2089 	case TX_CMD_SEC_CCM:
2090 		len += IEEE80211_CCMP_MIC_LEN;
2091 		break;
2092 	case TX_CMD_SEC_TKIP:
2093 		len += IEEE80211_TKIP_ICV_LEN;
2094 		break;
2095 	case TX_CMD_SEC_WEP:
2096 		len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
2097 		break;
2098 	}
2099 	if (trans_pcie->txqs.bc_table_dword)
2100 		len = DIV_ROUND_UP(len, 4);
2101 
2102 	if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
2103 		return;
2104 
2105 	bc_ent = cpu_to_le16(len | (sta_id << 12));
2106 
2107 	scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
2108 
2109 	if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
2110 		scd_bc_tbl[txq_id].tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] =
2111 			bc_ent;
2112 }
2113 
2114 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2115 		      struct iwl_device_tx_cmd *dev_cmd, int txq_id)
2116 {
2117 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2118 	struct ieee80211_hdr *hdr;
2119 	struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2120 	struct iwl_cmd_meta *out_meta;
2121 	struct iwl_txq *txq;
2122 	dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2123 	void *tb1_addr;
2124 	void *tfd;
2125 	u16 len, tb1_len;
2126 	bool wait_write_ptr;
2127 	__le16 fc;
2128 	u8 hdr_len;
2129 	u16 wifi_seq;
2130 	bool amsdu;
2131 
2132 	txq = trans_pcie->txqs.txq[txq_id];
2133 
2134 	if (WARN_ONCE(!test_bit(txq_id, trans_pcie->txqs.queue_used),
2135 		      "TX on unused queue %d\n", txq_id))
2136 		return -EINVAL;
2137 
2138 	if (skb_is_nonlinear(skb) &&
2139 	    skb_shinfo(skb)->nr_frags > IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie) &&
2140 	    __skb_linearize(skb))
2141 		return -ENOMEM;
2142 
2143 	/* mac80211 always puts the full header into the SKB's head,
2144 	 * so there's no need to check if it's readable there
2145 	 */
2146 	hdr = (struct ieee80211_hdr *)skb->data;
2147 	fc = hdr->frame_control;
2148 	hdr_len = ieee80211_hdrlen(fc);
2149 
2150 	spin_lock(&txq->lock);
2151 
2152 	if (iwl_txq_space(trans, txq) < txq->high_mark) {
2153 		iwl_txq_stop(trans, txq);
2154 
2155 		/* don't put the packet on the ring, if there is no room */
2156 		if (unlikely(iwl_txq_space(trans, txq) < 3)) {
2157 			struct iwl_device_tx_cmd **dev_cmd_ptr;
2158 
2159 			dev_cmd_ptr = (void *)((u8 *)skb->cb +
2160 					       trans_pcie->txqs.dev_cmd_offs);
2161 
2162 			*dev_cmd_ptr = dev_cmd;
2163 			__skb_queue_tail(&txq->overflow_q, skb);
2164 
2165 			spin_unlock(&txq->lock);
2166 			return 0;
2167 		}
2168 	}
2169 
2170 	/* In AGG mode, the index in the ring must correspond to the WiFi
2171 	 * sequence number. This is a HW requirements to help the SCD to parse
2172 	 * the BA.
2173 	 * Check here that the packets are in the right place on the ring.
2174 	 */
2175 	wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2176 	WARN_ONCE(txq->ampdu &&
2177 		  (wifi_seq & 0xff) != txq->write_ptr,
2178 		  "Q: %d WiFi Seq %d tfdNum %d",
2179 		  txq_id, wifi_seq, txq->write_ptr);
2180 
2181 	/* Set up driver data for this TFD */
2182 	txq->entries[txq->write_ptr].skb = skb;
2183 	txq->entries[txq->write_ptr].cmd = dev_cmd;
2184 
2185 	dev_cmd->hdr.sequence =
2186 		cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2187 			    INDEX_TO_SEQ(txq->write_ptr)));
2188 
2189 	tb0_phys = iwl_txq_get_first_tb_dma(txq, txq->write_ptr);
2190 	scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2191 		       offsetof(struct iwl_tx_cmd, scratch);
2192 
2193 	tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2194 	tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2195 
2196 	/* Set up first empty entry in queue's array of Tx/cmd buffers */
2197 	out_meta = &txq->entries[txq->write_ptr].meta;
2198 	memset(out_meta, 0, sizeof(*out_meta));
2199 
2200 	/*
2201 	 * The second TB (tb1) points to the remainder of the TX command
2202 	 * and the 802.11 header - dword aligned size
2203 	 * (This calculation modifies the TX command, so do it before the
2204 	 * setup of the first TB)
2205 	 */
2206 	len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2207 	      hdr_len - IWL_FIRST_TB_SIZE;
2208 	/* do not align A-MSDU to dword as the subframe header aligns it */
2209 	amsdu = ieee80211_is_data_qos(fc) &&
2210 		(*ieee80211_get_qos_ctl(hdr) &
2211 		 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2212 	if (!amsdu) {
2213 		tb1_len = ALIGN(len, 4);
2214 		/* Tell NIC about any 2-byte padding after MAC header */
2215 		if (tb1_len != len)
2216 			tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2217 	} else {
2218 		tb1_len = len;
2219 	}
2220 
2221 	/*
2222 	 * The first TB points to bi-directional DMA data, we'll
2223 	 * memcpy the data into it later.
2224 	 */
2225 	iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2226 			       IWL_FIRST_TB_SIZE, true);
2227 
2228 	/* there must be data left over for TB1 or this code must be changed */
2229 	BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2230 	BUILD_BUG_ON(sizeof(struct iwl_cmd_header) +
2231 		     offsetofend(struct iwl_tx_cmd, scratch) >
2232 		     IWL_FIRST_TB_SIZE);
2233 
2234 	/* map the data for TB1 */
2235 	tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2236 	tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2237 	if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2238 		goto out_err;
2239 	iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2240 
2241 	trace_iwlwifi_dev_tx(trans->dev, skb,
2242 			     iwl_txq_get_tfd(trans, txq, txq->write_ptr),
2243 			     trans_pcie->txqs.tfd.size,
2244 			     &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2245 			     hdr_len);
2246 
2247 	/*
2248 	 * If gso_size wasn't set, don't give the frame "amsdu treatment"
2249 	 * (adding subframes, etc.).
2250 	 * This can happen in some testing flows when the amsdu was already
2251 	 * pre-built, and we just need to send the resulting skb.
2252 	 */
2253 	if (amsdu && skb_shinfo(skb)->gso_size) {
2254 		if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2255 						     out_meta, dev_cmd,
2256 						     tb1_len)))
2257 			goto out_err;
2258 	} else {
2259 		struct sk_buff *frag;
2260 
2261 		if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2262 					       out_meta)))
2263 			goto out_err;
2264 
2265 		skb_walk_frags(skb, frag) {
2266 			if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0,
2267 						       out_meta)))
2268 				goto out_err;
2269 		}
2270 	}
2271 
2272 	/* building the A-MSDU might have changed this data, so memcpy it now */
2273 	memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE);
2274 
2275 	tfd = iwl_txq_get_tfd(trans, txq, txq->write_ptr);
2276 	/* Set up entry for this TFD in Tx byte-count array */
2277 	iwl_txq_gen1_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2278 					 iwl_txq_gen1_tfd_get_num_tbs(tfd));
2279 
2280 	wait_write_ptr = ieee80211_has_morefrags(fc);
2281 
2282 	/* start timer if queue currently empty */
2283 	if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) {
2284 		/*
2285 		 * If the TXQ is active, then set the timer, if not,
2286 		 * set the timer in remainder so that the timer will
2287 		 * be armed with the right value when the station will
2288 		 * wake up.
2289 		 */
2290 		if (!txq->frozen)
2291 			mod_timer(&txq->stuck_timer,
2292 				  jiffies + txq->wd_timeout);
2293 		else
2294 			txq->frozen_expiry_remainder = txq->wd_timeout;
2295 	}
2296 
2297 	/* Tell device the write index *just past* this latest filled TFD */
2298 	txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr);
2299 	if (!wait_write_ptr)
2300 		iwl_pcie_txq_inc_wr_ptr(trans, txq);
2301 
2302 	/*
2303 	 * At this point the frame is "transmitted" successfully
2304 	 * and we will get a TX status notification eventually.
2305 	 */
2306 	spin_unlock(&txq->lock);
2307 	return 0;
2308 out_err:
2309 	iwl_txq_gen1_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2310 	spin_unlock(&txq->lock);
2311 	return -1;
2312 }
2313 
2314 static void iwl_txq_gen1_inval_byte_cnt_tbl(struct iwl_trans *trans,
2315 					    struct iwl_txq *txq,
2316 					    int read_ptr)
2317 {
2318 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2319 	struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->txqs.scd_bc_tbls.addr;
2320 	int txq_id = txq->id;
2321 	u8 sta_id = 0;
2322 	__le16 bc_ent;
2323 	struct iwl_device_tx_cmd *dev_cmd = txq->entries[read_ptr].cmd;
2324 	struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2325 
2326 	WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
2327 
2328 	if (txq_id != trans_pcie->txqs.cmd.q_id)
2329 		sta_id = tx_cmd->sta_id;
2330 
2331 	bc_ent = cpu_to_le16(1 | (sta_id << 12));
2332 
2333 	scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
2334 
2335 	if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
2336 		scd_bc_tbl[txq_id].tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =
2337 			bc_ent;
2338 }
2339 
2340 /* Frees buffers until index _not_ inclusive */
2341 void iwl_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
2342 		      struct sk_buff_head *skbs, bool is_flush)
2343 {
2344 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2345 	struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
2346 	int tfd_num, read_ptr, last_to_free;
2347 	int txq_read_ptr, txq_write_ptr;
2348 
2349 	/* This function is not meant to release cmd queue*/
2350 	if (WARN_ON(txq_id == trans_pcie->txqs.cmd.q_id))
2351 		return;
2352 
2353 	if (WARN_ON(!txq))
2354 		return;
2355 
2356 	tfd_num = iwl_txq_get_cmd_index(txq, ssn);
2357 
2358 	spin_lock_bh(&txq->reclaim_lock);
2359 
2360 	spin_lock(&txq->lock);
2361 	txq_read_ptr = txq->read_ptr;
2362 	txq_write_ptr = txq->write_ptr;
2363 	spin_unlock(&txq->lock);
2364 
2365 	read_ptr = iwl_txq_get_cmd_index(txq, txq_read_ptr);
2366 
2367 	if (!test_bit(txq_id, trans_pcie->txqs.queue_used)) {
2368 		IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
2369 				    txq_id, ssn);
2370 		goto out;
2371 	}
2372 
2373 	if (read_ptr == tfd_num)
2374 		goto out;
2375 
2376 	IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d (%d) -> %d (%d)\n",
2377 			   txq_id, read_ptr, txq_read_ptr, tfd_num, ssn);
2378 
2379 	/* Since we free until index _not_ inclusive, the one before index is
2380 	 * the last we will free. This one must be used
2381 	 */
2382 	last_to_free = iwl_txq_dec_wrap(trans, tfd_num);
2383 
2384 	if (!iwl_txq_used(txq, last_to_free, txq_read_ptr, txq_write_ptr)) {
2385 		IWL_ERR(trans,
2386 			"%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
2387 			__func__, txq_id, last_to_free,
2388 			trans->trans_cfg->base_params->max_tfd_queue_size,
2389 			txq_write_ptr, txq_read_ptr);
2390 
2391 		iwl_op_mode_time_point(trans->op_mode,
2392 				       IWL_FW_INI_TIME_POINT_FAKE_TX,
2393 				       NULL);
2394 		goto out;
2395 	}
2396 
2397 	if (WARN_ON(!skb_queue_empty(skbs)))
2398 		goto out;
2399 
2400 	for (;
2401 	     read_ptr != tfd_num;
2402 	     txq_read_ptr = iwl_txq_inc_wrap(trans, txq_read_ptr),
2403 	     read_ptr = iwl_txq_get_cmd_index(txq, txq_read_ptr)) {
2404 		struct iwl_cmd_meta *cmd_meta = &txq->entries[read_ptr].meta;
2405 		struct sk_buff *skb = txq->entries[read_ptr].skb;
2406 
2407 		if (WARN_ONCE(!skb, "no SKB at %d (%d) on queue %d\n",
2408 			      read_ptr, txq_read_ptr, txq_id))
2409 			continue;
2410 
2411 		iwl_pcie_free_tso_pages(trans, skb, cmd_meta);
2412 
2413 		__skb_queue_tail(skbs, skb);
2414 
2415 		txq->entries[read_ptr].skb = NULL;
2416 
2417 		if (!trans->trans_cfg->gen2)
2418 			iwl_txq_gen1_inval_byte_cnt_tbl(trans, txq,
2419 							txq_read_ptr);
2420 
2421 		iwl_txq_free_tfd(trans, txq, txq_read_ptr);
2422 	}
2423 
2424 	spin_lock(&txq->lock);
2425 	txq->read_ptr = txq_read_ptr;
2426 
2427 	iwl_txq_progress(txq);
2428 
2429 	if (iwl_txq_space(trans, txq) > txq->low_mark &&
2430 	    test_bit(txq_id, trans_pcie->txqs.queue_stopped)) {
2431 		struct sk_buff_head overflow_skbs;
2432 		struct sk_buff *skb;
2433 
2434 		__skb_queue_head_init(&overflow_skbs);
2435 		skb_queue_splice_init(&txq->overflow_q,
2436 				      is_flush ? skbs : &overflow_skbs);
2437 
2438 		/*
2439 		 * We are going to transmit from the overflow queue.
2440 		 * Remember this state so that wait_for_txq_empty will know we
2441 		 * are adding more packets to the TFD queue. It cannot rely on
2442 		 * the state of &txq->overflow_q, as we just emptied it, but
2443 		 * haven't TXed the content yet.
2444 		 */
2445 		txq->overflow_tx = true;
2446 
2447 		/*
2448 		 * This is tricky: we are in reclaim path and are holding
2449 		 * reclaim_lock, so noone will try to access the txq data
2450 		 * from that path. We stopped tx, so we can't have tx as well.
2451 		 * Bottom line, we can unlock and re-lock later.
2452 		 */
2453 		spin_unlock(&txq->lock);
2454 
2455 		while ((skb = __skb_dequeue(&overflow_skbs))) {
2456 			struct iwl_device_tx_cmd *dev_cmd_ptr;
2457 
2458 			dev_cmd_ptr = *(void **)((u8 *)skb->cb +
2459 						 trans_pcie->txqs.dev_cmd_offs);
2460 
2461 			/*
2462 			 * Note that we can very well be overflowing again.
2463 			 * In that case, iwl_txq_space will be small again
2464 			 * and we won't wake mac80211's queue.
2465 			 */
2466 			iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id);
2467 		}
2468 
2469 		if (iwl_txq_space(trans, txq) > txq->low_mark)
2470 			iwl_trans_pcie_wake_queue(trans, txq);
2471 
2472 		spin_lock(&txq->lock);
2473 		txq->overflow_tx = false;
2474 	}
2475 
2476 	spin_unlock(&txq->lock);
2477 out:
2478 	spin_unlock_bh(&txq->reclaim_lock);
2479 }
2480 
2481 /* Set wr_ptr of specific device and txq  */
2482 void iwl_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr)
2483 {
2484 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2485 	struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
2486 
2487 	spin_lock_bh(&txq->lock);
2488 
2489 	txq->write_ptr = ptr;
2490 	txq->read_ptr = txq->write_ptr;
2491 
2492 	spin_unlock_bh(&txq->lock);
2493 }
2494 
2495 void iwl_pcie_freeze_txq_timer(struct iwl_trans *trans,
2496 			       unsigned long txqs, bool freeze)
2497 {
2498 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2499 	int queue;
2500 
2501 	for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2502 		struct iwl_txq *txq = trans_pcie->txqs.txq[queue];
2503 		unsigned long now;
2504 
2505 		spin_lock_bh(&txq->lock);
2506 
2507 		now = jiffies;
2508 
2509 		if (txq->frozen == freeze)
2510 			goto next_queue;
2511 
2512 		IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2513 				    freeze ? "Freezing" : "Waking", queue);
2514 
2515 		txq->frozen = freeze;
2516 
2517 		if (txq->read_ptr == txq->write_ptr)
2518 			goto next_queue;
2519 
2520 		if (freeze) {
2521 			if (unlikely(time_after(now,
2522 						txq->stuck_timer.expires))) {
2523 				/*
2524 				 * The timer should have fired, maybe it is
2525 				 * spinning right now on the lock.
2526 				 */
2527 				goto next_queue;
2528 			}
2529 			/* remember how long until the timer fires */
2530 			txq->frozen_expiry_remainder =
2531 				txq->stuck_timer.expires - now;
2532 			del_timer(&txq->stuck_timer);
2533 			goto next_queue;
2534 		}
2535 
2536 		/*
2537 		 * Wake a non-empty queue -> arm timer with the
2538 		 * remainder before it froze
2539 		 */
2540 		mod_timer(&txq->stuck_timer,
2541 			  now + txq->frozen_expiry_remainder);
2542 
2543 next_queue:
2544 		spin_unlock_bh(&txq->lock);
2545 	}
2546 }
2547 
2548 #define HOST_COMPLETE_TIMEOUT	(2 * HZ)
2549 
2550 static int iwl_trans_pcie_send_hcmd_sync(struct iwl_trans *trans,
2551 					 struct iwl_host_cmd *cmd)
2552 {
2553 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2554 	const char *cmd_str = iwl_get_cmd_string(trans, cmd->id);
2555 	struct iwl_txq *txq = trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id];
2556 	int cmd_idx;
2557 	int ret;
2558 
2559 	IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", cmd_str);
2560 
2561 	if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
2562 				  &trans->status),
2563 		 "Command %s: a command is already active!\n", cmd_str))
2564 		return -EIO;
2565 
2566 	IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", cmd_str);
2567 
2568 	if (trans->trans_cfg->gen2)
2569 		cmd_idx = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
2570 	else
2571 		cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
2572 
2573 	if (cmd_idx < 0) {
2574 		ret = cmd_idx;
2575 		clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
2576 		IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
2577 			cmd_str, ret);
2578 		return ret;
2579 	}
2580 
2581 	ret = wait_event_timeout(trans->wait_command_queue,
2582 				 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
2583 					   &trans->status),
2584 				 HOST_COMPLETE_TIMEOUT);
2585 	if (!ret) {
2586 		IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
2587 			cmd_str, jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
2588 
2589 		IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
2590 			txq->read_ptr, txq->write_ptr);
2591 
2592 		clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
2593 		IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
2594 			       cmd_str);
2595 		ret = -ETIMEDOUT;
2596 
2597 		iwl_trans_sync_nmi(trans);
2598 		goto cancel;
2599 	}
2600 
2601 	if (test_bit(STATUS_FW_ERROR, &trans->status)) {
2602 		if (!test_and_clear_bit(STATUS_SUPPRESS_CMD_ERROR_ONCE,
2603 					&trans->status)) {
2604 			IWL_ERR(trans, "FW error in SYNC CMD %s\n", cmd_str);
2605 			dump_stack();
2606 		}
2607 		ret = -EIO;
2608 		goto cancel;
2609 	}
2610 
2611 	if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
2612 	    test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
2613 		IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
2614 		ret = -ERFKILL;
2615 		goto cancel;
2616 	}
2617 
2618 	if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
2619 		IWL_ERR(trans, "Error: Response NULL in '%s'\n", cmd_str);
2620 		ret = -EIO;
2621 		goto cancel;
2622 	}
2623 
2624 	return 0;
2625 
2626 cancel:
2627 	if (cmd->flags & CMD_WANT_SKB) {
2628 		/*
2629 		 * Cancel the CMD_WANT_SKB flag for the cmd in the
2630 		 * TX cmd queue. Otherwise in case the cmd comes
2631 		 * in later, it will possibly set an invalid
2632 		 * address (cmd->meta.source).
2633 		 */
2634 		txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
2635 	}
2636 
2637 	if (cmd->resp_pkt) {
2638 		iwl_free_resp(cmd);
2639 		cmd->resp_pkt = NULL;
2640 	}
2641 
2642 	return ret;
2643 }
2644 
2645 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans,
2646 			     struct iwl_host_cmd *cmd)
2647 {
2648 	/* Make sure the NIC is still alive in the bus */
2649 	if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2650 		return -ENODEV;
2651 
2652 	if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
2653 	    test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
2654 		IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
2655 				  cmd->id);
2656 		return -ERFKILL;
2657 	}
2658 
2659 	if (unlikely(trans->system_pm_mode == IWL_PLAT_PM_MODE_D3 &&
2660 		     !(cmd->flags & CMD_SEND_IN_D3))) {
2661 		IWL_DEBUG_WOWLAN(trans, "Dropping CMD 0x%x: D3\n", cmd->id);
2662 		return -EHOSTDOWN;
2663 	}
2664 
2665 	if (cmd->flags & CMD_ASYNC) {
2666 		int ret;
2667 
2668 		/* An asynchronous command can not expect an SKB to be set. */
2669 		if (WARN_ON(cmd->flags & CMD_WANT_SKB))
2670 			return -EINVAL;
2671 
2672 		if (trans->trans_cfg->gen2)
2673 			ret = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
2674 		else
2675 			ret = iwl_pcie_enqueue_hcmd(trans, cmd);
2676 
2677 		if (ret < 0) {
2678 			IWL_ERR(trans,
2679 				"Error sending %s: enqueue_hcmd failed: %d\n",
2680 				iwl_get_cmd_string(trans, cmd->id), ret);
2681 			return ret;
2682 		}
2683 		return 0;
2684 	}
2685 
2686 	return iwl_trans_pcie_send_hcmd_sync(trans, cmd);
2687 }
2688 IWL_EXPORT_SYMBOL(iwl_trans_pcie_send_hcmd);
2689