1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
6 */
7 #include <linux/devcoredump.h>
8 #include "iwl-drv.h"
9 #include "runtime.h"
10 #include "dbg.h"
11 #include "debugfs.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
15 #include "iwl-fh.h"
16 /**
17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump
18 *
19 * @fwrt_ptr: pointer to the buffer coming from fwrt
20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the
21 * transport's data.
22 * @fwrt_len: length of the valid data in fwrt_ptr
23 */
24 struct iwl_fw_dump_ptrs {
25 struct iwl_trans_dump_data *trans_ptr;
26 void *fwrt_ptr;
27 u32 fwrt_len;
28 };
29
30 #define RADIO_REG_MAX_READ 0x2ad
iwl_read_radio_regs(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)31 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt,
32 struct iwl_fw_error_dump_data **dump_data)
33 {
34 u8 *pos = (void *)(*dump_data)->data;
35 int i;
36
37 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n");
38
39 if (!iwl_trans_grab_nic_access(fwrt->trans))
40 return;
41
42 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
43 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
44
45 for (i = 0; i < RADIO_REG_MAX_READ; i++) {
46 u32 rd_cmd = RADIO_RSP_RD_CMD;
47
48 rd_cmd |= i << RADIO_RSP_ADDR_POS;
49 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd);
50 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT);
51
52 pos++;
53 }
54
55 *dump_data = iwl_fw_error_next_data(*dump_data);
56
57 iwl_trans_release_nic_access(fwrt->trans);
58 }
59
iwl_fwrt_dump_rxf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,int size,u32 offset,int fifo_num)60 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt,
61 struct iwl_fw_error_dump_data **dump_data,
62 int size, u32 offset, int fifo_num)
63 {
64 struct iwl_fw_error_dump_fifo *fifo_hdr;
65 u32 *fifo_data;
66 u32 fifo_len;
67 int i;
68
69 fifo_hdr = (void *)(*dump_data)->data;
70 fifo_data = (void *)fifo_hdr->data;
71 fifo_len = size;
72
73 /* No need to try to read the data if the length is 0 */
74 if (fifo_len == 0)
75 return;
76
77 /* Add a TLV for the RXF */
78 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
79 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
80
81 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
82 fifo_hdr->available_bytes =
83 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
84 RXF_RD_D_SPACE + offset));
85 fifo_hdr->wr_ptr =
86 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
87 RXF_RD_WR_PTR + offset));
88 fifo_hdr->rd_ptr =
89 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
90 RXF_RD_RD_PTR + offset));
91 fifo_hdr->fence_ptr =
92 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
93 RXF_RD_FENCE_PTR + offset));
94 fifo_hdr->fence_mode =
95 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
96 RXF_SET_FENCE_MODE + offset));
97
98 /* Lock fence */
99 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
100 /* Set fence pointer to the same place like WR pointer */
101 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
102 /* Set fence offset */
103 iwl_trans_write_prph(fwrt->trans,
104 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
105
106 /* Read FIFO */
107 fifo_len /= sizeof(u32); /* Size in DWORDS */
108 for (i = 0; i < fifo_len; i++)
109 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
110 RXF_FIFO_RD_FENCE_INC +
111 offset);
112 *dump_data = iwl_fw_error_next_data(*dump_data);
113 }
114
iwl_fwrt_dump_txf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,int size,u32 offset,int fifo_num)115 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt,
116 struct iwl_fw_error_dump_data **dump_data,
117 int size, u32 offset, int fifo_num)
118 {
119 struct iwl_fw_error_dump_fifo *fifo_hdr;
120 u32 *fifo_data;
121 u32 fifo_len;
122 int i;
123
124 fifo_hdr = (void *)(*dump_data)->data;
125 fifo_data = (void *)fifo_hdr->data;
126 fifo_len = size;
127
128 /* No need to try to read the data if the length is 0 */
129 if (fifo_len == 0)
130 return;
131
132 /* Add a TLV for the FIFO */
133 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
134 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
135
136 fifo_hdr->fifo_num = cpu_to_le32(fifo_num);
137 fifo_hdr->available_bytes =
138 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
139 TXF_FIFO_ITEM_CNT + offset));
140 fifo_hdr->wr_ptr =
141 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
142 TXF_WR_PTR + offset));
143 fifo_hdr->rd_ptr =
144 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
145 TXF_RD_PTR + offset));
146 fifo_hdr->fence_ptr =
147 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
148 TXF_FENCE_PTR + offset));
149 fifo_hdr->fence_mode =
150 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
151 TXF_LOCK_FENCE + offset));
152
153 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
154 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset,
155 TXF_WR_PTR + offset);
156
157 /* Dummy-read to advance the read pointer to the head */
158 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset);
159
160 /* Read FIFO */
161 for (i = 0; i < fifo_len / sizeof(u32); i++)
162 fifo_data[i] = iwl_trans_read_prph(fwrt->trans,
163 TXF_READ_MODIFY_DATA +
164 offset);
165
166 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
167 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
168 fifo_data, fifo_len);
169
170 *dump_data = iwl_fw_error_next_data(*dump_data);
171 }
172
iwl_fw_dump_rxf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)173 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt,
174 struct iwl_fw_error_dump_data **dump_data)
175 {
176 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
177
178 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n");
179
180 if (!iwl_trans_grab_nic_access(fwrt->trans))
181 return;
182
183 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) {
184 /* Pull RXF1 */
185 iwl_fwrt_dump_rxf(fwrt, dump_data,
186 cfg->lmac[0].rxfifo1_size, 0, 0);
187 /* Pull RXF2 */
188 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size,
189 RXF_DIFF_FROM_PREV +
190 fwrt->trans->mac_cfg->umac_prph_offset, 1);
191 /* Pull LMAC2 RXF1 */
192 if (fwrt->smem_cfg.num_lmacs > 1)
193 iwl_fwrt_dump_rxf(fwrt, dump_data,
194 cfg->lmac[1].rxfifo1_size,
195 LMAC2_PRPH_OFFSET, 2);
196 }
197
198 iwl_trans_release_nic_access(fwrt->trans);
199 }
200
iwl_fw_dump_txf(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data)201 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt,
202 struct iwl_fw_error_dump_data **dump_data)
203 {
204 struct iwl_fw_error_dump_fifo *fifo_hdr;
205 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
206 u32 *fifo_data;
207 u32 fifo_len;
208 int i, j;
209
210 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n");
211
212 if (!iwl_trans_grab_nic_access(fwrt->trans))
213 return;
214
215 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) {
216 /* Pull TXF data from LMAC1 */
217 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
218 /* Mark the number of TXF we're pulling now */
219 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i);
220 iwl_fwrt_dump_txf(fwrt, dump_data,
221 cfg->lmac[0].txfifo_size[i], 0, i);
222 }
223
224 /* Pull TXF data from LMAC2 */
225 if (fwrt->smem_cfg.num_lmacs > 1) {
226 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
227 i++) {
228 /* Mark the number of TXF we're pulling now */
229 iwl_trans_write_prph(fwrt->trans,
230 TXF_LARC_NUM +
231 LMAC2_PRPH_OFFSET, i);
232 iwl_fwrt_dump_txf(fwrt, dump_data,
233 cfg->lmac[1].txfifo_size[i],
234 LMAC2_PRPH_OFFSET,
235 i + cfg->num_txfifo_entries);
236 }
237 }
238 }
239
240 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
241 fw_has_capa(&fwrt->fw->ucode_capa,
242 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
243 /* Pull UMAC internal TXF data from all TXFs */
244 for (i = 0;
245 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size);
246 i++) {
247 fifo_hdr = (void *)(*dump_data)->data;
248 fifo_data = (void *)fifo_hdr->data;
249 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i];
250
251 /* No need to try to read the data if the length is 0 */
252 if (fifo_len == 0)
253 continue;
254
255 /* Add a TLV for the internal FIFOs */
256 (*dump_data)->type =
257 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
258 (*dump_data)->len =
259 cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
260
261 fifo_hdr->fifo_num = cpu_to_le32(i);
262
263 /* Mark the number of TXF we're pulling now */
264 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i +
265 fwrt->smem_cfg.num_txfifo_entries);
266
267 fifo_hdr->available_bytes =
268 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
269 TXF_CPU2_FIFO_ITEM_CNT));
270 fifo_hdr->wr_ptr =
271 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
272 TXF_CPU2_WR_PTR));
273 fifo_hdr->rd_ptr =
274 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
275 TXF_CPU2_RD_PTR));
276 fifo_hdr->fence_ptr =
277 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
278 TXF_CPU2_FENCE_PTR));
279 fifo_hdr->fence_mode =
280 cpu_to_le32(iwl_trans_read_prph(fwrt->trans,
281 TXF_CPU2_LOCK_FENCE));
282
283 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
284 iwl_trans_write_prph(fwrt->trans,
285 TXF_CPU2_READ_MODIFY_ADDR,
286 TXF_CPU2_WR_PTR);
287
288 /* Dummy-read to advance the read pointer to head */
289 iwl_trans_read_prph(fwrt->trans,
290 TXF_CPU2_READ_MODIFY_DATA);
291
292 /* Read FIFO */
293 fifo_len /= sizeof(u32); /* Size in DWORDS */
294 for (j = 0; j < fifo_len; j++)
295 fifo_data[j] =
296 iwl_trans_read_prph(fwrt->trans,
297 TXF_CPU2_READ_MODIFY_DATA);
298 *dump_data = iwl_fw_error_next_data(*dump_data);
299 }
300 }
301
302 iwl_trans_release_nic_access(fwrt->trans);
303 }
304
305 struct iwl_prph_range {
306 u32 start, end;
307 };
308
309 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = {
310 { .start = 0x00a00000, .end = 0x00a00000 },
311 { .start = 0x00a0000c, .end = 0x00a00024 },
312 { .start = 0x00a0002c, .end = 0x00a0003c },
313 { .start = 0x00a00410, .end = 0x00a00418 },
314 { .start = 0x00a00420, .end = 0x00a00420 },
315 { .start = 0x00a00428, .end = 0x00a00428 },
316 { .start = 0x00a00430, .end = 0x00a0043c },
317 { .start = 0x00a00444, .end = 0x00a00444 },
318 { .start = 0x00a004c0, .end = 0x00a004cc },
319 { .start = 0x00a004d8, .end = 0x00a004d8 },
320 { .start = 0x00a004e0, .end = 0x00a004f0 },
321 { .start = 0x00a00840, .end = 0x00a00840 },
322 { .start = 0x00a00850, .end = 0x00a00858 },
323 { .start = 0x00a01004, .end = 0x00a01008 },
324 { .start = 0x00a01010, .end = 0x00a01010 },
325 { .start = 0x00a01018, .end = 0x00a01018 },
326 { .start = 0x00a01024, .end = 0x00a01024 },
327 { .start = 0x00a0102c, .end = 0x00a01034 },
328 { .start = 0x00a0103c, .end = 0x00a01040 },
329 { .start = 0x00a01048, .end = 0x00a01094 },
330 { .start = 0x00a01c00, .end = 0x00a01c20 },
331 { .start = 0x00a01c58, .end = 0x00a01c58 },
332 { .start = 0x00a01c7c, .end = 0x00a01c7c },
333 { .start = 0x00a01c28, .end = 0x00a01c54 },
334 { .start = 0x00a01c5c, .end = 0x00a01c5c },
335 { .start = 0x00a01c60, .end = 0x00a01cdc },
336 { .start = 0x00a01ce0, .end = 0x00a01d0c },
337 { .start = 0x00a01d18, .end = 0x00a01d20 },
338 { .start = 0x00a01d2c, .end = 0x00a01d30 },
339 { .start = 0x00a01d40, .end = 0x00a01d5c },
340 { .start = 0x00a01d80, .end = 0x00a01d80 },
341 { .start = 0x00a01d98, .end = 0x00a01d9c },
342 { .start = 0x00a01da8, .end = 0x00a01da8 },
343 { .start = 0x00a01db8, .end = 0x00a01df4 },
344 { .start = 0x00a01dc0, .end = 0x00a01dfc },
345 { .start = 0x00a01e00, .end = 0x00a01e2c },
346 { .start = 0x00a01e40, .end = 0x00a01e60 },
347 { .start = 0x00a01e68, .end = 0x00a01e6c },
348 { .start = 0x00a01e74, .end = 0x00a01e74 },
349 { .start = 0x00a01e84, .end = 0x00a01e90 },
350 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
351 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
352 { .start = 0x00a01f00, .end = 0x00a01f1c },
353 { .start = 0x00a01f44, .end = 0x00a01ffc },
354 { .start = 0x00a02000, .end = 0x00a02048 },
355 { .start = 0x00a02068, .end = 0x00a020f0 },
356 { .start = 0x00a02100, .end = 0x00a02118 },
357 { .start = 0x00a02140, .end = 0x00a0214c },
358 { .start = 0x00a02168, .end = 0x00a0218c },
359 { .start = 0x00a021c0, .end = 0x00a021c0 },
360 { .start = 0x00a02400, .end = 0x00a02410 },
361 { .start = 0x00a02418, .end = 0x00a02420 },
362 { .start = 0x00a02428, .end = 0x00a0242c },
363 { .start = 0x00a02434, .end = 0x00a02434 },
364 { .start = 0x00a02440, .end = 0x00a02460 },
365 { .start = 0x00a02468, .end = 0x00a024b0 },
366 { .start = 0x00a024c8, .end = 0x00a024cc },
367 { .start = 0x00a02500, .end = 0x00a02504 },
368 { .start = 0x00a0250c, .end = 0x00a02510 },
369 { .start = 0x00a02540, .end = 0x00a02554 },
370 { .start = 0x00a02580, .end = 0x00a025f4 },
371 { .start = 0x00a02600, .end = 0x00a0260c },
372 { .start = 0x00a02648, .end = 0x00a02650 },
373 { .start = 0x00a02680, .end = 0x00a02680 },
374 { .start = 0x00a026c0, .end = 0x00a026d0 },
375 { .start = 0x00a02700, .end = 0x00a0270c },
376 { .start = 0x00a02804, .end = 0x00a02804 },
377 { .start = 0x00a02818, .end = 0x00a0281c },
378 { .start = 0x00a02c00, .end = 0x00a02db4 },
379 { .start = 0x00a02df4, .end = 0x00a02fb0 },
380 { .start = 0x00a03000, .end = 0x00a03014 },
381 { .start = 0x00a0301c, .end = 0x00a0302c },
382 { .start = 0x00a03034, .end = 0x00a03038 },
383 { .start = 0x00a03040, .end = 0x00a03048 },
384 { .start = 0x00a03060, .end = 0x00a03068 },
385 { .start = 0x00a03070, .end = 0x00a03074 },
386 { .start = 0x00a0307c, .end = 0x00a0307c },
387 { .start = 0x00a03080, .end = 0x00a03084 },
388 { .start = 0x00a0308c, .end = 0x00a03090 },
389 { .start = 0x00a03098, .end = 0x00a03098 },
390 { .start = 0x00a030a0, .end = 0x00a030a0 },
391 { .start = 0x00a030a8, .end = 0x00a030b4 },
392 { .start = 0x00a030bc, .end = 0x00a030bc },
393 { .start = 0x00a030c0, .end = 0x00a0312c },
394 { .start = 0x00a03c00, .end = 0x00a03c5c },
395 { .start = 0x00a04400, .end = 0x00a04454 },
396 { .start = 0x00a04460, .end = 0x00a04474 },
397 { .start = 0x00a044c0, .end = 0x00a044ec },
398 { .start = 0x00a04500, .end = 0x00a04504 },
399 { .start = 0x00a04510, .end = 0x00a04538 },
400 { .start = 0x00a04540, .end = 0x00a04548 },
401 { .start = 0x00a04560, .end = 0x00a0457c },
402 { .start = 0x00a04590, .end = 0x00a04598 },
403 { .start = 0x00a045c0, .end = 0x00a045f4 },
404 };
405
406 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = {
407 { .start = 0x00a05c00, .end = 0x00a05c18 },
408 { .start = 0x00a05400, .end = 0x00a056e8 },
409 { .start = 0x00a08000, .end = 0x00a098bc },
410 { .start = 0x00a02400, .end = 0x00a02758 },
411 { .start = 0x00a04764, .end = 0x00a0476c },
412 { .start = 0x00a04770, .end = 0x00a04774 },
413 { .start = 0x00a04620, .end = 0x00a04624 },
414 };
415
416 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = {
417 { .start = 0x00a00000, .end = 0x00a00000 },
418 { .start = 0x00a0000c, .end = 0x00a00024 },
419 { .start = 0x00a0002c, .end = 0x00a00034 },
420 { .start = 0x00a0003c, .end = 0x00a0003c },
421 { .start = 0x00a00410, .end = 0x00a00418 },
422 { .start = 0x00a00420, .end = 0x00a00420 },
423 { .start = 0x00a00428, .end = 0x00a00428 },
424 { .start = 0x00a00430, .end = 0x00a0043c },
425 { .start = 0x00a00444, .end = 0x00a00444 },
426 { .start = 0x00a00840, .end = 0x00a00840 },
427 { .start = 0x00a00850, .end = 0x00a00858 },
428 { .start = 0x00a01004, .end = 0x00a01008 },
429 { .start = 0x00a01010, .end = 0x00a01010 },
430 { .start = 0x00a01018, .end = 0x00a01018 },
431 { .start = 0x00a01024, .end = 0x00a01024 },
432 { .start = 0x00a0102c, .end = 0x00a01034 },
433 { .start = 0x00a0103c, .end = 0x00a01040 },
434 { .start = 0x00a01048, .end = 0x00a01050 },
435 { .start = 0x00a01058, .end = 0x00a01058 },
436 { .start = 0x00a01060, .end = 0x00a01070 },
437 { .start = 0x00a0108c, .end = 0x00a0108c },
438 { .start = 0x00a01c20, .end = 0x00a01c28 },
439 { .start = 0x00a01d10, .end = 0x00a01d10 },
440 { .start = 0x00a01e28, .end = 0x00a01e2c },
441 { .start = 0x00a01e60, .end = 0x00a01e60 },
442 { .start = 0x00a01e80, .end = 0x00a01e80 },
443 { .start = 0x00a01ea0, .end = 0x00a01ea0 },
444 { .start = 0x00a02000, .end = 0x00a0201c },
445 { .start = 0x00a02024, .end = 0x00a02024 },
446 { .start = 0x00a02040, .end = 0x00a02048 },
447 { .start = 0x00a020c0, .end = 0x00a020e0 },
448 { .start = 0x00a02400, .end = 0x00a02404 },
449 { .start = 0x00a0240c, .end = 0x00a02414 },
450 { .start = 0x00a0241c, .end = 0x00a0243c },
451 { .start = 0x00a02448, .end = 0x00a024bc },
452 { .start = 0x00a024c4, .end = 0x00a024cc },
453 { .start = 0x00a02508, .end = 0x00a02508 },
454 { .start = 0x00a02510, .end = 0x00a02514 },
455 { .start = 0x00a0251c, .end = 0x00a0251c },
456 { .start = 0x00a0252c, .end = 0x00a0255c },
457 { .start = 0x00a02564, .end = 0x00a025a0 },
458 { .start = 0x00a025a8, .end = 0x00a025b4 },
459 { .start = 0x00a025c0, .end = 0x00a025c0 },
460 { .start = 0x00a025e8, .end = 0x00a025f4 },
461 { .start = 0x00a02c08, .end = 0x00a02c18 },
462 { .start = 0x00a02c2c, .end = 0x00a02c38 },
463 { .start = 0x00a02c68, .end = 0x00a02c78 },
464 { .start = 0x00a03000, .end = 0x00a03000 },
465 { .start = 0x00a03010, .end = 0x00a03014 },
466 { .start = 0x00a0301c, .end = 0x00a0302c },
467 { .start = 0x00a03034, .end = 0x00a03038 },
468 { .start = 0x00a03040, .end = 0x00a03044 },
469 { .start = 0x00a03060, .end = 0x00a03068 },
470 { .start = 0x00a03070, .end = 0x00a03070 },
471 { .start = 0x00a0307c, .end = 0x00a03084 },
472 { .start = 0x00a0308c, .end = 0x00a03090 },
473 { .start = 0x00a03098, .end = 0x00a03098 },
474 { .start = 0x00a030a0, .end = 0x00a030a0 },
475 { .start = 0x00a030a8, .end = 0x00a030b4 },
476 { .start = 0x00a030bc, .end = 0x00a030c0 },
477 { .start = 0x00a030c8, .end = 0x00a030f4 },
478 { .start = 0x00a03100, .end = 0x00a0312c },
479 { .start = 0x00a03c00, .end = 0x00a03c5c },
480 { .start = 0x00a04400, .end = 0x00a04454 },
481 { .start = 0x00a04460, .end = 0x00a04474 },
482 { .start = 0x00a044c0, .end = 0x00a044ec },
483 { .start = 0x00a04500, .end = 0x00a04504 },
484 { .start = 0x00a04510, .end = 0x00a04538 },
485 { .start = 0x00a04540, .end = 0x00a04548 },
486 { .start = 0x00a04560, .end = 0x00a04560 },
487 { .start = 0x00a04570, .end = 0x00a0457c },
488 { .start = 0x00a04590, .end = 0x00a04590 },
489 { .start = 0x00a04598, .end = 0x00a04598 },
490 { .start = 0x00a045c0, .end = 0x00a045f4 },
491 { .start = 0x00a05c18, .end = 0x00a05c1c },
492 { .start = 0x00a0c000, .end = 0x00a0c018 },
493 { .start = 0x00a0c020, .end = 0x00a0c028 },
494 { .start = 0x00a0c038, .end = 0x00a0c094 },
495 { .start = 0x00a0c0c0, .end = 0x00a0c104 },
496 { .start = 0x00a0c10c, .end = 0x00a0c118 },
497 { .start = 0x00a0c150, .end = 0x00a0c174 },
498 { .start = 0x00a0c17c, .end = 0x00a0c188 },
499 { .start = 0x00a0c190, .end = 0x00a0c198 },
500 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 },
501 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 },
502 };
503
504 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = {
505 { .start = 0x00d03c00, .end = 0x00d03c64 },
506 { .start = 0x00d05c18, .end = 0x00d05c1c },
507 { .start = 0x00d0c000, .end = 0x00d0c174 },
508 };
509
iwl_read_prph_block(struct iwl_trans * trans,u32 start,u32 len_bytes,__le32 * data)510 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start,
511 u32 len_bytes, __le32 *data)
512 {
513 u32 i;
514
515 for (i = 0; i < len_bytes; i += 4)
516 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i));
517 }
518
iwl_dump_prph(struct iwl_fw_runtime * fwrt,const struct iwl_prph_range * iwl_prph_dump_addr,u32 range_len,void * ptr)519 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt,
520 const struct iwl_prph_range *iwl_prph_dump_addr,
521 u32 range_len, void *ptr)
522 {
523 struct iwl_fw_error_dump_prph *prph;
524 struct iwl_trans *trans = fwrt->trans;
525 struct iwl_fw_error_dump_data **data =
526 (struct iwl_fw_error_dump_data **)ptr;
527 u32 i;
528
529 if (!data)
530 return;
531
532 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n");
533
534 if (!iwl_trans_grab_nic_access(trans))
535 return;
536
537 for (i = 0; i < range_len; i++) {
538 /* The range includes both boundaries */
539 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
540 iwl_prph_dump_addr[i].start + 4;
541
542 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
543 (*data)->len = cpu_to_le32(sizeof(*prph) +
544 num_bytes_in_chunk);
545 prph = (void *)(*data)->data;
546 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
547
548 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start,
549 /* our range is inclusive, hence + 4 */
550 iwl_prph_dump_addr[i].end -
551 iwl_prph_dump_addr[i].start + 4,
552 (void *)prph->data);
553
554 *data = iwl_fw_error_next_data(*data);
555 }
556
557 iwl_trans_release_nic_access(trans);
558 }
559
560 /*
561 * alloc_sgtable - allocates (chained) scatterlist in the given size,
562 * fills it with pages and returns it
563 * @size: the size (in bytes) of the table
564 */
alloc_sgtable(ssize_t size)565 static struct scatterlist *alloc_sgtable(ssize_t size)
566 {
567 struct scatterlist *result = NULL, *prev;
568 int nents, i, n_prev;
569
570 nents = DIV_ROUND_UP(size, PAGE_SIZE);
571
572 #define N_ENTRIES_PER_PAGE (PAGE_SIZE / sizeof(*result))
573 /*
574 * We need an additional entry for table chaining,
575 * this ensures the loop can finish i.e. we can
576 * fit at least two entries per page (obviously,
577 * many more really fit.)
578 */
579 BUILD_BUG_ON(N_ENTRIES_PER_PAGE < 2);
580
581 while (nents > 0) {
582 struct scatterlist *new, *iter;
583 int n_fill, n_alloc;
584
585 if (nents <= N_ENTRIES_PER_PAGE) {
586 /* last needed table */
587 n_fill = nents;
588 n_alloc = nents;
589 nents = 0;
590 } else {
591 /* fill a page with entries */
592 n_alloc = N_ENTRIES_PER_PAGE;
593 /* reserve one for chaining */
594 n_fill = n_alloc - 1;
595 nents -= n_fill;
596 }
597
598 new = kcalloc(n_alloc, sizeof(*new), GFP_KERNEL);
599 if (!new) {
600 if (result)
601 _devcd_free_sgtable(result);
602 return NULL;
603 }
604 sg_init_table(new, n_alloc);
605
606 if (!result)
607 result = new;
608 else
609 sg_chain(prev, n_prev, new);
610 prev = new;
611 n_prev = n_alloc;
612
613 for_each_sg(new, iter, n_fill, i) {
614 struct page *new_page = alloc_page(GFP_KERNEL);
615
616 if (!new_page) {
617 _devcd_free_sgtable(result);
618 return NULL;
619 }
620
621 sg_set_page(iter, new_page, PAGE_SIZE, 0);
622 }
623 }
624
625 return result;
626 }
627
iwl_fw_get_prph_len(struct iwl_fw_runtime * fwrt,const struct iwl_prph_range * iwl_prph_dump_addr,u32 range_len,void * ptr)628 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt,
629 const struct iwl_prph_range *iwl_prph_dump_addr,
630 u32 range_len, void *ptr)
631 {
632 u32 *prph_len = (u32 *)ptr;
633 int i, num_bytes_in_chunk;
634
635 if (!prph_len)
636 return;
637
638 for (i = 0; i < range_len; i++) {
639 /* The range includes both boundaries */
640 num_bytes_in_chunk =
641 iwl_prph_dump_addr[i].end -
642 iwl_prph_dump_addr[i].start + 4;
643
644 *prph_len += sizeof(struct iwl_fw_error_dump_data) +
645 sizeof(struct iwl_fw_error_dump_prph) +
646 num_bytes_in_chunk;
647 }
648 }
649
iwl_fw_prph_handler(struct iwl_fw_runtime * fwrt,void * ptr,void (* handler)(struct iwl_fw_runtime *,const struct iwl_prph_range *,u32,void *))650 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr,
651 void (*handler)(struct iwl_fw_runtime *,
652 const struct iwl_prph_range *,
653 u32, void *))
654 {
655 u32 range_len;
656
657 if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
658 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210);
659 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr);
660 } else if (fwrt->trans->mac_cfg->device_family >=
661 IWL_DEVICE_FAMILY_22000) {
662 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000);
663 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr);
664 } else {
665 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm);
666 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr);
667
668 if (fwrt->trans->mac_cfg->mq_rx_supported) {
669 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000);
670 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr);
671 }
672 }
673 }
674
iwl_fw_dump_mem(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** dump_data,u32 len,u32 ofs,u32 type)675 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
676 struct iwl_fw_error_dump_data **dump_data,
677 u32 len, u32 ofs, u32 type)
678 {
679 struct iwl_fw_error_dump_mem *dump_mem;
680
681 if (!len)
682 return;
683
684 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
685 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem));
686 dump_mem = (void *)(*dump_data)->data;
687 dump_mem->type = cpu_to_le32(type);
688 dump_mem->offset = cpu_to_le32(ofs);
689 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len);
690 *dump_data = iwl_fw_error_next_data(*dump_data);
691
692 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
693 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs,
694 dump_mem->data, len);
695
696 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type);
697 }
698
699 #define ADD_LEN(len, item_len, const_len) \
700 do {size_t item = item_len; len += (!!item) * const_len + item; } \
701 while (0)
702
iwl_fw_rxf_len(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_shared_mem_cfg * mem_cfg)703 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt,
704 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
705 {
706 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
707 sizeof(struct iwl_fw_error_dump_fifo);
708 u32 fifo_len = 0;
709 int i;
710
711 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF))
712 return 0;
713
714 /* Count RXF2 size */
715 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len);
716
717 /* Count RXF1 sizes */
718 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
719 mem_cfg->num_lmacs = MAX_NUM_LMAC;
720
721 for (i = 0; i < mem_cfg->num_lmacs; i++)
722 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len);
723
724 return fifo_len;
725 }
726
iwl_fw_txf_len(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_shared_mem_cfg * mem_cfg)727 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt,
728 struct iwl_fwrt_shared_mem_cfg *mem_cfg)
729 {
730 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) +
731 sizeof(struct iwl_fw_error_dump_fifo);
732 u32 fifo_len = 0;
733 int i;
734
735 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF))
736 goto dump_internal_txf;
737
738 /* Count TXF sizes */
739 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC))
740 mem_cfg->num_lmacs = MAX_NUM_LMAC;
741
742 for (i = 0; i < mem_cfg->num_lmacs; i++) {
743 int j;
744
745 for (j = 0; j < mem_cfg->num_txfifo_entries; j++)
746 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j],
747 hdr_len);
748 }
749
750 dump_internal_txf:
751 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
752 fw_has_capa(&fwrt->fw->ucode_capa,
753 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)))
754 goto out;
755
756 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)
757 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len);
758
759 out:
760 return fifo_len;
761 }
762
iwl_dump_paging(struct iwl_fw_runtime * fwrt,struct iwl_fw_error_dump_data ** data)763 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt,
764 struct iwl_fw_error_dump_data **data)
765 {
766 int i;
767
768 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n");
769 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) {
770 struct iwl_fw_error_dump_paging *paging;
771 struct page *pages =
772 fwrt->fw_paging_db[i].fw_paging_block;
773 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys;
774
775 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
776 (*data)->len = cpu_to_le32(sizeof(*paging) +
777 PAGING_BLOCK_SIZE);
778 paging = (void *)(*data)->data;
779 paging->index = cpu_to_le32(i);
780 dma_sync_single_for_cpu(fwrt->trans->dev, addr,
781 PAGING_BLOCK_SIZE,
782 DMA_BIDIRECTIONAL);
783 memcpy(paging->data, page_address(pages),
784 PAGING_BLOCK_SIZE);
785 dma_sync_single_for_device(fwrt->trans->dev, addr,
786 PAGING_BLOCK_SIZE,
787 DMA_BIDIRECTIONAL);
788 (*data) = iwl_fw_error_next_data(*data);
789
790 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
791 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx,
792 fwrt->fw_paging_db[i].fw_offs,
793 paging->data,
794 PAGING_BLOCK_SIZE);
795 }
796 }
797
798 static struct iwl_fw_error_dump_file *
iwl_fw_error_dump_file(struct iwl_fw_runtime * fwrt,struct iwl_fw_dump_ptrs * fw_error_dump,struct iwl_fwrt_dump_data * data)799 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt,
800 struct iwl_fw_dump_ptrs *fw_error_dump,
801 struct iwl_fwrt_dump_data *data)
802 {
803 struct iwl_fw_error_dump_file *dump_file;
804 struct iwl_fw_error_dump_data *dump_data;
805 struct iwl_fw_error_dump_info *dump_info;
806 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg;
807 struct iwl_fw_error_dump_trigger_desc *dump_trig;
808 u32 sram_len, sram_ofs;
809 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv;
810 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg;
811 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;
812 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->mac_cfg->base->smem_len;
813 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ?
814 0 : fwrt->trans->cfg->dccm2_len;
815 int i;
816
817 /* SRAM - include stack CCM if driver knows the values for it */
818 if (!fwrt->trans->cfg->dccm_offset ||
819 !fwrt->trans->cfg->dccm_len) {
820 const struct fw_img *img;
821
822 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX)
823 return NULL;
824 img = &fwrt->fw->img[fwrt->cur_fw_img];
825 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
826 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
827 } else {
828 sram_ofs = fwrt->trans->cfg->dccm_offset;
829 sram_len = fwrt->trans->cfg->dccm_len;
830 }
831
832 /* reading RXF/TXF sizes */
833 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) {
834 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg);
835 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg);
836
837 /* Make room for PRPH registers */
838 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH))
839 iwl_fw_prph_handler(fwrt, &prph_len,
840 iwl_fw_get_prph_len);
841
842 if (fwrt->trans->mac_cfg->device_family ==
843 IWL_DEVICE_FAMILY_7000 &&
844 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG))
845 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
846 }
847
848 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len;
849
850 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO))
851 file_len += sizeof(*dump_data) + sizeof(*dump_info);
852 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG))
853 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg);
854
855 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
856 size_t hdr_len = sizeof(*dump_data) +
857 sizeof(struct iwl_fw_error_dump_mem);
858
859 /* Dump SRAM only if no mem_tlvs */
860 if (!fwrt->fw->dbg.n_mem_tlv)
861 ADD_LEN(file_len, sram_len, hdr_len);
862
863 /* Make room for all mem types that exist */
864 ADD_LEN(file_len, smem_len, hdr_len);
865 ADD_LEN(file_len, sram2_len, hdr_len);
866
867 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)
868 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len);
869 }
870
871 /* Make room for fw's virtual image pages, if it exists */
872 if (iwl_fw_dbg_is_paging_enabled(fwrt))
873 file_len += fwrt->num_of_paging_blk *
874 (sizeof(*dump_data) +
875 sizeof(struct iwl_fw_error_dump_paging) +
876 PAGING_BLOCK_SIZE);
877
878 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
879 file_len += sizeof(*dump_data) +
880 fwrt->trans->mac_cfg->base->d3_debug_data_length * 2;
881 }
882
883 /* If we only want a monitor dump, reset the file length */
884 if (data->monitor_only) {
885 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 +
886 sizeof(*dump_info) + sizeof(*dump_smem_cfg);
887 }
888
889 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
890 data->desc)
891 file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
892 data->desc->len;
893
894 dump_file = vzalloc(file_len);
895 if (!dump_file)
896 return NULL;
897
898 fw_error_dump->fwrt_ptr = dump_file;
899
900 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
901 dump_data = (void *)dump_file->data;
902
903 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
904 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
905 dump_data->len = cpu_to_le32(sizeof(*dump_info));
906 dump_info = (void *)dump_data->data;
907 dump_info->hw_type =
908 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->info.hw_rev));
909 dump_info->hw_step =
910 cpu_to_le32(fwrt->trans->info.hw_rev_step);
911 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable,
912 sizeof(dump_info->fw_human_readable));
913 strscpy_pad(dump_info->dev_human_readable,
914 fwrt->trans->info.name,
915 sizeof(dump_info->dev_human_readable));
916 strscpy_pad(dump_info->bus_human_readable, fwrt->dev->bus->name,
917 sizeof(dump_info->bus_human_readable));
918 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs;
919 dump_info->lmac_err_id[0] =
920 cpu_to_le32(fwrt->dump.lmac_err_id[0]);
921 if (fwrt->smem_cfg.num_lmacs > 1)
922 dump_info->lmac_err_id[1] =
923 cpu_to_le32(fwrt->dump.lmac_err_id[1]);
924 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id);
925
926 dump_data = iwl_fw_error_next_data(dump_data);
927 }
928
929 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) {
930 /* Dump shared memory configuration */
931 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG);
932 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg));
933 dump_smem_cfg = (void *)dump_data->data;
934 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs);
935 dump_smem_cfg->num_txfifo_entries =
936 cpu_to_le32(mem_cfg->num_txfifo_entries);
937 for (i = 0; i < MAX_NUM_LMAC; i++) {
938 int j;
939 u32 *txf_size = mem_cfg->lmac[i].txfifo_size;
940
941 for (j = 0; j < TX_FIFO_MAX_NUM; j++)
942 dump_smem_cfg->lmac[i].txfifo_size[j] =
943 cpu_to_le32(txf_size[j]);
944 dump_smem_cfg->lmac[i].rxfifo1_size =
945 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size);
946 }
947 dump_smem_cfg->rxfifo2_size =
948 cpu_to_le32(mem_cfg->rxfifo2_size);
949 dump_smem_cfg->internal_txfifo_addr =
950 cpu_to_le32(mem_cfg->internal_txfifo_addr);
951 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {
952 dump_smem_cfg->internal_txfifo_size[i] =
953 cpu_to_le32(mem_cfg->internal_txfifo_size[i]);
954 }
955
956 dump_data = iwl_fw_error_next_data(dump_data);
957 }
958
959 /* We only dump the FIFOs if the FW is in error state */
960 if (fifo_len) {
961 iwl_fw_dump_rxf(fwrt, &dump_data);
962 iwl_fw_dump_txf(fwrt, &dump_data);
963 }
964
965 if (radio_len)
966 iwl_read_radio_regs(fwrt, &dump_data);
967
968 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) &&
969 data->desc) {
970 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
971 dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
972 data->desc->len);
973 dump_trig = (void *)dump_data->data;
974 memcpy(dump_trig, &data->desc->trig_desc,
975 sizeof(*dump_trig) + data->desc->len);
976
977 dump_data = iwl_fw_error_next_data(dump_data);
978 }
979
980 /* In case we only want monitor dump, skip to dump trasport data */
981 if (data->monitor_only)
982 goto out;
983
984 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) {
985 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem =
986 fwrt->fw->dbg.mem_tlv;
987
988 if (!fwrt->fw->dbg.n_mem_tlv)
989 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs,
990 IWL_FW_ERROR_DUMP_MEM_SRAM);
991
992 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
993 u32 len = le32_to_cpu(fw_dbg_mem[i].len);
994 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
995
996 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs,
997 le32_to_cpu(fw_dbg_mem[i].data_type));
998 }
999
1000 iwl_fw_dump_mem(fwrt, &dump_data, smem_len,
1001 fwrt->trans->mac_cfg->base->smem_offset,
1002 IWL_FW_ERROR_DUMP_MEM_SMEM);
1003
1004 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len,
1005 fwrt->trans->cfg->dccm2_offset,
1006 IWL_FW_ERROR_DUMP_MEM_SRAM);
1007 }
1008
1009 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) {
1010 u32 addr = fwrt->trans->mac_cfg->base->d3_debug_data_base_addr;
1011 size_t data_size = fwrt->trans->mac_cfg->base->d3_debug_data_length;
1012
1013 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
1014 dump_data->len = cpu_to_le32(data_size * 2);
1015
1016 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size);
1017
1018 kfree(fwrt->dump.d3_debug_data);
1019 fwrt->dump.d3_debug_data = NULL;
1020
1021 iwl_trans_read_mem_bytes(fwrt->trans, addr,
1022 dump_data->data + data_size,
1023 data_size);
1024
1025 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
1026 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr,
1027 dump_data->data + data_size,
1028 data_size);
1029
1030 dump_data = iwl_fw_error_next_data(dump_data);
1031 }
1032
1033 /* Dump fw's virtual image */
1034 if (iwl_fw_dbg_is_paging_enabled(fwrt))
1035 iwl_dump_paging(fwrt, &dump_data);
1036
1037 if (prph_len)
1038 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph);
1039
1040 out:
1041 dump_file->file_len = cpu_to_le32(file_len);
1042 return dump_file;
1043 }
1044
1045 /**
1046 * struct iwl_dump_ini_region_data - region data
1047 * @reg_tlv: region TLV
1048 * @dump_data: dump data
1049 */
1050 struct iwl_dump_ini_region_data {
1051 struct iwl_ucode_tlv *reg_tlv;
1052 struct iwl_fwrt_dump_data *dump_data;
1053 };
1054
iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime * fwrt,void * range_ptr,u32 addr,__le32 size)1055 static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt,
1056 void *range_ptr, u32 addr,
1057 __le32 size)
1058 {
1059 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1060 __le32 *val = range->data;
1061 int i;
1062
1063 range->internal_base_addr = cpu_to_le32(addr);
1064 range->range_data_size = size;
1065 for (i = 0; i < le32_to_cpu(size); i += 4)
1066 *val++ = cpu_to_le32(iwl_read_prph(fwrt->trans, addr + i));
1067
1068 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1069 }
1070
1071 static int
iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1072 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt,
1073 struct iwl_dump_ini_region_data *reg_data,
1074 void *range_ptr, u32 range_len, int idx)
1075 {
1076 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1077 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1078 le32_to_cpu(reg->dev_addr.offset);
1079
1080 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr,
1081 reg->dev_addr.size);
1082 }
1083
1084 static int
iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1085 iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime *fwrt,
1086 struct iwl_dump_ini_region_data *reg_data,
1087 void *range_ptr, u32 range_len, int idx)
1088 {
1089 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1090 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs;
1091 u32 addr = le32_to_cpu(reg->dev_addr_range.offset) +
1092 le32_to_cpu(pairs[idx].addr);
1093
1094 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr,
1095 pairs[idx].size);
1096 }
1097
iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime * fwrt,void * range_ptr,u32 addr,__le32 size,__le32 offset)1098 static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt,
1099 void *range_ptr, u32 addr,
1100 __le32 size, __le32 offset)
1101 {
1102 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1103 __le32 *val = range->data;
1104 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1;
1105 u32 indirect_rd_addr = WMAL_MRSPF_1;
1106 u32 prph_val;
1107 u32 dphy_state;
1108 u32 dphy_addr;
1109 u32 prph_stts;
1110 int i;
1111
1112 range->internal_base_addr = cpu_to_le32(addr);
1113 range->range_data_size = size;
1114
1115 if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
1116 indirect_wr_addr = WMAL_INDRCT_CMD1;
1117
1118 indirect_wr_addr += le32_to_cpu(offset);
1119 indirect_rd_addr += le32_to_cpu(offset);
1120
1121 if (!iwl_trans_grab_nic_access(fwrt->trans))
1122 return -EBUSY;
1123
1124 dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;
1125 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
1126
1127 for (i = 0; i < le32_to_cpu(size); i += 4) {
1128 if (dphy_state == HBUS_TIMEOUT ||
1129 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) !=
1130 WFPM_PHYRF_STATE_ON) {
1131 *val++ = cpu_to_le32(WFPM_DPHY_OFF);
1132 continue;
1133 }
1134
1135 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr,
1136 WMAL_INDRCT_CMD(addr + i));
1137
1138 if (fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_JF1 &&
1139 fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_JF2 &&
1140 fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_HR1 &&
1141 fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_HR2) {
1142 udelay(2);
1143 prph_stts = iwl_read_prph_no_grab(fwrt->trans,
1144 WMAL_MRSPF_STTS);
1145
1146 /* Abort dump if status is 0xA5A5A5A2 or FIFO1 empty */
1147 if (prph_stts == WMAL_TIMEOUT_VAL ||
1148 !WMAL_MRSPF_STTS_IS_FIFO1_NOT_EMPTY(prph_stts))
1149 break;
1150 }
1151
1152 prph_val = iwl_read_prph_no_grab(fwrt->trans,
1153 indirect_rd_addr);
1154 *val++ = cpu_to_le32(prph_val);
1155 }
1156
1157 iwl_trans_release_nic_access(fwrt->trans);
1158 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1159 }
1160
1161 static int
iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1162 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt,
1163 struct iwl_dump_ini_region_data *reg_data,
1164 void *range_ptr, u32 range_len, int idx)
1165 {
1166 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1167 u32 addr = le32_to_cpu(reg->addrs[idx]);
1168
1169 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr,
1170 reg->dev_addr.size,
1171 reg->dev_addr.offset);
1172 }
1173
1174 static int
iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1175 iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime *fwrt,
1176 struct iwl_dump_ini_region_data *reg_data,
1177 void *range_ptr, u32 range_len, int idx)
1178 {
1179 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1180 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs;
1181 u32 addr = le32_to_cpu(pairs[idx].addr);
1182
1183 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr,
1184 pairs[idx].size,
1185 reg->dev_addr_range.offset);
1186 }
1187
iwl_dump_ini_csr_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1188 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt,
1189 struct iwl_dump_ini_region_data *reg_data,
1190 void *range_ptr, u32 range_len, int idx)
1191 {
1192 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1193 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1194 __le32 *val = range->data;
1195 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1196 le32_to_cpu(reg->dev_addr.offset);
1197 int i;
1198
1199 range->internal_base_addr = cpu_to_le32(addr);
1200 range->range_data_size = reg->dev_addr.size;
1201 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4)
1202 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i));
1203
1204 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1205 }
1206
iwl_dump_ini_config_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1207 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt,
1208 struct iwl_dump_ini_region_data *reg_data,
1209 void *range_ptr, u32 range_len, int idx)
1210 {
1211 struct iwl_trans *trans = fwrt->trans;
1212 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1213 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1214 __le32 *val = range->data;
1215 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1216 le32_to_cpu(reg->dev_addr.offset);
1217 int i;
1218
1219 range->internal_base_addr = cpu_to_le32(addr);
1220 range->range_data_size = reg->dev_addr.size;
1221 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1222 int ret;
1223 u32 tmp;
1224
1225 ret = iwl_trans_read_config32(trans, addr + i, &tmp);
1226 if (ret < 0)
1227 return ret;
1228
1229 *val++ = cpu_to_le32(tmp);
1230 }
1231
1232 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1233 }
1234
iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1235 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt,
1236 struct iwl_dump_ini_region_data *reg_data,
1237 void *range_ptr, u32 range_len, int idx)
1238 {
1239 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1240 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1241 u32 addr = le32_to_cpu(reg->addrs[idx]) +
1242 le32_to_cpu(reg->dev_addr.offset);
1243
1244 range->internal_base_addr = cpu_to_le32(addr);
1245 range->range_data_size = reg->dev_addr.size;
1246 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1247 le32_to_cpu(reg->dev_addr.size));
1248
1249 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM &&
1250 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
1251 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
1252 range->data,
1253 le32_to_cpu(reg->dev_addr.size));
1254
1255 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1256 }
1257
_iwl_dump_ini_paging_iter(struct iwl_fw_runtime * fwrt,void * range_ptr,u32 range_len,int idx)1258 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1259 void *range_ptr, u32 range_len, int idx)
1260 {
1261 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block;
1262 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1263 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys;
1264 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size;
1265
1266 range->page_num = cpu_to_le32(idx);
1267 range->range_data_size = cpu_to_le32(page_size);
1268 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size,
1269 DMA_BIDIRECTIONAL);
1270 memcpy(range->data, page_address(page), page_size);
1271 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size,
1272 DMA_BIDIRECTIONAL);
1273
1274 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1275 }
1276
iwl_dump_ini_paging_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1277 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt,
1278 struct iwl_dump_ini_region_data *reg_data,
1279 void *range_ptr, u32 range_len, int idx)
1280 {
1281 struct iwl_fw_ini_error_dump_range *range;
1282 u32 page_size;
1283
1284 /* all paged index start from 1 to skip CSS section */
1285 idx++;
1286
1287 if (!fwrt->trans->mac_cfg->gen2)
1288 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx);
1289
1290 range = range_ptr;
1291 page_size = fwrt->trans->init_dram.paging[idx].size;
1292
1293 range->page_num = cpu_to_le32(idx);
1294 range->range_data_size = cpu_to_le32(page_size);
1295 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block,
1296 page_size);
1297
1298 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1299 }
1300
1301 static int
iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1302 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt,
1303 struct iwl_dump_ini_region_data *reg_data,
1304 void *range_ptr, u32 range_len, int idx)
1305 {
1306 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1307 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1308 struct iwl_dram_data *frag;
1309 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1310
1311 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx];
1312
1313 range->dram_base_addr = cpu_to_le64(frag->physical);
1314 range->range_data_size = cpu_to_le32(frag->size);
1315
1316 memcpy(range->data, frag->block, frag->size);
1317
1318 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1319 }
1320
iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1321 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt,
1322 struct iwl_dump_ini_region_data *reg_data,
1323 void *range_ptr, u32 range_len, int idx)
1324 {
1325 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1326 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1327 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr);
1328
1329 range->internal_base_addr = cpu_to_le32(addr);
1330 range->range_data_size = reg->internal_buffer.size;
1331 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1332 le32_to_cpu(reg->internal_buffer.size));
1333
1334 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1335 }
1336
iwl_ini_txf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,int idx)1337 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1338 struct iwl_dump_ini_region_data *reg_data, int idx)
1339 {
1340 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1341 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1342 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg;
1343 int txf_num = cfg->num_txfifo_entries;
1344 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size);
1345 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]);
1346
1347 if (!idx) {
1348 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) {
1349 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n",
1350 le32_to_cpu(reg->fifos.offset));
1351 return false;
1352 }
1353
1354 iter->internal_txf = 0;
1355 iter->fifo_size = 0;
1356 iter->fifo = -1;
1357 if (le32_to_cpu(reg->fifos.offset))
1358 iter->lmac = 1;
1359 else
1360 iter->lmac = 0;
1361 }
1362
1363 if (!iter->internal_txf) {
1364 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) {
1365 iter->fifo_size =
1366 cfg->lmac[iter->lmac].txfifo_size[iter->fifo];
1367 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1368 return true;
1369 }
1370 iter->fifo--;
1371 }
1372
1373 iter->internal_txf = 1;
1374
1375 if (!fw_has_capa(&fwrt->fw->ucode_capa,
1376 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
1377 return false;
1378
1379 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) {
1380 iter->fifo_size =
1381 cfg->internal_txfifo_size[iter->fifo - txf_num];
1382 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo)))
1383 return true;
1384 }
1385
1386 return false;
1387 }
1388
iwl_dump_ini_txf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1389 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt,
1390 struct iwl_dump_ini_region_data *reg_data,
1391 void *range_ptr, u32 range_len, int idx)
1392 {
1393 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1394 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1395 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
1396 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1397 u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1398 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1399 u32 registers_size = registers_num * sizeof(*reg_dump);
1400 __le32 *data;
1401 int i;
1402
1403 if (!iwl_ini_txf_iter(fwrt, reg_data, idx))
1404 return -EIO;
1405
1406 if (!iwl_trans_grab_nic_access(fwrt->trans))
1407 return -EBUSY;
1408
1409 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo);
1410 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1411 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size);
1412
1413 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo);
1414
1415 /*
1416 * read txf registers. for each register, write to the dump the
1417 * register address and its value
1418 */
1419 for (i = 0; i < registers_num; i++) {
1420 addr = le32_to_cpu(reg->addrs[i]) + offs;
1421
1422 reg_dump->addr = cpu_to_le32(addr);
1423 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1424 addr));
1425
1426 reg_dump++;
1427 }
1428
1429 if (reg->fifos.hdr_only) {
1430 range->range_data_size = cpu_to_le32(registers_size);
1431 goto out;
1432 }
1433
1434 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
1435 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs,
1436 TXF_WR_PTR + offs);
1437
1438 /* Dummy-read to advance the read pointer to the head */
1439 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs);
1440
1441 /* Read FIFO */
1442 addr = TXF_READ_MODIFY_DATA + offs;
1443 data = (void *)reg_dump;
1444 for (i = 0; i < iter->fifo_size; i += sizeof(*data))
1445 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1446
1447 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf)
1448 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx,
1449 reg_dump, iter->fifo_size);
1450
1451 out:
1452 iwl_trans_release_nic_access(fwrt->trans);
1453
1454 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1455 }
1456
1457 static int
iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1458 iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt,
1459 struct iwl_dump_ini_region_data *reg_data,
1460 void *range_ptr, u32 range_len, int idx)
1461 {
1462 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1463 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1464 __le32 *val = range->data;
1465 __le32 offset = reg->dev_addr.offset;
1466 u32 indirect_rd_wr_addr = DPHYIP_INDIRECT;
1467 u32 addr = le32_to_cpu(reg->addrs[idx]);
1468 u32 dphy_state, dphy_addr, prph_val;
1469 int i;
1470
1471 range->internal_base_addr = cpu_to_le32(addr);
1472 range->range_data_size = reg->dev_addr.size;
1473
1474 if (!iwl_trans_grab_nic_access(fwrt->trans))
1475 return -EBUSY;
1476
1477 indirect_rd_wr_addr += le32_to_cpu(offset);
1478
1479 dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW;
1480 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr);
1481
1482 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1483 if (dphy_state == HBUS_TIMEOUT ||
1484 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) !=
1485 WFPM_PHYRF_STATE_ON) {
1486 *val++ = cpu_to_le32(WFPM_DPHY_OFF);
1487 continue;
1488 }
1489
1490 iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr,
1491 addr + i);
1492 /* wait a bit for value to be ready in register */
1493 udelay(1);
1494 prph_val = iwl_read_prph_no_grab(fwrt->trans,
1495 indirect_rd_wr_addr);
1496 *val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >>
1497 DPHYIP_INDIRECT_RD_SHIFT);
1498 }
1499
1500 iwl_trans_release_nic_access(fwrt->trans);
1501 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1502 }
1503
1504 struct iwl_ini_rxf_data {
1505 u32 fifo_num;
1506 u32 size;
1507 u32 offset;
1508 };
1509
iwl_ini_get_rxf_data(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,struct iwl_ini_rxf_data * data)1510 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt,
1511 struct iwl_dump_ini_region_data *reg_data,
1512 struct iwl_ini_rxf_data *data)
1513 {
1514 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1515 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]);
1516 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]);
1517 u8 fifo_idx;
1518
1519 if (!data)
1520 return;
1521
1522 memset(data, 0, sizeof(*data));
1523
1524 /* make sure only one bit is set in only one fid */
1525 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1,
1526 "fid1=%x, fid2=%x\n", fid1, fid2))
1527 return;
1528
1529 if (fid1) {
1530 fifo_idx = ffs(fid1) - 1;
1531 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n",
1532 fifo_idx))
1533 return;
1534
1535 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size;
1536 data->fifo_num = fifo_idx;
1537 } else {
1538 u8 max_idx;
1539
1540 fifo_idx = ffs(fid2) - 1;
1541 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP,
1542 SHARED_MEM_CFG_CMD, 0) <= 3)
1543 max_idx = 0;
1544 else
1545 max_idx = 1;
1546
1547 if (WARN_ONCE(fifo_idx > max_idx,
1548 "invalid umac fifo idx %d", fifo_idx))
1549 return;
1550
1551 /* use bit 31 to distinguish between umac and lmac rxf while
1552 * parsing the dump
1553 */
1554 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT;
1555
1556 switch (fifo_idx) {
1557 case 0:
1558 data->size = fwrt->smem_cfg.rxfifo2_size;
1559 data->offset = iwl_umac_prph(fwrt->trans,
1560 RXF_DIFF_FROM_PREV);
1561 break;
1562 case 1:
1563 data->size = fwrt->smem_cfg.rxfifo2_control_size;
1564 data->offset = iwl_umac_prph(fwrt->trans,
1565 RXF2C_DIFF_FROM_PREV);
1566 break;
1567 }
1568 }
1569 }
1570
iwl_dump_ini_rxf_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1571 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt,
1572 struct iwl_dump_ini_region_data *reg_data,
1573 void *range_ptr, u32 range_len, int idx)
1574 {
1575 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1576 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1577 struct iwl_ini_rxf_data rxf_data;
1578 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data;
1579 u32 offs = le32_to_cpu(reg->fifos.offset), addr;
1580 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1581 u32 registers_size = registers_num * sizeof(*reg_dump);
1582 __le32 *data;
1583 int i;
1584
1585 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data);
1586 if (!rxf_data.size)
1587 return -EIO;
1588
1589 if (!iwl_trans_grab_nic_access(fwrt->trans))
1590 return -EBUSY;
1591
1592 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num);
1593 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num);
1594 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size);
1595
1596 /*
1597 * read rxf registers. for each register, write to the dump the
1598 * register address and its value
1599 */
1600 for (i = 0; i < registers_num; i++) {
1601 addr = le32_to_cpu(reg->addrs[i]) + offs;
1602
1603 reg_dump->addr = cpu_to_le32(addr);
1604 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans,
1605 addr));
1606
1607 reg_dump++;
1608 }
1609
1610 if (reg->fifos.hdr_only) {
1611 range->range_data_size = cpu_to_le32(registers_size);
1612 goto out;
1613 }
1614
1615 offs = rxf_data.offset;
1616
1617 /* Lock fence */
1618 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
1619 /* Set fence pointer to the same place like WR pointer */
1620 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
1621 /* Set fence offset */
1622 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs,
1623 0x0);
1624
1625 /* Read FIFO */
1626 addr = RXF_FIFO_RD_FENCE_INC + offs;
1627 data = (void *)reg_dump;
1628 for (i = 0; i < rxf_data.size; i += sizeof(*data))
1629 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr));
1630
1631 out:
1632 iwl_trans_release_nic_access(fwrt->trans);
1633
1634 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1635 }
1636
1637 static int
iwl_dump_ini_err_table_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1638 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt,
1639 struct iwl_dump_ini_region_data *reg_data,
1640 void *range_ptr, u32 range_len, int idx)
1641 {
1642 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1643 struct iwl_fw_ini_region_err_table *err_table = ®->err_table;
1644 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1645 u32 addr = le32_to_cpu(err_table->base_addr) +
1646 le32_to_cpu(err_table->offset);
1647
1648 range->internal_base_addr = cpu_to_le32(addr);
1649 range->range_data_size = err_table->size;
1650 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1651 le32_to_cpu(err_table->size));
1652
1653 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1654 }
1655
1656 static int
iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1657 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt,
1658 struct iwl_dump_ini_region_data *reg_data,
1659 void *range_ptr, u32 range_len, int idx)
1660 {
1661 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1662 struct iwl_fw_ini_region_special_device_memory *special_mem =
1663 ®->special_mem;
1664
1665 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1666 u32 addr = le32_to_cpu(special_mem->base_addr) +
1667 le32_to_cpu(special_mem->offset);
1668
1669 range->internal_base_addr = cpu_to_le32(addr);
1670 range->range_data_size = special_mem->size;
1671 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data,
1672 le32_to_cpu(special_mem->size));
1673
1674 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1675 }
1676
1677 static int
iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1678 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt,
1679 struct iwl_dump_ini_region_data *reg_data,
1680 void *range_ptr, u32 range_len, int idx)
1681 {
1682 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1683 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1684 __le32 *val = range->data;
1685 u32 prph_data;
1686 int i;
1687
1688 if (!iwl_trans_grab_nic_access(fwrt->trans))
1689 return -EBUSY;
1690
1691 range->range_data_size = reg->dev_addr.size;
1692 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) {
1693 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ?
1694 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :
1695 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);
1696 if (iwl_trans_is_hw_error_value(prph_data)) {
1697 iwl_trans_release_nic_access(fwrt->trans);
1698 return -EBUSY;
1699 }
1700 *val++ = cpu_to_le32(prph_data);
1701 }
1702 iwl_trans_release_nic_access(fwrt->trans);
1703 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1704 }
1705
iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1706 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt,
1707 struct iwl_dump_ini_region_data *reg_data,
1708 void *range_ptr, u32 range_len, int idx)
1709 {
1710 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1711 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt;
1712 u32 pkt_len;
1713
1714 if (!pkt)
1715 return -EIO;
1716
1717 pkt_len = iwl_rx_packet_payload_len(pkt);
1718
1719 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr));
1720 range->range_data_size = cpu_to_le32(pkt_len);
1721
1722 memcpy(range->data, pkt->data, pkt_len);
1723
1724 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1725 }
1726
iwl_dump_ini_imr_iter(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * range_ptr,u32 range_len,int idx)1727 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt,
1728 struct iwl_dump_ini_region_data *reg_data,
1729 void *range_ptr, u32 range_len, int idx)
1730 {
1731 /* read the IMR memory and DMA it to SRAM */
1732 struct iwl_fw_ini_error_dump_range *range = range_ptr;
1733 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr;
1734 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte;
1735 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr;
1736 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size;
1737 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes;
1738
1739 range->range_data_size = cpu_to_le32(size_to_dump);
1740 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr,
1741 imr_curr_addr, size_to_dump)) {
1742 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n");
1743 return -1;
1744 }
1745
1746 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump;
1747 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump;
1748
1749 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data,
1750 size_to_dump);
1751 return sizeof(*range) + le32_to_cpu(range->range_data_size);
1752 }
1753
1754 static void *
iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1755 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt,
1756 struct iwl_dump_ini_region_data *reg_data,
1757 void *data, u32 data_len)
1758 {
1759 struct iwl_fw_ini_error_dump *dump = data;
1760
1761 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1762
1763 return dump->data;
1764 }
1765
1766 /**
1767 * mask_apply_and_normalize - applies mask on val and normalize the result
1768 *
1769 * @val: value
1770 * @mask: mask to apply and to normalize with
1771 *
1772 * The normalization is based on the first set bit in the mask
1773 *
1774 * Returns: the extracted value
1775 */
mask_apply_and_normalize(u32 val,u32 mask)1776 static u32 mask_apply_and_normalize(u32 val, u32 mask)
1777 {
1778 return (val & mask) >> (ffs(mask) - 1);
1779 }
1780
iwl_get_mon_reg(struct iwl_fw_runtime * fwrt,u32 alloc_id,const struct iwl_fw_mon_reg * reg_info)1781 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id,
1782 const struct iwl_fw_mon_reg *reg_info)
1783 {
1784 u32 val, offs;
1785
1786 /* The header addresses of DBGCi is calculate as follows:
1787 * DBGC1 address + (0x100 * i)
1788 */
1789 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100;
1790
1791 if (!reg_info || !reg_info->addr || !reg_info->mask)
1792 return 0;
1793
1794 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs);
1795
1796 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask));
1797 }
1798
1799 static void *
iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime * fwrt,u32 alloc_id,struct iwl_fw_ini_monitor_dump * data,const struct iwl_fw_mon_regs * addrs)1800 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id,
1801 struct iwl_fw_ini_monitor_dump *data,
1802 const struct iwl_fw_mon_regs *addrs)
1803 {
1804 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
1805 IWL_ERR(fwrt, "Failed to get monitor header\n");
1806 return NULL;
1807 }
1808
1809 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id,
1810 &addrs->write_ptr);
1811 if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1812 u32 wrt_ptr = le32_to_cpu(data->write_ptr);
1813
1814 data->write_ptr = cpu_to_le32(wrt_ptr >> 2);
1815 }
1816 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id,
1817 &addrs->cycle_cnt);
1818 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id,
1819 &addrs->cur_frag);
1820
1821 iwl_trans_release_nic_access(fwrt->trans);
1822
1823 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1824
1825 return data->data;
1826 }
1827
1828 static void *
iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1829 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt,
1830 struct iwl_dump_ini_region_data *reg_data,
1831 void *data, u32 data_len)
1832 {
1833 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1834 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1835 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id);
1836
1837 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump,
1838 &fwrt->trans->mac_cfg->base->mon_dram_regs);
1839 }
1840
1841 static void *
iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1842 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt,
1843 struct iwl_dump_ini_region_data *reg_data,
1844 void *data, u32 data_len)
1845 {
1846 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1847 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1848 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id);
1849
1850 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump,
1851 &fwrt->trans->mac_cfg->base->mon_smem_regs);
1852 }
1853
1854 static void *
iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1855 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt,
1856 struct iwl_dump_ini_region_data *reg_data,
1857 void *data, u32 data_len)
1858 {
1859 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data;
1860
1861 return iwl_dump_ini_mon_fill_header(fwrt,
1862 /* no offset calculation later */
1863 IWL_FW_INI_ALLOCATION_ID_DBGC1,
1864 mon_dump,
1865 &fwrt->trans->mac_cfg->base->mon_dbgi_regs);
1866 }
1867
1868 static void *
iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1869 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt,
1870 struct iwl_dump_ini_region_data *reg_data,
1871 void *data, u32 data_len)
1872 {
1873 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1874 struct iwl_fw_ini_err_table_dump *dump = data;
1875
1876 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1877 dump->version = reg->err_table.version;
1878
1879 return dump->data;
1880 }
1881
1882 static void *
iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1883 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt,
1884 struct iwl_dump_ini_region_data *reg_data,
1885 void *data, u32 data_len)
1886 {
1887 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1888 struct iwl_fw_ini_special_device_memory *dump = data;
1889
1890 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1891 dump->type = reg->special_mem.type;
1892 dump->version = reg->special_mem.version;
1893
1894 return dump->data;
1895 }
1896
1897 static void *
iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data,void * data,u32 data_len)1898 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt,
1899 struct iwl_dump_ini_region_data *reg_data,
1900 void *data, u32 data_len)
1901 {
1902 struct iwl_fw_ini_error_dump *dump = data;
1903
1904 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER);
1905
1906 return dump->data;
1907 }
1908
iwl_dump_ini_mem_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1909 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt,
1910 struct iwl_dump_ini_region_data *reg_data)
1911 {
1912 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1913
1914 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
1915 }
1916
1917 static u32
iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1918 iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime *fwrt,
1919 struct iwl_dump_ini_region_data *reg_data)
1920 {
1921 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1922 size_t size = sizeof(struct iwl_fw_ini_addr_size);
1923
1924 return iwl_tlv_array_len_with_size(reg_data->reg_tlv, reg, size);
1925 }
1926
iwl_dump_ini_paging_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1927 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt,
1928 struct iwl_dump_ini_region_data *reg_data)
1929 {
1930 if (fwrt->trans->mac_cfg->gen2) {
1931 if (fwrt->trans->init_dram.paging_cnt)
1932 return fwrt->trans->init_dram.paging_cnt - 1;
1933 else
1934 return 0;
1935 }
1936
1937 return fwrt->num_of_paging_blk;
1938 }
1939
1940 static u32
iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1941 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt,
1942 struct iwl_dump_ini_region_data *reg_data)
1943 {
1944 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
1945 struct iwl_fw_mon *fw_mon;
1946 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1947 int i;
1948
1949 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
1950
1951 for (i = 0; i < fw_mon->num_frags; i++) {
1952 if (!fw_mon->frags[i].size)
1953 break;
1954
1955 ranges++;
1956 }
1957
1958 return ranges;
1959 }
1960
iwl_dump_ini_txf_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1961 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt,
1962 struct iwl_dump_ini_region_data *reg_data)
1963 {
1964 u32 num_of_fifos = 0;
1965
1966 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos))
1967 num_of_fifos++;
1968
1969 return num_of_fifos;
1970 }
1971
iwl_dump_ini_single_range(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1972 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt,
1973 struct iwl_dump_ini_region_data *reg_data)
1974 {
1975 return 1;
1976 }
1977
iwl_dump_ini_imr_ranges(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1978 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt,
1979 struct iwl_dump_ini_region_data *reg_data)
1980 {
1981 /* range is total number of pages need to copied from
1982 *IMR memory to SRAM and later from SRAM to DRAM
1983 */
1984 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable;
1985 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size;
1986 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size;
1987
1988 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {
1989 IWL_DEBUG_INFO(fwrt,
1990 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n",
1991 imr_enable, imr_size, sram_size);
1992 return 0;
1993 }
1994
1995 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size));
1996 }
1997
iwl_dump_ini_mem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)1998 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt,
1999 struct iwl_dump_ini_region_data *reg_data)
2000 {
2001 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2002 u32 size = le32_to_cpu(reg->dev_addr.size);
2003 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data);
2004
2005 if (!size || !ranges)
2006 return 0;
2007
2008 return sizeof(struct iwl_fw_ini_error_dump) + ranges *
2009 (size + sizeof(struct iwl_fw_ini_error_dump_range));
2010 }
2011
2012 static u32
iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2013 iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime *fwrt,
2014 struct iwl_dump_ini_region_data *reg_data)
2015 {
2016 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2017 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs;
2018 u32 ranges = iwl_dump_ini_mem_block_ranges(fwrt, reg_data);
2019 u32 size = sizeof(struct iwl_fw_ini_error_dump);
2020 int range;
2021
2022 if (!ranges)
2023 return 0;
2024
2025 for (range = 0; range < ranges; range++)
2026 size += le32_to_cpu(pairs[range].size);
2027
2028 return size + ranges * sizeof(struct iwl_fw_ini_error_dump_range);
2029 }
2030
2031 static u32
iwl_dump_ini_paging_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2032 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt,
2033 struct iwl_dump_ini_region_data *reg_data)
2034 {
2035 int i;
2036 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range);
2037 u32 size = sizeof(struct iwl_fw_ini_error_dump);
2038
2039 /* start from 1 to skip CSS section */
2040 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) {
2041 size += range_header_len;
2042 if (fwrt->trans->mac_cfg->gen2)
2043 size += fwrt->trans->init_dram.paging[i].size;
2044 else
2045 size += fwrt->fw_paging_db[i].fw_paging_size;
2046 }
2047
2048 return size;
2049 }
2050
2051 static u32
iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2052 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt,
2053 struct iwl_dump_ini_region_data *reg_data)
2054 {
2055 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2056 struct iwl_fw_mon *fw_mon;
2057 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
2058 int i;
2059
2060 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
2061
2062 for (i = 0; i < fw_mon->num_frags; i++) {
2063 struct iwl_dram_data *frag = &fw_mon->frags[i];
2064
2065 if (!frag->size)
2066 break;
2067
2068 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size;
2069 }
2070
2071 if (size)
2072 size += sizeof(struct iwl_fw_ini_monitor_dump);
2073
2074 return size;
2075 }
2076
2077 static u32
iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2078 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt,
2079 struct iwl_dump_ini_region_data *reg_data)
2080 {
2081 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2082 u32 size;
2083
2084 size = le32_to_cpu(reg->internal_buffer.size);
2085 if (!size)
2086 return 0;
2087
2088 size += sizeof(struct iwl_fw_ini_monitor_dump) +
2089 sizeof(struct iwl_fw_ini_error_dump_range);
2090
2091 return size;
2092 }
2093
iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2094 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt,
2095 struct iwl_dump_ini_region_data *reg_data)
2096 {
2097 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2098 u32 size = le32_to_cpu(reg->dev_addr.size);
2099 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data);
2100
2101 if (!size || !ranges)
2102 return 0;
2103
2104 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges *
2105 (size + sizeof(struct iwl_fw_ini_error_dump_range));
2106 }
2107
iwl_dump_ini_txf_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2108 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt,
2109 struct iwl_dump_ini_region_data *reg_data)
2110 {
2111 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2112 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data;
2113 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
2114 u32 size = 0;
2115 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) +
2116 registers_num *
2117 sizeof(struct iwl_fw_ini_error_dump_register);
2118
2119 while (iwl_ini_txf_iter(fwrt, reg_data, size)) {
2120 size += fifo_hdr;
2121 if (!reg->fifos.hdr_only)
2122 size += iter->fifo_size;
2123 }
2124
2125 if (!size)
2126 return 0;
2127
2128 return size + sizeof(struct iwl_fw_ini_error_dump);
2129 }
2130
iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2131 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt,
2132 struct iwl_dump_ini_region_data *reg_data)
2133 {
2134 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2135 struct iwl_ini_rxf_data rx_data;
2136 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs);
2137 u32 size = sizeof(struct iwl_fw_ini_error_dump) +
2138 sizeof(struct iwl_fw_ini_error_dump_range) +
2139 registers_num * sizeof(struct iwl_fw_ini_error_dump_register);
2140
2141 if (reg->fifos.hdr_only)
2142 return size;
2143
2144 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data);
2145 size += rx_data.size;
2146
2147 return size;
2148 }
2149
2150 static u32
iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2151 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt,
2152 struct iwl_dump_ini_region_data *reg_data)
2153 {
2154 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2155 u32 size = le32_to_cpu(reg->err_table.size);
2156
2157 if (size)
2158 size += sizeof(struct iwl_fw_ini_err_table_dump) +
2159 sizeof(struct iwl_fw_ini_error_dump_range);
2160
2161 return size;
2162 }
2163
2164 static u32
iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2165 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt,
2166 struct iwl_dump_ini_region_data *reg_data)
2167 {
2168 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2169 u32 size = le32_to_cpu(reg->special_mem.size);
2170
2171 if (size)
2172 size += sizeof(struct iwl_fw_ini_special_device_memory) +
2173 sizeof(struct iwl_fw_ini_error_dump_range);
2174
2175 return size;
2176 }
2177
2178 static u32
iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2179 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt,
2180 struct iwl_dump_ini_region_data *reg_data)
2181 {
2182 u32 size = 0;
2183
2184 if (!reg_data->dump_data->fw_pkt)
2185 return 0;
2186
2187 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt);
2188 if (size)
2189 size += sizeof(struct iwl_fw_ini_error_dump) +
2190 sizeof(struct iwl_fw_ini_error_dump_range);
2191
2192 return size;
2193 }
2194
2195 static u32
iwl_dump_ini_imr_get_size(struct iwl_fw_runtime * fwrt,struct iwl_dump_ini_region_data * reg_data)2196 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt,
2197 struct iwl_dump_ini_region_data *reg_data)
2198 {
2199 u32 ranges = 0;
2200 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable;
2201 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size;
2202 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size;
2203
2204 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {
2205 IWL_DEBUG_INFO(fwrt,
2206 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n",
2207 imr_enable, imr_size, sram_size);
2208 return 0;
2209 }
2210 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data);
2211 if (!ranges) {
2212 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges);
2213 return 0;
2214 }
2215 imr_size += sizeof(struct iwl_fw_ini_error_dump) +
2216 ranges * sizeof(struct iwl_fw_ini_error_dump_range);
2217 return imr_size;
2218 }
2219
2220 /**
2221 * struct iwl_dump_ini_mem_ops - ini memory dump operations
2222 * @get_num_of_ranges: returns the number of memory ranges in the region.
2223 * @get_size: returns the total size of the region.
2224 * @fill_mem_hdr: fills region type specific headers and returns pointer to
2225 * the first range or NULL if failed to fill headers.
2226 * @fill_range: copies a given memory range into the dump.
2227 * Returns the size of the range or negative error value otherwise.
2228 */
2229 struct iwl_dump_ini_mem_ops {
2230 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt,
2231 struct iwl_dump_ini_region_data *reg_data);
2232 u32 (*get_size)(struct iwl_fw_runtime *fwrt,
2233 struct iwl_dump_ini_region_data *reg_data);
2234 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt,
2235 struct iwl_dump_ini_region_data *reg_data,
2236 void *data, u32 data_len);
2237 int (*fill_range)(struct iwl_fw_runtime *fwrt,
2238 struct iwl_dump_ini_region_data *reg_data,
2239 void *range, u32 range_len, int idx);
2240 };
2241
2242 /**
2243 * iwl_dump_ini_mem - dump memory region
2244 *
2245 * @fwrt: fw runtime struct
2246 * @list: list to add the dump tlv to
2247 * @reg_data: memory region
2248 * @ops: memory dump operations
2249 *
2250 * Creates a dump tlv and copy a memory region into it.
2251 *
2252 * Returns: the size of the current dump tlv or 0 if failed
2253 */
iwl_dump_ini_mem(struct iwl_fw_runtime * fwrt,struct list_head * list,struct iwl_dump_ini_region_data * reg_data,const struct iwl_dump_ini_mem_ops * ops)2254 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list,
2255 struct iwl_dump_ini_region_data *reg_data,
2256 const struct iwl_dump_ini_mem_ops *ops)
2257 {
2258 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
2259 struct iwl_fw_ini_dump_entry *entry;
2260 struct iwl_fw_ini_error_dump_data *tlv;
2261 struct iwl_fw_ini_error_dump_header *header;
2262 u32 type = reg->type;
2263 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK);
2264 u32 num_of_ranges, i, size;
2265 u8 *range;
2266 u32 free_size;
2267 u64 header_size;
2268 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE;
2269
2270 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n",
2271 dump_policy, id, type);
2272
2273 if (le32_to_cpu(reg->hdr.version) >= 2) {
2274 u32 dp = le32_get_bits(reg->id,
2275 IWL_FW_INI_REGION_DUMP_POLICY_MASK);
2276
2277 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE &&
2278 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) {
2279 IWL_DEBUG_FW(fwrt,
2280 "WRT: no dump - type %d and policy mismatch=%d\n",
2281 dump_policy, dp);
2282 return 0;
2283 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM &&
2284 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) {
2285 IWL_DEBUG_FW(fwrt,
2286 "WRT: no dump - type %d and policy mismatch=%d\n",
2287 dump_policy, dp);
2288 return 0;
2289 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF &&
2290 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) {
2291 IWL_DEBUG_FW(fwrt,
2292 "WRT: no dump - type %d and policy mismatch=%d\n",
2293 dump_policy, dp);
2294 return 0;
2295 }
2296 }
2297
2298 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr ||
2299 !ops->fill_range) {
2300 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n");
2301 return 0;
2302 }
2303
2304 size = ops->get_size(fwrt, reg_data);
2305
2306 if (size < sizeof(*header)) {
2307 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n");
2308 return 0;
2309 }
2310
2311 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size);
2312 if (!entry)
2313 return 0;
2314
2315 entry->size = sizeof(*tlv) + size;
2316
2317 tlv = (void *)entry->data;
2318 tlv->type = reg->type;
2319 tlv->sub_type = reg->sub_type;
2320 tlv->sub_type_ver = reg->sub_type_ver;
2321 tlv->reserved = reg->reserved;
2322 tlv->len = cpu_to_le32(size);
2323
2324 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data);
2325
2326 header = (void *)tlv->data;
2327 header->region_id = cpu_to_le32(id);
2328 header->num_of_ranges = cpu_to_le32(num_of_ranges);
2329 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME);
2330 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME);
2331
2332 free_size = size;
2333 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size);
2334 if (!range) {
2335 IWL_ERR(fwrt,
2336 "WRT: Failed to fill region header: id=%d, type=%d\n",
2337 id, type);
2338 goto out_err;
2339 }
2340
2341 header_size = range - (u8 *)header;
2342
2343 if (WARN(header_size > free_size,
2344 "header size %llu > free_size %d",
2345 header_size, free_size)) {
2346 IWL_ERR(fwrt,
2347 "WRT: fill_mem_hdr used more than given free_size\n");
2348 goto out_err;
2349 }
2350
2351 free_size -= header_size;
2352
2353 for (i = 0; i < num_of_ranges; i++) {
2354 int range_size = ops->fill_range(fwrt, reg_data, range,
2355 free_size, i);
2356
2357 if (range_size < 0) {
2358 IWL_ERR(fwrt,
2359 "WRT: Failed to dump region: id=%d, type=%d\n",
2360 id, type);
2361 goto out_err;
2362 }
2363
2364 if (WARN(range_size > free_size, "range_size %d > free_size %d",
2365 range_size, free_size)) {
2366 IWL_ERR(fwrt,
2367 "WRT: fill_raged used more than given free_size\n");
2368 goto out_err;
2369 }
2370
2371 free_size -= range_size;
2372 range = range + range_size;
2373 }
2374
2375 list_add_tail(&entry->list, list);
2376
2377 return entry->size;
2378
2379 out_err:
2380 vfree(entry);
2381
2382 return 0;
2383 }
2384
iwl_dump_ini_info(struct iwl_fw_runtime * fwrt,struct iwl_fw_ini_trigger_tlv * trigger,struct list_head * list)2385 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt,
2386 struct iwl_fw_ini_trigger_tlv *trigger,
2387 struct list_head *list)
2388 {
2389 struct iwl_fw_ini_dump_entry *entry;
2390 struct iwl_fw_error_dump_data *tlv;
2391 struct iwl_fw_ini_dump_info *dump;
2392 struct iwl_dbg_tlv_node *node;
2393 struct iwl_fw_ini_dump_cfg_name *cfg_name;
2394 u32 size = sizeof(*tlv) + sizeof(*dump);
2395 u32 num_of_cfg_names = 0;
2396 u32 hw_type, is_cdb, is_jacket;
2397
2398 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2399 size += sizeof(*cfg_name);
2400 num_of_cfg_names++;
2401 }
2402
2403 entry = vzalloc(sizeof(*entry) + size);
2404 if (!entry)
2405 return 0;
2406
2407 entry->size = size;
2408
2409 tlv = (void *)entry->data;
2410 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE);
2411 tlv->len = cpu_to_le32(size - sizeof(*tlv));
2412
2413 dump = (void *)tlv->data;
2414
2415 dump->version = cpu_to_le32(IWL_INI_DUMP_VER);
2416 dump->time_point = trigger->time_point;
2417 dump->trigger_reason = trigger->trigger_reason;
2418 dump->external_cfg_state =
2419 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg);
2420
2421 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type);
2422 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype);
2423
2424 dump->hw_step = cpu_to_le32(fwrt->trans->info.hw_rev_step);
2425
2426 hw_type = CSR_HW_REV_TYPE(fwrt->trans->info.hw_rev);
2427
2428 is_cdb = CSR_HW_RFID_IS_CDB(fwrt->trans->info.hw_rf_id);
2429 is_jacket = !!(iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR) &
2430 WFPM_OTP_CFG1_IS_JACKET_BIT);
2431
2432 /* Use bits 12 and 13 to indicate jacket/CDB, respectively */
2433 hw_type |= (is_jacket | (is_cdb << 1)) << IWL_JACKET_CDB_SHIFT;
2434
2435 dump->hw_type = cpu_to_le32(hw_type);
2436
2437 dump->rf_id_flavor =
2438 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->info.hw_rf_id));
2439 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->info.hw_rf_id));
2440 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->info.hw_rf_id));
2441 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->info.hw_rf_id));
2442
2443 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major);
2444 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor);
2445 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major);
2446 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor);
2447
2448 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest);
2449 dump->regions_mask = trigger->regions_mask &
2450 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk);
2451
2452 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag));
2453 memcpy(dump->build_tag, fwrt->fw->human_readable,
2454 sizeof(dump->build_tag));
2455
2456 cfg_name = dump->cfg_names;
2457 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names);
2458 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) {
2459 struct iwl_fw_ini_debug_info_tlv *debug_info =
2460 (void *)node->tlv.data;
2461
2462 BUILD_BUG_ON(sizeof(cfg_name->cfg_name) !=
2463 sizeof(debug_info->debug_cfg_name));
2464
2465 cfg_name->image_type = debug_info->image_type;
2466 cfg_name->cfg_name_len =
2467 cpu_to_le32(sizeof(cfg_name->cfg_name));
2468 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name,
2469 sizeof(cfg_name->cfg_name));
2470 cfg_name++;
2471 }
2472
2473 /* add dump info TLV to the beginning of the list since it needs to be
2474 * the first TLV in the dump
2475 */
2476 list_add(&entry->list, list);
2477
2478 return entry->size;
2479 }
2480
iwl_dump_ini_file_name_info(struct iwl_fw_runtime * fwrt,struct list_head * list)2481 static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt,
2482 struct list_head *list)
2483 {
2484 struct iwl_fw_ini_dump_entry *entry;
2485 struct iwl_dump_file_name_info *tlv;
2486 u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext,
2487 IWL_FW_INI_MAX_NAME);
2488
2489 if (!fwrt->trans->dbg.dump_file_name_ext_valid)
2490 return 0;
2491
2492 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len);
2493 if (!entry)
2494 return 0;
2495
2496 entry->size = sizeof(*tlv) + len;
2497
2498 tlv = (void *)entry->data;
2499 tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE);
2500 tlv->len = cpu_to_le32(len);
2501 memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len);
2502
2503 /* add the dump file name extension tlv to the list */
2504 list_add_tail(&entry->list, list);
2505
2506 fwrt->trans->dbg.dump_file_name_ext_valid = false;
2507
2508 return entry->size;
2509 }
2510
2511 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = {
2512 [IWL_FW_INI_REGION_INVALID] = {},
2513 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = {
2514 .get_num_of_ranges = iwl_dump_ini_single_range,
2515 .get_size = iwl_dump_ini_mon_smem_get_size,
2516 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header,
2517 .fill_range = iwl_dump_ini_mon_smem_iter,
2518 },
2519 [IWL_FW_INI_REGION_DRAM_BUFFER] = {
2520 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges,
2521 .get_size = iwl_dump_ini_mon_dram_get_size,
2522 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header,
2523 .fill_range = iwl_dump_ini_mon_dram_iter,
2524 },
2525 [IWL_FW_INI_REGION_TXF] = {
2526 .get_num_of_ranges = iwl_dump_ini_txf_ranges,
2527 .get_size = iwl_dump_ini_txf_get_size,
2528 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2529 .fill_range = iwl_dump_ini_txf_iter,
2530 },
2531 [IWL_FW_INI_REGION_RXF] = {
2532 .get_num_of_ranges = iwl_dump_ini_single_range,
2533 .get_size = iwl_dump_ini_rxf_get_size,
2534 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2535 .fill_range = iwl_dump_ini_rxf_iter,
2536 },
2537 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = {
2538 .get_num_of_ranges = iwl_dump_ini_single_range,
2539 .get_size = iwl_dump_ini_err_table_get_size,
2540 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2541 .fill_range = iwl_dump_ini_err_table_iter,
2542 },
2543 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = {
2544 .get_num_of_ranges = iwl_dump_ini_single_range,
2545 .get_size = iwl_dump_ini_err_table_get_size,
2546 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header,
2547 .fill_range = iwl_dump_ini_err_table_iter,
2548 },
2549 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = {
2550 .get_num_of_ranges = iwl_dump_ini_single_range,
2551 .get_size = iwl_dump_ini_fw_pkt_get_size,
2552 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2553 .fill_range = iwl_dump_ini_fw_pkt_iter,
2554 },
2555 [IWL_FW_INI_REGION_DEVICE_MEMORY] = {
2556 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2557 .get_size = iwl_dump_ini_mem_get_size,
2558 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2559 .fill_range = iwl_dump_ini_dev_mem_iter,
2560 },
2561 [IWL_FW_INI_REGION_PERIPHERY_MAC] = {
2562 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2563 .get_size = iwl_dump_ini_mem_get_size,
2564 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2565 .fill_range = iwl_dump_ini_prph_mac_iter,
2566 },
2567 [IWL_FW_INI_REGION_PERIPHERY_PHY] = {
2568 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2569 .get_size = iwl_dump_ini_mem_get_size,
2570 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2571 .fill_range = iwl_dump_ini_prph_phy_iter,
2572 },
2573 [IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE] = {
2574 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges,
2575 .get_size = iwl_dump_ini_mem_block_get_size,
2576 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2577 .fill_range = iwl_dump_ini_prph_mac_block_iter,
2578 },
2579 [IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE] = {
2580 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges,
2581 .get_size = iwl_dump_ini_mem_block_get_size,
2582 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2583 .fill_range = iwl_dump_ini_prph_phy_block_iter,
2584 },
2585 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {},
2586 [IWL_FW_INI_REGION_PAGING] = {
2587 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2588 .get_num_of_ranges = iwl_dump_ini_paging_ranges,
2589 .get_size = iwl_dump_ini_paging_get_size,
2590 .fill_range = iwl_dump_ini_paging_iter,
2591 },
2592 [IWL_FW_INI_REGION_CSR] = {
2593 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2594 .get_size = iwl_dump_ini_mem_get_size,
2595 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2596 .fill_range = iwl_dump_ini_csr_iter,
2597 },
2598 [IWL_FW_INI_REGION_DRAM_IMR] = {
2599 .get_num_of_ranges = iwl_dump_ini_imr_ranges,
2600 .get_size = iwl_dump_ini_imr_get_size,
2601 .fill_mem_hdr = iwl_dump_ini_imr_fill_header,
2602 .fill_range = iwl_dump_ini_imr_iter,
2603 },
2604 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = {
2605 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2606 .get_size = iwl_dump_ini_mem_get_size,
2607 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2608 .fill_range = iwl_dump_ini_config_iter,
2609 },
2610 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = {
2611 .get_num_of_ranges = iwl_dump_ini_single_range,
2612 .get_size = iwl_dump_ini_special_mem_get_size,
2613 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header,
2614 .fill_range = iwl_dump_ini_special_mem_iter,
2615 },
2616 [IWL_FW_INI_REGION_DBGI_SRAM] = {
2617 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2618 .get_size = iwl_dump_ini_mon_dbgi_get_size,
2619 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header,
2620 .fill_range = iwl_dump_ini_dbgi_sram_iter,
2621 },
2622 [IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = {
2623 .get_num_of_ranges = iwl_dump_ini_mem_ranges,
2624 .get_size = iwl_dump_ini_mem_get_size,
2625 .fill_mem_hdr = iwl_dump_ini_mem_fill_header,
2626 .fill_range = iwl_dump_ini_prph_snps_dphyip_iter,
2627 },
2628 };
2629
2630 enum iwl_dump_ini_region_selector {
2631 IWL_INI_DUMP_ALL_REGIONS,
2632 IWL_INI_DUMP_EARLY_REGIONS,
2633 IWL_INI_DUMP_LATE_REGIONS,
2634 };
2635
iwl_dump_due_to_error(enum iwl_fw_ini_time_point tp_id)2636 static bool iwl_dump_due_to_error(enum iwl_fw_ini_time_point tp_id)
2637 {
2638 return tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT ||
2639 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR;
2640 }
2641
2642 static u32
iwl_dump_ini_dump_regions(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,struct list_head * list,enum iwl_fw_ini_time_point tp_id,u64 regions_mask,struct iwl_dump_ini_region_data * imr_reg_data,enum iwl_dump_ini_region_selector which)2643 iwl_dump_ini_dump_regions(struct iwl_fw_runtime *fwrt,
2644 struct iwl_fwrt_dump_data *dump_data,
2645 struct list_head *list,
2646 enum iwl_fw_ini_time_point tp_id,
2647 u64 regions_mask,
2648 struct iwl_dump_ini_region_data *imr_reg_data,
2649 enum iwl_dump_ini_region_selector which)
2650 {
2651 u32 size = 0;
2652
2653 for (int i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) {
2654 struct iwl_dump_ini_region_data reg_data = {
2655 .dump_data = dump_data,
2656 };
2657 u32 reg_type, dp;
2658 struct iwl_fw_ini_region_tlv *reg;
2659
2660 if (!(BIT_ULL(i) & regions_mask))
2661 continue;
2662
2663 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i];
2664 if (!reg_data.reg_tlv) {
2665 IWL_WARN(fwrt,
2666 "WRT: Unassigned region id %d, skipping\n", i);
2667 continue;
2668 }
2669
2670 reg = (void *)reg_data.reg_tlv->data;
2671 reg_type = reg->type;
2672 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops))
2673 continue;
2674
2675 dp = le32_get_bits(reg->id, IWL_FW_INI_REGION_DUMP_POLICY_MASK);
2676
2677 if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY ||
2678 reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE ||
2679 reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) &&
2680 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) {
2681 IWL_WARN(fwrt,
2682 "WRT: trying to collect phy prph at time point: %d, skipping\n",
2683 tp_id);
2684 continue;
2685 }
2686
2687 switch (which) {
2688 case IWL_INI_DUMP_ALL_REGIONS:
2689 break;
2690 case IWL_INI_DUMP_EARLY_REGIONS:
2691 if (!(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_BEFORE_RESET))
2692 continue;
2693 break;
2694 case IWL_INI_DUMP_LATE_REGIONS:
2695 if (dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_BEFORE_RESET)
2696 continue;
2697 break;
2698 }
2699
2700 /*
2701 * DRAM_IMR can be collected only for FW/HW error timepoint
2702 * when fw is not alive. In addition, it must be collected
2703 * lastly as it overwrites SRAM that can possibly contain
2704 * debug data which also need to be collected.
2705 */
2706 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) {
2707 if (iwl_dump_due_to_error(tp_id))
2708 imr_reg_data->reg_tlv =
2709 fwrt->trans->dbg.active_regions[i];
2710 else
2711 IWL_INFO(fwrt,
2712 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n",
2713 tp_id);
2714 /* continue to next region */
2715 continue;
2716 }
2717
2718
2719 size += iwl_dump_ini_mem(fwrt, list, ®_data,
2720 &iwl_dump_ini_region_ops[reg_type]);
2721 }
2722
2723 return size;
2724 }
2725
iwl_dump_ini_trigger(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,struct list_head * list)2726 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,
2727 struct iwl_fwrt_dump_data *dump_data,
2728 struct list_head *list)
2729 {
2730 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2731 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point);
2732 struct iwl_dump_ini_region_data imr_reg_data = {
2733 .dump_data = dump_data,
2734 };
2735 u32 size = 0;
2736 u64 regions_mask = le64_to_cpu(trigger->regions_mask) &
2737 ~(fwrt->trans->dbg.unsupported_region_msk);
2738
2739 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask));
2740 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) <
2741 ARRAY_SIZE(fwrt->trans->dbg.active_regions));
2742
2743 if (trigger->apply_policy &
2744 cpu_to_le32(IWL_FW_INI_APPLY_POLICY_SPLIT_DUMP_RESET)) {
2745 size += iwl_dump_ini_dump_regions(fwrt, dump_data, list, tp_id,
2746 regions_mask, &imr_reg_data,
2747 IWL_INI_DUMP_EARLY_REGIONS);
2748 iwl_trans_pcie_fw_reset_handshake(fwrt->trans);
2749 size += iwl_dump_ini_dump_regions(fwrt, dump_data, list, tp_id,
2750 regions_mask, &imr_reg_data,
2751 IWL_INI_DUMP_LATE_REGIONS);
2752 } else {
2753 if (fw_has_capa(&fwrt->fw->ucode_capa,
2754 IWL_UCODE_TLV_CAPA_RESET_DURING_ASSERT) &&
2755 iwl_dump_due_to_error(tp_id))
2756 iwl_trans_pcie_fw_reset_handshake(fwrt->trans);
2757 size += iwl_dump_ini_dump_regions(fwrt, dump_data, list, tp_id,
2758 regions_mask, &imr_reg_data,
2759 IWL_INI_DUMP_ALL_REGIONS);
2760 }
2761 /* collect DRAM_IMR region in the last */
2762 if (imr_reg_data.reg_tlv)
2763 size += iwl_dump_ini_mem(fwrt, list, &imr_reg_data,
2764 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]);
2765
2766 if (size) {
2767 size += iwl_dump_ini_file_name_info(fwrt, list);
2768 size += iwl_dump_ini_info(fwrt, trigger, list);
2769 }
2770
2771 return size;
2772 }
2773
iwl_fw_ini_trigger_on(struct iwl_fw_runtime * fwrt,struct iwl_fw_ini_trigger_tlv * trig)2774 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt,
2775 struct iwl_fw_ini_trigger_tlv *trig)
2776 {
2777 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
2778 u32 usec = le32_to_cpu(trig->ignore_consec);
2779
2780 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
2781 tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
2782 tp_id >= IWL_FW_INI_TIME_POINT_NUM ||
2783 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec))
2784 return false;
2785
2786 return true;
2787 }
2788
iwl_dump_ini_file_gen(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,struct list_head * list)2789 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt,
2790 struct iwl_fwrt_dump_data *dump_data,
2791 struct list_head *list)
2792 {
2793 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig;
2794 struct iwl_fw_ini_dump_entry *entry;
2795 struct iwl_fw_ini_dump_file_hdr *hdr;
2796 u32 size;
2797
2798 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) ||
2799 !le64_to_cpu(trigger->regions_mask))
2800 return 0;
2801
2802 entry = vzalloc(sizeof(*entry) + sizeof(*hdr));
2803 if (!entry)
2804 return 0;
2805
2806 entry->size = sizeof(*hdr);
2807
2808 size = iwl_dump_ini_trigger(fwrt, dump_data, list);
2809 if (!size) {
2810 vfree(entry);
2811 return 0;
2812 }
2813
2814 hdr = (void *)entry->data;
2815 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER);
2816 hdr->file_len = cpu_to_le32(size + entry->size);
2817
2818 list_add(&entry->list, list);
2819
2820 return le32_to_cpu(hdr->file_len);
2821 }
2822
iwl_fw_free_dump_desc(struct iwl_fw_runtime * fwrt,const struct iwl_fw_dump_desc * desc)2823 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt,
2824 const struct iwl_fw_dump_desc *desc)
2825 {
2826 if (desc && desc != &iwl_dump_desc_assert)
2827 kfree(desc);
2828
2829 fwrt->dump.lmac_err_id[0] = 0;
2830 if (fwrt->smem_cfg.num_lmacs > 1)
2831 fwrt->dump.lmac_err_id[1] = 0;
2832 fwrt->dump.umac_err_id = 0;
2833 }
2834
iwl_fw_error_dump(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data)2835 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt,
2836 struct iwl_fwrt_dump_data *dump_data)
2837 {
2838 struct iwl_fw_dump_ptrs fw_error_dump = {};
2839 struct iwl_fw_error_dump_file *dump_file;
2840 struct scatterlist *sg_dump_data;
2841 u32 file_len;
2842 u32 dump_mask = fwrt->fw->dbg.dump_mask;
2843
2844 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data);
2845 if (!dump_file)
2846 return;
2847
2848 if (dump_data->monitor_only)
2849 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR);
2850
2851 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask,
2852 fwrt->sanitize_ops,
2853 fwrt->sanitize_ctx);
2854 file_len = le32_to_cpu(dump_file->file_len);
2855 fw_error_dump.fwrt_len = file_len;
2856
2857 if (fw_error_dump.trans_ptr) {
2858 file_len += fw_error_dump.trans_ptr->len;
2859 dump_file->file_len = cpu_to_le32(file_len);
2860 }
2861
2862 sg_dump_data = alloc_sgtable(file_len);
2863 if (sg_dump_data) {
2864 sg_pcopy_from_buffer(sg_dump_data,
2865 sg_nents(sg_dump_data),
2866 fw_error_dump.fwrt_ptr,
2867 fw_error_dump.fwrt_len, 0);
2868 if (fw_error_dump.trans_ptr)
2869 sg_pcopy_from_buffer(sg_dump_data,
2870 sg_nents(sg_dump_data),
2871 fw_error_dump.trans_ptr->data,
2872 fw_error_dump.trans_ptr->len,
2873 fw_error_dump.fwrt_len);
2874 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2875 GFP_KERNEL);
2876 }
2877 vfree(fw_error_dump.fwrt_ptr);
2878 vfree(fw_error_dump.trans_ptr);
2879 }
2880
iwl_dump_ini_list_free(struct list_head * list)2881 static void iwl_dump_ini_list_free(struct list_head *list)
2882 {
2883 while (!list_empty(list)) {
2884 struct iwl_fw_ini_dump_entry *entry =
2885 list_entry(list->next, typeof(*entry), list);
2886
2887 list_del(&entry->list);
2888 vfree(entry);
2889 }
2890 }
2891
iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data * dump_data)2892 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data)
2893 {
2894 dump_data->trig = NULL;
2895 kfree(dump_data->fw_pkt);
2896 dump_data->fw_pkt = NULL;
2897 }
2898
iwl_fw_error_ini_dump(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data)2899 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt,
2900 struct iwl_fwrt_dump_data *dump_data)
2901 {
2902 LIST_HEAD(dump_list);
2903 struct scatterlist *sg_dump_data;
2904 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list);
2905
2906 if (!file_len)
2907 return;
2908
2909 sg_dump_data = alloc_sgtable(file_len);
2910 if (sg_dump_data) {
2911 struct iwl_fw_ini_dump_entry *entry;
2912 int sg_entries = sg_nents(sg_dump_data);
2913 u32 offs = 0;
2914
2915 list_for_each_entry(entry, &dump_list, list) {
2916 sg_pcopy_from_buffer(sg_dump_data, sg_entries,
2917 entry->data, entry->size, offs);
2918 offs += entry->size;
2919 }
2920 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len,
2921 GFP_KERNEL);
2922 }
2923 iwl_dump_ini_list_free(&dump_list);
2924 }
2925
2926 const struct iwl_fw_dump_desc iwl_dump_desc_assert = {
2927 .trig_desc = {
2928 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
2929 },
2930 };
2931 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert);
2932
iwl_fw_dbg_collect_desc(struct iwl_fw_runtime * fwrt,const struct iwl_fw_dump_desc * desc,bool monitor_only,unsigned int delay)2933 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt,
2934 const struct iwl_fw_dump_desc *desc,
2935 bool monitor_only,
2936 unsigned int delay)
2937 {
2938 struct iwl_fwrt_wk_data *wk_data;
2939 unsigned long idx;
2940
2941 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2942 iwl_fw_free_dump_desc(fwrt, desc);
2943 return 0;
2944 }
2945
2946 /*
2947 * Check there is an available worker.
2948 * ffz return value is undefined if no zero exists,
2949 * so check against ~0UL first.
2950 */
2951 if (fwrt->dump.active_wks == ~0UL)
2952 return -EBUSY;
2953
2954 idx = ffz(fwrt->dump.active_wks);
2955
2956 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
2957 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
2958 return -EBUSY;
2959
2960 wk_data = &fwrt->dump.wks[idx];
2961
2962 if (WARN_ON(wk_data->dump_data.desc))
2963 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc);
2964
2965 wk_data->dump_data.desc = desc;
2966 wk_data->dump_data.monitor_only = monitor_only;
2967
2968 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n",
2969 le32_to_cpu(desc->trig_desc.type));
2970
2971 queue_delayed_work(system_unbound_wq, &wk_data->wk,
2972 usecs_to_jiffies(delay));
2973
2974 return 0;
2975 }
2976 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc);
2977
iwl_fw_dbg_error_collect(struct iwl_fw_runtime * fwrt,enum iwl_fw_dbg_trigger trig_type)2978 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt,
2979 enum iwl_fw_dbg_trigger trig_type)
2980 {
2981 if (!iwl_trans_device_enabled(fwrt->trans))
2982 return -EIO;
2983
2984 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
2985 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT &&
2986 trig_type != FW_DBG_TRIGGER_DRIVER)
2987 return -EIO;
2988
2989 iwl_dbg_tlv_time_point(fwrt,
2990 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT,
2991 NULL);
2992 } else {
2993 struct iwl_fw_dump_desc *iwl_dump_error_desc;
2994 int ret;
2995
2996 iwl_dump_error_desc =
2997 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL);
2998
2999 if (!iwl_dump_error_desc)
3000 return -ENOMEM;
3001
3002 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type);
3003 iwl_dump_error_desc->len = 0;
3004
3005 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc,
3006 false, 0);
3007 if (ret) {
3008 kfree(iwl_dump_error_desc);
3009 return ret;
3010 }
3011 }
3012
3013 iwl_trans_sync_nmi(fwrt->trans);
3014
3015 return 0;
3016 }
3017 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect);
3018
iwl_fw_dbg_collect(struct iwl_fw_runtime * fwrt,enum iwl_fw_dbg_trigger trig,const char * str,size_t len,struct iwl_fw_dbg_trigger_tlv * trigger)3019 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt,
3020 enum iwl_fw_dbg_trigger trig,
3021 const char *str, size_t len,
3022 struct iwl_fw_dbg_trigger_tlv *trigger)
3023 {
3024 struct iwl_fw_dump_desc *desc;
3025 unsigned int delay = 0;
3026 bool monitor_only = false;
3027 int ret;
3028
3029 if (trigger) {
3030 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1;
3031
3032 if (!le16_to_cpu(trigger->occurrences))
3033 return 0;
3034
3035 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) {
3036 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n",
3037 trig);
3038 iwl_force_nmi(fwrt->trans);
3039 return 0;
3040 }
3041
3042 trigger->occurrences = cpu_to_le16(occurrences);
3043 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY;
3044
3045 /* convert msec to usec */
3046 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC;
3047 }
3048
3049 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC);
3050 if (!desc)
3051 return -ENOMEM;
3052
3053
3054 desc->len = len;
3055 desc->trig_desc.type = cpu_to_le32(trig);
3056 memcpy(desc->trig_desc.data, str, len);
3057
3058 ret = iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay);
3059 if (ret)
3060 kfree(desc);
3061
3062 return ret;
3063 }
3064 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect);
3065
iwl_fw_dbg_collect_trig(struct iwl_fw_runtime * fwrt,struct iwl_fw_dbg_trigger_tlv * trigger,const char * fmt,...)3066 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt,
3067 struct iwl_fw_dbg_trigger_tlv *trigger,
3068 const char *fmt, ...)
3069 {
3070 int len = 0;
3071 char buf[64];
3072
3073 if (iwl_trans_dbg_ini_valid(fwrt->trans))
3074 return 0;
3075
3076 if (fmt) {
3077 va_list ap;
3078
3079 buf[sizeof(buf) - 1] = '\0';
3080
3081 va_start(ap, fmt);
3082 vsnprintf(buf, sizeof(buf), fmt, ap);
3083 va_end(ap);
3084
3085 /* check for truncation */
3086 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
3087 buf[sizeof(buf) - 1] = '\0';
3088
3089 len = strlen(buf) + 1;
3090 }
3091
3092 return iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len,
3093 trigger);
3094 }
3095 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig);
3096
iwl_fw_start_dbg_conf(struct iwl_fw_runtime * fwrt,u8 conf_id)3097 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
3098 {
3099 u8 *ptr;
3100 int ret;
3101 int i;
3102
3103 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv),
3104 "Invalid configuration %d\n", conf_id))
3105 return -EINVAL;
3106
3107 /* EARLY START - firmware's configuration is hard coded */
3108 if ((!fwrt->fw->dbg.conf_tlv[conf_id] ||
3109 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) &&
3110 conf_id == FW_DBG_START_FROM_ALIVE)
3111 return 0;
3112
3113 if (!fwrt->fw->dbg.conf_tlv[conf_id])
3114 return -EINVAL;
3115
3116 if (fwrt->dump.conf != FW_DBG_INVALID)
3117 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n",
3118 fwrt->dump.conf);
3119
3120 /* Send all HCMDs for configuring the FW debug */
3121 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd;
3122 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
3123 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
3124 struct iwl_host_cmd hcmd = {
3125 .id = cmd->id,
3126 .len = { le16_to_cpu(cmd->len), },
3127 .data = { cmd->data, },
3128 };
3129
3130 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
3131 if (ret)
3132 return ret;
3133
3134 ptr += sizeof(*cmd);
3135 ptr += le16_to_cpu(cmd->len);
3136 }
3137
3138 fwrt->dump.conf = conf_id;
3139
3140 return 0;
3141 }
3142 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf);
3143
iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime * fwrt,u32 timepoint,u32 timepoint_data)3144 static void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt,
3145 u32 timepoint, u32 timepoint_data)
3146 {
3147 struct iwl_dbg_dump_complete_cmd hcmd_data;
3148 struct iwl_host_cmd hcmd = {
3149 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD),
3150 .data[0] = &hcmd_data,
3151 .len[0] = sizeof(hcmd_data),
3152 };
3153
3154 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status))
3155 return;
3156
3157 if (fw_has_capa(&fwrt->fw->ucode_capa,
3158 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) {
3159 hcmd_data.tp = cpu_to_le32(timepoint);
3160 hcmd_data.tp_data = cpu_to_le32(timepoint_data);
3161 iwl_trans_send_cmd(fwrt->trans, &hcmd);
3162 }
3163 }
3164
3165 /* this function assumes dump_start was called beforehand and dump_end will be
3166 * called afterwards
3167 */
iwl_fw_dbg_collect_sync(struct iwl_fw_runtime * fwrt,u8 wk_idx)3168 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx)
3169 {
3170 struct iwl_fw_dbg_params params = {0};
3171 struct iwl_fwrt_dump_data *dump_data =
3172 &fwrt->dump.wks[wk_idx].dump_data;
3173
3174 if (!test_bit(wk_idx, &fwrt->dump.active_wks))
3175 return;
3176
3177 /* also checks 'desc' for pre-ini mode, since that shadows in union */
3178 if (!dump_data->trig) {
3179 IWL_ERR(fwrt, "dump trigger data is not set\n");
3180 goto out;
3181 }
3182
3183 if (!iwl_trans_device_enabled(fwrt->trans)) {
3184 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n");
3185 goto out;
3186 }
3187
3188 /* there's no point in fw dump if the bus is dead */
3189 if (iwl_trans_is_dead(fwrt->trans)) {
3190 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n");
3191 goto out;
3192 }
3193
3194 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true);
3195
3196 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n");
3197 if (iwl_trans_dbg_ini_valid(fwrt->trans))
3198 iwl_fw_error_ini_dump(fwrt, dump_data);
3199 else
3200 iwl_fw_error_dump(fwrt, dump_data);
3201 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n");
3202
3203 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false);
3204
3205 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
3206 u32 policy = le32_to_cpu(dump_data->trig->apply_policy);
3207 u32 time_point = le32_to_cpu(dump_data->trig->time_point);
3208
3209 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) {
3210 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n");
3211 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0);
3212 }
3213 }
3214
3215 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY)
3216 iwl_force_nmi(fwrt->trans);
3217 out:
3218 if (iwl_trans_dbg_ini_valid(fwrt->trans)) {
3219 iwl_fw_error_dump_data_free(dump_data);
3220 } else {
3221 iwl_fw_free_dump_desc(fwrt, dump_data->desc);
3222 dump_data->desc = NULL;
3223 }
3224
3225 clear_bit(wk_idx, &fwrt->dump.active_wks);
3226 }
3227
iwl_fw_dbg_ini_collect(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,bool sync)3228 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt,
3229 struct iwl_fwrt_dump_data *dump_data,
3230 bool sync)
3231 {
3232 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig;
3233 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point);
3234 u32 occur, delay;
3235 unsigned long idx;
3236
3237 if (!iwl_fw_ini_trigger_on(fwrt, trig)) {
3238 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n",
3239 tp_id);
3240 return -EINVAL;
3241 }
3242
3243 delay = le32_to_cpu(trig->dump_delay);
3244 occur = le32_to_cpu(trig->occurrences);
3245 if (!occur)
3246 return 0;
3247
3248 trig->occurrences = cpu_to_le32(--occur);
3249
3250 /* Check there is an available worker.
3251 * ffz return value is undefined if no zero exists,
3252 * so check against ~0UL first.
3253 */
3254 if (fwrt->dump.active_wks == ~0UL)
3255 return -EBUSY;
3256
3257 idx = ffz(fwrt->dump.active_wks);
3258
3259 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM ||
3260 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks))
3261 return -EBUSY;
3262
3263 fwrt->dump.wks[idx].dump_data = *dump_data;
3264
3265 if (sync)
3266 delay = 0;
3267
3268 IWL_WARN(fwrt,
3269 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n",
3270 tp_id, (u32)(delay / USEC_PER_MSEC));
3271
3272 if (sync)
3273 iwl_fw_dbg_collect_sync(fwrt, idx);
3274 else
3275 queue_delayed_work(system_unbound_wq,
3276 &fwrt->dump.wks[idx].wk,
3277 usecs_to_jiffies(delay));
3278
3279 return 0;
3280 }
3281
iwl_fw_error_dump_wk(struct work_struct * work)3282 void iwl_fw_error_dump_wk(struct work_struct *work)
3283 {
3284 struct iwl_fwrt_wk_data *wks =
3285 container_of(work, typeof(*wks), wk.work);
3286 struct iwl_fw_runtime *fwrt =
3287 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]);
3288
3289 /* assumes the op mode mutex is locked in dump_start since
3290 * iwl_fw_dbg_collect_sync can't run in parallel
3291 */
3292 if (fwrt->ops && fwrt->ops->dump_start)
3293 fwrt->ops->dump_start(fwrt->ops_ctx);
3294
3295 iwl_fw_dbg_collect_sync(fwrt, wks->idx);
3296
3297 if (fwrt->ops && fwrt->ops->dump_end)
3298 fwrt->ops->dump_end(fwrt->ops_ctx);
3299 }
3300
iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime * fwrt)3301 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt)
3302 {
3303 const struct iwl_mac_cfg *mac_cfg = fwrt->trans->mac_cfg;
3304
3305 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt))
3306 return;
3307
3308 if (!fwrt->dump.d3_debug_data) {
3309 fwrt->dump.d3_debug_data = kmalloc(mac_cfg->base->d3_debug_data_length,
3310 GFP_KERNEL);
3311 if (!fwrt->dump.d3_debug_data) {
3312 IWL_ERR(fwrt,
3313 "failed to allocate memory for D3 debug data\n");
3314 return;
3315 }
3316 }
3317
3318 /* if the buffer holds previous debug data it is overwritten */
3319 iwl_trans_read_mem_bytes(fwrt->trans, mac_cfg->base->d3_debug_data_base_addr,
3320 fwrt->dump.d3_debug_data,
3321 mac_cfg->base->d3_debug_data_length);
3322
3323 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem)
3324 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx,
3325 mac_cfg->base->d3_debug_data_base_addr,
3326 fwrt->dump.d3_debug_data,
3327 mac_cfg->base->d3_debug_data_length);
3328 }
3329 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data);
3330
iwl_fw_dbg_stop_sync(struct iwl_fw_runtime * fwrt)3331 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt)
3332 {
3333 int i;
3334
3335 iwl_dbg_tlv_del_timers(fwrt->trans);
3336 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++)
3337 iwl_fw_dbg_collect_sync(fwrt, i);
3338
3339 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true);
3340 }
3341 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync);
3342
iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans * trans,bool suspend)3343 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend)
3344 {
3345 struct iwl_dbg_suspend_resume_cmd cmd = {
3346 .operation = suspend ?
3347 cpu_to_le32(DBGC_SUSPEND_CMD) :
3348 cpu_to_le32(DBGC_RESUME_CMD),
3349 };
3350 struct iwl_host_cmd hcmd = {
3351 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME),
3352 .data[0] = &cmd,
3353 .len[0] = sizeof(cmd),
3354 };
3355
3356 return iwl_trans_send_cmd(trans, &hcmd);
3357 }
3358
iwl_fw_dbg_stop_recording(struct iwl_trans * trans,struct iwl_fw_dbg_params * params)3359 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans,
3360 struct iwl_fw_dbg_params *params)
3361 {
3362 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
3363 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
3364 return;
3365 }
3366
3367 if (params) {
3368 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE);
3369 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL);
3370 }
3371
3372 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
3373 /* wait for the DBGC to finish writing the internal buffer to DRAM to
3374 * avoid halting the HW while writing
3375 */
3376 usleep_range(700, 1000);
3377 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
3378 }
3379
iwl_fw_dbg_restart_recording(struct iwl_trans * trans,struct iwl_fw_dbg_params * params)3380 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans,
3381 struct iwl_fw_dbg_params *params)
3382 {
3383 if (!params)
3384 return -EIO;
3385
3386 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
3387 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
3388 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
3389 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
3390 } else {
3391 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample);
3392 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl);
3393 }
3394
3395 return 0;
3396 }
3397
iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime * fwrt)3398 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt)
3399 {
3400 struct iwl_mvm_marker marker = {
3401 .dw_len = sizeof(struct iwl_mvm_marker) / 4,
3402 .marker_id = MARKER_ID_SYNC_CLOCK,
3403 };
3404 struct iwl_host_cmd hcmd = {
3405 .flags = CMD_ASYNC,
3406 .id = WIDE_ID(LONG_GROUP, MARKER_CMD),
3407 .dataflags = {},
3408 };
3409 struct iwl_mvm_marker_rsp *resp;
3410 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw,
3411 WIDE_ID(LONG_GROUP, MARKER_CMD),
3412 IWL_FW_CMD_VER_UNKNOWN);
3413 int ret;
3414
3415 if (cmd_ver == 1) {
3416 /* the real timestamp is taken from the ftrace clock
3417 * this is for finding the match between fw and kernel logs
3418 */
3419 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++);
3420 } else if (cmd_ver == 2) {
3421 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns());
3422 } else {
3423 IWL_DEBUG_INFO(fwrt,
3424 "Invalid version of Marker CMD. Ver = %d\n",
3425 cmd_ver);
3426 return -EINVAL;
3427 }
3428
3429 hcmd.data[0] = ▮
3430 hcmd.len[0] = sizeof(marker);
3431
3432 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
3433
3434 if (cmd_ver > 1 && hcmd.resp_pkt) {
3435 resp = (void *)hcmd.resp_pkt->data;
3436 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n",
3437 le32_to_cpu(resp->gp2));
3438 }
3439
3440 return ret;
3441 }
3442
iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime * fwrt,struct iwl_fw_dbg_params * params,bool stop)3443 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt,
3444 struct iwl_fw_dbg_params *params,
3445 bool stop)
3446 {
3447 int ret __maybe_unused = 0;
3448
3449 if (!iwl_trans_fw_running(fwrt->trans))
3450 return;
3451
3452 if (fw_has_capa(&fwrt->fw->ucode_capa,
3453 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) {
3454 if (stop)
3455 iwl_fw_send_timestamp_marker_cmd(fwrt);
3456 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop);
3457 } else if (stop) {
3458 iwl_fw_dbg_stop_recording(fwrt->trans, params);
3459 } else {
3460 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params);
3461 }
3462 #ifdef CONFIG_IWLWIFI_DEBUGFS
3463 if (!ret) {
3464 if (stop)
3465 fwrt->trans->dbg.rec_on = false;
3466 else
3467 iwl_fw_set_dbg_rec_on(fwrt);
3468 }
3469 #endif
3470 }
3471 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording);
3472
iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime * fwrt)3473 void iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime *fwrt)
3474 {
3475 struct iwl_fw_dbg_config_cmd cmd = {
3476 .type = cpu_to_le32(DEBUG_TOKEN_CONFIG_TYPE),
3477 .conf = cpu_to_le32(IWL_FW_DBG_CONFIG_TOKEN),
3478 };
3479 struct iwl_host_cmd hcmd = {
3480 .id = WIDE_ID(LONG_GROUP, LDBG_CONFIG_CMD),
3481 .data[0] = &cmd,
3482 .len[0] = sizeof(cmd),
3483 };
3484 u32 preset = u32_get_bits(fwrt->trans->dbg.domains_bitmap,
3485 GENMASK(31, IWL_FW_DBG_DOMAIN_POS + 1));
3486
3487 /* supported starting from 9000 devices */
3488 if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_9000)
3489 return;
3490
3491 if (fwrt->trans->dbg.yoyo_bin_loaded || (preset && preset != 1))
3492 return;
3493
3494 iwl_trans_send_cmd(fwrt->trans, &hcmd);
3495 }
3496 IWL_EXPORT_SYMBOL(iwl_fw_disable_dbg_asserts);
3497
iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime * fwrt)3498 void iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime *fwrt)
3499 {
3500 struct iwl_fw_dbg_params params = {0};
3501
3502 iwl_fw_dbg_stop_sync(fwrt);
3503
3504 if (fw_has_api(&fwrt->fw->ucode_capa,
3505 IWL_UCODE_TLV_API_INT_DBG_BUF_CLEAR)) {
3506 struct iwl_host_cmd hcmd = {
3507 .id = WIDE_ID(DEBUG_GROUP, FW_CLEAR_BUFFER),
3508 };
3509 iwl_trans_send_cmd(fwrt->trans, &hcmd);
3510 }
3511
3512 iwl_dbg_tlv_init_cfg(fwrt);
3513 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false);
3514 }
3515 IWL_EXPORT_SYMBOL(iwl_fw_dbg_clear_monitor_buf);
3516