1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #if defined(__FreeBSD__) 9 #include <linux/delay.h> 10 #endif 11 #include "iwl-drv.h" 12 #include "runtime.h" 13 #include "dbg.h" 14 #include "debugfs.h" 15 #include "iwl-io.h" 16 #include "iwl-prph.h" 17 #include "iwl-csr.h" 18 #include "iwl-fh.h" 19 /** 20 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 21 * 22 * @fwrt_ptr: pointer to the buffer coming from fwrt 23 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 24 * transport's data. 25 * @fwrt_len: length of the valid data in fwrt_ptr 26 */ 27 struct iwl_fw_dump_ptrs { 28 struct iwl_trans_dump_data *trans_ptr; 29 void *fwrt_ptr; 30 u32 fwrt_len; 31 }; 32 33 #define RADIO_REG_MAX_READ 0x2ad 34 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 35 struct iwl_fw_error_dump_data **dump_data) 36 { 37 u8 *pos = (void *)(*dump_data)->data; 38 int i; 39 40 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 41 42 if (!iwl_trans_grab_nic_access(fwrt->trans)) 43 return; 44 45 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 46 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 47 48 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 49 u32 rd_cmd = RADIO_RSP_RD_CMD; 50 51 rd_cmd |= i << RADIO_RSP_ADDR_POS; 52 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 53 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 54 55 pos++; 56 } 57 58 *dump_data = iwl_fw_error_next_data(*dump_data); 59 60 iwl_trans_release_nic_access(fwrt->trans); 61 } 62 63 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 64 struct iwl_fw_error_dump_data **dump_data, 65 int size, u32 offset, int fifo_num) 66 { 67 struct iwl_fw_error_dump_fifo *fifo_hdr; 68 u32 *fifo_data; 69 u32 fifo_len; 70 int i; 71 72 fifo_hdr = (void *)(*dump_data)->data; 73 fifo_data = (void *)fifo_hdr->data; 74 fifo_len = size; 75 76 /* No need to try to read the data if the length is 0 */ 77 if (fifo_len == 0) 78 return; 79 80 /* Add a TLV for the RXF */ 81 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 82 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 83 84 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 85 fifo_hdr->available_bytes = 86 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 87 RXF_RD_D_SPACE + offset)); 88 fifo_hdr->wr_ptr = 89 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 90 RXF_RD_WR_PTR + offset)); 91 fifo_hdr->rd_ptr = 92 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 93 RXF_RD_RD_PTR + offset)); 94 fifo_hdr->fence_ptr = 95 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 96 RXF_RD_FENCE_PTR + offset)); 97 fifo_hdr->fence_mode = 98 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 99 RXF_SET_FENCE_MODE + offset)); 100 101 /* Lock fence */ 102 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 103 /* Set fence pointer to the same place like WR pointer */ 104 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 105 /* Set fence offset */ 106 iwl_trans_write_prph(fwrt->trans, 107 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 108 109 /* Read FIFO */ 110 fifo_len /= sizeof(u32); /* Size in DWORDS */ 111 for (i = 0; i < fifo_len; i++) 112 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 113 RXF_FIFO_RD_FENCE_INC + 114 offset); 115 *dump_data = iwl_fw_error_next_data(*dump_data); 116 } 117 118 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 119 struct iwl_fw_error_dump_data **dump_data, 120 int size, u32 offset, int fifo_num) 121 { 122 struct iwl_fw_error_dump_fifo *fifo_hdr; 123 u32 *fifo_data; 124 u32 fifo_len; 125 int i; 126 127 fifo_hdr = (void *)(*dump_data)->data; 128 fifo_data = (void *)fifo_hdr->data; 129 fifo_len = size; 130 131 /* No need to try to read the data if the length is 0 */ 132 if (fifo_len == 0) 133 return; 134 135 /* Add a TLV for the FIFO */ 136 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 137 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 138 139 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 140 fifo_hdr->available_bytes = 141 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 142 TXF_FIFO_ITEM_CNT + offset)); 143 fifo_hdr->wr_ptr = 144 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 145 TXF_WR_PTR + offset)); 146 fifo_hdr->rd_ptr = 147 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 148 TXF_RD_PTR + offset)); 149 fifo_hdr->fence_ptr = 150 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 151 TXF_FENCE_PTR + offset)); 152 fifo_hdr->fence_mode = 153 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 154 TXF_LOCK_FENCE + offset)); 155 156 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 157 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 158 TXF_WR_PTR + offset); 159 160 /* Dummy-read to advance the read pointer to the head */ 161 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 162 163 /* Read FIFO */ 164 for (i = 0; i < fifo_len / sizeof(u32); i++) 165 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 166 TXF_READ_MODIFY_DATA + 167 offset); 168 169 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 170 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 171 fifo_data, fifo_len); 172 173 *dump_data = iwl_fw_error_next_data(*dump_data); 174 } 175 176 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 177 struct iwl_fw_error_dump_data **dump_data) 178 { 179 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 180 181 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 182 183 if (!iwl_trans_grab_nic_access(fwrt->trans)) 184 return; 185 186 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 187 /* Pull RXF1 */ 188 iwl_fwrt_dump_rxf(fwrt, dump_data, 189 cfg->lmac[0].rxfifo1_size, 0, 0); 190 /* Pull RXF2 */ 191 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 192 RXF_DIFF_FROM_PREV + 193 fwrt->trans->trans_cfg->umac_prph_offset, 1); 194 /* Pull LMAC2 RXF1 */ 195 if (fwrt->smem_cfg.num_lmacs > 1) 196 iwl_fwrt_dump_rxf(fwrt, dump_data, 197 cfg->lmac[1].rxfifo1_size, 198 LMAC2_PRPH_OFFSET, 2); 199 } 200 201 iwl_trans_release_nic_access(fwrt->trans); 202 } 203 204 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 205 struct iwl_fw_error_dump_data **dump_data) 206 { 207 struct iwl_fw_error_dump_fifo *fifo_hdr; 208 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 209 u32 *fifo_data; 210 u32 fifo_len; 211 int i, j; 212 213 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 214 215 if (!iwl_trans_grab_nic_access(fwrt->trans)) 216 return; 217 218 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 219 /* Pull TXF data from LMAC1 */ 220 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 221 /* Mark the number of TXF we're pulling now */ 222 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 223 iwl_fwrt_dump_txf(fwrt, dump_data, 224 cfg->lmac[0].txfifo_size[i], 0, i); 225 } 226 227 /* Pull TXF data from LMAC2 */ 228 if (fwrt->smem_cfg.num_lmacs > 1) { 229 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 230 i++) { 231 /* Mark the number of TXF we're pulling now */ 232 iwl_trans_write_prph(fwrt->trans, 233 TXF_LARC_NUM + 234 LMAC2_PRPH_OFFSET, i); 235 iwl_fwrt_dump_txf(fwrt, dump_data, 236 cfg->lmac[1].txfifo_size[i], 237 LMAC2_PRPH_OFFSET, 238 i + cfg->num_txfifo_entries); 239 } 240 } 241 } 242 243 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 244 fw_has_capa(&fwrt->fw->ucode_capa, 245 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 246 /* Pull UMAC internal TXF data from all TXFs */ 247 for (i = 0; 248 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 249 i++) { 250 fifo_hdr = (void *)(*dump_data)->data; 251 fifo_data = (void *)fifo_hdr->data; 252 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 253 254 /* No need to try to read the data if the length is 0 */ 255 if (fifo_len == 0) 256 continue; 257 258 /* Add a TLV for the internal FIFOs */ 259 (*dump_data)->type = 260 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 261 (*dump_data)->len = 262 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 263 264 fifo_hdr->fifo_num = cpu_to_le32(i); 265 266 /* Mark the number of TXF we're pulling now */ 267 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 268 fwrt->smem_cfg.num_txfifo_entries); 269 270 fifo_hdr->available_bytes = 271 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 272 TXF_CPU2_FIFO_ITEM_CNT)); 273 fifo_hdr->wr_ptr = 274 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 275 TXF_CPU2_WR_PTR)); 276 fifo_hdr->rd_ptr = 277 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 278 TXF_CPU2_RD_PTR)); 279 fifo_hdr->fence_ptr = 280 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 281 TXF_CPU2_FENCE_PTR)); 282 fifo_hdr->fence_mode = 283 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 284 TXF_CPU2_LOCK_FENCE)); 285 286 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 287 iwl_trans_write_prph(fwrt->trans, 288 TXF_CPU2_READ_MODIFY_ADDR, 289 TXF_CPU2_WR_PTR); 290 291 /* Dummy-read to advance the read pointer to head */ 292 iwl_trans_read_prph(fwrt->trans, 293 TXF_CPU2_READ_MODIFY_DATA); 294 295 /* Read FIFO */ 296 fifo_len /= sizeof(u32); /* Size in DWORDS */ 297 for (j = 0; j < fifo_len; j++) 298 fifo_data[j] = 299 iwl_trans_read_prph(fwrt->trans, 300 TXF_CPU2_READ_MODIFY_DATA); 301 *dump_data = iwl_fw_error_next_data(*dump_data); 302 } 303 } 304 305 iwl_trans_release_nic_access(fwrt->trans); 306 } 307 308 struct iwl_prph_range { 309 u32 start, end; 310 }; 311 312 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 313 { .start = 0x00a00000, .end = 0x00a00000 }, 314 { .start = 0x00a0000c, .end = 0x00a00024 }, 315 { .start = 0x00a0002c, .end = 0x00a0003c }, 316 { .start = 0x00a00410, .end = 0x00a00418 }, 317 { .start = 0x00a00420, .end = 0x00a00420 }, 318 { .start = 0x00a00428, .end = 0x00a00428 }, 319 { .start = 0x00a00430, .end = 0x00a0043c }, 320 { .start = 0x00a00444, .end = 0x00a00444 }, 321 { .start = 0x00a004c0, .end = 0x00a004cc }, 322 { .start = 0x00a004d8, .end = 0x00a004d8 }, 323 { .start = 0x00a004e0, .end = 0x00a004f0 }, 324 { .start = 0x00a00840, .end = 0x00a00840 }, 325 { .start = 0x00a00850, .end = 0x00a00858 }, 326 { .start = 0x00a01004, .end = 0x00a01008 }, 327 { .start = 0x00a01010, .end = 0x00a01010 }, 328 { .start = 0x00a01018, .end = 0x00a01018 }, 329 { .start = 0x00a01024, .end = 0x00a01024 }, 330 { .start = 0x00a0102c, .end = 0x00a01034 }, 331 { .start = 0x00a0103c, .end = 0x00a01040 }, 332 { .start = 0x00a01048, .end = 0x00a01094 }, 333 { .start = 0x00a01c00, .end = 0x00a01c20 }, 334 { .start = 0x00a01c58, .end = 0x00a01c58 }, 335 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 336 { .start = 0x00a01c28, .end = 0x00a01c54 }, 337 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 338 { .start = 0x00a01c60, .end = 0x00a01cdc }, 339 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 340 { .start = 0x00a01d18, .end = 0x00a01d20 }, 341 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 342 { .start = 0x00a01d40, .end = 0x00a01d5c }, 343 { .start = 0x00a01d80, .end = 0x00a01d80 }, 344 { .start = 0x00a01d98, .end = 0x00a01d9c }, 345 { .start = 0x00a01da8, .end = 0x00a01da8 }, 346 { .start = 0x00a01db8, .end = 0x00a01df4 }, 347 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 348 { .start = 0x00a01e00, .end = 0x00a01e2c }, 349 { .start = 0x00a01e40, .end = 0x00a01e60 }, 350 { .start = 0x00a01e68, .end = 0x00a01e6c }, 351 { .start = 0x00a01e74, .end = 0x00a01e74 }, 352 { .start = 0x00a01e84, .end = 0x00a01e90 }, 353 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 354 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 355 { .start = 0x00a01f00, .end = 0x00a01f1c }, 356 { .start = 0x00a01f44, .end = 0x00a01ffc }, 357 { .start = 0x00a02000, .end = 0x00a02048 }, 358 { .start = 0x00a02068, .end = 0x00a020f0 }, 359 { .start = 0x00a02100, .end = 0x00a02118 }, 360 { .start = 0x00a02140, .end = 0x00a0214c }, 361 { .start = 0x00a02168, .end = 0x00a0218c }, 362 { .start = 0x00a021c0, .end = 0x00a021c0 }, 363 { .start = 0x00a02400, .end = 0x00a02410 }, 364 { .start = 0x00a02418, .end = 0x00a02420 }, 365 { .start = 0x00a02428, .end = 0x00a0242c }, 366 { .start = 0x00a02434, .end = 0x00a02434 }, 367 { .start = 0x00a02440, .end = 0x00a02460 }, 368 { .start = 0x00a02468, .end = 0x00a024b0 }, 369 { .start = 0x00a024c8, .end = 0x00a024cc }, 370 { .start = 0x00a02500, .end = 0x00a02504 }, 371 { .start = 0x00a0250c, .end = 0x00a02510 }, 372 { .start = 0x00a02540, .end = 0x00a02554 }, 373 { .start = 0x00a02580, .end = 0x00a025f4 }, 374 { .start = 0x00a02600, .end = 0x00a0260c }, 375 { .start = 0x00a02648, .end = 0x00a02650 }, 376 { .start = 0x00a02680, .end = 0x00a02680 }, 377 { .start = 0x00a026c0, .end = 0x00a026d0 }, 378 { .start = 0x00a02700, .end = 0x00a0270c }, 379 { .start = 0x00a02804, .end = 0x00a02804 }, 380 { .start = 0x00a02818, .end = 0x00a0281c }, 381 { .start = 0x00a02c00, .end = 0x00a02db4 }, 382 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 383 { .start = 0x00a03000, .end = 0x00a03014 }, 384 { .start = 0x00a0301c, .end = 0x00a0302c }, 385 { .start = 0x00a03034, .end = 0x00a03038 }, 386 { .start = 0x00a03040, .end = 0x00a03048 }, 387 { .start = 0x00a03060, .end = 0x00a03068 }, 388 { .start = 0x00a03070, .end = 0x00a03074 }, 389 { .start = 0x00a0307c, .end = 0x00a0307c }, 390 { .start = 0x00a03080, .end = 0x00a03084 }, 391 { .start = 0x00a0308c, .end = 0x00a03090 }, 392 { .start = 0x00a03098, .end = 0x00a03098 }, 393 { .start = 0x00a030a0, .end = 0x00a030a0 }, 394 { .start = 0x00a030a8, .end = 0x00a030b4 }, 395 { .start = 0x00a030bc, .end = 0x00a030bc }, 396 { .start = 0x00a030c0, .end = 0x00a0312c }, 397 { .start = 0x00a03c00, .end = 0x00a03c5c }, 398 { .start = 0x00a04400, .end = 0x00a04454 }, 399 { .start = 0x00a04460, .end = 0x00a04474 }, 400 { .start = 0x00a044c0, .end = 0x00a044ec }, 401 { .start = 0x00a04500, .end = 0x00a04504 }, 402 { .start = 0x00a04510, .end = 0x00a04538 }, 403 { .start = 0x00a04540, .end = 0x00a04548 }, 404 { .start = 0x00a04560, .end = 0x00a0457c }, 405 { .start = 0x00a04590, .end = 0x00a04598 }, 406 { .start = 0x00a045c0, .end = 0x00a045f4 }, 407 }; 408 409 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 410 { .start = 0x00a05c00, .end = 0x00a05c18 }, 411 { .start = 0x00a05400, .end = 0x00a056e8 }, 412 { .start = 0x00a08000, .end = 0x00a098bc }, 413 { .start = 0x00a02400, .end = 0x00a02758 }, 414 { .start = 0x00a04764, .end = 0x00a0476c }, 415 { .start = 0x00a04770, .end = 0x00a04774 }, 416 { .start = 0x00a04620, .end = 0x00a04624 }, 417 }; 418 419 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 420 { .start = 0x00a00000, .end = 0x00a00000 }, 421 { .start = 0x00a0000c, .end = 0x00a00024 }, 422 { .start = 0x00a0002c, .end = 0x00a00034 }, 423 { .start = 0x00a0003c, .end = 0x00a0003c }, 424 { .start = 0x00a00410, .end = 0x00a00418 }, 425 { .start = 0x00a00420, .end = 0x00a00420 }, 426 { .start = 0x00a00428, .end = 0x00a00428 }, 427 { .start = 0x00a00430, .end = 0x00a0043c }, 428 { .start = 0x00a00444, .end = 0x00a00444 }, 429 { .start = 0x00a00840, .end = 0x00a00840 }, 430 { .start = 0x00a00850, .end = 0x00a00858 }, 431 { .start = 0x00a01004, .end = 0x00a01008 }, 432 { .start = 0x00a01010, .end = 0x00a01010 }, 433 { .start = 0x00a01018, .end = 0x00a01018 }, 434 { .start = 0x00a01024, .end = 0x00a01024 }, 435 { .start = 0x00a0102c, .end = 0x00a01034 }, 436 { .start = 0x00a0103c, .end = 0x00a01040 }, 437 { .start = 0x00a01048, .end = 0x00a01050 }, 438 { .start = 0x00a01058, .end = 0x00a01058 }, 439 { .start = 0x00a01060, .end = 0x00a01070 }, 440 { .start = 0x00a0108c, .end = 0x00a0108c }, 441 { .start = 0x00a01c20, .end = 0x00a01c28 }, 442 { .start = 0x00a01d10, .end = 0x00a01d10 }, 443 { .start = 0x00a01e28, .end = 0x00a01e2c }, 444 { .start = 0x00a01e60, .end = 0x00a01e60 }, 445 { .start = 0x00a01e80, .end = 0x00a01e80 }, 446 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 447 { .start = 0x00a02000, .end = 0x00a0201c }, 448 { .start = 0x00a02024, .end = 0x00a02024 }, 449 { .start = 0x00a02040, .end = 0x00a02048 }, 450 { .start = 0x00a020c0, .end = 0x00a020e0 }, 451 { .start = 0x00a02400, .end = 0x00a02404 }, 452 { .start = 0x00a0240c, .end = 0x00a02414 }, 453 { .start = 0x00a0241c, .end = 0x00a0243c }, 454 { .start = 0x00a02448, .end = 0x00a024bc }, 455 { .start = 0x00a024c4, .end = 0x00a024cc }, 456 { .start = 0x00a02508, .end = 0x00a02508 }, 457 { .start = 0x00a02510, .end = 0x00a02514 }, 458 { .start = 0x00a0251c, .end = 0x00a0251c }, 459 { .start = 0x00a0252c, .end = 0x00a0255c }, 460 { .start = 0x00a02564, .end = 0x00a025a0 }, 461 { .start = 0x00a025a8, .end = 0x00a025b4 }, 462 { .start = 0x00a025c0, .end = 0x00a025c0 }, 463 { .start = 0x00a025e8, .end = 0x00a025f4 }, 464 { .start = 0x00a02c08, .end = 0x00a02c18 }, 465 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 466 { .start = 0x00a02c68, .end = 0x00a02c78 }, 467 { .start = 0x00a03000, .end = 0x00a03000 }, 468 { .start = 0x00a03010, .end = 0x00a03014 }, 469 { .start = 0x00a0301c, .end = 0x00a0302c }, 470 { .start = 0x00a03034, .end = 0x00a03038 }, 471 { .start = 0x00a03040, .end = 0x00a03044 }, 472 { .start = 0x00a03060, .end = 0x00a03068 }, 473 { .start = 0x00a03070, .end = 0x00a03070 }, 474 { .start = 0x00a0307c, .end = 0x00a03084 }, 475 { .start = 0x00a0308c, .end = 0x00a03090 }, 476 { .start = 0x00a03098, .end = 0x00a03098 }, 477 { .start = 0x00a030a0, .end = 0x00a030a0 }, 478 { .start = 0x00a030a8, .end = 0x00a030b4 }, 479 { .start = 0x00a030bc, .end = 0x00a030c0 }, 480 { .start = 0x00a030c8, .end = 0x00a030f4 }, 481 { .start = 0x00a03100, .end = 0x00a0312c }, 482 { .start = 0x00a03c00, .end = 0x00a03c5c }, 483 { .start = 0x00a04400, .end = 0x00a04454 }, 484 { .start = 0x00a04460, .end = 0x00a04474 }, 485 { .start = 0x00a044c0, .end = 0x00a044ec }, 486 { .start = 0x00a04500, .end = 0x00a04504 }, 487 { .start = 0x00a04510, .end = 0x00a04538 }, 488 { .start = 0x00a04540, .end = 0x00a04548 }, 489 { .start = 0x00a04560, .end = 0x00a04560 }, 490 { .start = 0x00a04570, .end = 0x00a0457c }, 491 { .start = 0x00a04590, .end = 0x00a04590 }, 492 { .start = 0x00a04598, .end = 0x00a04598 }, 493 { .start = 0x00a045c0, .end = 0x00a045f4 }, 494 { .start = 0x00a05c18, .end = 0x00a05c1c }, 495 { .start = 0x00a0c000, .end = 0x00a0c018 }, 496 { .start = 0x00a0c020, .end = 0x00a0c028 }, 497 { .start = 0x00a0c038, .end = 0x00a0c094 }, 498 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 499 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 500 { .start = 0x00a0c150, .end = 0x00a0c174 }, 501 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 502 { .start = 0x00a0c190, .end = 0x00a0c198 }, 503 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 504 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 505 }; 506 507 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 508 { .start = 0x00d03c00, .end = 0x00d03c64 }, 509 { .start = 0x00d05c18, .end = 0x00d05c1c }, 510 { .start = 0x00d0c000, .end = 0x00d0c174 }, 511 }; 512 513 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 514 u32 len_bytes, __le32 *data) 515 { 516 u32 i; 517 518 for (i = 0; i < len_bytes; i += 4) 519 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 520 } 521 522 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 523 const struct iwl_prph_range *iwl_prph_dump_addr, 524 u32 range_len, void *ptr) 525 { 526 struct iwl_fw_error_dump_prph *prph; 527 struct iwl_trans *trans = fwrt->trans; 528 struct iwl_fw_error_dump_data **data = 529 (struct iwl_fw_error_dump_data **)ptr; 530 u32 i; 531 532 if (!data) 533 return; 534 535 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 536 537 if (!iwl_trans_grab_nic_access(trans)) 538 return; 539 540 for (i = 0; i < range_len; i++) { 541 /* The range includes both boundaries */ 542 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 543 iwl_prph_dump_addr[i].start + 4; 544 545 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 546 (*data)->len = cpu_to_le32(sizeof(*prph) + 547 num_bytes_in_chunk); 548 prph = (void *)(*data)->data; 549 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 550 551 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 552 /* our range is inclusive, hence + 4 */ 553 iwl_prph_dump_addr[i].end - 554 iwl_prph_dump_addr[i].start + 4, 555 (void *)prph->data); 556 557 *data = iwl_fw_error_next_data(*data); 558 } 559 560 iwl_trans_release_nic_access(trans); 561 } 562 563 /* 564 * alloc_sgtable - allocates scallerlist table in the given size, 565 * fills it with pages and returns it 566 * @size: the size (in bytes) of the table 567 */ 568 static struct scatterlist *alloc_sgtable(int size) 569 { 570 int alloc_size, nents, i; 571 struct page *new_page; 572 struct scatterlist *iter; 573 struct scatterlist *table; 574 575 nents = DIV_ROUND_UP(size, PAGE_SIZE); 576 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 577 if (!table) 578 return NULL; 579 sg_init_table(table, nents); 580 iter = table; 581 for_each_sg(table, iter, sg_nents(table), i) { 582 new_page = alloc_page(GFP_KERNEL); 583 if (!new_page) { 584 /* release all previous allocated pages in the table */ 585 iter = table; 586 for_each_sg(table, iter, sg_nents(table), i) { 587 new_page = sg_page(iter); 588 if (new_page) 589 __free_page(new_page); 590 } 591 kfree(table); 592 return NULL; 593 } 594 alloc_size = min_t(int, size, PAGE_SIZE); 595 size -= PAGE_SIZE; 596 sg_set_page(iter, new_page, alloc_size, 0); 597 } 598 return table; 599 } 600 601 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 602 const struct iwl_prph_range *iwl_prph_dump_addr, 603 u32 range_len, void *ptr) 604 { 605 u32 *prph_len = (u32 *)ptr; 606 int i, num_bytes_in_chunk; 607 608 if (!prph_len) 609 return; 610 611 for (i = 0; i < range_len; i++) { 612 /* The range includes both boundaries */ 613 num_bytes_in_chunk = 614 iwl_prph_dump_addr[i].end - 615 iwl_prph_dump_addr[i].start + 4; 616 617 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 618 sizeof(struct iwl_fw_error_dump_prph) + 619 num_bytes_in_chunk; 620 } 621 } 622 623 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 624 void (*handler)(struct iwl_fw_runtime *, 625 const struct iwl_prph_range *, 626 u32, void *)) 627 { 628 u32 range_len; 629 630 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 631 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 632 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 633 } else if (fwrt->trans->trans_cfg->device_family >= 634 IWL_DEVICE_FAMILY_22000) { 635 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 636 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 637 } else { 638 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 639 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 640 641 if (fwrt->trans->trans_cfg->mq_rx_supported) { 642 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 643 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 644 } 645 } 646 } 647 648 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 649 struct iwl_fw_error_dump_data **dump_data, 650 u32 len, u32 ofs, u32 type) 651 { 652 struct iwl_fw_error_dump_mem *dump_mem; 653 654 if (!len) 655 return; 656 657 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 658 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 659 dump_mem = (void *)(*dump_data)->data; 660 dump_mem->type = cpu_to_le32(type); 661 dump_mem->offset = cpu_to_le32(ofs); 662 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 663 *dump_data = iwl_fw_error_next_data(*dump_data); 664 665 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 666 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 667 dump_mem->data, len); 668 669 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 670 } 671 672 #define ADD_LEN(len, item_len, const_len) \ 673 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 674 while (0) 675 676 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 677 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 678 { 679 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 680 sizeof(struct iwl_fw_error_dump_fifo); 681 u32 fifo_len = 0; 682 int i; 683 684 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 685 return 0; 686 687 /* Count RXF2 size */ 688 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 689 690 /* Count RXF1 sizes */ 691 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 692 mem_cfg->num_lmacs = MAX_NUM_LMAC; 693 694 for (i = 0; i < mem_cfg->num_lmacs; i++) 695 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 696 697 return fifo_len; 698 } 699 700 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 701 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 702 { 703 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 704 sizeof(struct iwl_fw_error_dump_fifo); 705 u32 fifo_len = 0; 706 int i; 707 708 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 709 goto dump_internal_txf; 710 711 /* Count TXF sizes */ 712 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 713 mem_cfg->num_lmacs = MAX_NUM_LMAC; 714 715 for (i = 0; i < mem_cfg->num_lmacs; i++) { 716 int j; 717 718 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 719 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 720 hdr_len); 721 } 722 723 dump_internal_txf: 724 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 725 fw_has_capa(&fwrt->fw->ucode_capa, 726 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 727 goto out; 728 729 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 730 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 731 732 out: 733 return fifo_len; 734 } 735 736 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 737 struct iwl_fw_error_dump_data **data) 738 { 739 int i; 740 741 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 742 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 743 struct iwl_fw_error_dump_paging *paging; 744 struct page *pages = 745 fwrt->fw_paging_db[i].fw_paging_block; 746 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 747 748 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 749 (*data)->len = cpu_to_le32(sizeof(*paging) + 750 PAGING_BLOCK_SIZE); 751 paging = (void *)(*data)->data; 752 paging->index = cpu_to_le32(i); 753 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 754 PAGING_BLOCK_SIZE, 755 DMA_BIDIRECTIONAL); 756 memcpy(paging->data, page_address(pages), 757 PAGING_BLOCK_SIZE); 758 dma_sync_single_for_device(fwrt->trans->dev, addr, 759 PAGING_BLOCK_SIZE, 760 DMA_BIDIRECTIONAL); 761 (*data) = iwl_fw_error_next_data(*data); 762 763 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 764 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 765 fwrt->fw_paging_db[i].fw_offs, 766 paging->data, 767 PAGING_BLOCK_SIZE); 768 } 769 } 770 771 static struct iwl_fw_error_dump_file * 772 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 773 struct iwl_fw_dump_ptrs *fw_error_dump, 774 struct iwl_fwrt_dump_data *data) 775 { 776 struct iwl_fw_error_dump_file *dump_file; 777 struct iwl_fw_error_dump_data *dump_data; 778 struct iwl_fw_error_dump_info *dump_info; 779 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 780 struct iwl_fw_error_dump_trigger_desc *dump_trig; 781 u32 sram_len, sram_ofs; 782 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 783 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 784 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 785 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 786 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 787 0 : fwrt->trans->cfg->dccm2_len; 788 int i; 789 790 /* SRAM - include stack CCM if driver knows the values for it */ 791 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 792 const struct fw_img *img; 793 794 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 795 return NULL; 796 img = &fwrt->fw->img[fwrt->cur_fw_img]; 797 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 798 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 799 } else { 800 sram_ofs = fwrt->trans->cfg->dccm_offset; 801 sram_len = fwrt->trans->cfg->dccm_len; 802 } 803 804 /* reading RXF/TXF sizes */ 805 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 806 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 807 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 808 809 /* Make room for PRPH registers */ 810 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 811 iwl_fw_prph_handler(fwrt, &prph_len, 812 iwl_fw_get_prph_len); 813 814 if (fwrt->trans->trans_cfg->device_family == 815 IWL_DEVICE_FAMILY_7000 && 816 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 817 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 818 } 819 820 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 821 822 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 823 file_len += sizeof(*dump_data) + sizeof(*dump_info); 824 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 825 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 826 827 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 828 size_t hdr_len = sizeof(*dump_data) + 829 sizeof(struct iwl_fw_error_dump_mem); 830 831 /* Dump SRAM only if no mem_tlvs */ 832 if (!fwrt->fw->dbg.n_mem_tlv) 833 ADD_LEN(file_len, sram_len, hdr_len); 834 835 /* Make room for all mem types that exist */ 836 ADD_LEN(file_len, smem_len, hdr_len); 837 ADD_LEN(file_len, sram2_len, hdr_len); 838 839 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 840 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 841 } 842 843 /* Make room for fw's virtual image pages, if it exists */ 844 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 845 file_len += fwrt->num_of_paging_blk * 846 (sizeof(*dump_data) + 847 sizeof(struct iwl_fw_error_dump_paging) + 848 PAGING_BLOCK_SIZE); 849 850 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 851 file_len += sizeof(*dump_data) + 852 fwrt->trans->cfg->d3_debug_data_length * 2; 853 } 854 855 /* If we only want a monitor dump, reset the file length */ 856 if (data->monitor_only) { 857 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 858 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 859 } 860 861 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 862 data->desc) 863 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 864 data->desc->len; 865 866 dump_file = vzalloc(file_len); 867 if (!dump_file) 868 return NULL; 869 870 fw_error_dump->fwrt_ptr = dump_file; 871 872 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 873 dump_data = (void *)dump_file->data; 874 875 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 876 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 877 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 878 dump_info = (void *)dump_data->data; 879 dump_info->hw_type = 880 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 881 dump_info->hw_step = 882 cpu_to_le32(fwrt->trans->hw_rev_step); 883 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 884 sizeof(dump_info->fw_human_readable)); 885 strscpy_pad(dump_info->dev_human_readable, fwrt->trans->name, 886 sizeof(dump_info->dev_human_readable)); 887 #if defined(__linux__) 888 strscpy_pad(dump_info->bus_human_readable, fwrt->dev->bus->name, 889 sizeof(dump_info->bus_human_readable)); 890 #elif defined(__FreeBSD__) /* XXX TODO */ 891 strscpy_pad(dump_info->bus_human_readable, "<bus>", 892 sizeof(dump_info->bus_human_readable)); 893 #endif 894 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 895 dump_info->lmac_err_id[0] = 896 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 897 if (fwrt->smem_cfg.num_lmacs > 1) 898 dump_info->lmac_err_id[1] = 899 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 900 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 901 902 dump_data = iwl_fw_error_next_data(dump_data); 903 } 904 905 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 906 /* Dump shared memory configuration */ 907 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 908 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 909 dump_smem_cfg = (void *)dump_data->data; 910 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 911 dump_smem_cfg->num_txfifo_entries = 912 cpu_to_le32(mem_cfg->num_txfifo_entries); 913 for (i = 0; i < MAX_NUM_LMAC; i++) { 914 int j; 915 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 916 917 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 918 dump_smem_cfg->lmac[i].txfifo_size[j] = 919 cpu_to_le32(txf_size[j]); 920 dump_smem_cfg->lmac[i].rxfifo1_size = 921 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 922 } 923 dump_smem_cfg->rxfifo2_size = 924 cpu_to_le32(mem_cfg->rxfifo2_size); 925 dump_smem_cfg->internal_txfifo_addr = 926 cpu_to_le32(mem_cfg->internal_txfifo_addr); 927 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 928 dump_smem_cfg->internal_txfifo_size[i] = 929 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 930 } 931 932 dump_data = iwl_fw_error_next_data(dump_data); 933 } 934 935 /* We only dump the FIFOs if the FW is in error state */ 936 if (fifo_len) { 937 iwl_fw_dump_rxf(fwrt, &dump_data); 938 iwl_fw_dump_txf(fwrt, &dump_data); 939 } 940 941 if (radio_len) 942 iwl_read_radio_regs(fwrt, &dump_data); 943 944 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 945 data->desc) { 946 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 947 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 948 data->desc->len); 949 dump_trig = (void *)dump_data->data; 950 memcpy(dump_trig, &data->desc->trig_desc, 951 sizeof(*dump_trig) + data->desc->len); 952 953 dump_data = iwl_fw_error_next_data(dump_data); 954 } 955 956 /* In case we only want monitor dump, skip to dump trasport data */ 957 if (data->monitor_only) 958 goto out; 959 960 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 961 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 962 fwrt->fw->dbg.mem_tlv; 963 964 if (!fwrt->fw->dbg.n_mem_tlv) 965 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 966 IWL_FW_ERROR_DUMP_MEM_SRAM); 967 968 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 969 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 970 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 971 972 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 973 le32_to_cpu(fw_dbg_mem[i].data_type)); 974 } 975 976 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 977 fwrt->trans->cfg->smem_offset, 978 IWL_FW_ERROR_DUMP_MEM_SMEM); 979 980 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 981 fwrt->trans->cfg->dccm2_offset, 982 IWL_FW_ERROR_DUMP_MEM_SRAM); 983 } 984 985 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 986 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 987 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 988 989 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 990 dump_data->len = cpu_to_le32(data_size * 2); 991 992 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 993 994 kfree(fwrt->dump.d3_debug_data); 995 fwrt->dump.d3_debug_data = NULL; 996 997 iwl_trans_read_mem_bytes(fwrt->trans, addr, 998 dump_data->data + data_size, 999 data_size); 1000 1001 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 1002 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 1003 dump_data->data + data_size, 1004 data_size); 1005 1006 dump_data = iwl_fw_error_next_data(dump_data); 1007 } 1008 1009 /* Dump fw's virtual image */ 1010 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1011 iwl_dump_paging(fwrt, &dump_data); 1012 1013 if (prph_len) 1014 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1015 1016 out: 1017 dump_file->file_len = cpu_to_le32(file_len); 1018 return dump_file; 1019 } 1020 1021 /** 1022 * struct iwl_dump_ini_region_data - region data 1023 * @reg_tlv: region TLV 1024 * @dump_data: dump data 1025 */ 1026 struct iwl_dump_ini_region_data { 1027 struct iwl_ucode_tlv *reg_tlv; 1028 struct iwl_fwrt_dump_data *dump_data; 1029 }; 1030 1031 static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt, 1032 void *range_ptr, u32 addr, 1033 __le32 size) 1034 { 1035 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1036 __le32 *val = range->data; 1037 int i; 1038 1039 range->internal_base_addr = cpu_to_le32(addr); 1040 range->range_data_size = size; 1041 for (i = 0; i < le32_to_cpu(size); i += 4) 1042 *val++ = cpu_to_le32(iwl_read_prph(fwrt->trans, addr + i)); 1043 1044 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1045 } 1046 1047 static int 1048 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1049 struct iwl_dump_ini_region_data *reg_data, 1050 void *range_ptr, u32 range_len, int idx) 1051 { 1052 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1053 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1054 le32_to_cpu(reg->dev_addr.offset); 1055 1056 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1057 reg->dev_addr.size); 1058 } 1059 1060 static int 1061 iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime *fwrt, 1062 struct iwl_dump_ini_region_data *reg_data, 1063 void *range_ptr, u32 range_len, int idx) 1064 { 1065 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1066 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1067 u32 addr = le32_to_cpu(reg->dev_addr_range.offset) + 1068 le32_to_cpu(pairs[idx].addr); 1069 1070 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1071 pairs[idx].size); 1072 } 1073 1074 static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt, 1075 void *range_ptr, u32 addr, 1076 __le32 size, __le32 offset) 1077 { 1078 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1079 __le32 *val = range->data; 1080 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1081 u32 indirect_rd_addr = WMAL_MRSPF_1; 1082 u32 prph_val; 1083 u32 dphy_state; 1084 u32 dphy_addr; 1085 int i; 1086 1087 range->internal_base_addr = cpu_to_le32(addr); 1088 range->range_data_size = size; 1089 1090 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1091 indirect_wr_addr = WMAL_INDRCT_CMD1; 1092 1093 indirect_wr_addr += le32_to_cpu(offset); 1094 indirect_rd_addr += le32_to_cpu(offset); 1095 1096 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1097 return -EBUSY; 1098 1099 dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1100 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1101 1102 for (i = 0; i < le32_to_cpu(size); i += 4) { 1103 if (dphy_state == HBUS_TIMEOUT || 1104 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1105 WFPM_PHYRF_STATE_ON) { 1106 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1107 continue; 1108 } 1109 1110 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1111 WMAL_INDRCT_CMD(addr + i)); 1112 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1113 indirect_rd_addr); 1114 *val++ = cpu_to_le32(prph_val); 1115 } 1116 1117 iwl_trans_release_nic_access(fwrt->trans); 1118 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1119 } 1120 1121 static int 1122 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1123 struct iwl_dump_ini_region_data *reg_data, 1124 void *range_ptr, u32 range_len, int idx) 1125 { 1126 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1127 u32 addr = le32_to_cpu(reg->addrs[idx]); 1128 1129 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1130 reg->dev_addr.size, 1131 reg->dev_addr.offset); 1132 } 1133 1134 static int 1135 iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime *fwrt, 1136 struct iwl_dump_ini_region_data *reg_data, 1137 void *range_ptr, u32 range_len, int idx) 1138 { 1139 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1140 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1141 u32 addr = le32_to_cpu(pairs[idx].addr); 1142 1143 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1144 pairs[idx].size, 1145 reg->dev_addr_range.offset); 1146 } 1147 1148 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1149 struct iwl_dump_ini_region_data *reg_data, 1150 void *range_ptr, u32 range_len, int idx) 1151 { 1152 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1153 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1154 __le32 *val = range->data; 1155 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1156 le32_to_cpu(reg->dev_addr.offset); 1157 int i; 1158 1159 range->internal_base_addr = cpu_to_le32(addr); 1160 range->range_data_size = reg->dev_addr.size; 1161 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1162 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1163 1164 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1165 } 1166 1167 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1168 struct iwl_dump_ini_region_data *reg_data, 1169 void *range_ptr, u32 range_len, int idx) 1170 { 1171 struct iwl_trans *trans = fwrt->trans; 1172 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1173 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1174 __le32 *val = range->data; 1175 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1176 le32_to_cpu(reg->dev_addr.offset); 1177 int i; 1178 1179 range->internal_base_addr = cpu_to_le32(addr); 1180 range->range_data_size = reg->dev_addr.size; 1181 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1182 int ret; 1183 u32 tmp; 1184 1185 ret = iwl_trans_read_config32(trans, addr + i, &tmp); 1186 if (ret < 0) 1187 return ret; 1188 1189 *val++ = cpu_to_le32(tmp); 1190 } 1191 1192 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1193 } 1194 1195 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1196 struct iwl_dump_ini_region_data *reg_data, 1197 void *range_ptr, u32 range_len, int idx) 1198 { 1199 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1200 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1201 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1202 le32_to_cpu(reg->dev_addr.offset); 1203 1204 range->internal_base_addr = cpu_to_le32(addr); 1205 range->range_data_size = reg->dev_addr.size; 1206 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1207 le32_to_cpu(reg->dev_addr.size)); 1208 1209 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM && 1210 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1211 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1212 range->data, 1213 le32_to_cpu(reg->dev_addr.size)); 1214 1215 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1216 } 1217 1218 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1219 void *range_ptr, u32 range_len, int idx) 1220 { 1221 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1222 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1223 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1224 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1225 1226 range->page_num = cpu_to_le32(idx); 1227 range->range_data_size = cpu_to_le32(page_size); 1228 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1229 DMA_BIDIRECTIONAL); 1230 memcpy(range->data, page_address(page), page_size); 1231 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1232 DMA_BIDIRECTIONAL); 1233 1234 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1235 } 1236 1237 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1238 struct iwl_dump_ini_region_data *reg_data, 1239 void *range_ptr, u32 range_len, int idx) 1240 { 1241 struct iwl_fw_ini_error_dump_range *range; 1242 u32 page_size; 1243 1244 /* all paged index start from 1 to skip CSS section */ 1245 idx++; 1246 1247 if (!fwrt->trans->trans_cfg->gen2) 1248 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx); 1249 1250 range = range_ptr; 1251 page_size = fwrt->trans->init_dram.paging[idx].size; 1252 1253 range->page_num = cpu_to_le32(idx); 1254 range->range_data_size = cpu_to_le32(page_size); 1255 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1256 page_size); 1257 1258 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1259 } 1260 1261 static int 1262 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1263 struct iwl_dump_ini_region_data *reg_data, 1264 void *range_ptr, u32 range_len, int idx) 1265 { 1266 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1267 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1268 struct iwl_dram_data *frag; 1269 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1270 1271 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1272 1273 range->dram_base_addr = cpu_to_le64(frag->physical); 1274 range->range_data_size = cpu_to_le32(frag->size); 1275 1276 memcpy(range->data, frag->block, frag->size); 1277 1278 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1279 } 1280 1281 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1282 struct iwl_dump_ini_region_data *reg_data, 1283 void *range_ptr, u32 range_len, int idx) 1284 { 1285 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1286 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1287 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1288 1289 range->internal_base_addr = cpu_to_le32(addr); 1290 range->range_data_size = reg->internal_buffer.size; 1291 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1292 le32_to_cpu(reg->internal_buffer.size)); 1293 1294 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1295 } 1296 1297 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1298 struct iwl_dump_ini_region_data *reg_data, int idx) 1299 { 1300 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1301 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1302 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1303 int txf_num = cfg->num_txfifo_entries; 1304 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1305 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1306 1307 if (!idx) { 1308 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1309 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1310 le32_to_cpu(reg->fifos.offset)); 1311 return false; 1312 } 1313 1314 iter->internal_txf = 0; 1315 iter->fifo_size = 0; 1316 iter->fifo = -1; 1317 if (le32_to_cpu(reg->fifos.offset)) 1318 iter->lmac = 1; 1319 else 1320 iter->lmac = 0; 1321 } 1322 1323 if (!iter->internal_txf) { 1324 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1325 iter->fifo_size = 1326 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1327 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1328 return true; 1329 } 1330 iter->fifo--; 1331 } 1332 1333 iter->internal_txf = 1; 1334 1335 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1336 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1337 return false; 1338 1339 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1340 iter->fifo_size = 1341 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1342 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1343 return true; 1344 } 1345 1346 return false; 1347 } 1348 1349 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1350 struct iwl_dump_ini_region_data *reg_data, 1351 void *range_ptr, u32 range_len, int idx) 1352 { 1353 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1354 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1355 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1356 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1357 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1358 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1359 u32 registers_size = registers_num * sizeof(*reg_dump); 1360 __le32 *data; 1361 int i; 1362 1363 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1364 return -EIO; 1365 1366 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1367 return -EBUSY; 1368 1369 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1370 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1371 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1372 1373 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1374 1375 /* 1376 * read txf registers. for each register, write to the dump the 1377 * register address and its value 1378 */ 1379 for (i = 0; i < registers_num; i++) { 1380 addr = le32_to_cpu(reg->addrs[i]) + offs; 1381 1382 reg_dump->addr = cpu_to_le32(addr); 1383 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1384 addr)); 1385 1386 reg_dump++; 1387 } 1388 1389 if (reg->fifos.hdr_only) { 1390 range->range_data_size = cpu_to_le32(registers_size); 1391 goto out; 1392 } 1393 1394 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1395 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1396 TXF_WR_PTR + offs); 1397 1398 /* Dummy-read to advance the read pointer to the head */ 1399 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1400 1401 /* Read FIFO */ 1402 addr = TXF_READ_MODIFY_DATA + offs; 1403 data = (void *)reg_dump; 1404 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1405 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1406 1407 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1408 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1409 reg_dump, iter->fifo_size); 1410 1411 out: 1412 iwl_trans_release_nic_access(fwrt->trans); 1413 1414 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1415 } 1416 1417 static int 1418 iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt, 1419 struct iwl_dump_ini_region_data *reg_data, 1420 void *range_ptr, u32 range_len, int idx) 1421 { 1422 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1423 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1424 __le32 *val = range->data; 1425 __le32 offset = reg->dev_addr.offset; 1426 u32 indirect_rd_wr_addr = DPHYIP_INDIRECT; 1427 u32 addr = le32_to_cpu(reg->addrs[idx]); 1428 u32 dphy_state, dphy_addr, prph_val; 1429 int i; 1430 1431 range->internal_base_addr = cpu_to_le32(addr); 1432 range->range_data_size = reg->dev_addr.size; 1433 1434 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1435 return -EBUSY; 1436 1437 indirect_rd_wr_addr += le32_to_cpu(offset); 1438 1439 dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1440 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1441 1442 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1443 if (dphy_state == HBUS_TIMEOUT || 1444 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1445 WFPM_PHYRF_STATE_ON) { 1446 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1447 continue; 1448 } 1449 1450 iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr, 1451 addr + i); 1452 /* wait a bit for value to be ready in register */ 1453 udelay(1); 1454 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1455 indirect_rd_wr_addr); 1456 *val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >> 1457 DPHYIP_INDIRECT_RD_SHIFT); 1458 } 1459 1460 iwl_trans_release_nic_access(fwrt->trans); 1461 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1462 } 1463 1464 struct iwl_ini_rxf_data { 1465 u32 fifo_num; 1466 u32 size; 1467 u32 offset; 1468 }; 1469 1470 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1471 struct iwl_dump_ini_region_data *reg_data, 1472 struct iwl_ini_rxf_data *data) 1473 { 1474 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1475 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1476 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1477 u8 fifo_idx; 1478 1479 if (!data) 1480 return; 1481 1482 memset(data, 0, sizeof(*data)); 1483 1484 /* make sure only one bit is set in only one fid */ 1485 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1486 "fid1=%x, fid2=%x\n", fid1, fid2)) 1487 return; 1488 1489 if (fid1) { 1490 fifo_idx = ffs(fid1) - 1; 1491 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1492 fifo_idx)) 1493 return; 1494 1495 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1496 data->fifo_num = fifo_idx; 1497 } else { 1498 u8 max_idx; 1499 1500 fifo_idx = ffs(fid2) - 1; 1501 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1502 SHARED_MEM_CFG_CMD, 0) <= 3) 1503 max_idx = 0; 1504 else 1505 max_idx = 1; 1506 1507 if (WARN_ONCE(fifo_idx > max_idx, 1508 "invalid umac fifo idx %d", fifo_idx)) 1509 return; 1510 1511 /* use bit 31 to distinguish between umac and lmac rxf while 1512 * parsing the dump 1513 */ 1514 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1515 1516 switch (fifo_idx) { 1517 case 0: 1518 data->size = fwrt->smem_cfg.rxfifo2_size; 1519 data->offset = iwl_umac_prph(fwrt->trans, 1520 RXF_DIFF_FROM_PREV); 1521 break; 1522 case 1: 1523 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1524 data->offset = iwl_umac_prph(fwrt->trans, 1525 RXF2C_DIFF_FROM_PREV); 1526 break; 1527 } 1528 } 1529 } 1530 1531 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1532 struct iwl_dump_ini_region_data *reg_data, 1533 void *range_ptr, u32 range_len, int idx) 1534 { 1535 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1536 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1537 struct iwl_ini_rxf_data rxf_data; 1538 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1539 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1540 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1541 u32 registers_size = registers_num * sizeof(*reg_dump); 1542 __le32 *data; 1543 int i; 1544 1545 #if defined(__FreeBSD__) 1546 rxf_data.size = 0; 1547 #endif 1548 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1549 if (!rxf_data.size) 1550 return -EIO; 1551 1552 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1553 return -EBUSY; 1554 1555 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1556 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1557 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1558 1559 /* 1560 * read rxf registers. for each register, write to the dump the 1561 * register address and its value 1562 */ 1563 for (i = 0; i < registers_num; i++) { 1564 addr = le32_to_cpu(reg->addrs[i]) + offs; 1565 1566 reg_dump->addr = cpu_to_le32(addr); 1567 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1568 addr)); 1569 1570 reg_dump++; 1571 } 1572 1573 if (reg->fifos.hdr_only) { 1574 range->range_data_size = cpu_to_le32(registers_size); 1575 goto out; 1576 } 1577 1578 offs = rxf_data.offset; 1579 1580 /* Lock fence */ 1581 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1582 /* Set fence pointer to the same place like WR pointer */ 1583 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1584 /* Set fence offset */ 1585 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1586 0x0); 1587 1588 /* Read FIFO */ 1589 addr = RXF_FIFO_RD_FENCE_INC + offs; 1590 data = (void *)reg_dump; 1591 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1592 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1593 1594 out: 1595 iwl_trans_release_nic_access(fwrt->trans); 1596 1597 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1598 } 1599 1600 static int 1601 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1602 struct iwl_dump_ini_region_data *reg_data, 1603 void *range_ptr, u32 range_len, int idx) 1604 { 1605 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1606 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1607 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1608 u32 addr = le32_to_cpu(err_table->base_addr) + 1609 le32_to_cpu(err_table->offset); 1610 1611 range->internal_base_addr = cpu_to_le32(addr); 1612 range->range_data_size = err_table->size; 1613 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1614 le32_to_cpu(err_table->size)); 1615 1616 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1617 } 1618 1619 static int 1620 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1621 struct iwl_dump_ini_region_data *reg_data, 1622 void *range_ptr, u32 range_len, int idx) 1623 { 1624 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1625 struct iwl_fw_ini_region_special_device_memory *special_mem = 1626 ®->special_mem; 1627 1628 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1629 u32 addr = le32_to_cpu(special_mem->base_addr) + 1630 le32_to_cpu(special_mem->offset); 1631 1632 range->internal_base_addr = cpu_to_le32(addr); 1633 range->range_data_size = special_mem->size; 1634 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1635 le32_to_cpu(special_mem->size)); 1636 1637 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1638 } 1639 1640 static int 1641 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1642 struct iwl_dump_ini_region_data *reg_data, 1643 void *range_ptr, u32 range_len, int idx) 1644 { 1645 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1646 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1647 __le32 *val = range->data; 1648 u32 prph_data; 1649 int i; 1650 1651 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1652 return -EBUSY; 1653 1654 range->range_data_size = reg->dev_addr.size; 1655 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1656 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ? 1657 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1658 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1659 if (iwl_trans_is_hw_error_value(prph_data)) { 1660 iwl_trans_release_nic_access(fwrt->trans); 1661 return -EBUSY; 1662 } 1663 *val++ = cpu_to_le32(prph_data); 1664 } 1665 iwl_trans_release_nic_access(fwrt->trans); 1666 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1667 } 1668 1669 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1670 struct iwl_dump_ini_region_data *reg_data, 1671 void *range_ptr, u32 range_len, int idx) 1672 { 1673 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1674 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1675 u32 pkt_len; 1676 1677 if (!pkt) 1678 return -EIO; 1679 1680 pkt_len = iwl_rx_packet_payload_len(pkt); 1681 1682 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1683 range->range_data_size = cpu_to_le32(pkt_len); 1684 1685 memcpy(range->data, pkt->data, pkt_len); 1686 1687 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1688 } 1689 1690 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt, 1691 struct iwl_dump_ini_region_data *reg_data, 1692 void *range_ptr, u32 range_len, int idx) 1693 { 1694 /* read the IMR memory and DMA it to SRAM */ 1695 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1696 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr; 1697 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte; 1698 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr; 1699 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1700 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes; 1701 1702 range->range_data_size = cpu_to_le32(size_to_dump); 1703 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr, 1704 imr_curr_addr, size_to_dump)) { 1705 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n"); 1706 return -1; 1707 } 1708 1709 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump; 1710 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump; 1711 1712 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data, 1713 size_to_dump); 1714 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1715 } 1716 1717 static void * 1718 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1719 struct iwl_dump_ini_region_data *reg_data, 1720 void *data, u32 data_len) 1721 { 1722 struct iwl_fw_ini_error_dump *dump = data; 1723 1724 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1725 1726 return dump->data; 1727 } 1728 1729 /** 1730 * mask_apply_and_normalize - applies mask on val and normalize the result 1731 * 1732 * @val: value 1733 * @mask: mask to apply and to normalize with 1734 * 1735 * The normalization is based on the first set bit in the mask 1736 * 1737 * Returns: the extracted value 1738 */ 1739 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1740 { 1741 return (val & mask) >> (ffs(mask) - 1); 1742 } 1743 1744 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1745 const struct iwl_fw_mon_reg *reg_info) 1746 { 1747 u32 val, offs; 1748 1749 /* The header addresses of DBGCi is calculate as follows: 1750 * DBGC1 address + (0x100 * i) 1751 */ 1752 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1753 1754 if (!reg_info || !reg_info->addr || !reg_info->mask) 1755 return 0; 1756 1757 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1758 1759 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1760 } 1761 1762 static void * 1763 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1764 struct iwl_fw_ini_monitor_dump *data, 1765 const struct iwl_fw_mon_regs *addrs) 1766 { 1767 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1768 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1769 return NULL; 1770 } 1771 1772 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1773 &addrs->write_ptr); 1774 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1775 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1776 1777 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1778 } 1779 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1780 &addrs->cycle_cnt); 1781 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1782 &addrs->cur_frag); 1783 1784 iwl_trans_release_nic_access(fwrt->trans); 1785 1786 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1787 1788 return data->data; 1789 } 1790 1791 static void * 1792 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1793 struct iwl_dump_ini_region_data *reg_data, 1794 void *data, u32 data_len) 1795 { 1796 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1797 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1798 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1799 1800 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1801 &fwrt->trans->cfg->mon_dram_regs); 1802 } 1803 1804 static void * 1805 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1806 struct iwl_dump_ini_region_data *reg_data, 1807 void *data, u32 data_len) 1808 { 1809 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1810 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1811 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id); 1812 1813 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1814 &fwrt->trans->cfg->mon_smem_regs); 1815 } 1816 1817 static void * 1818 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt, 1819 struct iwl_dump_ini_region_data *reg_data, 1820 void *data, u32 data_len) 1821 { 1822 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1823 1824 return iwl_dump_ini_mon_fill_header(fwrt, 1825 /* no offset calculation later */ 1826 IWL_FW_INI_ALLOCATION_ID_DBGC1, 1827 mon_dump, 1828 &fwrt->trans->cfg->mon_dbgi_regs); 1829 } 1830 1831 static void * 1832 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1833 struct iwl_dump_ini_region_data *reg_data, 1834 void *data, u32 data_len) 1835 { 1836 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1837 struct iwl_fw_ini_err_table_dump *dump = data; 1838 1839 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1840 dump->version = reg->err_table.version; 1841 1842 return dump->data; 1843 } 1844 1845 static void * 1846 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1847 struct iwl_dump_ini_region_data *reg_data, 1848 void *data, u32 data_len) 1849 { 1850 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1851 struct iwl_fw_ini_special_device_memory *dump = data; 1852 1853 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1854 dump->type = reg->special_mem.type; 1855 dump->version = reg->special_mem.version; 1856 1857 return dump->data; 1858 } 1859 1860 static void * 1861 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt, 1862 struct iwl_dump_ini_region_data *reg_data, 1863 void *data, u32 data_len) 1864 { 1865 struct iwl_fw_ini_error_dump *dump = data; 1866 1867 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1868 1869 return dump->data; 1870 } 1871 1872 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1873 struct iwl_dump_ini_region_data *reg_data) 1874 { 1875 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1876 1877 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1878 } 1879 1880 static u32 1881 iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime *fwrt, 1882 struct iwl_dump_ini_region_data *reg_data) 1883 { 1884 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1885 size_t size = sizeof(struct iwl_fw_ini_addr_size); 1886 1887 return iwl_tlv_array_len_with_size(reg_data->reg_tlv, reg, size); 1888 } 1889 1890 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1891 struct iwl_dump_ini_region_data *reg_data) 1892 { 1893 if (fwrt->trans->trans_cfg->gen2) { 1894 if (fwrt->trans->init_dram.paging_cnt) 1895 return fwrt->trans->init_dram.paging_cnt - 1; 1896 else 1897 return 0; 1898 } 1899 1900 return fwrt->num_of_paging_blk; 1901 } 1902 1903 static u32 1904 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1905 struct iwl_dump_ini_region_data *reg_data) 1906 { 1907 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1908 struct iwl_fw_mon *fw_mon; 1909 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1910 int i; 1911 1912 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1913 1914 for (i = 0; i < fw_mon->num_frags; i++) { 1915 if (!fw_mon->frags[i].size) 1916 break; 1917 1918 ranges++; 1919 } 1920 1921 return ranges; 1922 } 1923 1924 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1925 struct iwl_dump_ini_region_data *reg_data) 1926 { 1927 u32 num_of_fifos = 0; 1928 1929 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1930 num_of_fifos++; 1931 1932 return num_of_fifos; 1933 } 1934 1935 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1936 struct iwl_dump_ini_region_data *reg_data) 1937 { 1938 return 1; 1939 } 1940 1941 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt, 1942 struct iwl_dump_ini_region_data *reg_data) 1943 { 1944 /* range is total number of pages need to copied from 1945 *IMR memory to SRAM and later from SRAM to DRAM 1946 */ 1947 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 1948 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 1949 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1950 1951 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 1952 IWL_DEBUG_INFO(fwrt, 1953 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 1954 imr_enable, imr_size, sram_size); 1955 return 0; 1956 } 1957 1958 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size)); 1959 } 1960 1961 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1962 struct iwl_dump_ini_region_data *reg_data) 1963 { 1964 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1965 u32 size = le32_to_cpu(reg->dev_addr.size); 1966 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1967 1968 if (!size || !ranges) 1969 return 0; 1970 1971 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1972 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1973 } 1974 1975 static u32 1976 iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime *fwrt, 1977 struct iwl_dump_ini_region_data *reg_data) 1978 { 1979 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1980 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1981 u32 ranges = iwl_dump_ini_mem_block_ranges(fwrt, reg_data); 1982 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1983 int range; 1984 1985 if (!ranges) 1986 return 0; 1987 1988 for (range = 0; range < ranges; range++) 1989 size += le32_to_cpu(pairs[range].size); 1990 1991 return size + ranges * sizeof(struct iwl_fw_ini_error_dump_range); 1992 } 1993 1994 static u32 1995 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1996 struct iwl_dump_ini_region_data *reg_data) 1997 { 1998 int i; 1999 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 2000 u32 size = sizeof(struct iwl_fw_ini_error_dump); 2001 2002 /* start from 1 to skip CSS section */ 2003 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 2004 size += range_header_len; 2005 if (fwrt->trans->trans_cfg->gen2) 2006 size += fwrt->trans->init_dram.paging[i].size; 2007 else 2008 size += fwrt->fw_paging_db[i].fw_paging_size; 2009 } 2010 2011 return size; 2012 } 2013 2014 static u32 2015 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 2016 struct iwl_dump_ini_region_data *reg_data) 2017 { 2018 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2019 struct iwl_fw_mon *fw_mon; 2020 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 2021 int i; 2022 2023 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 2024 2025 for (i = 0; i < fw_mon->num_frags; i++) { 2026 struct iwl_dram_data *frag = &fw_mon->frags[i]; 2027 2028 if (!frag->size) 2029 break; 2030 2031 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 2032 } 2033 2034 if (size) 2035 size += sizeof(struct iwl_fw_ini_monitor_dump); 2036 2037 return size; 2038 } 2039 2040 static u32 2041 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 2042 struct iwl_dump_ini_region_data *reg_data) 2043 { 2044 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2045 u32 size; 2046 2047 size = le32_to_cpu(reg->internal_buffer.size); 2048 if (!size) 2049 return 0; 2050 2051 size += sizeof(struct iwl_fw_ini_monitor_dump) + 2052 sizeof(struct iwl_fw_ini_error_dump_range); 2053 2054 return size; 2055 } 2056 2057 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt, 2058 struct iwl_dump_ini_region_data *reg_data) 2059 { 2060 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2061 u32 size = le32_to_cpu(reg->dev_addr.size); 2062 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 2063 2064 if (!size || !ranges) 2065 return 0; 2066 2067 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges * 2068 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 2069 } 2070 2071 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 2072 struct iwl_dump_ini_region_data *reg_data) 2073 { 2074 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2075 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 2076 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2077 u32 size = 0; 2078 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 2079 registers_num * 2080 sizeof(struct iwl_fw_ini_error_dump_register); 2081 2082 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 2083 size += fifo_hdr; 2084 if (!reg->fifos.hdr_only) 2085 size += iter->fifo_size; 2086 } 2087 2088 if (!size) 2089 return 0; 2090 2091 return size + sizeof(struct iwl_fw_ini_error_dump); 2092 } 2093 2094 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 2095 struct iwl_dump_ini_region_data *reg_data) 2096 { 2097 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2098 struct iwl_ini_rxf_data rx_data; 2099 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2100 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 2101 sizeof(struct iwl_fw_ini_error_dump_range) + 2102 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 2103 2104 if (reg->fifos.hdr_only) 2105 return size; 2106 2107 #if defined(__FreeBSD__) 2108 rx_data.size = 0; 2109 #endif 2110 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 2111 size += rx_data.size; 2112 2113 return size; 2114 } 2115 2116 static u32 2117 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 2118 struct iwl_dump_ini_region_data *reg_data) 2119 { 2120 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2121 u32 size = le32_to_cpu(reg->err_table.size); 2122 2123 if (size) 2124 size += sizeof(struct iwl_fw_ini_err_table_dump) + 2125 sizeof(struct iwl_fw_ini_error_dump_range); 2126 2127 return size; 2128 } 2129 2130 static u32 2131 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 2132 struct iwl_dump_ini_region_data *reg_data) 2133 { 2134 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2135 u32 size = le32_to_cpu(reg->special_mem.size); 2136 2137 if (size) 2138 size += sizeof(struct iwl_fw_ini_special_device_memory) + 2139 sizeof(struct iwl_fw_ini_error_dump_range); 2140 2141 return size; 2142 } 2143 2144 static u32 2145 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 2146 struct iwl_dump_ini_region_data *reg_data) 2147 { 2148 u32 size = 0; 2149 2150 if (!reg_data->dump_data->fw_pkt) 2151 return 0; 2152 2153 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 2154 if (size) 2155 size += sizeof(struct iwl_fw_ini_error_dump) + 2156 sizeof(struct iwl_fw_ini_error_dump_range); 2157 2158 return size; 2159 } 2160 2161 static u32 2162 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt, 2163 struct iwl_dump_ini_region_data *reg_data) 2164 { 2165 u32 ranges = 0; 2166 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 2167 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 2168 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 2169 2170 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 2171 IWL_DEBUG_INFO(fwrt, 2172 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 2173 imr_enable, imr_size, sram_size); 2174 return 0; 2175 } 2176 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data); 2177 if (!ranges) { 2178 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges); 2179 return 0; 2180 } 2181 imr_size += sizeof(struct iwl_fw_ini_error_dump) + 2182 ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2183 return imr_size; 2184 } 2185 2186 /** 2187 * struct iwl_dump_ini_mem_ops - ini memory dump operations 2188 * @get_num_of_ranges: returns the number of memory ranges in the region. 2189 * @get_size: returns the total size of the region. 2190 * @fill_mem_hdr: fills region type specific headers and returns pointer to 2191 * the first range or NULL if failed to fill headers. 2192 * @fill_range: copies a given memory range into the dump. 2193 * Returns the size of the range or negative error value otherwise. 2194 */ 2195 struct iwl_dump_ini_mem_ops { 2196 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 2197 struct iwl_dump_ini_region_data *reg_data); 2198 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 2199 struct iwl_dump_ini_region_data *reg_data); 2200 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 2201 struct iwl_dump_ini_region_data *reg_data, 2202 void *data, u32 data_len); 2203 int (*fill_range)(struct iwl_fw_runtime *fwrt, 2204 struct iwl_dump_ini_region_data *reg_data, 2205 void *range, u32 range_len, int idx); 2206 }; 2207 2208 /** 2209 * iwl_dump_ini_mem - dump memory region 2210 * 2211 * @fwrt: fw runtime struct 2212 * @list: list to add the dump tlv to 2213 * @reg_data: memory region 2214 * @ops: memory dump operations 2215 * 2216 * Creates a dump tlv and copy a memory region into it. 2217 * 2218 * Returns: the size of the current dump tlv or 0 if failed 2219 */ 2220 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 2221 struct iwl_dump_ini_region_data *reg_data, 2222 const struct iwl_dump_ini_mem_ops *ops) 2223 { 2224 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2225 struct iwl_fw_ini_dump_entry *entry; 2226 struct iwl_fw_ini_error_dump_data *tlv; 2227 struct iwl_fw_ini_error_dump_header *header; 2228 u32 type = reg->type; 2229 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK); 2230 u32 num_of_ranges, i, size; 2231 u8 *range; 2232 u32 free_size; 2233 u64 header_size; 2234 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE; 2235 2236 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n", 2237 dump_policy, id, type); 2238 2239 if (le32_to_cpu(reg->hdr.version) >= 2) { 2240 u32 dp = le32_get_bits(reg->id, 2241 IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2242 2243 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE && 2244 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) { 2245 IWL_DEBUG_FW(fwrt, 2246 "WRT: no dump - type %d and policy mismatch=%d\n", 2247 dump_policy, dp); 2248 return 0; 2249 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM && 2250 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) { 2251 IWL_DEBUG_FW(fwrt, 2252 "WRT: no dump - type %d and policy mismatch=%d\n", 2253 dump_policy, dp); 2254 return 0; 2255 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF && 2256 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) { 2257 IWL_DEBUG_FW(fwrt, 2258 "WRT: no dump - type %d and policy mismatch=%d\n", 2259 dump_policy, dp); 2260 return 0; 2261 } 2262 } 2263 2264 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2265 !ops->fill_range) { 2266 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n"); 2267 return 0; 2268 } 2269 2270 size = ops->get_size(fwrt, reg_data); 2271 2272 if (size < sizeof(*header)) { 2273 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n"); 2274 return 0; 2275 } 2276 2277 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2278 if (!entry) 2279 return 0; 2280 2281 entry->size = sizeof(*tlv) + size; 2282 2283 tlv = (void *)entry->data; 2284 tlv->type = reg->type; 2285 tlv->sub_type = reg->sub_type; 2286 tlv->sub_type_ver = reg->sub_type_ver; 2287 tlv->reserved = reg->reserved; 2288 tlv->len = cpu_to_le32(size); 2289 2290 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2291 2292 header = (void *)tlv->data; 2293 header->region_id = cpu_to_le32(id); 2294 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2295 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2296 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2297 2298 free_size = size; 2299 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size); 2300 if (!range) { 2301 IWL_ERR(fwrt, 2302 "WRT: Failed to fill region header: id=%d, type=%d\n", 2303 id, type); 2304 goto out_err; 2305 } 2306 2307 header_size = range - (u8 *)header; 2308 2309 if (WARN(header_size > free_size, 2310 #if defined(__linux__) 2311 "header size %llu > free_size %d", 2312 header_size, free_size)) { 2313 #elif defined(__FreeBSD__) 2314 "header size %ju > free_size %d", 2315 (uintmax_t)header_size, free_size)) { 2316 #endif 2317 IWL_ERR(fwrt, 2318 "WRT: fill_mem_hdr used more than given free_size\n"); 2319 goto out_err; 2320 } 2321 2322 free_size -= header_size; 2323 2324 for (i = 0; i < num_of_ranges; i++) { 2325 int range_size = ops->fill_range(fwrt, reg_data, range, 2326 free_size, i); 2327 2328 if (range_size < 0) { 2329 IWL_ERR(fwrt, 2330 "WRT: Failed to dump region: id=%d, type=%d\n", 2331 id, type); 2332 goto out_err; 2333 } 2334 2335 if (WARN(range_size > free_size, "range_size %d > free_size %d", 2336 range_size, free_size)) { 2337 IWL_ERR(fwrt, 2338 "WRT: fill_raged used more than given free_size\n"); 2339 goto out_err; 2340 } 2341 2342 free_size -= range_size; 2343 range = range + range_size; 2344 } 2345 2346 list_add_tail(&entry->list, list); 2347 2348 return entry->size; 2349 2350 out_err: 2351 vfree(entry); 2352 2353 return 0; 2354 } 2355 2356 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2357 struct iwl_fw_ini_trigger_tlv *trigger, 2358 struct list_head *list) 2359 { 2360 struct iwl_fw_ini_dump_entry *entry; 2361 struct iwl_fw_error_dump_data *tlv; 2362 struct iwl_fw_ini_dump_info *dump; 2363 struct iwl_dbg_tlv_node *node; 2364 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2365 u32 size = sizeof(*tlv) + sizeof(*dump); 2366 u32 num_of_cfg_names = 0; 2367 u32 hw_type; 2368 2369 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2370 size += sizeof(*cfg_name); 2371 num_of_cfg_names++; 2372 } 2373 2374 entry = vzalloc(sizeof(*entry) + size); 2375 if (!entry) 2376 return 0; 2377 2378 entry->size = size; 2379 2380 tlv = (void *)entry->data; 2381 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2382 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2383 2384 dump = (void *)tlv->data; 2385 2386 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2387 dump->time_point = trigger->time_point; 2388 dump->trigger_reason = trigger->trigger_reason; 2389 dump->external_cfg_state = 2390 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2391 2392 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2393 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2394 2395 dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step); 2396 2397 /* 2398 * Several HWs all have type == 0x42, so we'll override this value 2399 * according to the detected HW 2400 */ 2401 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2402 if (hw_type == IWL_AX210_HW_TYPE) { 2403 u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR); 2404 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2405 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2406 u32 masked_bits = is_jacket | (is_cdb << 1); 2407 2408 /* 2409 * The HW type depends on certain bits in this case, so add 2410 * these bits to the HW type. We won't have collisions since we 2411 * add these bits after the highest possible bit in the mask. 2412 */ 2413 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2414 } 2415 dump->hw_type = cpu_to_le32(hw_type); 2416 2417 dump->rf_id_flavor = 2418 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2419 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2420 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2421 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2422 2423 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2424 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2425 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2426 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2427 2428 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2429 dump->regions_mask = trigger->regions_mask & 2430 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2431 2432 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2433 memcpy(dump->build_tag, fwrt->fw->human_readable, 2434 sizeof(dump->build_tag)); 2435 2436 cfg_name = dump->cfg_names; 2437 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2438 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2439 struct iwl_fw_ini_debug_info_tlv *debug_info = 2440 (void *)node->tlv.data; 2441 2442 BUILD_BUG_ON(sizeof(cfg_name->cfg_name) != 2443 sizeof(debug_info->debug_cfg_name)); 2444 2445 cfg_name->image_type = debug_info->image_type; 2446 cfg_name->cfg_name_len = 2447 cpu_to_le32(sizeof(cfg_name->cfg_name)); 2448 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2449 sizeof(cfg_name->cfg_name)); 2450 cfg_name++; 2451 } 2452 2453 /* add dump info TLV to the beginning of the list since it needs to be 2454 * the first TLV in the dump 2455 */ 2456 list_add(&entry->list, list); 2457 2458 return entry->size; 2459 } 2460 2461 static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt, 2462 struct list_head *list) 2463 { 2464 struct iwl_fw_ini_dump_entry *entry; 2465 struct iwl_dump_file_name_info *tlv; 2466 u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext, 2467 IWL_FW_INI_MAX_NAME); 2468 2469 if (!fwrt->trans->dbg.dump_file_name_ext_valid) 2470 return 0; 2471 2472 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len); 2473 if (!entry) 2474 return 0; 2475 2476 entry->size = sizeof(*tlv) + len; 2477 2478 tlv = (void *)entry->data; 2479 tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE); 2480 tlv->len = cpu_to_le32(len); 2481 memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len); 2482 2483 /* add the dump file name extension tlv to the list */ 2484 list_add_tail(&entry->list, list); 2485 2486 fwrt->trans->dbg.dump_file_name_ext_valid = false; 2487 2488 return entry->size; 2489 } 2490 2491 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2492 [IWL_FW_INI_REGION_INVALID] = {}, 2493 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2494 .get_num_of_ranges = iwl_dump_ini_single_range, 2495 .get_size = iwl_dump_ini_mon_smem_get_size, 2496 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2497 .fill_range = iwl_dump_ini_mon_smem_iter, 2498 }, 2499 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2500 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2501 .get_size = iwl_dump_ini_mon_dram_get_size, 2502 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2503 .fill_range = iwl_dump_ini_mon_dram_iter, 2504 }, 2505 [IWL_FW_INI_REGION_TXF] = { 2506 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2507 .get_size = iwl_dump_ini_txf_get_size, 2508 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2509 .fill_range = iwl_dump_ini_txf_iter, 2510 }, 2511 [IWL_FW_INI_REGION_RXF] = { 2512 .get_num_of_ranges = iwl_dump_ini_single_range, 2513 .get_size = iwl_dump_ini_rxf_get_size, 2514 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2515 .fill_range = iwl_dump_ini_rxf_iter, 2516 }, 2517 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2518 .get_num_of_ranges = iwl_dump_ini_single_range, 2519 .get_size = iwl_dump_ini_err_table_get_size, 2520 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2521 .fill_range = iwl_dump_ini_err_table_iter, 2522 }, 2523 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2524 .get_num_of_ranges = iwl_dump_ini_single_range, 2525 .get_size = iwl_dump_ini_err_table_get_size, 2526 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2527 .fill_range = iwl_dump_ini_err_table_iter, 2528 }, 2529 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2530 .get_num_of_ranges = iwl_dump_ini_single_range, 2531 .get_size = iwl_dump_ini_fw_pkt_get_size, 2532 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2533 .fill_range = iwl_dump_ini_fw_pkt_iter, 2534 }, 2535 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2536 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2537 .get_size = iwl_dump_ini_mem_get_size, 2538 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2539 .fill_range = iwl_dump_ini_dev_mem_iter, 2540 }, 2541 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2542 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2543 .get_size = iwl_dump_ini_mem_get_size, 2544 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2545 .fill_range = iwl_dump_ini_prph_mac_iter, 2546 }, 2547 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2548 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2549 .get_size = iwl_dump_ini_mem_get_size, 2550 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2551 .fill_range = iwl_dump_ini_prph_phy_iter, 2552 }, 2553 [IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE] = { 2554 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2555 .get_size = iwl_dump_ini_mem_block_get_size, 2556 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2557 .fill_range = iwl_dump_ini_prph_mac_block_iter, 2558 }, 2559 [IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE] = { 2560 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2561 .get_size = iwl_dump_ini_mem_block_get_size, 2562 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2563 .fill_range = iwl_dump_ini_prph_phy_block_iter, 2564 }, 2565 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2566 [IWL_FW_INI_REGION_PAGING] = { 2567 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2568 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2569 .get_size = iwl_dump_ini_paging_get_size, 2570 .fill_range = iwl_dump_ini_paging_iter, 2571 }, 2572 [IWL_FW_INI_REGION_CSR] = { 2573 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2574 .get_size = iwl_dump_ini_mem_get_size, 2575 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2576 .fill_range = iwl_dump_ini_csr_iter, 2577 }, 2578 [IWL_FW_INI_REGION_DRAM_IMR] = { 2579 .get_num_of_ranges = iwl_dump_ini_imr_ranges, 2580 .get_size = iwl_dump_ini_imr_get_size, 2581 .fill_mem_hdr = iwl_dump_ini_imr_fill_header, 2582 .fill_range = iwl_dump_ini_imr_iter, 2583 }, 2584 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2585 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2586 .get_size = iwl_dump_ini_mem_get_size, 2587 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2588 .fill_range = iwl_dump_ini_config_iter, 2589 }, 2590 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2591 .get_num_of_ranges = iwl_dump_ini_single_range, 2592 .get_size = iwl_dump_ini_special_mem_get_size, 2593 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2594 .fill_range = iwl_dump_ini_special_mem_iter, 2595 }, 2596 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2597 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2598 .get_size = iwl_dump_ini_mon_dbgi_get_size, 2599 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header, 2600 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2601 }, 2602 [IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = { 2603 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2604 .get_size = iwl_dump_ini_mem_get_size, 2605 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2606 .fill_range = iwl_dump_ini_prph_snps_dphyip_iter, 2607 }, 2608 }; 2609 2610 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2611 struct iwl_fwrt_dump_data *dump_data, 2612 struct list_head *list) 2613 { 2614 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2615 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2616 struct iwl_dump_ini_region_data reg_data = { 2617 .dump_data = dump_data, 2618 }; 2619 struct iwl_dump_ini_region_data imr_reg_data = { 2620 .dump_data = dump_data, 2621 }; 2622 int i; 2623 u32 size = 0; 2624 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2625 ~(fwrt->trans->dbg.unsupported_region_msk); 2626 2627 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2628 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2629 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2630 2631 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2632 u32 reg_type; 2633 struct iwl_fw_ini_region_tlv *reg; 2634 2635 if (!(BIT_ULL(i) & regions_mask)) 2636 continue; 2637 2638 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2639 if (!reg_data.reg_tlv) { 2640 IWL_WARN(fwrt, 2641 "WRT: Unassigned region id %d, skipping\n", i); 2642 continue; 2643 } 2644 2645 reg = (void *)reg_data.reg_tlv->data; 2646 reg_type = reg->type; 2647 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2648 continue; 2649 2650 if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY || 2651 reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE || 2652 reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) && 2653 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2654 IWL_WARN(fwrt, 2655 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2656 tp_id); 2657 continue; 2658 } 2659 /* 2660 * DRAM_IMR can be collected only for FW/HW error timepoint 2661 * when fw is not alive. In addition, it must be collected 2662 * lastly as it overwrites SRAM that can possibly contain 2663 * debug data which also need to be collected. 2664 */ 2665 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) { 2666 if (tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT || 2667 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR) 2668 imr_reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2669 else 2670 IWL_INFO(fwrt, 2671 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n", 2672 tp_id); 2673 /* continue to next region */ 2674 continue; 2675 } 2676 2677 2678 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2679 &iwl_dump_ini_region_ops[reg_type]); 2680 } 2681 /* collect DRAM_IMR region in the last */ 2682 if (imr_reg_data.reg_tlv) 2683 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2684 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]); 2685 2686 if (size) { 2687 size += iwl_dump_ini_file_name_info(fwrt, list); 2688 size += iwl_dump_ini_info(fwrt, trigger, list); 2689 } 2690 2691 return size; 2692 } 2693 2694 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2695 struct iwl_fw_ini_trigger_tlv *trig) 2696 { 2697 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2698 u32 usec = le32_to_cpu(trig->ignore_consec); 2699 2700 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2701 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2702 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2703 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2704 return false; 2705 2706 return true; 2707 } 2708 2709 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2710 struct iwl_fwrt_dump_data *dump_data, 2711 struct list_head *list) 2712 { 2713 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2714 struct iwl_fw_ini_dump_entry *entry; 2715 struct iwl_fw_ini_dump_file_hdr *hdr; 2716 u32 size; 2717 2718 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2719 !le64_to_cpu(trigger->regions_mask)) 2720 return 0; 2721 2722 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2723 if (!entry) 2724 return 0; 2725 2726 entry->size = sizeof(*hdr); 2727 2728 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2729 if (!size) { 2730 vfree(entry); 2731 return 0; 2732 } 2733 2734 hdr = (void *)entry->data; 2735 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2736 hdr->file_len = cpu_to_le32(size + entry->size); 2737 2738 list_add(&entry->list, list); 2739 2740 return le32_to_cpu(hdr->file_len); 2741 } 2742 2743 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2744 const struct iwl_fw_dump_desc *desc) 2745 { 2746 if (desc && desc != &iwl_dump_desc_assert) 2747 kfree(desc); 2748 2749 fwrt->dump.lmac_err_id[0] = 0; 2750 if (fwrt->smem_cfg.num_lmacs > 1) 2751 fwrt->dump.lmac_err_id[1] = 0; 2752 fwrt->dump.umac_err_id = 0; 2753 } 2754 2755 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2756 struct iwl_fwrt_dump_data *dump_data) 2757 { 2758 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2759 struct iwl_fw_error_dump_file *dump_file; 2760 struct scatterlist *sg_dump_data; 2761 u32 file_len; 2762 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2763 2764 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2765 if (!dump_file) 2766 return; 2767 2768 if (dump_data->monitor_only) 2769 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2770 2771 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2772 fwrt->sanitize_ops, 2773 fwrt->sanitize_ctx); 2774 file_len = le32_to_cpu(dump_file->file_len); 2775 fw_error_dump.fwrt_len = file_len; 2776 2777 if (fw_error_dump.trans_ptr) { 2778 file_len += fw_error_dump.trans_ptr->len; 2779 dump_file->file_len = cpu_to_le32(file_len); 2780 } 2781 2782 sg_dump_data = alloc_sgtable(file_len); 2783 if (sg_dump_data) { 2784 sg_pcopy_from_buffer(sg_dump_data, 2785 sg_nents(sg_dump_data), 2786 fw_error_dump.fwrt_ptr, 2787 fw_error_dump.fwrt_len, 0); 2788 if (fw_error_dump.trans_ptr) 2789 sg_pcopy_from_buffer(sg_dump_data, 2790 sg_nents(sg_dump_data), 2791 fw_error_dump.trans_ptr->data, 2792 fw_error_dump.trans_ptr->len, 2793 fw_error_dump.fwrt_len); 2794 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2795 GFP_KERNEL); 2796 } 2797 vfree(fw_error_dump.fwrt_ptr); 2798 vfree(fw_error_dump.trans_ptr); 2799 } 2800 2801 static void iwl_dump_ini_list_free(struct list_head *list) 2802 { 2803 while (!list_empty(list)) { 2804 struct iwl_fw_ini_dump_entry *entry = 2805 list_entry(list->next, typeof(*entry), list); 2806 2807 list_del(&entry->list); 2808 vfree(entry); 2809 } 2810 } 2811 2812 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2813 { 2814 dump_data->trig = NULL; 2815 kfree(dump_data->fw_pkt); 2816 dump_data->fw_pkt = NULL; 2817 } 2818 2819 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2820 struct iwl_fwrt_dump_data *dump_data) 2821 { 2822 #if defined(__linux__) 2823 LIST_HEAD(dump_list); 2824 #elif defined(__FreeBSD__) 2825 LINUX_LIST_HEAD(dump_list); 2826 #endif 2827 struct scatterlist *sg_dump_data; 2828 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2829 2830 if (!file_len) 2831 return; 2832 2833 sg_dump_data = alloc_sgtable(file_len); 2834 if (sg_dump_data) { 2835 struct iwl_fw_ini_dump_entry *entry; 2836 int sg_entries = sg_nents(sg_dump_data); 2837 u32 offs = 0; 2838 2839 list_for_each_entry(entry, &dump_list, list) { 2840 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2841 entry->data, entry->size, offs); 2842 offs += entry->size; 2843 } 2844 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2845 GFP_KERNEL); 2846 } 2847 iwl_dump_ini_list_free(&dump_list); 2848 } 2849 2850 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2851 .trig_desc = { 2852 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2853 }, 2854 }; 2855 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2856 2857 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2858 const struct iwl_fw_dump_desc *desc, 2859 bool monitor_only, 2860 unsigned int delay) 2861 { 2862 struct iwl_fwrt_wk_data *wk_data; 2863 unsigned long idx; 2864 2865 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2866 iwl_fw_free_dump_desc(fwrt, desc); 2867 return 0; 2868 } 2869 2870 /* 2871 * Check there is an available worker. 2872 * ffz return value is undefined if no zero exists, 2873 * so check against ~0UL first. 2874 */ 2875 if (fwrt->dump.active_wks == ~0UL) 2876 return -EBUSY; 2877 2878 idx = ffz(fwrt->dump.active_wks); 2879 2880 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2881 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2882 return -EBUSY; 2883 2884 wk_data = &fwrt->dump.wks[idx]; 2885 2886 if (WARN_ON(wk_data->dump_data.desc)) 2887 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2888 2889 wk_data->dump_data.desc = desc; 2890 wk_data->dump_data.monitor_only = monitor_only; 2891 2892 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2893 le32_to_cpu(desc->trig_desc.type)); 2894 2895 queue_delayed_work(system_unbound_wq, &wk_data->wk, 2896 usecs_to_jiffies(delay)); 2897 2898 return 0; 2899 } 2900 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2901 2902 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2903 enum iwl_fw_dbg_trigger trig_type) 2904 { 2905 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2906 return -EIO; 2907 2908 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2909 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2910 trig_type != FW_DBG_TRIGGER_DRIVER) 2911 return -EIO; 2912 2913 iwl_dbg_tlv_time_point(fwrt, 2914 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2915 NULL); 2916 } else { 2917 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2918 int ret; 2919 2920 iwl_dump_error_desc = 2921 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2922 2923 if (!iwl_dump_error_desc) 2924 return -ENOMEM; 2925 2926 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2927 iwl_dump_error_desc->len = 0; 2928 2929 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2930 false, 0); 2931 if (ret) { 2932 kfree(iwl_dump_error_desc); 2933 return ret; 2934 } 2935 } 2936 2937 iwl_trans_sync_nmi(fwrt->trans); 2938 2939 return 0; 2940 } 2941 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2942 2943 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2944 enum iwl_fw_dbg_trigger trig, 2945 const char *str, size_t len, 2946 struct iwl_fw_dbg_trigger_tlv *trigger) 2947 { 2948 struct iwl_fw_dump_desc *desc; 2949 unsigned int delay = 0; 2950 bool monitor_only = false; 2951 2952 if (trigger) { 2953 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2954 2955 if (!le16_to_cpu(trigger->occurrences)) 2956 return 0; 2957 2958 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2959 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2960 trig); 2961 iwl_force_nmi(fwrt->trans); 2962 return 0; 2963 } 2964 2965 trigger->occurrences = cpu_to_le16(occurrences); 2966 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2967 2968 /* convert msec to usec */ 2969 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2970 } 2971 2972 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC); 2973 if (!desc) 2974 return -ENOMEM; 2975 2976 2977 desc->len = len; 2978 desc->trig_desc.type = cpu_to_le32(trig); 2979 memcpy(desc->trig_desc.data, str, len); 2980 2981 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2982 } 2983 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2984 2985 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2986 struct iwl_fw_dbg_trigger_tlv *trigger, 2987 const char *fmt, ...) 2988 { 2989 int ret, len = 0; 2990 char buf[64]; 2991 2992 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2993 return 0; 2994 2995 if (fmt) { 2996 va_list ap; 2997 2998 buf[sizeof(buf) - 1] = '\0'; 2999 3000 va_start(ap, fmt); 3001 vsnprintf(buf, sizeof(buf), fmt, ap); 3002 va_end(ap); 3003 3004 /* check for truncation */ 3005 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 3006 buf[sizeof(buf) - 1] = '\0'; 3007 3008 len = strlen(buf) + 1; 3009 } 3010 3011 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 3012 trigger); 3013 3014 if (ret) 3015 return ret; 3016 3017 return 0; 3018 } 3019 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 3020 3021 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 3022 { 3023 u8 *ptr; 3024 int ret; 3025 int i; 3026 3027 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 3028 "Invalid configuration %d\n", conf_id)) 3029 return -EINVAL; 3030 3031 /* EARLY START - firmware's configuration is hard coded */ 3032 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 3033 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 3034 conf_id == FW_DBG_START_FROM_ALIVE) 3035 return 0; 3036 3037 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 3038 return -EINVAL; 3039 3040 if (fwrt->dump.conf != FW_DBG_INVALID) 3041 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 3042 fwrt->dump.conf); 3043 3044 /* Send all HCMDs for configuring the FW debug */ 3045 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 3046 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 3047 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 3048 struct iwl_host_cmd hcmd = { 3049 .id = cmd->id, 3050 .len = { le16_to_cpu(cmd->len), }, 3051 .data = { cmd->data, }, 3052 }; 3053 3054 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3055 if (ret) 3056 return ret; 3057 3058 ptr += sizeof(*cmd); 3059 ptr += le16_to_cpu(cmd->len); 3060 } 3061 3062 fwrt->dump.conf = conf_id; 3063 3064 return 0; 3065 } 3066 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 3067 3068 void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt, 3069 u32 timepoint, 3070 u32 timepoint_data) 3071 { 3072 struct iwl_dbg_dump_complete_cmd hcmd_data; 3073 struct iwl_host_cmd hcmd = { 3074 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD), 3075 .data[0] = &hcmd_data, 3076 .len[0] = sizeof(hcmd_data), 3077 }; 3078 3079 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3080 return; 3081 3082 if (fw_has_capa(&fwrt->fw->ucode_capa, 3083 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) { 3084 hcmd_data.tp = cpu_to_le32(timepoint); 3085 hcmd_data.tp_data = cpu_to_le32(timepoint_data); 3086 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3087 } 3088 } 3089 3090 /* this function assumes dump_start was called beforehand and dump_end will be 3091 * called afterwards 3092 */ 3093 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 3094 { 3095 struct iwl_fw_dbg_params params = {0}; 3096 struct iwl_fwrt_dump_data *dump_data = 3097 &fwrt->dump.wks[wk_idx].dump_data; 3098 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 3099 return; 3100 3101 /* also checks 'desc' for pre-ini mode, since that shadows in union */ 3102 if (!dump_data->trig) { 3103 IWL_ERR(fwrt, "dump trigger data is not set\n"); 3104 goto out; 3105 } 3106 3107 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 3108 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 3109 goto out; 3110 } 3111 3112 /* there's no point in fw dump if the bus is dead */ 3113 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 3114 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 3115 goto out; 3116 } 3117 3118 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 3119 3120 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 3121 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 3122 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 3123 else 3124 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 3125 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 3126 3127 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3128 3129 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3130 u32 policy = le32_to_cpu(dump_data->trig->apply_policy); 3131 u32 time_point = le32_to_cpu(dump_data->trig->time_point); 3132 3133 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) { 3134 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n"); 3135 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0); 3136 } 3137 } 3138 3139 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) 3140 iwl_force_nmi(fwrt->trans); 3141 3142 out: 3143 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3144 iwl_fw_error_dump_data_free(dump_data); 3145 } else { 3146 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 3147 dump_data->desc = NULL; 3148 } 3149 3150 clear_bit(wk_idx, &fwrt->dump.active_wks); 3151 } 3152 3153 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 3154 struct iwl_fwrt_dump_data *dump_data, 3155 bool sync) 3156 { 3157 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 3158 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 3159 u32 occur, delay; 3160 unsigned long idx; 3161 3162 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 3163 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 3164 tp_id); 3165 return -EINVAL; 3166 } 3167 3168 delay = le32_to_cpu(trig->dump_delay); 3169 occur = le32_to_cpu(trig->occurrences); 3170 if (!occur) 3171 return 0; 3172 3173 trig->occurrences = cpu_to_le32(--occur); 3174 3175 /* Check there is an available worker. 3176 * ffz return value is undefined if no zero exists, 3177 * so check against ~0UL first. 3178 */ 3179 if (fwrt->dump.active_wks == ~0UL) 3180 return -EBUSY; 3181 3182 idx = ffz(fwrt->dump.active_wks); 3183 3184 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 3185 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 3186 return -EBUSY; 3187 3188 fwrt->dump.wks[idx].dump_data = *dump_data; 3189 3190 if (sync) 3191 delay = 0; 3192 3193 IWL_WARN(fwrt, 3194 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 3195 tp_id, (u32)(delay / USEC_PER_MSEC)); 3196 3197 if (sync) 3198 iwl_fw_dbg_collect_sync(fwrt, idx); 3199 else 3200 queue_delayed_work(system_unbound_wq, 3201 &fwrt->dump.wks[idx].wk, 3202 usecs_to_jiffies(delay)); 3203 3204 return 0; 3205 } 3206 3207 void iwl_fw_error_dump_wk(struct work_struct *work) 3208 { 3209 struct iwl_fwrt_wk_data *wks = 3210 container_of(work, typeof(*wks), wk.work); 3211 struct iwl_fw_runtime *fwrt = 3212 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 3213 3214 /* assumes the op mode mutex is locked in dump_start since 3215 * iwl_fw_dbg_collect_sync can't run in parallel 3216 */ 3217 if (fwrt->ops && fwrt->ops->dump_start) 3218 fwrt->ops->dump_start(fwrt->ops_ctx); 3219 3220 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 3221 3222 if (fwrt->ops && fwrt->ops->dump_end) 3223 fwrt->ops->dump_end(fwrt->ops_ctx); 3224 } 3225 3226 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 3227 { 3228 const struct iwl_cfg *cfg = fwrt->trans->cfg; 3229 3230 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 3231 return; 3232 3233 if (!fwrt->dump.d3_debug_data) { 3234 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 3235 GFP_KERNEL); 3236 if (!fwrt->dump.d3_debug_data) { 3237 IWL_ERR(fwrt, 3238 "failed to allocate memory for D3 debug data\n"); 3239 return; 3240 } 3241 } 3242 3243 /* if the buffer holds previous debug data it is overwritten */ 3244 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 3245 fwrt->dump.d3_debug_data, 3246 cfg->d3_debug_data_length); 3247 3248 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 3249 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 3250 cfg->d3_debug_data_base_addr, 3251 fwrt->dump.d3_debug_data, 3252 cfg->d3_debug_data_length); 3253 } 3254 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 3255 3256 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 3257 { 3258 int i; 3259 3260 iwl_dbg_tlv_del_timers(fwrt->trans); 3261 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 3262 iwl_fw_dbg_collect_sync(fwrt, i); 3263 3264 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 3265 } 3266 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 3267 3268 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 3269 { 3270 struct iwl_dbg_suspend_resume_cmd cmd = { 3271 .operation = suspend ? 3272 cpu_to_le32(DBGC_SUSPEND_CMD) : 3273 cpu_to_le32(DBGC_RESUME_CMD), 3274 }; 3275 struct iwl_host_cmd hcmd = { 3276 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 3277 .data[0] = &cmd, 3278 .len[0] = sizeof(cmd), 3279 }; 3280 3281 return iwl_trans_send_cmd(trans, &hcmd); 3282 } 3283 3284 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 3285 struct iwl_fw_dbg_params *params) 3286 { 3287 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3288 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3289 return; 3290 } 3291 3292 if (params) { 3293 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 3294 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 3295 } 3296 3297 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 3298 /* wait for the DBGC to finish writing the internal buffer to DRAM to 3299 * avoid halting the HW while writing 3300 */ 3301 usleep_range(700, 1000); 3302 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 3303 } 3304 3305 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 3306 struct iwl_fw_dbg_params *params) 3307 { 3308 if (!params) 3309 return -EIO; 3310 3311 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3312 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3313 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3314 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3315 } else { 3316 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 3317 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 3318 } 3319 3320 return 0; 3321 } 3322 3323 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt) 3324 { 3325 struct iwl_mvm_marker marker = { 3326 .dw_len = sizeof(struct iwl_mvm_marker) / 4, 3327 .marker_id = MARKER_ID_SYNC_CLOCK, 3328 }; 3329 struct iwl_host_cmd hcmd = { 3330 .flags = CMD_ASYNC, 3331 .id = WIDE_ID(LONG_GROUP, MARKER_CMD), 3332 .dataflags = {}, 3333 }; 3334 struct iwl_mvm_marker_rsp *resp; 3335 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw, 3336 WIDE_ID(LONG_GROUP, MARKER_CMD), 3337 IWL_FW_CMD_VER_UNKNOWN); 3338 int ret; 3339 3340 if (cmd_ver == 1) { 3341 /* the real timestamp is taken from the ftrace clock 3342 * this is for finding the match between fw and kernel logs 3343 */ 3344 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++); 3345 } else if (cmd_ver == 2) { 3346 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns()); 3347 } else { 3348 IWL_DEBUG_INFO(fwrt, 3349 "Invalid version of Marker CMD. Ver = %d\n", 3350 cmd_ver); 3351 return -EINVAL; 3352 } 3353 3354 hcmd.data[0] = ▮ 3355 hcmd.len[0] = sizeof(marker); 3356 3357 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3358 3359 if (cmd_ver > 1 && hcmd.resp_pkt) { 3360 resp = (void *)hcmd.resp_pkt->data; 3361 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n", 3362 le32_to_cpu(resp->gp2)); 3363 } 3364 3365 return ret; 3366 } 3367 3368 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3369 struct iwl_fw_dbg_params *params, 3370 bool stop) 3371 { 3372 int ret __maybe_unused = 0; 3373 3374 if (!iwl_trans_fw_running(fwrt->trans)) 3375 return; 3376 3377 if (fw_has_capa(&fwrt->fw->ucode_capa, 3378 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) { 3379 if (stop) 3380 iwl_fw_send_timestamp_marker_cmd(fwrt); 3381 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3382 } else if (stop) { 3383 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3384 } else { 3385 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3386 } 3387 #ifdef CONFIG_IWLWIFI_DEBUGFS 3388 if (!ret) { 3389 if (stop) 3390 fwrt->trans->dbg.rec_on = false; 3391 else 3392 iwl_fw_set_dbg_rec_on(fwrt); 3393 } 3394 #endif 3395 } 3396 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3397 3398 void iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime *fwrt) 3399 { 3400 struct iwl_fw_dbg_config_cmd cmd = { 3401 .type = cpu_to_le32(DEBUG_TOKEN_CONFIG_TYPE), 3402 .conf = cpu_to_le32(IWL_FW_DBG_CONFIG_TOKEN), 3403 }; 3404 struct iwl_host_cmd hcmd = { 3405 .id = WIDE_ID(LONG_GROUP, LDBG_CONFIG_CMD), 3406 .data[0] = &cmd, 3407 .len[0] = sizeof(cmd), 3408 }; 3409 u32 preset = u32_get_bits(fwrt->trans->dbg.domains_bitmap, 3410 GENMASK(31, IWL_FW_DBG_DOMAIN_POS + 1)); 3411 3412 /* supported starting from 9000 devices */ 3413 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000) 3414 return; 3415 3416 if (fwrt->trans->dbg.yoyo_bin_loaded || (preset && preset != 1)) 3417 return; 3418 3419 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3420 } 3421 IWL_EXPORT_SYMBOL(iwl_fw_disable_dbg_asserts); 3422 3423 void iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime *fwrt) 3424 { 3425 struct iwl_fw_dbg_params params = {0}; 3426 3427 iwl_fw_dbg_stop_sync(fwrt); 3428 3429 if (fw_has_api(&fwrt->fw->ucode_capa, 3430 IWL_UCODE_TLV_API_INT_DBG_BUF_CLEAR)) { 3431 struct iwl_host_cmd hcmd = { 3432 .id = WIDE_ID(DEBUG_GROUP, FW_CLEAR_BUFFER), 3433 }; 3434 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3435 } 3436 3437 iwl_dbg_tlv_init_cfg(fwrt); 3438 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3439 } 3440 IWL_EXPORT_SYMBOL(iwl_fw_dbg_clear_monitor_buf); 3441