1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2024-2025 Intel Corporation 4 */ 5 #include <linux/module.h> 6 #include <linux/stringify.h> 7 #include "iwl-config.h" 8 #include "iwl-prph.h" 9 #include "fw/api/txq.h" 10 11 /* Highest firmware API version supported */ 12 #define IWL_DR_UCODE_API_MAX 102 13 14 /* Lowest firmware API version supported */ 15 #define IWL_DR_UCODE_API_MIN 98 16 17 /* Memory offsets and lengths */ 18 #define IWL_DR_SMEM_OFFSET 0x400000 19 #define IWL_DR_SMEM_LEN 0xD0000 20 21 #define IWL_DR_A_PE_A_FW_PRE "iwlwifi-dr-a0-pe-a0" 22 23 #define IWL_DR_A_PE_A_FW_MODULE_FIRMWARE(api) \ 24 IWL_DR_A_PE_A_FW_PRE "-" __stringify(api) ".ucode" 25 26 static const struct iwl_family_base_params iwl_dr_base = { 27 .num_of_queues = 512, 28 .max_tfd_queue_size = 65536, 29 .shadow_ram_support = true, 30 .led_compensation = 57, 31 .wd_timeout = IWL_LONG_WD_TIMEOUT, 32 .max_event_log_size = 512, 33 .shadow_reg_enable = true, 34 .pcie_l1_allowed = true, 35 .smem_offset = IWL_DR_SMEM_OFFSET, 36 .smem_len = IWL_DR_SMEM_LEN, 37 .apmg_not_supported = true, 38 .mac_addr_from_csr = 0x30, 39 .min_umac_error_event_table = 0xD0000, 40 .d3_debug_data_base_addr = 0x401000, 41 .d3_debug_data_length = 60 * 1024, 42 .mon_smem_regs = { 43 .write_ptr = { 44 .addr = LDBG_M2S_BUF_WPTR, 45 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, 46 }, 47 .cycle_cnt = { 48 .addr = LDBG_M2S_BUF_WRAP_CNT, 49 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, 50 }, 51 }, 52 .min_txq_size = 128, 53 .gp2_reg_addr = 0xd02c68, 54 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, 55 .mon_dram_regs = { 56 .write_ptr = { 57 .addr = DBGC_CUR_DBGBUF_STATUS, 58 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, 59 }, 60 .cycle_cnt = { 61 .addr = DBGC_DBGBUF_WRAP_AROUND, 62 .mask = 0xffffffff, 63 }, 64 .cur_frag = { 65 .addr = DBGC_CUR_DBGBUF_STATUS, 66 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, 67 }, 68 }, 69 .mon_dbgi_regs = { 70 .write_ptr = { 71 .addr = DBGI_SRAM_FIFO_POINTERS, 72 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, 73 }, 74 }, 75 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 76 .ucode_api_max = IWL_DR_UCODE_API_MAX, 77 .ucode_api_min = IWL_DR_UCODE_API_MIN, 78 }; 79 80 const struct iwl_mac_cfg iwl_dr_mac_cfg = { 81 .device_family = IWL_DEVICE_FAMILY_DR, 82 .base = &iwl_dr_base, 83 .mq_rx_supported = true, 84 .gen2 = true, 85 .integrated = true, 86 .umac_prph_offset = 0x300000, 87 .xtal_latency = 12000, 88 .low_latency_xtal = true, 89 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 90 }; 91 92 MODULE_FIRMWARE(IWL_DR_A_PE_A_FW_MODULE_FIRMWARE(IWL_DR_UCODE_API_MAX)); 93 94