1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2024 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_BZ_UCODE_API_MAX 96 14 15 /* Lowest firmware API version supported */ 16 #define IWL_BZ_UCODE_API_MIN 92 17 18 /* NVM versions */ 19 #define IWL_BZ_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_BZ_DCCM2_OFFSET 0x880000 25 #define IWL_BZ_DCCM2_LEN 0x8000 26 #define IWL_BZ_SMEM_OFFSET 0x400000 27 #define IWL_BZ_SMEM_LEN 0xD0000 28 29 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0" 30 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0" 31 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0" 32 #define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0" 33 #define IWL_BZ_A_FM_C_FW_PRE "iwlwifi-bz-a0-fm-c0" 34 #define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0" 35 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0" 36 #define IWL_GL_C_FM_C_FW_PRE "iwlwifi-gl-c0-fm-c0" 37 38 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 39 IWL_BZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 40 41 static const struct iwl_base_params iwl_bz_base_params = { 42 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 43 .num_of_queues = 512, 44 .max_tfd_queue_size = 65536, 45 .shadow_ram_support = true, 46 .led_compensation = 57, 47 .wd_timeout = IWL_LONG_WD_TIMEOUT, 48 .max_event_log_size = 512, 49 .shadow_reg_enable = true, 50 .pcie_l1_allowed = true, 51 }; 52 53 #define IWL_DEVICE_BZ_COMMON \ 54 .ucode_api_max = IWL_BZ_UCODE_API_MAX, \ 55 .ucode_api_min = IWL_BZ_UCODE_API_MIN, \ 56 .led_mode = IWL_LED_RF_STATE, \ 57 .nvm_hw_section_num = 10, \ 58 .non_shared_ant = ANT_B, \ 59 .dccm_offset = IWL_BZ_DCCM_OFFSET, \ 60 .dccm_len = IWL_BZ_DCCM_LEN, \ 61 .dccm2_offset = IWL_BZ_DCCM2_OFFSET, \ 62 .dccm2_len = IWL_BZ_DCCM2_LEN, \ 63 .smem_offset = IWL_BZ_SMEM_OFFSET, \ 64 .smem_len = IWL_BZ_SMEM_LEN, \ 65 .apmg_not_supported = true, \ 66 .trans.mq_rx_supported = true, \ 67 .vht_mu_mimo_supported = true, \ 68 .mac_addr_from_csr = 0x30, \ 69 .nvm_ver = IWL_BZ_NVM_VERSION, \ 70 .trans.rf_id = true, \ 71 .trans.gen2 = true, \ 72 .nvm_type = IWL_NVM_EXT, \ 73 .dbgc_supported = true, \ 74 .min_umac_error_event_table = 0xD0000, \ 75 .d3_debug_data_base_addr = 0x401000, \ 76 .d3_debug_data_length = 60 * 1024, \ 77 .mon_smem_regs = { \ 78 .write_ptr = { \ 79 .addr = LDBG_M2S_BUF_WPTR, \ 80 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 81 }, \ 82 .cycle_cnt = { \ 83 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 84 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 85 }, \ 86 }, \ 87 .trans.umac_prph_offset = 0x300000, \ 88 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 89 .trans.base_params = &iwl_bz_base_params, \ 90 .min_txq_size = 128, \ 91 .gp2_reg_addr = 0xd02c68, \ 92 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 93 .mon_dram_regs = { \ 94 .write_ptr = { \ 95 .addr = DBGC_CUR_DBGBUF_STATUS, \ 96 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 97 }, \ 98 .cycle_cnt = { \ 99 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 100 .mask = 0xffffffff, \ 101 }, \ 102 .cur_frag = { \ 103 .addr = DBGC_CUR_DBGBUF_STATUS, \ 104 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 105 }, \ 106 }, \ 107 .mon_dbgi_regs = { \ 108 .write_ptr = { \ 109 .addr = DBGI_SRAM_FIFO_POINTERS, \ 110 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 111 }, \ 112 } 113 114 #define IWL_DEVICE_BZ \ 115 IWL_DEVICE_BZ_COMMON, \ 116 .ht_params = &iwl_22000_ht_params 117 118 /* 119 * This size was picked according to 8 MSDUs inside 512 A-MSDUs in an 120 * A-MPDU, with additional overhead to account for processing time. 121 */ 122 #define IWL_NUM_RBDS_BZ_EHT (512 * 16) 123 124 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 125 .device_family = IWL_DEVICE_FAMILY_BZ, 126 .base_params = &iwl_bz_base_params, 127 .mq_rx_supported = true, 128 .rf_id = true, 129 .gen2 = true, 130 .integrated = true, 131 .umac_prph_offset = 0x300000, 132 .xtal_latency = 12000, 133 .low_latency_xtal = true, 134 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 135 }; 136 137 const struct iwl_cfg_trans_params iwl_gl_trans_cfg = { 138 .device_family = IWL_DEVICE_FAMILY_BZ, 139 .base_params = &iwl_bz_base_params, 140 .mq_rx_supported = true, 141 .rf_id = true, 142 .gen2 = true, 143 .umac_prph_offset = 0x300000, 144 .xtal_latency = 12000, 145 .low_latency_xtal = true, 146 }; 147 148 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 149 const char iwl_fm_name[] = "Intel(R) Wi-Fi 7 BE201 320MHz"; 150 const char iwl_wh_name[] = "Intel(R) Wi-Fi 7 BE211 320MHz"; 151 const char iwl_gl_name[] = "Intel(R) Wi-Fi 7 BE200 320MHz"; 152 const char iwl_mtp_name[] = "Intel(R) Wi-Fi 7 BE202 160MHz"; 153 154 const struct iwl_cfg iwl_cfg_bz = { 155 .fw_name_mac = "bz", 156 .uhb_supported = true, 157 IWL_DEVICE_BZ, 158 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 159 .num_rbds = IWL_NUM_RBDS_BZ_EHT, 160 }; 161 162 const struct iwl_cfg iwl_cfg_gl = { 163 .fw_name_mac = "gl", 164 .uhb_supported = true, 165 IWL_DEVICE_BZ, 166 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 167 .num_rbds = IWL_NUM_RBDS_BZ_EHT, 168 }; 169 170 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 171 IWL_FW_AND_PNVM(IWL_BZ_A_GF_A_FW_PRE, IWL_BZ_UCODE_API_MAX); 172 IWL_FW_AND_PNVM(IWL_BZ_A_GF4_A_FW_PRE, IWL_BZ_UCODE_API_MAX); 173 IWL_FW_AND_PNVM(IWL_BZ_A_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX); 174 IWL_FW_AND_PNVM(IWL_BZ_A_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX); 175 IWL_FW_AND_PNVM(IWL_BZ_A_FM4_B_FW_PRE, IWL_BZ_UCODE_API_MAX); 176 IWL_FW_AND_PNVM(IWL_GL_B_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX); 177 IWL_FW_AND_PNVM(IWL_GL_C_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX); 178