xref: /linux/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi (revision ff202c5028a195c07b16e1a2fbb8ca6b7ba11a1c)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rk3588-cru.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/power/rk3588-power.h>
10#include <dt-bindings/reset/rockchip,rk3588-cru.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/ata/ahci.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	compatible = "rockchip,rk3588";
17
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		gpio0 = &gpio0;
24		gpio1 = &gpio1;
25		gpio2 = &gpio2;
26		gpio3 = &gpio3;
27		gpio4 = &gpio4;
28		i2c0 = &i2c0;
29		i2c1 = &i2c1;
30		i2c2 = &i2c2;
31		i2c3 = &i2c3;
32		i2c4 = &i2c4;
33		i2c5 = &i2c5;
34		i2c6 = &i2c6;
35		i2c7 = &i2c7;
36		i2c8 = &i2c8;
37		serial0 = &uart0;
38		serial1 = &uart1;
39		serial2 = &uart2;
40		serial3 = &uart3;
41		serial4 = &uart4;
42		serial5 = &uart5;
43		serial6 = &uart6;
44		serial7 = &uart7;
45		serial8 = &uart8;
46		serial9 = &uart9;
47		spi0 = &spi0;
48		spi1 = &spi1;
49		spi2 = &spi2;
50		spi3 = &spi3;
51		spi4 = &spi4;
52	};
53
54	cpus {
55		#address-cells = <1>;
56		#size-cells = <0>;
57
58		cpu-map {
59			cluster0 {
60				core0 {
61					cpu = <&cpu_l0>;
62				};
63				core1 {
64					cpu = <&cpu_l1>;
65				};
66				core2 {
67					cpu = <&cpu_l2>;
68				};
69				core3 {
70					cpu = <&cpu_l3>;
71				};
72			};
73			cluster1 {
74				core0 {
75					cpu = <&cpu_b0>;
76				};
77				core1 {
78					cpu = <&cpu_b1>;
79				};
80			};
81			cluster2 {
82				core0 {
83					cpu = <&cpu_b2>;
84				};
85				core1 {
86					cpu = <&cpu_b3>;
87				};
88			};
89		};
90
91		cpu_l0: cpu@0 {
92			device_type = "cpu";
93			compatible = "arm,cortex-a55";
94			reg = <0x0>;
95			enable-method = "psci";
96			capacity-dmips-mhz = <530>;
97			clocks = <&scmi_clk SCMI_CLK_CPUL>;
98			assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
99			assigned-clock-rates = <816000000>;
100			cpu-idle-states = <&CPU_SLEEP>;
101			i-cache-size = <32768>;
102			i-cache-line-size = <64>;
103			i-cache-sets = <128>;
104			d-cache-size = <32768>;
105			d-cache-line-size = <64>;
106			d-cache-sets = <128>;
107			next-level-cache = <&l2_cache_l0>;
108			dynamic-power-coefficient = <228>;
109			#cooling-cells = <2>;
110		};
111
112		cpu_l1: cpu@100 {
113			device_type = "cpu";
114			compatible = "arm,cortex-a55";
115			reg = <0x100>;
116			enable-method = "psci";
117			capacity-dmips-mhz = <530>;
118			clocks = <&scmi_clk SCMI_CLK_CPUL>;
119			cpu-idle-states = <&CPU_SLEEP>;
120			i-cache-size = <32768>;
121			i-cache-line-size = <64>;
122			i-cache-sets = <128>;
123			d-cache-size = <32768>;
124			d-cache-line-size = <64>;
125			d-cache-sets = <128>;
126			next-level-cache = <&l2_cache_l1>;
127			dynamic-power-coefficient = <228>;
128			#cooling-cells = <2>;
129		};
130
131		cpu_l2: cpu@200 {
132			device_type = "cpu";
133			compatible = "arm,cortex-a55";
134			reg = <0x200>;
135			enable-method = "psci";
136			capacity-dmips-mhz = <530>;
137			clocks = <&scmi_clk SCMI_CLK_CPUL>;
138			cpu-idle-states = <&CPU_SLEEP>;
139			i-cache-size = <32768>;
140			i-cache-line-size = <64>;
141			i-cache-sets = <128>;
142			d-cache-size = <32768>;
143			d-cache-line-size = <64>;
144			d-cache-sets = <128>;
145			next-level-cache = <&l2_cache_l2>;
146			dynamic-power-coefficient = <228>;
147			#cooling-cells = <2>;
148		};
149
150		cpu_l3: cpu@300 {
151			device_type = "cpu";
152			compatible = "arm,cortex-a55";
153			reg = <0x300>;
154			enable-method = "psci";
155			capacity-dmips-mhz = <530>;
156			clocks = <&scmi_clk SCMI_CLK_CPUL>;
157			cpu-idle-states = <&CPU_SLEEP>;
158			i-cache-size = <32768>;
159			i-cache-line-size = <64>;
160			i-cache-sets = <128>;
161			d-cache-size = <32768>;
162			d-cache-line-size = <64>;
163			d-cache-sets = <128>;
164			next-level-cache = <&l2_cache_l3>;
165			dynamic-power-coefficient = <228>;
166			#cooling-cells = <2>;
167		};
168
169		cpu_b0: cpu@400 {
170			device_type = "cpu";
171			compatible = "arm,cortex-a76";
172			reg = <0x400>;
173			enable-method = "psci";
174			capacity-dmips-mhz = <1024>;
175			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
176			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
177			assigned-clock-rates = <816000000>;
178			cpu-idle-states = <&CPU_SLEEP>;
179			i-cache-size = <65536>;
180			i-cache-line-size = <64>;
181			i-cache-sets = <256>;
182			d-cache-size = <65536>;
183			d-cache-line-size = <64>;
184			d-cache-sets = <256>;
185			next-level-cache = <&l2_cache_b0>;
186			dynamic-power-coefficient = <416>;
187			#cooling-cells = <2>;
188		};
189
190		cpu_b1: cpu@500 {
191			device_type = "cpu";
192			compatible = "arm,cortex-a76";
193			reg = <0x500>;
194			enable-method = "psci";
195			capacity-dmips-mhz = <1024>;
196			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
197			cpu-idle-states = <&CPU_SLEEP>;
198			i-cache-size = <65536>;
199			i-cache-line-size = <64>;
200			i-cache-sets = <256>;
201			d-cache-size = <65536>;
202			d-cache-line-size = <64>;
203			d-cache-sets = <256>;
204			next-level-cache = <&l2_cache_b1>;
205			dynamic-power-coefficient = <416>;
206			#cooling-cells = <2>;
207		};
208
209		cpu_b2: cpu@600 {
210			device_type = "cpu";
211			compatible = "arm,cortex-a76";
212			reg = <0x600>;
213			enable-method = "psci";
214			capacity-dmips-mhz = <1024>;
215			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
216			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
217			assigned-clock-rates = <816000000>;
218			cpu-idle-states = <&CPU_SLEEP>;
219			i-cache-size = <65536>;
220			i-cache-line-size = <64>;
221			i-cache-sets = <256>;
222			d-cache-size = <65536>;
223			d-cache-line-size = <64>;
224			d-cache-sets = <256>;
225			next-level-cache = <&l2_cache_b2>;
226			dynamic-power-coefficient = <416>;
227			#cooling-cells = <2>;
228		};
229
230		cpu_b3: cpu@700 {
231			device_type = "cpu";
232			compatible = "arm,cortex-a76";
233			reg = <0x700>;
234			enable-method = "psci";
235			capacity-dmips-mhz = <1024>;
236			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
237			cpu-idle-states = <&CPU_SLEEP>;
238			i-cache-size = <65536>;
239			i-cache-line-size = <64>;
240			i-cache-sets = <256>;
241			d-cache-size = <65536>;
242			d-cache-line-size = <64>;
243			d-cache-sets = <256>;
244			next-level-cache = <&l2_cache_b3>;
245			dynamic-power-coefficient = <416>;
246			#cooling-cells = <2>;
247		};
248
249		idle-states {
250			entry-method = "psci";
251			CPU_SLEEP: cpu-sleep {
252				compatible = "arm,idle-state";
253				local-timer-stop;
254				arm,psci-suspend-param = <0x0010000>;
255				entry-latency-us = <100>;
256				exit-latency-us = <120>;
257				min-residency-us = <1000>;
258			};
259		};
260
261		l2_cache_l0: l2-cache-l0 {
262			compatible = "cache";
263			cache-size = <131072>;
264			cache-line-size = <64>;
265			cache-sets = <512>;
266			cache-level = <2>;
267			cache-unified;
268			next-level-cache = <&l3_cache>;
269		};
270
271		l2_cache_l1: l2-cache-l1 {
272			compatible = "cache";
273			cache-size = <131072>;
274			cache-line-size = <64>;
275			cache-sets = <512>;
276			cache-level = <2>;
277			cache-unified;
278			next-level-cache = <&l3_cache>;
279		};
280
281		l2_cache_l2: l2-cache-l2 {
282			compatible = "cache";
283			cache-size = <131072>;
284			cache-line-size = <64>;
285			cache-sets = <512>;
286			cache-level = <2>;
287			cache-unified;
288			next-level-cache = <&l3_cache>;
289		};
290
291		l2_cache_l3: l2-cache-l3 {
292			compatible = "cache";
293			cache-size = <131072>;
294			cache-line-size = <64>;
295			cache-sets = <512>;
296			cache-level = <2>;
297			cache-unified;
298			next-level-cache = <&l3_cache>;
299		};
300
301		l2_cache_b0: l2-cache-b0 {
302			compatible = "cache";
303			cache-size = <524288>;
304			cache-line-size = <64>;
305			cache-sets = <1024>;
306			cache-level = <2>;
307			cache-unified;
308			next-level-cache = <&l3_cache>;
309		};
310
311		l2_cache_b1: l2-cache-b1 {
312			compatible = "cache";
313			cache-size = <524288>;
314			cache-line-size = <64>;
315			cache-sets = <1024>;
316			cache-level = <2>;
317			cache-unified;
318			next-level-cache = <&l3_cache>;
319		};
320
321		l2_cache_b2: l2-cache-b2 {
322			compatible = "cache";
323			cache-size = <524288>;
324			cache-line-size = <64>;
325			cache-sets = <1024>;
326			cache-level = <2>;
327			cache-unified;
328			next-level-cache = <&l3_cache>;
329		};
330
331		l2_cache_b3: l2-cache-b3 {
332			compatible = "cache";
333			cache-size = <524288>;
334			cache-line-size = <64>;
335			cache-sets = <1024>;
336			cache-level = <2>;
337			cache-unified;
338			next-level-cache = <&l3_cache>;
339		};
340	};
341
342	/*
343	 * The L3 cache belongs to the DynamIQ Shared Unit (DSU),
344	 * so it's represented here, outside the "cpus" node
345	 */
346	l3_cache: l3-cache {
347		compatible = "cache";
348		cache-size = <3145728>;
349		cache-line-size = <64>;
350		cache-sets = <4096>;
351		cache-level = <3>;
352		cache-unified;
353	};
354
355	display_subsystem: display-subsystem {
356		compatible = "rockchip,display-subsystem";
357		ports = <&vop_out>;
358	};
359
360	firmware {
361		optee: optee {
362			compatible = "linaro,optee-tz";
363			method = "smc";
364		};
365
366		scmi: scmi {
367			compatible = "arm,scmi-smc";
368			arm,smc-id = <0x82000010>;
369			shmem = <&scmi_shmem>;
370			#address-cells = <1>;
371			#size-cells = <0>;
372
373			scmi_clk: protocol@14 {
374				reg = <0x14>;
375				#clock-cells = <1>;
376			};
377
378			scmi_reset: protocol@16 {
379				reg = <0x16>;
380				#reset-cells = <1>;
381			};
382		};
383	};
384
385	pmu-a55 {
386		compatible = "arm,cortex-a55-pmu";
387		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
388	};
389
390	pmu-a76 {
391		compatible = "arm,cortex-a76-pmu";
392		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
393	};
394
395	psci {
396		compatible = "arm,psci-1.0";
397		method = "smc";
398	};
399
400	spll: clock-0 {
401		compatible = "fixed-clock";
402		clock-frequency = <702000000>;
403		clock-output-names = "spll";
404		#clock-cells = <0>;
405	};
406
407	timer {
408		compatible = "arm,armv8-timer";
409		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
410			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
411			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
412			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
413			     <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
414		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
415	};
416
417	xin24m: clock-1 {
418		compatible = "fixed-clock";
419		clock-frequency = <24000000>;
420		clock-output-names = "xin24m";
421		#clock-cells = <0>;
422	};
423
424	xin32k: clock-2 {
425		compatible = "fixed-clock";
426		clock-frequency = <32768>;
427		clock-output-names = "xin32k";
428		#clock-cells = <0>;
429	};
430
431	pmu_sram: sram@10f000 {
432		compatible = "mmio-sram";
433		reg = <0x0 0x0010f000 0x0 0x100>;
434		ranges = <0 0x0 0x0010f000 0x100>;
435		#address-cells = <1>;
436		#size-cells = <1>;
437
438		scmi_shmem: sram@0 {
439			compatible = "arm,scmi-shmem";
440			reg = <0x0 0x100>;
441		};
442	};
443
444	gpu: gpu@fb000000 {
445		compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
446		reg = <0x0 0xfb000000 0x0 0x200000>;
447		#cooling-cells = <2>;
448		assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
449		assigned-clock-rates = <200000000>;
450		clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
451			 <&cru CLK_GPU_STACKS>;
452		clock-names = "core", "coregroup", "stacks";
453		dynamic-power-coefficient = <2982>;
454		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
455			     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
456			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
457		interrupt-names = "job", "mmu", "gpu";
458		power-domains = <&power RK3588_PD_GPU>;
459		status = "disabled";
460	};
461
462	usb_host0_xhci: usb@fc000000 {
463		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
464		reg = <0x0 0xfc000000 0x0 0x400000>;
465		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
466		clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
467			 <&cru ACLK_USB3OTG0>;
468		clock-names = "ref_clk", "suspend_clk", "bus_clk";
469		dr_mode = "otg";
470		phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
471		phy-names = "usb2-phy", "usb3-phy";
472		phy_type = "utmi_wide";
473		power-domains = <&power RK3588_PD_USB>;
474		resets = <&cru SRST_A_USB3OTG0>;
475		snps,dis_enblslpm_quirk;
476		snps,dis-u1-entry-quirk;
477		snps,dis-u2-entry-quirk;
478		snps,dis-u2-freeclk-exists-quirk;
479		snps,dis-del-phy-power-chg-quirk;
480		snps,dis-tx-ipgap-linecheck-quirk;
481		status = "disabled";
482	};
483
484	usb_host0_ehci: usb@fc800000 {
485		compatible = "rockchip,rk3588-ehci", "generic-ehci";
486		reg = <0x0 0xfc800000 0x0 0x40000>;
487		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
488		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
489		phys = <&u2phy2_host>;
490		phy-names = "usb";
491		power-domains = <&power RK3588_PD_USB>;
492		status = "disabled";
493	};
494
495	usb_host0_ohci: usb@fc840000 {
496		compatible = "rockchip,rk3588-ohci", "generic-ohci";
497		reg = <0x0 0xfc840000 0x0 0x40000>;
498		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
499		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
500		phys = <&u2phy2_host>;
501		phy-names = "usb";
502		power-domains = <&power RK3588_PD_USB>;
503		status = "disabled";
504	};
505
506	usb_host1_ehci: usb@fc880000 {
507		compatible = "rockchip,rk3588-ehci", "generic-ehci";
508		reg = <0x0 0xfc880000 0x0 0x40000>;
509		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
510		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
511		phys = <&u2phy3_host>;
512		phy-names = "usb";
513		power-domains = <&power RK3588_PD_USB>;
514		status = "disabled";
515	};
516
517	usb_host1_ohci: usb@fc8c0000 {
518		compatible = "rockchip,rk3588-ohci", "generic-ohci";
519		reg = <0x0 0xfc8c0000 0x0 0x40000>;
520		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
521		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
522		phys = <&u2phy3_host>;
523		phy-names = "usb";
524		power-domains = <&power RK3588_PD_USB>;
525		status = "disabled";
526	};
527
528	usb_host2_xhci: usb@fcd00000 {
529		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
530		reg = <0x0 0xfcd00000 0x0 0x400000>;
531		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
532		clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
533			 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
534			 <&cru CLK_PIPEPHY2_PIPE_U3_G>;
535		clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
536		dr_mode = "host";
537		phys = <&combphy2_psu PHY_TYPE_USB3>;
538		phy-names = "usb3-phy";
539		phy_type = "utmi_wide";
540		resets = <&cru SRST_A_USB3OTG2>;
541		snps,dis_enblslpm_quirk;
542		snps,dis-u2-freeclk-exists-quirk;
543		snps,dis-del-phy-power-chg-quirk;
544		snps,dis-tx-ipgap-linecheck-quirk;
545		snps,dis_rxdet_inp3_quirk;
546		status = "disabled";
547	};
548
549	mmu600_pcie: iommu@fc900000 {
550		compatible = "arm,smmu-v3";
551		reg = <0x0 0xfc900000 0x0 0x200000>;
552		interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING 0>,
553			     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING 0>,
554			     <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>,
555			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
556		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
557		#iommu-cells = <1>;
558	};
559
560	mmu600_php: iommu@fcb00000 {
561		compatible = "arm,smmu-v3";
562		reg = <0x0 0xfcb00000 0x0 0x200000>;
563		interrupts = <GIC_SPI 381 IRQ_TYPE_EDGE_RISING 0>,
564			     <GIC_SPI 383 IRQ_TYPE_EDGE_RISING 0>,
565			     <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>,
566			     <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>;
567		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
568		#iommu-cells = <1>;
569		status = "disabled";
570	};
571
572	pmu1grf: syscon@fd58a000 {
573		compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
574		reg = <0x0 0xfd58a000 0x0 0x10000>;
575	};
576
577	sys_grf: syscon@fd58c000 {
578		compatible = "rockchip,rk3588-sys-grf", "syscon";
579		reg = <0x0 0xfd58c000 0x0 0x1000>;
580	};
581
582	vop_grf: syscon@fd5a4000 {
583		compatible = "rockchip,rk3588-vop-grf", "syscon";
584		reg = <0x0 0xfd5a4000 0x0 0x2000>;
585	};
586
587	vo0_grf: syscon@fd5a6000 {
588		compatible = "rockchip,rk3588-vo0-grf", "syscon";
589		reg = <0x0 0xfd5a6000 0x0 0x2000>;
590		clocks = <&cru PCLK_VO0GRF>;
591	};
592
593	vo1_grf: syscon@fd5a8000 {
594		compatible = "rockchip,rk3588-vo1-grf", "syscon";
595		reg = <0x0 0xfd5a8000 0x0 0x4000>;
596		clocks = <&cru PCLK_VO1GRF>;
597	};
598
599	usb_grf: syscon@fd5ac000 {
600		compatible = "rockchip,rk3588-usb-grf", "syscon";
601		reg = <0x0 0xfd5ac000 0x0 0x4000>;
602	};
603
604	php_grf: syscon@fd5b0000 {
605		compatible = "rockchip,rk3588-php-grf", "syscon";
606		reg = <0x0 0xfd5b0000 0x0 0x1000>;
607	};
608
609	pipe_phy0_grf: syscon@fd5bc000 {
610		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
611		reg = <0x0 0xfd5bc000 0x0 0x100>;
612	};
613
614	pipe_phy2_grf: syscon@fd5c4000 {
615		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
616		reg = <0x0 0xfd5c4000 0x0 0x100>;
617	};
618
619	usbdpphy0_grf: syscon@fd5c8000 {
620		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
621		reg = <0x0 0xfd5c8000 0x0 0x4000>;
622	};
623
624	usb2phy0_grf: syscon@fd5d0000 {
625		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
626		reg = <0x0 0xfd5d0000 0x0 0x4000>;
627		#address-cells = <1>;
628		#size-cells = <1>;
629
630		u2phy0: usb2phy@0 {
631			compatible = "rockchip,rk3588-usb2phy";
632			reg = <0x0 0x10>;
633			#clock-cells = <0>;
634			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
635			clock-names = "phyclk";
636			clock-output-names = "usb480m_phy0";
637			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
638			resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
639			reset-names = "phy", "apb";
640			status = "disabled";
641
642			u2phy0_otg: otg-port {
643				#phy-cells = <0>;
644				status = "disabled";
645			};
646		};
647	};
648
649	usb2phy2_grf: syscon@fd5d8000 {
650		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
651		reg = <0x0 0xfd5d8000 0x0 0x4000>;
652		#address-cells = <1>;
653		#size-cells = <1>;
654
655		u2phy2: usb2phy@8000 {
656			compatible = "rockchip,rk3588-usb2phy";
657			reg = <0x8000 0x10>;
658			#clock-cells = <0>;
659			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
660			clock-names = "phyclk";
661			clock-output-names = "usb480m_phy2";
662			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
663			resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
664			reset-names = "phy", "apb";
665			status = "disabled";
666
667			u2phy2_host: host-port {
668				#phy-cells = <0>;
669				status = "disabled";
670			};
671		};
672	};
673
674	usb2phy3_grf: syscon@fd5dc000 {
675		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
676		reg = <0x0 0xfd5dc000 0x0 0x4000>;
677		#address-cells = <1>;
678		#size-cells = <1>;
679
680		u2phy3: usb2phy@c000 {
681			compatible = "rockchip,rk3588-usb2phy";
682			reg = <0xc000 0x10>;
683			#clock-cells = <0>;
684			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
685			clock-names = "phyclk";
686			clock-output-names = "usb480m_phy3";
687			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
688			resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
689			reset-names = "phy", "apb";
690			status = "disabled";
691
692			u2phy3_host: host-port {
693				#phy-cells = <0>;
694				status = "disabled";
695			};
696		};
697	};
698
699	hdptxphy0_grf: syscon@fd5e0000 {
700		compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
701		reg = <0x0 0xfd5e0000 0x0 0x100>;
702	};
703
704	ioc: syscon@fd5f0000 {
705		compatible = "rockchip,rk3588-ioc", "syscon";
706		reg = <0x0 0xfd5f0000 0x0 0x10000>;
707	};
708
709	system_sram1: sram@fd600000 {
710		compatible = "mmio-sram";
711		reg = <0x0 0xfd600000 0x0 0x100000>;
712		ranges = <0x0 0x0 0xfd600000 0x100000>;
713		#address-cells = <1>;
714		#size-cells = <1>;
715	};
716
717	cru: clock-controller@fd7c0000 {
718		compatible = "rockchip,rk3588-cru";
719		reg = <0x0 0xfd7c0000 0x0 0x5c000>;
720		assigned-clocks =
721			<&cru PLL_PPLL>, <&cru PLL_AUPLL>,
722			<&cru PLL_NPLL>, <&cru PLL_GPLL>,
723			<&cru ACLK_CENTER_ROOT>,
724			<&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
725			<&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
726			<&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
727			<&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
728			<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
729			<&cru CLK_GPU>;
730		assigned-clock-rates =
731			<1100000000>, <786432000>,
732			<850000000>, <1188000000>,
733			<702000000>,
734			<400000000>, <500000000>,
735			<800000000>, <100000000>,
736			<400000000>, <100000000>,
737			<200000000>, <500000000>,
738			<375000000>, <150000000>,
739			<200000000>;
740		rockchip,grf = <&php_grf>;
741		#clock-cells = <1>;
742		#reset-cells = <1>;
743	};
744
745	i2c0: i2c@fd880000 {
746		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
747		reg = <0x0 0xfd880000 0x0 0x1000>;
748		interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
749		clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
750		clock-names = "i2c", "pclk";
751		pinctrl-0 = <&i2c0m0_xfer>;
752		pinctrl-names = "default";
753		#address-cells = <1>;
754		#size-cells = <0>;
755		status = "disabled";
756	};
757
758	uart0: serial@fd890000 {
759		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
760		reg = <0x0 0xfd890000 0x0 0x100>;
761		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
762		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
763		clock-names = "baudclk", "apb_pclk";
764		dmas = <&dmac0 6>, <&dmac0 7>;
765		dma-names = "tx", "rx";
766		pinctrl-0 = <&uart0m1_xfer>;
767		pinctrl-names = "default";
768		reg-shift = <2>;
769		reg-io-width = <4>;
770		status = "disabled";
771	};
772
773	pwm0: pwm@fd8b0000 {
774		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
775		reg = <0x0 0xfd8b0000 0x0 0x10>;
776		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
777		clock-names = "pwm", "pclk";
778		pinctrl-0 = <&pwm0m0_pins>;
779		pinctrl-names = "default";
780		#pwm-cells = <3>;
781		status = "disabled";
782	};
783
784	pwm1: pwm@fd8b0010 {
785		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
786		reg = <0x0 0xfd8b0010 0x0 0x10>;
787		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
788		clock-names = "pwm", "pclk";
789		pinctrl-0 = <&pwm1m0_pins>;
790		pinctrl-names = "default";
791		#pwm-cells = <3>;
792		status = "disabled";
793	};
794
795	pwm2: pwm@fd8b0020 {
796		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
797		reg = <0x0 0xfd8b0020 0x0 0x10>;
798		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
799		clock-names = "pwm", "pclk";
800		pinctrl-0 = <&pwm2m0_pins>;
801		pinctrl-names = "default";
802		#pwm-cells = <3>;
803		status = "disabled";
804	};
805
806	pwm3: pwm@fd8b0030 {
807		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
808		reg = <0x0 0xfd8b0030 0x0 0x10>;
809		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
810		clock-names = "pwm", "pclk";
811		pinctrl-0 = <&pwm3m0_pins>;
812		pinctrl-names = "default";
813		#pwm-cells = <3>;
814		status = "disabled";
815	};
816
817	pmu: power-management@fd8d8000 {
818		compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
819		reg = <0x0 0xfd8d8000 0x0 0x400>;
820
821		power: power-controller {
822			compatible = "rockchip,rk3588-power-controller";
823			#address-cells = <1>;
824			#power-domain-cells = <1>;
825			#size-cells = <0>;
826			status = "okay";
827
828			/* These power domains are grouped by VD_NPU */
829			power-domain@RK3588_PD_NPU {
830				reg = <RK3588_PD_NPU>;
831				#power-domain-cells = <0>;
832				#address-cells = <1>;
833				#size-cells = <0>;
834
835				power-domain@RK3588_PD_NPUTOP {
836					reg = <RK3588_PD_NPUTOP>;
837					clocks = <&cru HCLK_NPU_ROOT>,
838						 <&cru PCLK_NPU_ROOT>,
839						 <&cru CLK_NPU_DSU0>,
840						 <&cru HCLK_NPU_CM0_ROOT>;
841					pm_qos = <&qos_npu0_mwr>,
842						 <&qos_npu0_mro>,
843						 <&qos_mcu_npu>;
844					#power-domain-cells = <0>;
845					#address-cells = <1>;
846					#size-cells = <0>;
847
848					power-domain@RK3588_PD_NPU1 {
849						reg = <RK3588_PD_NPU1>;
850						clocks = <&cru HCLK_NPU_ROOT>,
851							 <&cru PCLK_NPU_ROOT>,
852							 <&cru CLK_NPU_DSU0>;
853						pm_qos = <&qos_npu1>;
854						#power-domain-cells = <0>;
855					};
856					power-domain@RK3588_PD_NPU2 {
857						reg = <RK3588_PD_NPU2>;
858						clocks = <&cru HCLK_NPU_ROOT>,
859							 <&cru PCLK_NPU_ROOT>,
860							 <&cru CLK_NPU_DSU0>;
861						pm_qos = <&qos_npu2>;
862						#power-domain-cells = <0>;
863					};
864				};
865			};
866			/* These power domains are grouped by VD_GPU */
867			power-domain@RK3588_PD_GPU {
868				reg = <RK3588_PD_GPU>;
869				clocks = <&cru CLK_GPU>,
870					 <&cru CLK_GPU_COREGROUP>,
871					 <&cru CLK_GPU_STACKS>;
872				pm_qos = <&qos_gpu_m0>,
873					 <&qos_gpu_m1>,
874					 <&qos_gpu_m2>,
875					 <&qos_gpu_m3>;
876				#power-domain-cells = <0>;
877			};
878			/* These power domains are grouped by VD_VCODEC */
879			power-domain@RK3588_PD_VCODEC {
880				reg = <RK3588_PD_VCODEC>;
881				#address-cells = <1>;
882				#size-cells = <0>;
883				#power-domain-cells = <0>;
884
885				power-domain@RK3588_PD_RKVDEC0 {
886					reg = <RK3588_PD_RKVDEC0>;
887					clocks = <&cru HCLK_RKVDEC0>,
888						 <&cru HCLK_VDPU_ROOT>,
889						 <&cru ACLK_VDPU_ROOT>,
890						 <&cru ACLK_RKVDEC0>,
891						 <&cru ACLK_RKVDEC_CCU>;
892					pm_qos = <&qos_rkvdec0>;
893					#power-domain-cells = <0>;
894				};
895				power-domain@RK3588_PD_RKVDEC1 {
896					reg = <RK3588_PD_RKVDEC1>;
897					clocks = <&cru HCLK_RKVDEC1>,
898						 <&cru HCLK_VDPU_ROOT>,
899						 <&cru ACLK_VDPU_ROOT>,
900						 <&cru ACLK_RKVDEC1>;
901					pm_qos = <&qos_rkvdec1>;
902					#power-domain-cells = <0>;
903				};
904				power-domain@RK3588_PD_VENC0 {
905					reg = <RK3588_PD_VENC0>;
906					clocks = <&cru HCLK_RKVENC0>,
907						 <&cru ACLK_RKVENC0>;
908					pm_qos = <&qos_rkvenc0_m0ro>,
909						 <&qos_rkvenc0_m1ro>,
910						 <&qos_rkvenc0_m2wo>;
911					#address-cells = <1>;
912					#size-cells = <0>;
913					#power-domain-cells = <0>;
914
915					power-domain@RK3588_PD_VENC1 {
916						reg = <RK3588_PD_VENC1>;
917						clocks = <&cru HCLK_RKVENC1>,
918							 <&cru HCLK_RKVENC0>,
919							 <&cru ACLK_RKVENC0>,
920							 <&cru ACLK_RKVENC1>;
921						pm_qos = <&qos_rkvenc1_m0ro>,
922							 <&qos_rkvenc1_m1ro>,
923							 <&qos_rkvenc1_m2wo>;
924						#power-domain-cells = <0>;
925					};
926				};
927			};
928			/* These power domains are grouped by VD_LOGIC */
929			power-domain@RK3588_PD_VDPU {
930				reg = <RK3588_PD_VDPU>;
931				clocks = <&cru HCLK_VDPU_ROOT>,
932					 <&cru ACLK_VDPU_LOW_ROOT>,
933					 <&cru ACLK_VDPU_ROOT>,
934					 <&cru ACLK_JPEG_DECODER_ROOT>,
935					 <&cru ACLK_IEP2P0>,
936					 <&cru HCLK_IEP2P0>,
937					 <&cru ACLK_JPEG_ENCODER0>,
938					 <&cru HCLK_JPEG_ENCODER0>,
939					 <&cru ACLK_JPEG_ENCODER1>,
940					 <&cru HCLK_JPEG_ENCODER1>,
941					 <&cru ACLK_JPEG_ENCODER2>,
942					 <&cru HCLK_JPEG_ENCODER2>,
943					 <&cru ACLK_JPEG_ENCODER3>,
944					 <&cru HCLK_JPEG_ENCODER3>,
945					 <&cru ACLK_JPEG_DECODER>,
946					 <&cru HCLK_JPEG_DECODER>,
947					 <&cru ACLK_RGA2>,
948					 <&cru HCLK_RGA2>;
949				pm_qos = <&qos_iep>,
950					 <&qos_jpeg_dec>,
951					 <&qos_jpeg_enc0>,
952					 <&qos_jpeg_enc1>,
953					 <&qos_jpeg_enc2>,
954					 <&qos_jpeg_enc3>,
955					 <&qos_rga2_mro>,
956					 <&qos_rga2_mwo>;
957				#address-cells = <1>;
958				#size-cells = <0>;
959				#power-domain-cells = <0>;
960
961
962				power-domain@RK3588_PD_AV1 {
963					reg = <RK3588_PD_AV1>;
964					clocks = <&cru PCLK_AV1>,
965						 <&cru ACLK_AV1>,
966						 <&cru HCLK_VDPU_ROOT>;
967					pm_qos = <&qos_av1>;
968					#power-domain-cells = <0>;
969				};
970				power-domain@RK3588_PD_RKVDEC0 {
971					reg = <RK3588_PD_RKVDEC0>;
972					clocks = <&cru HCLK_RKVDEC0>,
973						 <&cru HCLK_VDPU_ROOT>,
974						 <&cru ACLK_VDPU_ROOT>,
975						 <&cru ACLK_RKVDEC0>;
976					pm_qos = <&qos_rkvdec0>;
977					#power-domain-cells = <0>;
978				};
979				power-domain@RK3588_PD_RKVDEC1 {
980					reg = <RK3588_PD_RKVDEC1>;
981					clocks = <&cru HCLK_RKVDEC1>,
982						 <&cru HCLK_VDPU_ROOT>,
983						 <&cru ACLK_VDPU_ROOT>;
984					pm_qos = <&qos_rkvdec1>;
985					#power-domain-cells = <0>;
986				};
987				power-domain@RK3588_PD_RGA30 {
988					reg = <RK3588_PD_RGA30>;
989					clocks = <&cru ACLK_RGA3_0>,
990						 <&cru HCLK_RGA3_0>;
991					pm_qos = <&qos_rga3_0>;
992					#power-domain-cells = <0>;
993				};
994			};
995			power-domain@RK3588_PD_VOP {
996				reg = <RK3588_PD_VOP>;
997				clocks = <&cru PCLK_VOP_ROOT>,
998					 <&cru HCLK_VOP_ROOT>,
999					 <&cru ACLK_VOP>;
1000				pm_qos = <&qos_vop_m0>,
1001					 <&qos_vop_m1>;
1002				#address-cells = <1>;
1003				#size-cells = <0>;
1004				#power-domain-cells = <0>;
1005
1006				power-domain@RK3588_PD_VO0 {
1007					reg = <RK3588_PD_VO0>;
1008					clocks = <&cru PCLK_VO0_ROOT>,
1009						 <&cru PCLK_VO0_S_ROOT>,
1010						 <&cru HCLK_VO0_S_ROOT>,
1011						 <&cru ACLK_VO0_ROOT>,
1012						 <&cru HCLK_HDCP0>,
1013						 <&cru ACLK_HDCP0>,
1014						 <&cru HCLK_VOP_ROOT>;
1015					pm_qos = <&qos_hdcp0>;
1016					#power-domain-cells = <0>;
1017				};
1018			};
1019			power-domain@RK3588_PD_VO1 {
1020				reg = <RK3588_PD_VO1>;
1021				clocks = <&cru PCLK_VO1_ROOT>,
1022					 <&cru PCLK_VO1_S_ROOT>,
1023					 <&cru HCLK_VO1_S_ROOT>,
1024					 <&cru HCLK_HDCP1>,
1025					 <&cru ACLK_HDCP1>,
1026					 <&cru ACLK_HDMIRX_ROOT>,
1027					 <&cru HCLK_VO1USB_TOP_ROOT>;
1028				pm_qos = <&qos_hdcp1>,
1029					 <&qos_hdmirx>;
1030				#power-domain-cells = <0>;
1031			};
1032			power-domain@RK3588_PD_VI {
1033				reg = <RK3588_PD_VI>;
1034				clocks = <&cru HCLK_VI_ROOT>,
1035					 <&cru PCLK_VI_ROOT>,
1036					 <&cru HCLK_ISP0>,
1037					 <&cru ACLK_ISP0>,
1038					 <&cru HCLK_VICAP>,
1039					 <&cru ACLK_VICAP>;
1040				pm_qos = <&qos_isp0_mro>,
1041					 <&qos_isp0_mwo>,
1042					 <&qos_vicap_m0>,
1043					 <&qos_vicap_m1>;
1044				#address-cells = <1>;
1045				#size-cells = <0>;
1046				#power-domain-cells = <0>;
1047
1048				power-domain@RK3588_PD_ISP1 {
1049					reg = <RK3588_PD_ISP1>;
1050					clocks = <&cru HCLK_ISP1>,
1051						 <&cru ACLK_ISP1>,
1052						 <&cru HCLK_VI_ROOT>,
1053						 <&cru PCLK_VI_ROOT>;
1054					pm_qos = <&qos_isp1_mwo>,
1055						 <&qos_isp1_mro>;
1056					#power-domain-cells = <0>;
1057				};
1058				power-domain@RK3588_PD_FEC {
1059					reg = <RK3588_PD_FEC>;
1060					clocks = <&cru HCLK_FISHEYE0>,
1061						 <&cru ACLK_FISHEYE0>,
1062						 <&cru HCLK_FISHEYE1>,
1063						 <&cru ACLK_FISHEYE1>,
1064						 <&cru PCLK_VI_ROOT>;
1065					pm_qos = <&qos_fisheye0>,
1066						 <&qos_fisheye1>;
1067					#power-domain-cells = <0>;
1068				};
1069			};
1070			power-domain@RK3588_PD_RGA31 {
1071				reg = <RK3588_PD_RGA31>;
1072				clocks = <&cru HCLK_RGA3_1>,
1073					 <&cru ACLK_RGA3_1>;
1074				pm_qos = <&qos_rga3_1>;
1075				#power-domain-cells = <0>;
1076			};
1077			power-domain@RK3588_PD_USB {
1078				reg = <RK3588_PD_USB>;
1079				clocks = <&cru PCLK_PHP_ROOT>,
1080					 <&cru ACLK_USB_ROOT>,
1081					 <&cru ACLK_USB>,
1082					 <&cru HCLK_USB_ROOT>,
1083					 <&cru HCLK_HOST0>,
1084					 <&cru HCLK_HOST_ARB0>,
1085					 <&cru HCLK_HOST1>,
1086					 <&cru HCLK_HOST_ARB1>;
1087				pm_qos = <&qos_usb3_0>,
1088					 <&qos_usb3_1>,
1089					 <&qos_usb2host_0>,
1090					 <&qos_usb2host_1>;
1091				#power-domain-cells = <0>;
1092			};
1093			power-domain@RK3588_PD_GMAC {
1094				reg = <RK3588_PD_GMAC>;
1095				clocks = <&cru PCLK_PHP_ROOT>,
1096					 <&cru ACLK_PCIE_ROOT>,
1097					 <&cru ACLK_PHP_ROOT>;
1098				#power-domain-cells = <0>;
1099			};
1100			power-domain@RK3588_PD_PCIE {
1101				reg = <RK3588_PD_PCIE>;
1102				clocks = <&cru PCLK_PHP_ROOT>,
1103					 <&cru ACLK_PCIE_ROOT>,
1104					 <&cru ACLK_PHP_ROOT>;
1105				#power-domain-cells = <0>;
1106			};
1107			power-domain@RK3588_PD_SDIO {
1108				reg = <RK3588_PD_SDIO>;
1109				clocks = <&cru HCLK_SDIO>,
1110					 <&cru HCLK_NVM_ROOT>;
1111				pm_qos = <&qos_sdio>;
1112				#power-domain-cells = <0>;
1113			};
1114			power-domain@RK3588_PD_AUDIO {
1115				reg = <RK3588_PD_AUDIO>;
1116				clocks = <&cru HCLK_AUDIO_ROOT>,
1117					 <&cru PCLK_AUDIO_ROOT>;
1118				#power-domain-cells = <0>;
1119			};
1120			power-domain@RK3588_PD_SDMMC {
1121				reg = <RK3588_PD_SDMMC>;
1122				pm_qos = <&qos_sdmmc>;
1123				#power-domain-cells = <0>;
1124			};
1125		};
1126	};
1127
1128	vpu121: video-codec@fdb50000 {
1129		compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
1130		reg = <0x0 0xfdb50000 0x0 0x800>;
1131		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1132		interrupt-names = "vdpu";
1133		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1134		clock-names = "aclk", "hclk";
1135		iommus = <&vpu121_mmu>;
1136		power-domains = <&power RK3588_PD_VDPU>;
1137	};
1138
1139	vpu121_mmu: iommu@fdb50800 {
1140		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1141		reg = <0x0 0xfdb50800 0x0 0x40>;
1142		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1143		clock-names = "aclk", "iface";
1144		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1145		power-domains = <&power RK3588_PD_VDPU>;
1146		#iommu-cells = <0>;
1147	};
1148
1149	rga: rga@fdb80000 {
1150		compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga";
1151		reg = <0x0 0xfdb80000 0x0 0x180>;
1152		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1153		clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>;
1154		clock-names = "aclk", "hclk", "sclk";
1155		resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>;
1156		reset-names = "core", "axi", "ahb";
1157		power-domains = <&power RK3588_PD_VDPU>;
1158	};
1159
1160	vepu121_0: video-codec@fdba0000 {
1161		compatible = "rockchip,rk3588-vepu121";
1162		reg = <0x0 0xfdba0000 0x0 0x800>;
1163		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
1164		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
1165		clock-names = "aclk", "hclk";
1166		iommus = <&vepu121_0_mmu>;
1167		power-domains = <&power RK3588_PD_VDPU>;
1168	};
1169
1170	vepu121_0_mmu: iommu@fdba0800 {
1171		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1172		reg = <0x0 0xfdba0800 0x0 0x40>;
1173		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
1174		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
1175		clock-names = "aclk", "iface";
1176		power-domains = <&power RK3588_PD_VDPU>;
1177		#iommu-cells = <0>;
1178	};
1179
1180	vepu121_1: video-codec@fdba4000 {
1181		compatible = "rockchip,rk3588-vepu121";
1182		reg = <0x0 0xfdba4000 0x0 0x800>;
1183		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
1184		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
1185		clock-names = "aclk", "hclk";
1186		iommus = <&vepu121_1_mmu>;
1187		power-domains = <&power RK3588_PD_VDPU>;
1188	};
1189
1190	vepu121_1_mmu: iommu@fdba4800 {
1191		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1192		reg = <0x0 0xfdba4800 0x0 0x40>;
1193		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
1194		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
1195		clock-names = "aclk", "iface";
1196		power-domains = <&power RK3588_PD_VDPU>;
1197		#iommu-cells = <0>;
1198	};
1199
1200	vepu121_2: video-codec@fdba8000 {
1201		compatible = "rockchip,rk3588-vepu121";
1202		reg = <0x0 0xfdba8000 0x0 0x800>;
1203		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
1204		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
1205		clock-names = "aclk", "hclk";
1206		iommus = <&vepu121_2_mmu>;
1207		power-domains = <&power RK3588_PD_VDPU>;
1208	};
1209
1210	vepu121_2_mmu: iommu@fdba8800 {
1211		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1212		reg = <0x0 0xfdba8800 0x0 0x40>;
1213		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
1214		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
1215		clock-names = "aclk", "iface";
1216		power-domains = <&power RK3588_PD_VDPU>;
1217		#iommu-cells = <0>;
1218	};
1219
1220	vepu121_3: video-codec@fdbac000 {
1221		compatible = "rockchip,rk3588-vepu121";
1222		reg = <0x0 0xfdbac000 0x0 0x800>;
1223		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
1224		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
1225		clock-names = "aclk", "hclk";
1226		iommus = <&vepu121_3_mmu>;
1227		power-domains = <&power RK3588_PD_VDPU>;
1228	};
1229
1230	vepu121_3_mmu: iommu@fdbac800 {
1231		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1232		reg = <0x0 0xfdbac800 0x0 0x40>;
1233		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
1234		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
1235		clock-names = "aclk", "iface";
1236		power-domains = <&power RK3588_PD_VDPU>;
1237		#iommu-cells = <0>;
1238	};
1239
1240	av1d: video-codec@fdc70000 {
1241		compatible = "rockchip,rk3588-av1-vpu";
1242		reg = <0x0 0xfdc70000 0x0 0x800>;
1243		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1244		interrupt-names = "vdpu";
1245		assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1246		assigned-clock-rates = <400000000>, <400000000>;
1247		clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
1248		clock-names = "aclk", "hclk";
1249		power-domains = <&power RK3588_PD_AV1>;
1250		resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
1251	};
1252
1253	vop: vop@fdd90000 {
1254		compatible = "rockchip,rk3588-vop";
1255		reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
1256		reg-names = "vop", "gamma-lut";
1257		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1258		clocks = <&cru ACLK_VOP>,
1259			 <&cru HCLK_VOP>,
1260			 <&cru DCLK_VOP0>,
1261			 <&cru DCLK_VOP1>,
1262			 <&cru DCLK_VOP2>,
1263			 <&cru DCLK_VOP3>,
1264			 <&cru PCLK_VOP_ROOT>;
1265		clock-names = "aclk",
1266			      "hclk",
1267			      "dclk_vp0",
1268			      "dclk_vp1",
1269			      "dclk_vp2",
1270			      "dclk_vp3",
1271			      "pclk_vop";
1272		iommus = <&vop_mmu>;
1273		power-domains = <&power RK3588_PD_VOP>;
1274		rockchip,grf = <&sys_grf>;
1275		rockchip,vop-grf = <&vop_grf>;
1276		rockchip,vo1-grf = <&vo1_grf>;
1277		rockchip,pmu = <&pmu>;
1278		status = "disabled";
1279
1280		vop_out: ports {
1281			#address-cells = <1>;
1282			#size-cells = <0>;
1283
1284			vp0: port@0 {
1285				#address-cells = <1>;
1286				#size-cells = <0>;
1287				reg = <0>;
1288			};
1289
1290			vp1: port@1 {
1291				#address-cells = <1>;
1292				#size-cells = <0>;
1293				reg = <1>;
1294			};
1295
1296			vp2: port@2 {
1297				#address-cells = <1>;
1298				#size-cells = <0>;
1299				reg = <2>;
1300			};
1301
1302			vp3: port@3 {
1303				#address-cells = <1>;
1304				#size-cells = <0>;
1305				reg = <3>;
1306			};
1307		};
1308	};
1309
1310	vop_mmu: iommu@fdd97e00 {
1311		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
1312		reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
1313		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1314		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1315		clock-names = "aclk", "iface";
1316		#iommu-cells = <0>;
1317		power-domains = <&power RK3588_PD_VOP>;
1318		status = "disabled";
1319	};
1320
1321	i2s4_8ch: i2s@fddc0000 {
1322		compatible = "rockchip,rk3588-i2s-tdm";
1323		reg = <0x0 0xfddc0000 0x0 0x1000>;
1324		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
1325		clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
1326		clock-names = "mclk_tx", "mclk_rx", "hclk";
1327		assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1328		assigned-clock-parents = <&cru PLL_AUPLL>;
1329		dmas = <&dmac2 0>;
1330		dma-names = "tx";
1331		power-domains = <&power RK3588_PD_VO0>;
1332		resets = <&cru SRST_M_I2S4_8CH_TX>;
1333		reset-names = "tx-m";
1334		#sound-dai-cells = <0>;
1335		status = "disabled";
1336	};
1337
1338	i2s5_8ch: i2s@fddf0000 {
1339		compatible = "rockchip,rk3588-i2s-tdm";
1340		reg = <0x0 0xfddf0000 0x0 0x1000>;
1341		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
1342		clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
1343		clock-names = "mclk_tx", "mclk_rx", "hclk";
1344		assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1345		assigned-clock-parents = <&cru PLL_AUPLL>;
1346		dmas = <&dmac2 2>;
1347		dma-names = "tx";
1348		power-domains = <&power RK3588_PD_VO1>;
1349		resets = <&cru SRST_M_I2S5_8CH_TX>;
1350		reset-names = "tx-m";
1351		#sound-dai-cells = <0>;
1352		status = "disabled";
1353	};
1354
1355	i2s9_8ch: i2s@fddfc000 {
1356		compatible = "rockchip,rk3588-i2s-tdm";
1357		reg = <0x0 0xfddfc000 0x0 0x1000>;
1358		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
1359		clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
1360		clock-names = "mclk_tx", "mclk_rx", "hclk";
1361		assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1362		assigned-clock-parents = <&cru PLL_AUPLL>;
1363		dmas = <&dmac2 23>;
1364		dma-names = "rx";
1365		power-domains = <&power RK3588_PD_VO1>;
1366		resets = <&cru SRST_M_I2S9_8CH_RX>;
1367		reset-names = "rx-m";
1368		#sound-dai-cells = <0>;
1369		status = "disabled";
1370	};
1371
1372	hdmi0: hdmi@fde80000 {
1373		compatible = "rockchip,rk3588-dw-hdmi-qp";
1374		reg = <0x0 0xfde80000 0x0 0x20000>;
1375		clocks = <&cru PCLK_HDMITX0>,
1376			 <&cru CLK_HDMITX0_EARC>,
1377			 <&cru CLK_HDMITX0_REF>,
1378			 <&cru MCLK_I2S5_8CH_TX>,
1379			 <&cru CLK_HDMIHDP0>,
1380			 <&cru HCLK_VO1>;
1381		clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1382		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
1383			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
1384			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
1385			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
1386			     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
1387		interrupt-names = "avp", "cec", "earc", "main", "hpd";
1388		phys = <&hdptxphy_hdmi0>;
1389		pinctrl-names = "default";
1390		pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
1391			     &hdmim0_tx0_scl &hdmim0_tx0_sda>;
1392		power-domains = <&power RK3588_PD_VO1>;
1393		resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
1394		reset-names = "ref", "hdp";
1395		rockchip,grf = <&sys_grf>;
1396		rockchip,vo-grf = <&vo1_grf>;
1397		status = "disabled";
1398
1399		ports {
1400			#address-cells = <1>;
1401			#size-cells = <0>;
1402
1403			hdmi0_in: port@0 {
1404				reg = <0>;
1405			};
1406
1407			hdmi0_out: port@1 {
1408				reg = <1>;
1409			};
1410		};
1411	};
1412
1413	qos_gpu_m0: qos@fdf35000 {
1414		compatible = "rockchip,rk3588-qos", "syscon";
1415		reg = <0x0 0xfdf35000 0x0 0x20>;
1416	};
1417
1418	qos_gpu_m1: qos@fdf35200 {
1419		compatible = "rockchip,rk3588-qos", "syscon";
1420		reg = <0x0 0xfdf35200 0x0 0x20>;
1421	};
1422
1423	qos_gpu_m2: qos@fdf35400 {
1424		compatible = "rockchip,rk3588-qos", "syscon";
1425		reg = <0x0 0xfdf35400 0x0 0x20>;
1426	};
1427
1428	qos_gpu_m3: qos@fdf35600 {
1429		compatible = "rockchip,rk3588-qos", "syscon";
1430		reg = <0x0 0xfdf35600 0x0 0x20>;
1431	};
1432
1433	qos_rga3_1: qos@fdf36000 {
1434		compatible = "rockchip,rk3588-qos", "syscon";
1435		reg = <0x0 0xfdf36000 0x0 0x20>;
1436	};
1437
1438	qos_sdio: qos@fdf39000 {
1439		compatible = "rockchip,rk3588-qos", "syscon";
1440		reg = <0x0 0xfdf39000 0x0 0x20>;
1441	};
1442
1443	qos_sdmmc: qos@fdf3d800 {
1444		compatible = "rockchip,rk3588-qos", "syscon";
1445		reg = <0x0 0xfdf3d800 0x0 0x20>;
1446	};
1447
1448	qos_usb3_1: qos@fdf3e000 {
1449		compatible = "rockchip,rk3588-qos", "syscon";
1450		reg = <0x0 0xfdf3e000 0x0 0x20>;
1451	};
1452
1453	qos_usb3_0: qos@fdf3e200 {
1454		compatible = "rockchip,rk3588-qos", "syscon";
1455		reg = <0x0 0xfdf3e200 0x0 0x20>;
1456	};
1457
1458	qos_usb2host_0: qos@fdf3e400 {
1459		compatible = "rockchip,rk3588-qos", "syscon";
1460		reg = <0x0 0xfdf3e400 0x0 0x20>;
1461	};
1462
1463	qos_usb2host_1: qos@fdf3e600 {
1464		compatible = "rockchip,rk3588-qos", "syscon";
1465		reg = <0x0 0xfdf3e600 0x0 0x20>;
1466	};
1467
1468	qos_fisheye0: qos@fdf40000 {
1469		compatible = "rockchip,rk3588-qos", "syscon";
1470		reg = <0x0 0xfdf40000 0x0 0x20>;
1471	};
1472
1473	qos_fisheye1: qos@fdf40200 {
1474		compatible = "rockchip,rk3588-qos", "syscon";
1475		reg = <0x0 0xfdf40200 0x0 0x20>;
1476	};
1477
1478	qos_isp0_mro: qos@fdf40400 {
1479		compatible = "rockchip,rk3588-qos", "syscon";
1480		reg = <0x0 0xfdf40400 0x0 0x20>;
1481	};
1482
1483	qos_isp0_mwo: qos@fdf40500 {
1484		compatible = "rockchip,rk3588-qos", "syscon";
1485		reg = <0x0 0xfdf40500 0x0 0x20>;
1486	};
1487
1488	qos_vicap_m0: qos@fdf40600 {
1489		compatible = "rockchip,rk3588-qos", "syscon";
1490		reg = <0x0 0xfdf40600 0x0 0x20>;
1491	};
1492
1493	qos_vicap_m1: qos@fdf40800 {
1494		compatible = "rockchip,rk3588-qos", "syscon";
1495		reg = <0x0 0xfdf40800 0x0 0x20>;
1496	};
1497
1498	qos_isp1_mwo: qos@fdf41000 {
1499		compatible = "rockchip,rk3588-qos", "syscon";
1500		reg = <0x0 0xfdf41000 0x0 0x20>;
1501	};
1502
1503	qos_isp1_mro: qos@fdf41100 {
1504		compatible = "rockchip,rk3588-qos", "syscon";
1505		reg = <0x0 0xfdf41100 0x0 0x20>;
1506	};
1507
1508	qos_rkvenc0_m0ro: qos@fdf60000 {
1509		compatible = "rockchip,rk3588-qos", "syscon";
1510		reg = <0x0 0xfdf60000 0x0 0x20>;
1511	};
1512
1513	qos_rkvenc0_m1ro: qos@fdf60200 {
1514		compatible = "rockchip,rk3588-qos", "syscon";
1515		reg = <0x0 0xfdf60200 0x0 0x20>;
1516	};
1517
1518	qos_rkvenc0_m2wo: qos@fdf60400 {
1519		compatible = "rockchip,rk3588-qos", "syscon";
1520		reg = <0x0 0xfdf60400 0x0 0x20>;
1521	};
1522
1523	qos_rkvenc1_m0ro: qos@fdf61000 {
1524		compatible = "rockchip,rk3588-qos", "syscon";
1525		reg = <0x0 0xfdf61000 0x0 0x20>;
1526	};
1527
1528	qos_rkvenc1_m1ro: qos@fdf61200 {
1529		compatible = "rockchip,rk3588-qos", "syscon";
1530		reg = <0x0 0xfdf61200 0x0 0x20>;
1531	};
1532
1533	qos_rkvenc1_m2wo: qos@fdf61400 {
1534		compatible = "rockchip,rk3588-qos", "syscon";
1535		reg = <0x0 0xfdf61400 0x0 0x20>;
1536	};
1537
1538	qos_rkvdec0: qos@fdf62000 {
1539		compatible = "rockchip,rk3588-qos", "syscon";
1540		reg = <0x0 0xfdf62000 0x0 0x20>;
1541	};
1542
1543	qos_rkvdec1: qos@fdf63000 {
1544		compatible = "rockchip,rk3588-qos", "syscon";
1545		reg = <0x0 0xfdf63000 0x0 0x20>;
1546	};
1547
1548	qos_av1: qos@fdf64000 {
1549		compatible = "rockchip,rk3588-qos", "syscon";
1550		reg = <0x0 0xfdf64000 0x0 0x20>;
1551	};
1552
1553	qos_iep: qos@fdf66000 {
1554		compatible = "rockchip,rk3588-qos", "syscon";
1555		reg = <0x0 0xfdf66000 0x0 0x20>;
1556	};
1557
1558	qos_jpeg_dec: qos@fdf66200 {
1559		compatible = "rockchip,rk3588-qos", "syscon";
1560		reg = <0x0 0xfdf66200 0x0 0x20>;
1561	};
1562
1563	qos_jpeg_enc0: qos@fdf66400 {
1564		compatible = "rockchip,rk3588-qos", "syscon";
1565		reg = <0x0 0xfdf66400 0x0 0x20>;
1566	};
1567
1568	qos_jpeg_enc1: qos@fdf66600 {
1569		compatible = "rockchip,rk3588-qos", "syscon";
1570		reg = <0x0 0xfdf66600 0x0 0x20>;
1571	};
1572
1573	qos_jpeg_enc2: qos@fdf66800 {
1574		compatible = "rockchip,rk3588-qos", "syscon";
1575		reg = <0x0 0xfdf66800 0x0 0x20>;
1576	};
1577
1578	qos_jpeg_enc3: qos@fdf66a00 {
1579		compatible = "rockchip,rk3588-qos", "syscon";
1580		reg = <0x0 0xfdf66a00 0x0 0x20>;
1581	};
1582
1583	qos_rga2_mro: qos@fdf66c00 {
1584		compatible = "rockchip,rk3588-qos", "syscon";
1585		reg = <0x0 0xfdf66c00 0x0 0x20>;
1586	};
1587
1588	qos_rga2_mwo: qos@fdf66e00 {
1589		compatible = "rockchip,rk3588-qos", "syscon";
1590		reg = <0x0 0xfdf66e00 0x0 0x20>;
1591	};
1592
1593	qos_rga3_0: qos@fdf67000 {
1594		compatible = "rockchip,rk3588-qos", "syscon";
1595		reg = <0x0 0xfdf67000 0x0 0x20>;
1596	};
1597
1598	qos_vdpu: qos@fdf67200 {
1599		compatible = "rockchip,rk3588-qos", "syscon";
1600		reg = <0x0 0xfdf67200 0x0 0x20>;
1601	};
1602
1603	qos_npu1: qos@fdf70000 {
1604		compatible = "rockchip,rk3588-qos", "syscon";
1605		reg = <0x0 0xfdf70000 0x0 0x20>;
1606	};
1607
1608	qos_npu2: qos@fdf71000 {
1609		compatible = "rockchip,rk3588-qos", "syscon";
1610		reg = <0x0 0xfdf71000 0x0 0x20>;
1611	};
1612
1613	qos_npu0_mwr: qos@fdf72000 {
1614		compatible = "rockchip,rk3588-qos", "syscon";
1615		reg = <0x0 0xfdf72000 0x0 0x20>;
1616	};
1617
1618	qos_npu0_mro: qos@fdf72200 {
1619		compatible = "rockchip,rk3588-qos", "syscon";
1620		reg = <0x0 0xfdf72200 0x0 0x20>;
1621	};
1622
1623	qos_mcu_npu: qos@fdf72400 {
1624		compatible = "rockchip,rk3588-qos", "syscon";
1625		reg = <0x0 0xfdf72400 0x0 0x20>;
1626	};
1627
1628	qos_hdcp0: qos@fdf80000 {
1629		compatible = "rockchip,rk3588-qos", "syscon";
1630		reg = <0x0 0xfdf80000 0x0 0x20>;
1631	};
1632
1633	qos_hdcp1: qos@fdf81000 {
1634		compatible = "rockchip,rk3588-qos", "syscon";
1635		reg = <0x0 0xfdf81000 0x0 0x20>;
1636	};
1637
1638	qos_hdmirx: qos@fdf81200 {
1639		compatible = "rockchip,rk3588-qos", "syscon";
1640		reg = <0x0 0xfdf81200 0x0 0x20>;
1641	};
1642
1643	qos_vop_m0: qos@fdf82000 {
1644		compatible = "rockchip,rk3588-qos", "syscon";
1645		reg = <0x0 0xfdf82000 0x0 0x20>;
1646	};
1647
1648	qos_vop_m1: qos@fdf82200 {
1649		compatible = "rockchip,rk3588-qos", "syscon";
1650		reg = <0x0 0xfdf82200 0x0 0x20>;
1651	};
1652
1653	dfi: dfi@fe060000 {
1654		reg = <0x00 0xfe060000 0x00 0x10000>;
1655		compatible = "rockchip,rk3588-dfi";
1656		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
1657			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
1658			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
1659			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1660		rockchip,pmu = <&pmu1grf>;
1661	};
1662
1663	pcie2x1l1: pcie@fe180000 {
1664		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1665		bus-range = <0x30 0x3f>;
1666		clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1667			 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1668			 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1669		clock-names = "aclk_mst", "aclk_slv",
1670			      "aclk_dbi", "pclk",
1671			      "aux", "pipe";
1672		device_type = "pci";
1673		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1674			     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1675			     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1676			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1677			     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1678		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1679		#interrupt-cells = <1>;
1680		interrupt-map-mask = <0 0 0 7>;
1681		interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1682				<0 0 0 2 &pcie2x1l1_intc 1>,
1683				<0 0 0 3 &pcie2x1l1_intc 2>,
1684				<0 0 0 4 &pcie2x1l1_intc 3>;
1685		linux,pci-domain = <3>;
1686		max-link-speed = <2>;
1687		msi-map = <0x3000 &its0 0x3000 0x1000>;
1688		iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>;
1689		num-lanes = <1>;
1690		phys = <&combphy2_psu PHY_TYPE_PCIE>;
1691		phy-names = "pcie-phy";
1692		power-domains = <&power RK3588_PD_PCIE>;
1693		ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1694			 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1695			 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1696		reg = <0xa 0x40c00000 0x0 0x00400000>,
1697		      <0x0 0xfe180000 0x0 0x00010000>,
1698		      <0x0 0xf3000000 0x0 0x00100000>;
1699		reg-names = "dbi", "apb", "config";
1700		resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1701		reset-names = "pwr", "pipe";
1702		#address-cells = <3>;
1703		#size-cells = <2>;
1704		status = "disabled";
1705
1706		pcie2x1l1_intc: legacy-interrupt-controller {
1707			interrupt-controller;
1708			#address-cells = <0>;
1709			#interrupt-cells = <1>;
1710			interrupt-parent = <&gic>;
1711			interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1712		};
1713	};
1714
1715	pcie2x1l2: pcie@fe190000 {
1716		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1717		bus-range = <0x40 0x4f>;
1718		clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1719			 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1720			 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1721		clock-names = "aclk_mst", "aclk_slv",
1722			      "aclk_dbi", "pclk",
1723			      "aux", "pipe";
1724		device_type = "pci";
1725		interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1726			     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1727			     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1728			     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1729			     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1730		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1731		#interrupt-cells = <1>;
1732		interrupt-map-mask = <0 0 0 7>;
1733		interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1734				<0 0 0 2 &pcie2x1l2_intc 1>,
1735				<0 0 0 3 &pcie2x1l2_intc 2>,
1736				<0 0 0 4 &pcie2x1l2_intc 3>;
1737		linux,pci-domain = <4>;
1738		max-link-speed = <2>;
1739		msi-map = <0x4000 &its0 0x4000 0x1000>;
1740		iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>;
1741		num-lanes = <1>;
1742		phys = <&combphy0_ps PHY_TYPE_PCIE>;
1743		phy-names = "pcie-phy";
1744		power-domains = <&power RK3588_PD_PCIE>;
1745		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1746			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1747			 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1748		reg = <0xa 0x41000000 0x0 0x00400000>,
1749		      <0x0 0xfe190000 0x0 0x00010000>,
1750		      <0x0 0xf4000000 0x0 0x00100000>;
1751		reg-names = "dbi", "apb", "config";
1752		resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1753		reset-names = "pwr", "pipe";
1754		#address-cells = <3>;
1755		#size-cells = <2>;
1756		status = "disabled";
1757
1758		pcie2x1l2_intc: legacy-interrupt-controller {
1759			interrupt-controller;
1760			#address-cells = <0>;
1761			#interrupt-cells = <1>;
1762			interrupt-parent = <&gic>;
1763			interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1764		};
1765	};
1766
1767	gmac1: ethernet@fe1c0000 {
1768		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1769		reg = <0x0 0xfe1c0000 0x0 0x10000>;
1770		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1771			     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1772		interrupt-names = "macirq", "eth_wake_irq";
1773		clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1774			 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1775			 <&cru CLK_GMAC1_PTP_REF>;
1776		clock-names = "stmmaceth", "clk_mac_ref",
1777			      "pclk_mac", "aclk_mac",
1778			      "ptp_ref";
1779		power-domains = <&power RK3588_PD_GMAC>;
1780		resets = <&cru SRST_A_GMAC1>;
1781		reset-names = "stmmaceth";
1782		rockchip,grf = <&sys_grf>;
1783		rockchip,php-grf = <&php_grf>;
1784		snps,axi-config = <&gmac1_stmmac_axi_setup>;
1785		snps,mixed-burst;
1786		snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1787		snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1788		snps,tso;
1789		status = "disabled";
1790
1791		mdio1: mdio {
1792			compatible = "snps,dwmac-mdio";
1793			#address-cells = <0x1>;
1794			#size-cells = <0x0>;
1795		};
1796
1797		gmac1_stmmac_axi_setup: stmmac-axi-config {
1798			snps,blen = <0 0 0 0 16 8 4>;
1799			snps,wr_osr_lmt = <4>;
1800			snps,rd_osr_lmt = <8>;
1801		};
1802
1803		gmac1_mtl_rx_setup: rx-queues-config {
1804			snps,rx-queues-to-use = <2>;
1805			queue0 {};
1806			queue1 {};
1807		};
1808
1809		gmac1_mtl_tx_setup: tx-queues-config {
1810			snps,tx-queues-to-use = <2>;
1811			queue0 {};
1812			queue1 {};
1813		};
1814	};
1815
1816	sata0: sata@fe210000 {
1817		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1818		reg = <0 0xfe210000 0 0x1000>;
1819		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1820		clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1821			 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1822			 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1823		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1824		ports-implemented = <0x1>;
1825		#address-cells = <1>;
1826		#size-cells = <0>;
1827		status = "disabled";
1828
1829		sata-port@0 {
1830			reg = <0>;
1831			hba-port-cap = <HBA_PORT_FBSCP>;
1832			phys = <&combphy0_ps PHY_TYPE_SATA>;
1833			phy-names = "sata-phy";
1834			snps,rx-ts-max = <32>;
1835			snps,tx-ts-max = <32>;
1836		};
1837	};
1838
1839	sata2: sata@fe230000 {
1840		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1841		reg = <0 0xfe230000 0 0x1000>;
1842		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1843		clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1844			 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1845			 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1846		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1847		ports-implemented = <0x1>;
1848		#address-cells = <1>;
1849		#size-cells = <0>;
1850		status = "disabled";
1851
1852		sata-port@0 {
1853			reg = <0>;
1854			hba-port-cap = <HBA_PORT_FBSCP>;
1855			phys = <&combphy2_psu PHY_TYPE_SATA>;
1856			phy-names = "sata-phy";
1857			snps,rx-ts-max = <32>;
1858			snps,tx-ts-max = <32>;
1859		};
1860	};
1861
1862	sfc: spi@fe2b0000 {
1863		compatible = "rockchip,sfc";
1864		reg = <0x0 0xfe2b0000 0x0 0x4000>;
1865		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
1866		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1867		clock-names = "clk_sfc", "hclk_sfc";
1868		#address-cells = <1>;
1869		#size-cells = <0>;
1870		status = "disabled";
1871	};
1872
1873	sdmmc: mmc@fe2c0000 {
1874		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1875		reg = <0x0 0xfe2c0000 0x0 0x4000>;
1876		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1877		clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
1878			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1879		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1880		fifo-depth = <0x100>;
1881		max-frequency = <200000000>;
1882		pinctrl-names = "default";
1883		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1884		power-domains = <&power RK3588_PD_SDMMC>;
1885		status = "disabled";
1886	};
1887
1888	sdio: mmc@fe2d0000 {
1889		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1890		reg = <0x00 0xfe2d0000 0x00 0x4000>;
1891		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1892		clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1893			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1894		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1895		fifo-depth = <0x100>;
1896		max-frequency = <200000000>;
1897		pinctrl-names = "default";
1898		pinctrl-0 = <&sdiom1_pins>;
1899		power-domains = <&power RK3588_PD_SDIO>;
1900		status = "disabled";
1901	};
1902
1903	sdhci: mmc@fe2e0000 {
1904		compatible = "rockchip,rk3588-dwcmshc";
1905		reg = <0x0 0xfe2e0000 0x0 0x10000>;
1906		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1907		assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1908		assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1909		clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1910			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1911			 <&cru TMCLK_EMMC>;
1912		clock-names = "core", "bus", "axi", "block", "timer";
1913		max-frequency = <200000000>;
1914		pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1915			    <&emmc_cmd>, <&emmc_data_strobe>;
1916		pinctrl-names = "default";
1917		resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1918			 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1919			 <&cru SRST_T_EMMC>;
1920		reset-names = "core", "bus", "axi", "block", "timer";
1921		status = "disabled";
1922	};
1923
1924	i2s0_8ch: i2s@fe470000 {
1925		compatible = "rockchip,rk3588-i2s-tdm";
1926		reg = <0x0 0xfe470000 0x0 0x1000>;
1927		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1928		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1929		clock-names = "mclk_tx", "mclk_rx", "hclk";
1930		assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1931		assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1932		dmas = <&dmac0 0>, <&dmac0 1>;
1933		dma-names = "tx", "rx";
1934		power-domains = <&power RK3588_PD_AUDIO>;
1935		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1936		reset-names = "tx-m", "rx-m";
1937		rockchip,trcm-sync-tx-only;
1938		pinctrl-names = "default";
1939		pinctrl-0 = <&i2s0_lrck
1940			     &i2s0_sclk
1941			     &i2s0_sdi0
1942			     &i2s0_sdi1
1943			     &i2s0_sdi2
1944			     &i2s0_sdi3
1945			     &i2s0_sdo0
1946			     &i2s0_sdo1
1947			     &i2s0_sdo2
1948			     &i2s0_sdo3>;
1949		#sound-dai-cells = <0>;
1950		status = "disabled";
1951	};
1952
1953	i2s1_8ch: i2s@fe480000 {
1954		compatible = "rockchip,rk3588-i2s-tdm";
1955		reg = <0x0 0xfe480000 0x0 0x1000>;
1956		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1957		clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1958		clock-names = "mclk_tx", "mclk_rx", "hclk";
1959		dmas = <&dmac0 2>, <&dmac0 3>;
1960		dma-names = "tx", "rx";
1961		resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1962		reset-names = "tx-m", "rx-m";
1963		rockchip,trcm-sync-tx-only;
1964		pinctrl-names = "default";
1965		pinctrl-0 = <&i2s1m0_lrck
1966			     &i2s1m0_sclk
1967			     &i2s1m0_sdi0
1968			     &i2s1m0_sdi1
1969			     &i2s1m0_sdi2
1970			     &i2s1m0_sdi3
1971			     &i2s1m0_sdo0
1972			     &i2s1m0_sdo1
1973			     &i2s1m0_sdo2
1974			     &i2s1m0_sdo3>;
1975		#sound-dai-cells = <0>;
1976		status = "disabled";
1977	};
1978
1979	i2s2_2ch: i2s@fe490000 {
1980		compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1981		reg = <0x0 0xfe490000 0x0 0x1000>;
1982		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1983		clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1984		clock-names = "i2s_clk", "i2s_hclk";
1985		assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1986		assigned-clock-parents = <&cru PLL_AUPLL>;
1987		dmas = <&dmac1 0>, <&dmac1 1>;
1988		dma-names = "tx", "rx";
1989		power-domains = <&power RK3588_PD_AUDIO>;
1990		pinctrl-names = "default";
1991		pinctrl-0 = <&i2s2m1_lrck
1992			     &i2s2m1_sclk
1993			     &i2s2m1_sdi
1994			     &i2s2m1_sdo>;
1995		#sound-dai-cells = <0>;
1996		status = "disabled";
1997	};
1998
1999	i2s3_2ch: i2s@fe4a0000 {
2000		compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
2001		reg = <0x0 0xfe4a0000 0x0 0x1000>;
2002		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
2003		clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
2004		clock-names = "i2s_clk", "i2s_hclk";
2005		assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
2006		assigned-clock-parents = <&cru PLL_AUPLL>;
2007		dmas = <&dmac1 2>, <&dmac1 3>;
2008		dma-names = "tx", "rx";
2009		power-domains = <&power RK3588_PD_AUDIO>;
2010		pinctrl-names = "default";
2011		pinctrl-0 = <&i2s3_lrck
2012			     &i2s3_sclk
2013			     &i2s3_sdi
2014			     &i2s3_sdo>;
2015		#sound-dai-cells = <0>;
2016		status = "disabled";
2017	};
2018
2019	gic: interrupt-controller@fe600000 {
2020		compatible = "arm,gic-v3";
2021		reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
2022		      <0x0 0xfe680000 0 0x100000>; /* GICR */
2023		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
2024		interrupt-controller;
2025		mbi-alias = <0x0 0xfe610000>;
2026		mbi-ranges = <424 56>;
2027		msi-controller;
2028		ranges;
2029		#address-cells = <2>;
2030		#interrupt-cells = <4>;
2031		#size-cells = <2>;
2032
2033		its0: msi-controller@fe640000 {
2034			compatible = "arm,gic-v3-its";
2035			reg = <0x0 0xfe640000 0x0 0x20000>;
2036			msi-controller;
2037			#msi-cells = <1>;
2038		};
2039
2040		its1: msi-controller@fe660000 {
2041			compatible = "arm,gic-v3-its";
2042			reg = <0x0 0xfe660000 0x0 0x20000>;
2043			msi-controller;
2044			#msi-cells = <1>;
2045		};
2046
2047		ppi-partitions {
2048			ppi_partition0: interrupt-partition-0 {
2049				affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
2050			};
2051
2052			ppi_partition1: interrupt-partition-1 {
2053				affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
2054			};
2055		};
2056	};
2057
2058	dmac0: dma-controller@fea10000 {
2059		compatible = "arm,pl330", "arm,primecell";
2060		reg = <0x0 0xfea10000 0x0 0x4000>;
2061		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
2062			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
2063		arm,pl330-periph-burst;
2064		clocks = <&cru ACLK_DMAC0>;
2065		clock-names = "apb_pclk";
2066		#dma-cells = <1>;
2067	};
2068
2069	dmac1: dma-controller@fea30000 {
2070		compatible = "arm,pl330", "arm,primecell";
2071		reg = <0x0 0xfea30000 0x0 0x4000>;
2072		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
2073			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
2074		arm,pl330-periph-burst;
2075		clocks = <&cru ACLK_DMAC1>;
2076		clock-names = "apb_pclk";
2077		#dma-cells = <1>;
2078	};
2079
2080	i2c1: i2c@fea90000 {
2081		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2082		reg = <0x0 0xfea90000 0x0 0x1000>;
2083		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
2084		clock-names = "i2c", "pclk";
2085		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
2086		pinctrl-0 = <&i2c1m0_xfer>;
2087		pinctrl-names = "default";
2088		#address-cells = <1>;
2089		#size-cells = <0>;
2090		status = "disabled";
2091	};
2092
2093	i2c2: i2c@feaa0000 {
2094		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2095		reg = <0x0 0xfeaa0000 0x0 0x1000>;
2096		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
2097		clock-names = "i2c", "pclk";
2098		interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
2099		pinctrl-0 = <&i2c2m0_xfer>;
2100		pinctrl-names = "default";
2101		#address-cells = <1>;
2102		#size-cells = <0>;
2103		status = "disabled";
2104	};
2105
2106	i2c3: i2c@feab0000 {
2107		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2108		reg = <0x0 0xfeab0000 0x0 0x1000>;
2109		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
2110		clock-names = "i2c", "pclk";
2111		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
2112		pinctrl-0 = <&i2c3m0_xfer>;
2113		pinctrl-names = "default";
2114		#address-cells = <1>;
2115		#size-cells = <0>;
2116		status = "disabled";
2117	};
2118
2119	i2c4: i2c@feac0000 {
2120		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2121		reg = <0x0 0xfeac0000 0x0 0x1000>;
2122		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
2123		clock-names = "i2c", "pclk";
2124		interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
2125		pinctrl-0 = <&i2c4m0_xfer>;
2126		pinctrl-names = "default";
2127		#address-cells = <1>;
2128		#size-cells = <0>;
2129		status = "disabled";
2130	};
2131
2132	i2c5: i2c@fead0000 {
2133		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2134		reg = <0x0 0xfead0000 0x0 0x1000>;
2135		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
2136		clock-names = "i2c", "pclk";
2137		interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
2138		pinctrl-0 = <&i2c5m0_xfer>;
2139		pinctrl-names = "default";
2140		#address-cells = <1>;
2141		#size-cells = <0>;
2142		status = "disabled";
2143	};
2144
2145	timer0: timer@feae0000 {
2146		compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
2147		reg = <0x0 0xfeae0000 0x0 0x20>;
2148		interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
2149		clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
2150		clock-names = "pclk", "timer";
2151	};
2152
2153	wdt: watchdog@feaf0000 {
2154		compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
2155		reg = <0x0 0xfeaf0000 0x0 0x100>;
2156		clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
2157		clock-names = "tclk", "pclk";
2158		interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
2159	};
2160
2161	spi0: spi@feb00000 {
2162		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2163		reg = <0x0 0xfeb00000 0x0 0x1000>;
2164		interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
2165		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
2166		clock-names = "spiclk", "apb_pclk";
2167		dmas = <&dmac0 14>, <&dmac0 15>;
2168		dma-names = "tx", "rx";
2169		num-cs = <2>;
2170		pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
2171		pinctrl-names = "default";
2172		#address-cells = <1>;
2173		#size-cells = <0>;
2174		status = "disabled";
2175	};
2176
2177	spi1: spi@feb10000 {
2178		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2179		reg = <0x0 0xfeb10000 0x0 0x1000>;
2180		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
2181		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
2182		clock-names = "spiclk", "apb_pclk";
2183		dmas = <&dmac0 16>, <&dmac0 17>;
2184		dma-names = "tx", "rx";
2185		num-cs = <2>;
2186		pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
2187		pinctrl-names = "default";
2188		#address-cells = <1>;
2189		#size-cells = <0>;
2190		status = "disabled";
2191	};
2192
2193	spi2: spi@feb20000 {
2194		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2195		reg = <0x0 0xfeb20000 0x0 0x1000>;
2196		interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
2197		clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
2198		clock-names = "spiclk", "apb_pclk";
2199		dmas = <&dmac1 15>, <&dmac1 16>;
2200		dma-names = "tx", "rx";
2201		num-cs = <2>;
2202		pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
2203		pinctrl-names = "default";
2204		#address-cells = <1>;
2205		#size-cells = <0>;
2206		status = "disabled";
2207	};
2208
2209	spi3: spi@feb30000 {
2210		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2211		reg = <0x0 0xfeb30000 0x0 0x1000>;
2212		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
2213		clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
2214		clock-names = "spiclk", "apb_pclk";
2215		dmas = <&dmac1 17>, <&dmac1 18>;
2216		dma-names = "tx", "rx";
2217		num-cs = <2>;
2218		pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
2219		pinctrl-names = "default";
2220		#address-cells = <1>;
2221		#size-cells = <0>;
2222		status = "disabled";
2223	};
2224
2225	uart1: serial@feb40000 {
2226		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2227		reg = <0x0 0xfeb40000 0x0 0x100>;
2228		interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
2229		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
2230		clock-names = "baudclk", "apb_pclk";
2231		dmas = <&dmac0 8>, <&dmac0 9>;
2232		dma-names = "tx", "rx";
2233		pinctrl-0 = <&uart1m1_xfer>;
2234		pinctrl-names = "default";
2235		reg-io-width = <4>;
2236		reg-shift = <2>;
2237		status = "disabled";
2238	};
2239
2240	uart2: serial@feb50000 {
2241		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2242		reg = <0x0 0xfeb50000 0x0 0x100>;
2243		interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
2244		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
2245		clock-names = "baudclk", "apb_pclk";
2246		dmas = <&dmac0 10>, <&dmac0 11>;
2247		dma-names = "tx", "rx";
2248		pinctrl-0 = <&uart2m1_xfer>;
2249		pinctrl-names = "default";
2250		reg-io-width = <4>;
2251		reg-shift = <2>;
2252		status = "disabled";
2253	};
2254
2255	uart3: serial@feb60000 {
2256		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2257		reg = <0x0 0xfeb60000 0x0 0x100>;
2258		interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
2259		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
2260		clock-names = "baudclk", "apb_pclk";
2261		dmas = <&dmac0 12>, <&dmac0 13>;
2262		dma-names = "tx", "rx";
2263		pinctrl-0 = <&uart3m1_xfer>;
2264		pinctrl-names = "default";
2265		reg-io-width = <4>;
2266		reg-shift = <2>;
2267		status = "disabled";
2268	};
2269
2270	uart4: serial@feb70000 {
2271		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2272		reg = <0x0 0xfeb70000 0x0 0x100>;
2273		interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
2274		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
2275		clock-names = "baudclk", "apb_pclk";
2276		dmas = <&dmac1 9>, <&dmac1 10>;
2277		dma-names = "tx", "rx";
2278		pinctrl-0 = <&uart4m1_xfer>;
2279		pinctrl-names = "default";
2280		reg-io-width = <4>;
2281		reg-shift = <2>;
2282		status = "disabled";
2283	};
2284
2285	uart5: serial@feb80000 {
2286		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2287		reg = <0x0 0xfeb80000 0x0 0x100>;
2288		interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
2289		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
2290		clock-names = "baudclk", "apb_pclk";
2291		dmas = <&dmac1 11>, <&dmac1 12>;
2292		dma-names = "tx", "rx";
2293		pinctrl-0 = <&uart5m1_xfer>;
2294		pinctrl-names = "default";
2295		reg-io-width = <4>;
2296		reg-shift = <2>;
2297		status = "disabled";
2298	};
2299
2300	uart6: serial@feb90000 {
2301		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2302		reg = <0x0 0xfeb90000 0x0 0x100>;
2303		interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
2304		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
2305		clock-names = "baudclk", "apb_pclk";
2306		dmas = <&dmac1 13>, <&dmac1 14>;
2307		dma-names = "tx", "rx";
2308		pinctrl-0 = <&uart6m1_xfer>;
2309		pinctrl-names = "default";
2310		reg-io-width = <4>;
2311		reg-shift = <2>;
2312		status = "disabled";
2313	};
2314
2315	uart7: serial@feba0000 {
2316		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2317		reg = <0x0 0xfeba0000 0x0 0x100>;
2318		interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
2319		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
2320		clock-names = "baudclk", "apb_pclk";
2321		dmas = <&dmac2 7>, <&dmac2 8>;
2322		dma-names = "tx", "rx";
2323		pinctrl-0 = <&uart7m1_xfer>;
2324		pinctrl-names = "default";
2325		reg-io-width = <4>;
2326		reg-shift = <2>;
2327		status = "disabled";
2328	};
2329
2330	uart8: serial@febb0000 {
2331		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2332		reg = <0x0 0xfebb0000 0x0 0x100>;
2333		interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
2334		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
2335		clock-names = "baudclk", "apb_pclk";
2336		dmas = <&dmac2 9>, <&dmac2 10>;
2337		dma-names = "tx", "rx";
2338		pinctrl-0 = <&uart8m1_xfer>;
2339		pinctrl-names = "default";
2340		reg-io-width = <4>;
2341		reg-shift = <2>;
2342		status = "disabled";
2343	};
2344
2345	uart9: serial@febc0000 {
2346		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2347		reg = <0x0 0xfebc0000 0x0 0x100>;
2348		interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
2349		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
2350		clock-names = "baudclk", "apb_pclk";
2351		dmas = <&dmac2 11>, <&dmac2 12>;
2352		dma-names = "tx", "rx";
2353		pinctrl-0 = <&uart9m1_xfer>;
2354		pinctrl-names = "default";
2355		reg-io-width = <4>;
2356		reg-shift = <2>;
2357		status = "disabled";
2358	};
2359
2360	pwm4: pwm@febd0000 {
2361		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2362		reg = <0x0 0xfebd0000 0x0 0x10>;
2363		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2364		clock-names = "pwm", "pclk";
2365		pinctrl-0 = <&pwm4m0_pins>;
2366		pinctrl-names = "default";
2367		#pwm-cells = <3>;
2368		status = "disabled";
2369	};
2370
2371	pwm5: pwm@febd0010 {
2372		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2373		reg = <0x0 0xfebd0010 0x0 0x10>;
2374		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2375		clock-names = "pwm", "pclk";
2376		pinctrl-0 = <&pwm5m0_pins>;
2377		pinctrl-names = "default";
2378		#pwm-cells = <3>;
2379		status = "disabled";
2380	};
2381
2382	pwm6: pwm@febd0020 {
2383		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2384		reg = <0x0 0xfebd0020 0x0 0x10>;
2385		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2386		clock-names = "pwm", "pclk";
2387		pinctrl-0 = <&pwm6m0_pins>;
2388		pinctrl-names = "default";
2389		#pwm-cells = <3>;
2390		status = "disabled";
2391	};
2392
2393	pwm7: pwm@febd0030 {
2394		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2395		reg = <0x0 0xfebd0030 0x0 0x10>;
2396		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2397		clock-names = "pwm", "pclk";
2398		pinctrl-0 = <&pwm7m0_pins>;
2399		pinctrl-names = "default";
2400		#pwm-cells = <3>;
2401		status = "disabled";
2402	};
2403
2404	pwm8: pwm@febe0000 {
2405		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2406		reg = <0x0 0xfebe0000 0x0 0x10>;
2407		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2408		clock-names = "pwm", "pclk";
2409		pinctrl-0 = <&pwm8m0_pins>;
2410		pinctrl-names = "default";
2411		#pwm-cells = <3>;
2412		status = "disabled";
2413	};
2414
2415	pwm9: pwm@febe0010 {
2416		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2417		reg = <0x0 0xfebe0010 0x0 0x10>;
2418		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2419		clock-names = "pwm", "pclk";
2420		pinctrl-0 = <&pwm9m0_pins>;
2421		pinctrl-names = "default";
2422		#pwm-cells = <3>;
2423		status = "disabled";
2424	};
2425
2426	pwm10: pwm@febe0020 {
2427		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2428		reg = <0x0 0xfebe0020 0x0 0x10>;
2429		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2430		clock-names = "pwm", "pclk";
2431		pinctrl-0 = <&pwm10m0_pins>;
2432		pinctrl-names = "default";
2433		#pwm-cells = <3>;
2434		status = "disabled";
2435	};
2436
2437	pwm11: pwm@febe0030 {
2438		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2439		reg = <0x0 0xfebe0030 0x0 0x10>;
2440		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2441		clock-names = "pwm", "pclk";
2442		pinctrl-0 = <&pwm11m0_pins>;
2443		pinctrl-names = "default";
2444		#pwm-cells = <3>;
2445		status = "disabled";
2446	};
2447
2448	pwm12: pwm@febf0000 {
2449		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2450		reg = <0x0 0xfebf0000 0x0 0x10>;
2451		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2452		clock-names = "pwm", "pclk";
2453		pinctrl-0 = <&pwm12m0_pins>;
2454		pinctrl-names = "default";
2455		#pwm-cells = <3>;
2456		status = "disabled";
2457	};
2458
2459	pwm13: pwm@febf0010 {
2460		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2461		reg = <0x0 0xfebf0010 0x0 0x10>;
2462		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2463		clock-names = "pwm", "pclk";
2464		pinctrl-0 = <&pwm13m0_pins>;
2465		pinctrl-names = "default";
2466		#pwm-cells = <3>;
2467		status = "disabled";
2468	};
2469
2470	pwm14: pwm@febf0020 {
2471		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2472		reg = <0x0 0xfebf0020 0x0 0x10>;
2473		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2474		clock-names = "pwm", "pclk";
2475		pinctrl-0 = <&pwm14m0_pins>;
2476		pinctrl-names = "default";
2477		#pwm-cells = <3>;
2478		status = "disabled";
2479	};
2480
2481	pwm15: pwm@febf0030 {
2482		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2483		reg = <0x0 0xfebf0030 0x0 0x10>;
2484		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2485		clock-names = "pwm", "pclk";
2486		pinctrl-0 = <&pwm15m0_pins>;
2487		pinctrl-names = "default";
2488		#pwm-cells = <3>;
2489		status = "disabled";
2490	};
2491
2492	thermal_zones: thermal-zones {
2493		/* sensor near the center of the SoC */
2494		package_thermal: package-thermal {
2495			polling-delay-passive = <0>;
2496			polling-delay = <0>;
2497			thermal-sensors = <&tsadc 0>;
2498
2499			trips {
2500				package_crit: package-crit {
2501					temperature = <115000>;
2502					hysteresis = <0>;
2503					type = "critical";
2504				};
2505			};
2506		};
2507
2508		/* sensor between A76 cores 0 and 1 */
2509		bigcore0_thermal: bigcore0-thermal {
2510			polling-delay-passive = <100>;
2511			polling-delay = <0>;
2512			thermal-sensors = <&tsadc 1>;
2513
2514			trips {
2515				bigcore0_alert: bigcore0-alert {
2516					temperature = <85000>;
2517					hysteresis = <2000>;
2518					type = "passive";
2519				};
2520
2521				bigcore0_crit: bigcore0-crit {
2522					temperature = <115000>;
2523					hysteresis = <0>;
2524					type = "critical";
2525				};
2526			};
2527
2528			cooling-maps {
2529				map0 {
2530					trip = <&bigcore0_alert>;
2531					cooling-device =
2532						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2533						<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2534				};
2535			};
2536		};
2537
2538		/* sensor between A76 cores 2 and 3 */
2539		bigcore2_thermal: bigcore2-thermal {
2540			polling-delay-passive = <100>;
2541			polling-delay = <0>;
2542			thermal-sensors = <&tsadc 2>;
2543
2544			trips {
2545				bigcore2_alert: bigcore2-alert {
2546					temperature = <85000>;
2547					hysteresis = <2000>;
2548					type = "passive";
2549				};
2550
2551				bigcore2_crit: bigcore2-crit {
2552					temperature = <115000>;
2553					hysteresis = <0>;
2554					type = "critical";
2555				};
2556			};
2557
2558			cooling-maps {
2559				map0 {
2560					trip = <&bigcore2_alert>;
2561					cooling-device =
2562						<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2563						<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2564				};
2565			};
2566		};
2567
2568		/* sensor between the four A55 cores */
2569		little_core_thermal: littlecore-thermal {
2570			polling-delay-passive = <100>;
2571			polling-delay = <0>;
2572			thermal-sensors = <&tsadc 3>;
2573
2574			trips {
2575				littlecore_alert: littlecore-alert {
2576					temperature = <85000>;
2577					hysteresis = <2000>;
2578					type = "passive";
2579				};
2580
2581				littlecore_crit: littlecore-crit {
2582					temperature = <115000>;
2583					hysteresis = <0>;
2584					type = "critical";
2585				};
2586			};
2587
2588			cooling-maps {
2589				map0 {
2590					trip = <&littlecore_alert>;
2591					cooling-device =
2592						<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2593						<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2594						<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2595						<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2596				};
2597			};
2598		};
2599
2600		/* sensor near the PD_CENTER power domain */
2601		center_thermal: center-thermal {
2602			polling-delay-passive = <0>;
2603			polling-delay = <0>;
2604			thermal-sensors = <&tsadc 4>;
2605
2606			trips {
2607				center_crit: center-crit {
2608					temperature = <115000>;
2609					hysteresis = <0>;
2610					type = "critical";
2611				};
2612			};
2613		};
2614
2615		gpu_thermal: gpu-thermal {
2616			polling-delay-passive = <100>;
2617			polling-delay = <0>;
2618			thermal-sensors = <&tsadc 5>;
2619
2620			trips {
2621				gpu_alert: gpu-alert {
2622					temperature = <85000>;
2623					hysteresis = <2000>;
2624					type = "passive";
2625				};
2626
2627				gpu_crit: gpu-crit {
2628					temperature = <115000>;
2629					hysteresis = <0>;
2630					type = "critical";
2631				};
2632			};
2633
2634			cooling-maps {
2635				map0 {
2636					trip = <&gpu_alert>;
2637					cooling-device =
2638						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2639				};
2640			};
2641		};
2642
2643		npu_thermal: npu-thermal {
2644			polling-delay-passive = <0>;
2645			polling-delay = <0>;
2646			thermal-sensors = <&tsadc 6>;
2647
2648			trips {
2649				npu_crit: npu-crit {
2650					temperature = <115000>;
2651					hysteresis = <0>;
2652					type = "critical";
2653				};
2654			};
2655		};
2656	};
2657
2658	tsadc: tsadc@fec00000 {
2659		compatible = "rockchip,rk3588-tsadc";
2660		reg = <0x0 0xfec00000 0x0 0x400>;
2661		interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2662		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2663		clock-names = "tsadc", "apb_pclk";
2664		assigned-clocks = <&cru CLK_TSADC>;
2665		assigned-clock-rates = <2000000>;
2666		resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2667		reset-names = "tsadc-apb", "tsadc";
2668		rockchip,hw-tshut-temp = <120000>;
2669		rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2670		rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2671		pinctrl-0 = <&tsadc_shut_org>;
2672		pinctrl-1 = <&tsadc_gpio_func>;
2673		pinctrl-names = "default", "sleep";
2674		#thermal-sensor-cells = <1>;
2675		status = "disabled";
2676	};
2677
2678	saradc: adc@fec10000 {
2679		compatible = "rockchip,rk3588-saradc";
2680		reg = <0x0 0xfec10000 0x0 0x10000>;
2681		interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2682		#io-channel-cells = <1>;
2683		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2684		clock-names = "saradc", "apb_pclk";
2685		resets = <&cru SRST_P_SARADC>;
2686		reset-names = "saradc-apb";
2687		status = "disabled";
2688	};
2689
2690	i2c6: i2c@fec80000 {
2691		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2692		reg = <0x0 0xfec80000 0x0 0x1000>;
2693		clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2694		clock-names = "i2c", "pclk";
2695		interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2696		pinctrl-0 = <&i2c6m0_xfer>;
2697		pinctrl-names = "default";
2698		#address-cells = <1>;
2699		#size-cells = <0>;
2700		status = "disabled";
2701	};
2702
2703	i2c7: i2c@fec90000 {
2704		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2705		reg = <0x0 0xfec90000 0x0 0x1000>;
2706		clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2707		clock-names = "i2c", "pclk";
2708		interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2709		pinctrl-0 = <&i2c7m0_xfer>;
2710		pinctrl-names = "default";
2711		#address-cells = <1>;
2712		#size-cells = <0>;
2713		status = "disabled";
2714	};
2715
2716	i2c8: i2c@feca0000 {
2717		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2718		reg = <0x0 0xfeca0000 0x0 0x1000>;
2719		clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2720		clock-names = "i2c", "pclk";
2721		interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2722		pinctrl-0 = <&i2c8m0_xfer>;
2723		pinctrl-names = "default";
2724		#address-cells = <1>;
2725		#size-cells = <0>;
2726		status = "disabled";
2727	};
2728
2729	spi4: spi@fecb0000 {
2730		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2731		reg = <0x0 0xfecb0000 0x0 0x1000>;
2732		interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2733		clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2734		clock-names = "spiclk", "apb_pclk";
2735		dmas = <&dmac2 13>, <&dmac2 14>;
2736		dma-names = "tx", "rx";
2737		num-cs = <2>;
2738		pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2739		pinctrl-names = "default";
2740		#address-cells = <1>;
2741		#size-cells = <0>;
2742		status = "disabled";
2743	};
2744
2745	otp: efuse@fecc0000 {
2746		compatible = "rockchip,rk3588-otp";
2747		reg = <0x0 0xfecc0000 0x0 0x400>;
2748		clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2749			 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2750		clock-names = "otp", "apb_pclk", "phy", "arb";
2751		resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2752			 <&cru SRST_OTPC_ARB>;
2753		reset-names = "otp", "apb", "arb";
2754		#address-cells = <1>;
2755		#size-cells = <1>;
2756
2757		cpu_code: cpu-code@2 {
2758			reg = <0x02 0x2>;
2759		};
2760
2761		otp_id: id@7 {
2762			reg = <0x07 0x10>;
2763		};
2764
2765		cpub0_leakage: cpu-leakage@17 {
2766			reg = <0x17 0x1>;
2767		};
2768
2769		cpub1_leakage: cpu-leakage@18 {
2770			reg = <0x18 0x1>;
2771		};
2772
2773		cpul_leakage: cpu-leakage@19 {
2774			reg = <0x19 0x1>;
2775		};
2776
2777		log_leakage: log-leakage@1a {
2778			reg = <0x1a 0x1>;
2779		};
2780
2781		gpu_leakage: gpu-leakage@1b {
2782			reg = <0x1b 0x1>;
2783		};
2784
2785		otp_cpu_version: cpu-version@1c {
2786			reg = <0x1c 0x1>;
2787			bits = <3 3>;
2788		};
2789
2790		npu_leakage: npu-leakage@28 {
2791			reg = <0x28 0x1>;
2792		};
2793
2794		codec_leakage: codec-leakage@29 {
2795			reg = <0x29 0x1>;
2796		};
2797	};
2798
2799	dmac2: dma-controller@fed10000 {
2800		compatible = "arm,pl330", "arm,primecell";
2801		reg = <0x0 0xfed10000 0x0 0x4000>;
2802		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2803			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2804		arm,pl330-periph-burst;
2805		clocks = <&cru ACLK_DMAC2>;
2806		clock-names = "apb_pclk";
2807		#dma-cells = <1>;
2808	};
2809
2810	hdptxphy_hdmi0: phy@fed60000 {
2811		compatible = "rockchip,rk3588-hdptx-phy";
2812		reg = <0x0 0xfed60000 0x0 0x2000>;
2813		clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
2814		clock-names = "ref", "apb";
2815		#phy-cells = <0>;
2816		resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
2817			 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
2818			 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
2819			 <&cru SRST_HDPTX0_LCPLL>;
2820		reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
2821			      "lcpll";
2822		rockchip,grf = <&hdptxphy0_grf>;
2823		status = "disabled";
2824	};
2825
2826	usbdp_phy0: phy@fed80000 {
2827		compatible = "rockchip,rk3588-usbdp-phy";
2828		reg = <0x0 0xfed80000 0x0 0x10000>;
2829		#phy-cells = <1>;
2830		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
2831			 <&cru CLK_USBDP_PHY0_IMMORTAL>,
2832			 <&cru PCLK_USBDPPHY0>,
2833			 <&u2phy0>;
2834		clock-names = "refclk", "immortal", "pclk", "utmi";
2835		resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
2836			 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
2837			 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
2838			 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
2839			 <&cru SRST_P_USBDPPHY0>;
2840		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
2841		rockchip,u2phy-grf = <&usb2phy0_grf>;
2842		rockchip,usb-grf = <&usb_grf>;
2843		rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
2844		rockchip,vo-grf = <&vo0_grf>;
2845		status = "disabled";
2846	};
2847
2848	combphy0_ps: phy@fee00000 {
2849		compatible = "rockchip,rk3588-naneng-combphy";
2850		reg = <0x0 0xfee00000 0x0 0x100>;
2851		clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
2852			 <&cru PCLK_PHP_ROOT>;
2853		clock-names = "ref", "apb", "pipe";
2854		assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2855		assigned-clock-rates = <100000000>;
2856		#phy-cells = <1>;
2857		resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
2858		reset-names = "phy", "apb";
2859		rockchip,pipe-grf = <&php_grf>;
2860		rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2861		status = "disabled";
2862	};
2863
2864	combphy2_psu: phy@fee20000 {
2865		compatible = "rockchip,rk3588-naneng-combphy";
2866		reg = <0x0 0xfee20000 0x0 0x100>;
2867		clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
2868			 <&cru PCLK_PHP_ROOT>;
2869		clock-names = "ref", "apb", "pipe";
2870		assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2871		assigned-clock-rates = <100000000>;
2872		#phy-cells = <1>;
2873		resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
2874		reset-names = "phy", "apb";
2875		rockchip,pipe-grf = <&php_grf>;
2876		rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2877		status = "disabled";
2878	};
2879
2880	system_sram2: sram@ff001000 {
2881		compatible = "mmio-sram";
2882		reg = <0x0 0xff001000 0x0 0xef000>;
2883		ranges = <0x0 0x0 0xff001000 0xef000>;
2884		#address-cells = <1>;
2885		#size-cells = <1>;
2886	};
2887
2888	pinctrl: pinctrl {
2889		compatible = "rockchip,rk3588-pinctrl";
2890		ranges;
2891		rockchip,grf = <&ioc>;
2892		#address-cells = <2>;
2893		#size-cells = <2>;
2894
2895		gpio0: gpio@fd8a0000 {
2896			compatible = "rockchip,gpio-bank";
2897			reg = <0x0 0xfd8a0000 0x0 0x100>;
2898			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2899			clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2900			gpio-controller;
2901			gpio-ranges = <&pinctrl 0 0 32>;
2902			interrupt-controller;
2903			#gpio-cells = <2>;
2904			#interrupt-cells = <2>;
2905		};
2906
2907		gpio1: gpio@fec20000 {
2908			compatible = "rockchip,gpio-bank";
2909			reg = <0x0 0xfec20000 0x0 0x100>;
2910			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2911			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2912			gpio-controller;
2913			gpio-ranges = <&pinctrl 0 32 32>;
2914			interrupt-controller;
2915			#gpio-cells = <2>;
2916			#interrupt-cells = <2>;
2917		};
2918
2919		gpio2: gpio@fec30000 {
2920			compatible = "rockchip,gpio-bank";
2921			reg = <0x0 0xfec30000 0x0 0x100>;
2922			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2923			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2924			gpio-controller;
2925			gpio-ranges = <&pinctrl 0 64 32>;
2926			interrupt-controller;
2927			#gpio-cells = <2>;
2928			#interrupt-cells = <2>;
2929		};
2930
2931		gpio3: gpio@fec40000 {
2932			compatible = "rockchip,gpio-bank";
2933			reg = <0x0 0xfec40000 0x0 0x100>;
2934			interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2935			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2936			gpio-controller;
2937			gpio-ranges = <&pinctrl 0 96 32>;
2938			interrupt-controller;
2939			#gpio-cells = <2>;
2940			#interrupt-cells = <2>;
2941		};
2942
2943		gpio4: gpio@fec50000 {
2944			compatible = "rockchip,gpio-bank";
2945			reg = <0x0 0xfec50000 0x0 0x100>;
2946			interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2947			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
2948			gpio-controller;
2949			gpio-ranges = <&pinctrl 0 128 32>;
2950			interrupt-controller;
2951			#gpio-cells = <2>;
2952			#interrupt-cells = <2>;
2953		};
2954	};
2955};
2956
2957#include "rk3588-base-pinctrl.dtsi"
2958