1 /*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright (c) 2015, Joyent, Inc.
25 */
26
27 /*
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
30 */
31
32 /* Copyright (c) 1988 AT&T */
33 /* All Rights Reserved */
34
35 #include "dis_tables.h"
36
37 /* BEGIN CSTYLED */
38
39 /*
40 * Disassembly begins in dis_distable, which is equivalent to the One-byte
41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The
42 * decoding loops then traverse out through the other tables as necessary to
43 * decode a given instruction.
44 *
45 * The behavior of this file can be controlled by one of the following flags:
46 *
47 * DIS_TEXT Include text for disassembly
48 * DIS_MEM Include memory-size calculations
49 *
50 * Either or both of these can be defined.
51 *
52 * This file is not, and will never be, cstyled. If anything, the tables should
53 * be taken out another tab stop or two so nothing overlaps.
54 */
55
56 /*
57 * These functions must be provided for the consumer to do disassembly.
58 */
59 #ifdef DIS_TEXT
60 extern char *strncpy(char *, const char *, size_t);
61 extern size_t strlen(const char *);
62 extern int strcmp(const char *, const char *);
63 extern int strncmp(const char *, const char *, size_t);
64 extern size_t strlcat(char *, const char *, size_t);
65 #endif
66
67
68 #define TERM 0 /* used to indicate that the 'indirect' */
69 /* field terminates - no pointer. */
70
71 /* Used to decode instructions. */
72 typedef struct instable {
73 struct instable *it_indirect; /* for decode op codes */
74 uchar_t it_adrmode;
75 #ifdef DIS_TEXT
76 char it_name[NCPS];
77 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */
78 #endif
79 #ifdef DIS_MEM
80 uint_t it_size:16;
81 #endif
82 uint_t it_invalid64:1; /* opcode invalid in amd64 */
83 uint_t it_always64:1; /* 64 bit when in 64 bit mode */
84 uint_t it_invalid32:1; /* invalid in IA32 */
85 uint_t it_stackop:1; /* push/pop stack operation */
86 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */
87 uint_t it_avxsuf:1; /* AVX suffix required */
88 } instable_t;
89
90 /*
91 * Instruction formats.
92 */
93 enum {
94 UNKNOWN,
95 MRw,
96 IMlw,
97 IMw,
98 IR,
99 OA,
100 AO,
101 MS,
102 SM,
103 Mv,
104 Mw,
105 M, /* register or memory */
106 MG9, /* register or memory in group 9 (prefix optional) */
107 Mb, /* register or memory, always byte sized */
108 MO, /* memory only (no registers) */
109 PREF,
110 SWAPGS_RDTSCP,
111 MONITOR_MWAIT,
112 R,
113 RA,
114 SEG,
115 MR,
116 RM,
117 RM_66r, /* RM, but with a required 0x66 prefix */
118 IA,
119 MA,
120 SD,
121 AD,
122 SA,
123 D,
124 INM,
125 SO,
126 BD,
127 I,
128 P,
129 V,
130 DSHIFT, /* for double shift that has an 8-bit immediate */
131 U,
132 OVERRIDE,
133 NORM, /* instructions w/o ModR/M byte, no memory access */
134 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */
135 O, /* for call */
136 JTAB, /* jump table */
137 IMUL, /* for 186 iimul instr */
138 CBW, /* so data16 can be evaluated for cbw and variants */
139 MvI, /* for 186 logicals */
140 ENTER, /* for 186 enter instr */
141 RMw, /* for 286 arpl instr */
142 Ib, /* for push immediate byte */
143 F, /* for 287 instructions */
144 FF, /* for 287 instructions */
145 FFC, /* for 287 instructions */
146 DM, /* 16-bit data */
147 AM, /* 16-bit addr */
148 LSEG, /* for 3-bit seg reg encoding */
149 MIb, /* for 386 logicals */
150 SREG, /* for 386 special registers */
151 PREFIX, /* a REP instruction prefix */
152 LOCK, /* a LOCK instruction prefix */
153 INT3, /* The int 3 instruction, which has a fake operand */
154 INTx, /* The normal int instruction, with explicit int num */
155 DSHIFTcl, /* for double shift that implicitly uses %cl */
156 CWD, /* so data16 can be evaluated for cwd and variants */
157 RET, /* single immediate 16-bit operand */
158 MOVZ, /* for movs and movz, with different size operands */
159 CRC32, /* for crc32, with different size operands */
160 XADDB, /* for xaddb */
161 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */
162 MOVBE, /* movbe instruction */
163
164 /*
165 * MMX/SIMD addressing modes.
166 */
167
168 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */
169 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */
170 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */
171 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */
172 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */
173 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */
174 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */
175 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */
176 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */
177 MMOSH, /* Prefixable MMX mm,imm8 */
178 MM, /* MMX/SIMD-Int mm/mem -> mm */
179 MMS, /* MMX/SIMD-Int mm -> mm/mem */
180 MMSH, /* MMX mm,imm8 */
181 XMMO, /* Prefixable SIMD xmm/mem -> xmm */
182 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */
183 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */
184 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */
185 XMMOX3, /* Prefixable SIMD xmm -> r32 */
186 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */
187 XMMOM, /* Prefixable SIMD xmm -> mem */
188 XMMOMS, /* Prefixable SIMD mem -> xmm */
189 XMM, /* SIMD xmm/mem -> xmm */
190 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */
191 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */
192 XMMXIMPL, /* SIMD xmm -> xmm (mem) */
193 XMM3P, /* SIMD xmm -> r32,imm8 */
194 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */
195 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */
196 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */
197 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */
198 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */
199 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */
200 XMMS, /* SIMD xmm -> xmm/mem */
201 XMMM, /* SIMD mem -> xmm */
202 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */
203 XMMMS, /* SIMD xmm -> mem */
204 XMM3MX, /* SIMD r32/mem -> xmm */
205 XMM3MXS, /* SIMD xmm -> r32/mem */
206 XMMSH, /* SIMD xmm,imm8 */
207 XMMXM3, /* SIMD xmm/mem -> r32 */
208 XMMX3, /* SIMD xmm -> r32 */
209 XMMXMM, /* SIMD xmm/mem -> mm */
210 XMMMX, /* SIMD mm -> xmm */
211 XMMXM, /* SIMD xmm -> mm */
212 XMMX2I, /* SIMD xmm -> xmm, imm, imm */
213 XMM2I, /* SIMD xmm, imm, imm */
214 XMMFENCE, /* SIMD lfence or mfence */
215 XMMSFNC, /* SIMD sfence (none or mem) */
216 XGETBV_XSETBV,
217 VEX_NONE, /* VEX no operand */
218 VEX_MO, /* VEX mod_rm -> implicit reg */
219 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
220 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */
221 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */
222 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */
223 VEX_MX, /* VEX mod_rm -> mod_reg */
224 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */
225 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
226 VEX_MR, /* VEX mod_rm -> mod_reg */
227 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */
228 VEX_RX, /* VEX mod_reg -> mod_rm */
229 VEX_RR, /* VEX mod_rm -> mod_reg */
230 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
231 VEX_RM, /* VEX mod_reg -> mod_rm */
232 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */
233 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
234 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
235 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */
236 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */
237 VMxo, /* VMx instruction with optional prefix */
238 SVM, /* AMD SVM instructions */
239 BLS, /* BLSR, BLSMSK, BLSI */
240 FMA /* FMA instructions, all VEX_RMrX */
241 };
242
243 /*
244 * VEX prefixes
245 */
246 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */
247 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */
248
249 #define FILL 0x90 /* Fill byte used for alignment (nop) */
250
251 /*
252 ** Register numbers for the i386
253 */
254 #define EAX_REGNO 0
255 #define ECX_REGNO 1
256 #define EDX_REGNO 2
257 #define EBX_REGNO 3
258 #define ESP_REGNO 4
259 #define EBP_REGNO 5
260 #define ESI_REGNO 6
261 #define EDI_REGNO 7
262
263 /*
264 * modes for immediate values
265 */
266 #define MODE_NONE 0
267 #define MODE_IPREL 1 /* signed IP relative value */
268 #define MODE_SIGNED 2 /* sign extended immediate */
269 #define MODE_IMPLIED 3 /* constant value implied from opcode */
270 #define MODE_OFFSET 4 /* offset part of an address */
271 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */
272
273 /*
274 * The letters used in these macros are:
275 * IND - indirect to another to another table
276 * "T" - means to Terminate indirections (this is the final opcode)
277 * "S" - means "operand length suffix required"
278 * "Sa" - means AVX2 suffix (d/q) required
279 * "NS" - means "no suffix" which is the operand length suffix of the opcode
280 * "Z" - means instruction size arg required
281 * "u" - means the opcode is invalid in IA32 but valid in amd64
282 * "x" - means the opcode is invalid in amd64, but not IA32
283 * "y" - means the operand size is always 64 bits in 64 bit mode
284 * "p" - means push/pop stack operation
285 * "vr" - means VEX instruction that operates on normal registers, not fpu
286 */
287
288 #if defined(DIS_TEXT) && defined(DIS_MEM)
289 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0}
290 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0}
291 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0}
292 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0}
293 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0}
294 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0}
295 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1}
296 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0}
297 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0}
298 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1}
299 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0}
300 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0}
301 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0}
302 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1}
303 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0}
304 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1}
305 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0}
306 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0}
307 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
308 #elif defined(DIS_TEXT)
309 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
310 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0}
311 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0}
312 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0}
313 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0}
314 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0}
315 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1}
316 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0}
317 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0}
318 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1}
319 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0}
320 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0}
321 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0}
322 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1}
323 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0}
324 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1}
325 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0}
326 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0}
327 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
328 #elif defined(DIS_MEM)
329 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0}
330 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0}
331 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
332 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0}
333 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
334 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1}
335 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
336 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
337 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
338 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1}
339 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
340 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
341 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
342 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1}
343 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
344 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 1}
345 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0}
346 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
347 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0}
348 #else
349 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0}
350 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0}
351 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0}
352 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0}
353 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0}
354 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1}
355 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0}
356 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
357 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
358 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1}
359 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0}
360 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0}
361 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0}
362 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1}
363 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
364 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 1}
365 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0}
366 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
367 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0}
368 #endif
369
370 #ifdef DIS_TEXT
371 /*
372 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
373 */
374 const char *const dis_addr16[3][8] = {
375 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
376 "(%bx)",
377 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
378 "(%bx)",
379 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
380 "(%bx)",
381 };
382
383
384 /*
385 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
386 */
387 const char *const dis_addr32_mode0[16] = {
388 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)",
389 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)"
390 };
391
392 const char *const dis_addr32_mode12[16] = {
393 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)",
394 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
395 };
396
397 /*
398 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
399 */
400 const char *const dis_addr64_mode0[16] = {
401 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)",
402 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
403 };
404 const char *const dis_addr64_mode12[16] = {
405 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)",
406 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
407 };
408
409 /*
410 * decode for scale from SIB byte
411 */
412 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
413
414 /*
415 * decode for scale from VSIB byte, note that we always include the scale factor
416 * to match gas.
417 */
418 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" };
419
420 /*
421 * register decoding for normal references to registers (ie. not addressing)
422 */
423 const char *const dis_REG8[16] = {
424 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
425 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
426 };
427
428 const char *const dis_REG8_REX[16] = {
429 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
430 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
431 };
432
433 const char *const dis_REG16[16] = {
434 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
435 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
436 };
437
438 const char *const dis_REG32[16] = {
439 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
440 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
441 };
442
443 const char *const dis_REG64[16] = {
444 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
445 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
446 };
447
448 const char *const dis_DEBUGREG[16] = {
449 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7",
450 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
451 };
452
453 const char *const dis_CONTROLREG[16] = {
454 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
455 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
456 };
457
458 const char *const dis_TESTREG[16] = {
459 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
460 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
461 };
462
463 const char *const dis_MMREG[16] = {
464 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
465 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
466 };
467
468 const char *const dis_XMMREG[16] = {
469 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
470 "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15"
471 };
472
473 const char *const dis_YMMREG[16] = {
474 "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7",
475 "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15"
476 };
477
478 const char *const dis_SEGREG[16] = {
479 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
480 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
481 };
482
483 /*
484 * SIMD predicate suffixes
485 */
486 const char *const dis_PREDSUFFIX[8] = {
487 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
488 };
489
490 const char *const dis_AVXvgrp7[3][8] = {
491 /*0 1 2 3 4 5 6 7*/
492 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""},
493 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""},
494 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"}
495 };
496
497 #endif /* DIS_TEXT */
498
499 /*
500 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
501 */
502 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
503
504 /*
505 * "decode table" for pause and clflush instructions
506 */
507 const instable_t dis_opPause = TNS("pause", NORM);
508
509 /*
510 * Decode table for 0x0F00 opcodes
511 */
512 const instable_t dis_op0F00[8] = {
513
514 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M),
515 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID,
516 };
517
518
519 /*
520 * Decode table for 0x0F01 opcodes
521 */
522 const instable_t dis_op0F01[8] = {
523
524 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
525 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP),
526 };
527
528 /*
529 * Decode table for 0x0F18 opcodes -- SIMD prefetch
530 */
531 const instable_t dis_op0F18[8] = {
532
533 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),
534 /* [4] */ INVALID, INVALID, INVALID, INVALID,
535 };
536
537 /*
538 * Decode table for 0x0FAE opcodes -- SIMD state save/restore
539 */
540 const instable_t dis_op0FAE[8] = {
541 /* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M),
542 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
543 };
544
545 /*
546 * Decode table for 0x0FBA opcodes
547 */
548
549 const instable_t dis_op0FBA[8] = {
550
551 /* [0] */ INVALID, INVALID, INVALID, INVALID,
552 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
553 };
554
555 /*
556 * Decode table for 0x0FC7 opcode (group 9)
557 */
558
559 const instable_t dis_op0FC7[8] = {
560
561 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID,
562 /* [4] */ INVALID, INVALID, TNS("vmptrld",MG9), TNS("vmptrst",MG9),
563 };
564
565 /*
566 * Decode table for 0x0FC7 opcode (group 9) mode 3
567 */
568
569 const instable_t dis_op0FC7m3[8] = {
570
571 /* [0] */ INVALID, INVALID, INVALID, INVALID,
572 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), INVALID,
573 };
574
575 /*
576 * Decode table for 0x0FC7 opcode with 0x66 prefix
577 */
578
579 const instable_t dis_op660FC7[8] = {
580
581 /* [0] */ INVALID, INVALID, INVALID, INVALID,
582 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID,
583 };
584
585 /*
586 * Decode table for 0x0FC7 opcode with 0xF3 prefix
587 */
588
589 const instable_t dis_opF30FC7[8] = {
590
591 /* [0] */ INVALID, INVALID, INVALID, INVALID,
592 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID,
593 };
594
595 /*
596 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
597 *
598 *bit pattern: 0000 1111 1100 1reg
599 */
600 const instable_t dis_op0FC8[4] = {
601 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID,
602 };
603
604 /*
605 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
606 */
607 const instable_t dis_op0F7123[4][8] = {
608 {
609 /* [70].0 */ INVALID, INVALID, INVALID, INVALID,
610 /* .4 */ INVALID, INVALID, INVALID, INVALID,
611 }, {
612 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID,
613 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID,
614 }, {
615 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID,
616 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID,
617 }, {
618 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH),
619 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH),
620 } };
621
622 /*
623 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
624 */
625 const instable_t dis_opSIMD7123[32] = {
626 /* [70].0 */ INVALID, INVALID, INVALID, INVALID,
627 /* .4 */ INVALID, INVALID, INVALID, INVALID,
628
629 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID,
630 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID,
631
632 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID,
633 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID,
634
635 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH),
636 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH),
637 };
638
639 /*
640 * SIMD instructions have been wedged into the existing IA32 instruction
641 * set through the use of prefixes. That is, while 0xf0 0x58 may be
642 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
643 * instruction - addss. At present, three prefixes have been coopted in
644 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The
645 * following tables are used to provide the prefixed instruction names.
646 * The arrays are sparse, but they're fast.
647 */
648
649 /*
650 * Decode table for SIMD instructions with the address size (0x66) prefix.
651 */
652 const instable_t dis_opSIMDdata16[256] = {
653 /* [00] */ INVALID, INVALID, INVALID, INVALID,
654 /* [04] */ INVALID, INVALID, INVALID, INVALID,
655 /* [08] */ INVALID, INVALID, INVALID, INVALID,
656 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
657
658 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8),
659 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8),
660 /* [18] */ INVALID, INVALID, INVALID, INVALID,
661 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
662
663 /* [20] */ INVALID, INVALID, INVALID, INVALID,
664 /* [24] */ INVALID, INVALID, INVALID, INVALID,
665 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
666 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
667
668 /* [30] */ INVALID, INVALID, INVALID, INVALID,
669 /* [34] */ INVALID, INVALID, INVALID, INVALID,
670 /* [38] */ INVALID, INVALID, INVALID, INVALID,
671 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
672
673 /* [40] */ INVALID, INVALID, INVALID, INVALID,
674 /* [44] */ INVALID, INVALID, INVALID, INVALID,
675 /* [48] */ INVALID, INVALID, INVALID, INVALID,
676 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
677
678 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID,
679 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
680 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
681 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
682
683 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
684 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16),
685 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
686 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
687
688 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID,
689 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID,
690 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID,
691 /* [7C] */ INVALID, INVALID, TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16),
692
693 /* [80] */ INVALID, INVALID, INVALID, INVALID,
694 /* [84] */ INVALID, INVALID, INVALID, INVALID,
695 /* [88] */ INVALID, INVALID, INVALID, INVALID,
696 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
697
698 /* [90] */ INVALID, INVALID, INVALID, INVALID,
699 /* [94] */ INVALID, INVALID, INVALID, INVALID,
700 /* [98] */ INVALID, INVALID, INVALID, INVALID,
701 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
702
703 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
704 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
705 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
706 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
707
708 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
709 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
710 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
711 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
712
713 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID,
714 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID,
715 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
716 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
717
718 /* [D0] */ INVALID, TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16),
719 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3),
720 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16),
721 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16),
722
723 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16),
724 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
725 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16),
726 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16),
727
728 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16),
729 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16),
730 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16),
731 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID,
732 };
733
734 const instable_t dis_opAVX660F[256] = {
735 /* [00] */ INVALID, INVALID, INVALID, INVALID,
736 /* [04] */ INVALID, INVALID, INVALID, INVALID,
737 /* [08] */ INVALID, INVALID, INVALID, INVALID,
738 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
739
740 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8),
741 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8),
742 /* [18] */ INVALID, INVALID, INVALID, INVALID,
743 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
744
745 /* [20] */ INVALID, INVALID, INVALID, INVALID,
746 /* [24] */ INVALID, INVALID, INVALID, INVALID,
747 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16),
748 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
749
750 /* [30] */ INVALID, INVALID, INVALID, INVALID,
751 /* [34] */ INVALID, INVALID, INVALID, INVALID,
752 /* [38] */ INVALID, INVALID, INVALID, INVALID,
753 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
754
755 /* [40] */ INVALID, INVALID, INVALID, INVALID,
756 /* [44] */ INVALID, INVALID, INVALID, INVALID,
757 /* [48] */ INVALID, INVALID, INVALID, INVALID,
758 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
759
760 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID,
761 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16),
762 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
763 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16),
764
765 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
766 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16),
767 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
768 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
769
770 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16),
771 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID,
772 /* [78] */ INVALID, INVALID, INVALID, INVALID,
773 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
774
775 /* [80] */ INVALID, INVALID, INVALID, INVALID,
776 /* [84] */ INVALID, INVALID, INVALID, INVALID,
777 /* [88] */ INVALID, INVALID, INVALID, INVALID,
778 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
779
780 /* [90] */ INVALID, INVALID, INVALID, INVALID,
781 /* [94] */ INVALID, INVALID, INVALID, INVALID,
782 /* [98] */ INVALID, INVALID, INVALID, INVALID,
783 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
784
785 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
786 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
787 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
788 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
789
790 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
791 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
792 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
793 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
794
795 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID,
796 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID,
797 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
798 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
799
800 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16),
801 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
802 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16),
803 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16),
804
805 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16),
806 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
807 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
808 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
809
810 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
811 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
812 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
813 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID,
814 };
815
816 /*
817 * Decode table for SIMD instructions with the repnz (0xf2) prefix.
818 */
819 const instable_t dis_opSIMDrepnz[256] = {
820 /* [00] */ INVALID, INVALID, INVALID, INVALID,
821 /* [04] */ INVALID, INVALID, INVALID, INVALID,
822 /* [08] */ INVALID, INVALID, INVALID, INVALID,
823 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
824
825 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), INVALID, INVALID,
826 /* [14] */ INVALID, INVALID, INVALID, INVALID,
827 /* [18] */ INVALID, INVALID, INVALID, INVALID,
828 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
829
830 /* [20] */ INVALID, INVALID, INVALID, INVALID,
831 /* [24] */ INVALID, INVALID, INVALID, INVALID,
832 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
833 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID,
834
835 /* [30] */ INVALID, INVALID, INVALID, INVALID,
836 /* [34] */ INVALID, INVALID, INVALID, INVALID,
837 /* [38] */ INVALID, INVALID, INVALID, INVALID,
838 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
839
840 /* [40] */ INVALID, INVALID, INVALID, INVALID,
841 /* [44] */ INVALID, INVALID, INVALID, INVALID,
842 /* [48] */ INVALID, INVALID, INVALID, INVALID,
843 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
844
845 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID,
846 /* [54] */ INVALID, INVALID, INVALID, INVALID,
847 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID,
848 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8),
849
850 /* [60] */ INVALID, INVALID, INVALID, INVALID,
851 /* [64] */ INVALID, INVALID, INVALID, INVALID,
852 /* [68] */ INVALID, INVALID, INVALID, INVALID,
853 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
854
855 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID,
856 /* [74] */ INVALID, INVALID, INVALID, INVALID,
857 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID,
858 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
859
860 /* [80] */ INVALID, INVALID, INVALID, INVALID,
861 /* [84] */ INVALID, INVALID, INVALID, INVALID,
862 /* [88] */ INVALID, INVALID, INVALID, INVALID,
863 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
864
865 /* [90] */ INVALID, INVALID, INVALID, INVALID,
866 /* [94] */ INVALID, INVALID, INVALID, INVALID,
867 /* [98] */ INVALID, INVALID, INVALID, INVALID,
868 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
869
870 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
871 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
872 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
873 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
874
875 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
876 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
877 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
878 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
879
880 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID,
881 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
882 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
883 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
884
885 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
886 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID,
887 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
888 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
889
890 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
891 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID,
892 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
893 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
894
895 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
896 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
897 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
898 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
899 };
900
901 const instable_t dis_opAVXF20F[256] = {
902 /* [00] */ INVALID, INVALID, INVALID, INVALID,
903 /* [04] */ INVALID, INVALID, INVALID, INVALID,
904 /* [08] */ INVALID, INVALID, INVALID, INVALID,
905 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
906
907 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID,
908 /* [14] */ INVALID, INVALID, INVALID, INVALID,
909 /* [18] */ INVALID, INVALID, INVALID, INVALID,
910 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
911
912 /* [20] */ INVALID, INVALID, INVALID, INVALID,
913 /* [24] */ INVALID, INVALID, INVALID, INVALID,
914 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
915 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID,
916
917 /* [30] */ INVALID, INVALID, INVALID, INVALID,
918 /* [34] */ INVALID, INVALID, INVALID, INVALID,
919 /* [38] */ INVALID, INVALID, INVALID, INVALID,
920 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
921
922 /* [40] */ INVALID, INVALID, INVALID, INVALID,
923 /* [44] */ INVALID, INVALID, INVALID, INVALID,
924 /* [48] */ INVALID, INVALID, INVALID, INVALID,
925 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
926
927 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID,
928 /* [54] */ INVALID, INVALID, INVALID, INVALID,
929 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
930 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
931
932 /* [60] */ INVALID, INVALID, INVALID, INVALID,
933 /* [64] */ INVALID, INVALID, INVALID, INVALID,
934 /* [68] */ INVALID, INVALID, INVALID, INVALID,
935 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
936
937 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID,
938 /* [74] */ INVALID, INVALID, INVALID, INVALID,
939 /* [78] */ INVALID, INVALID, INVALID, INVALID,
940 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID,
941
942 /* [80] */ INVALID, INVALID, INVALID, INVALID,
943 /* [84] */ INVALID, INVALID, INVALID, INVALID,
944 /* [88] */ INVALID, INVALID, INVALID, INVALID,
945 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
946
947 /* [90] */ INVALID, INVALID, INVALID, INVALID,
948 /* [94] */ INVALID, INVALID, INVALID, INVALID,
949 /* [98] */ INVALID, INVALID, INVALID, INVALID,
950 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
951
952 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
953 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
954 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
955 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
956
957 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
958 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
959 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
960 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
961
962 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID,
963 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
964 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
965 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
966
967 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID,
968 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
969 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
970 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
971
972 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
973 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
974 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
975 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
976
977 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID,
978 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
979 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
980 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
981 };
982
983 const instable_t dis_opAVXF20F3A[256] = {
984 /* [00] */ INVALID, INVALID, INVALID, INVALID,
985 /* [04] */ INVALID, INVALID, INVALID, INVALID,
986 /* [08] */ INVALID, INVALID, INVALID, INVALID,
987 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
988
989 /* [10] */ INVALID, INVALID, INVALID, INVALID,
990 /* [14] */ INVALID, INVALID, INVALID, INVALID,
991 /* [18] */ INVALID, INVALID, INVALID, INVALID,
992 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
993
994 /* [20] */ INVALID, INVALID, INVALID, INVALID,
995 /* [24] */ INVALID, INVALID, INVALID, INVALID,
996 /* [28] */ INVALID, INVALID, INVALID, INVALID,
997 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
998
999 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1000 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1001 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1002 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1003
1004 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1005 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1006 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1007 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1008
1009 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1010 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1011 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1012 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1013
1014 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1015 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1016 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1017 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1018
1019 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1020 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1021 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1022 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1023
1024 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1025 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1026 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1027 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1028
1029 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1030 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1031 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1032 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1033
1034 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1035 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1036 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1037 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1038
1039 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1040 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1041 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1042 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1043
1044 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1045 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1046 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1047 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1048
1049 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1050 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1051 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1052 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1053
1054 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1055 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1056 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1057 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1058
1059 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID,
1060 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1061 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1062 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1063 };
1064
1065 const instable_t dis_opAVXF20F38[256] = {
1066 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1067 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1068 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1069 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1070
1071 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1072 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1073 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1074 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1075
1076 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1077 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1078 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1079 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1080
1081 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1082 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1083 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1084 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1085
1086 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1087 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1088 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1089 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1090
1091 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1092 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1093 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1094 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1095
1096 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1097 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1098 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1099 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1100
1101 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1102 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1103 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1104 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1105
1106 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1107 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1108 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1109 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1110
1111 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1112 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1113 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1114 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1115
1116 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1117 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1118 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1119 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1120
1121 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1122 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1123 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1124 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1125
1126 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1127 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1128 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1129 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1130
1131 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1132 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1133 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1134 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1135
1136 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1137 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1138 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1139 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1140
1141 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1142 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
1143 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1144 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1145 };
1146
1147 const instable_t dis_opAVXF30F38[256] = {
1148 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1149 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1150 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1151 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1152
1153 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1154 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1155 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1156 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1157
1158 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1159 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1160 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1161 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1162
1163 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1164 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1165 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1166 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1167
1168 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1169 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1170 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1171 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1172
1173 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1174 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1175 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1176 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1177
1178 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1179 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1180 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1181 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1182
1183 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1184 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1185 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1186 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1187
1188 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1189 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1190 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1191 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1192
1193 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1194 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1195 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1196 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1197
1198 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1199 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1200 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1201 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1202
1203 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1204 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1205 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1206 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1207
1208 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1209 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1210 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1211 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1212
1213 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1214 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1215 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1216 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1217
1218 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1219 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1220 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1221 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1222
1223 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1224 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5),
1225 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1226 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1227 };
1228 /*
1229 * Decode table for SIMD instructions with the repz (0xf3) prefix.
1230 */
1231 const instable_t dis_opSIMDrepz[256] = {
1232 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1233 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1234 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1235 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1236
1237 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), INVALID, INVALID,
1238 /* [14] */ INVALID, INVALID, INVALID, INVALID,
1239 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1240 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1241
1242 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1243 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1244 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
1245 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID,
1246
1247 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1248 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1249 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1250 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1251
1252 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1253 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1254 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1255 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1256
1257 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4),
1258 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1259 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
1260 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4),
1261
1262 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1263 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1264 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1265 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16),
1266
1267 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID,
1268 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1269 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1270 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16),
1271
1272 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1273 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1274 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1275 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1276
1277 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1278 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1279 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1280 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1281
1282 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1283 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1284 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1285 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1286
1287 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1288 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1289 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID,
1290 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID,
1291
1292 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID,
1293 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1294 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1295 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1296
1297 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1298 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID,
1299 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1300 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1301
1302 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1303 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID,
1304 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1305 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1306
1307 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1308 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1309 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1310 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1311 };
1312
1313 const instable_t dis_opAVXF30F[256] = {
1314 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1315 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1316 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1317 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1318
1319 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID,
1320 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID,
1321 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1322 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1323
1324 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1325 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1326 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID,
1327 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID,
1328
1329 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1330 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1331 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1332 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1333
1334 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1335 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1336 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1337 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1338
1339 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4),
1340 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1341 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16),
1342 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4),
1343
1344 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1345 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1346 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1347 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16),
1348
1349 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID,
1350 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1351 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1352 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16),
1353
1354 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1355 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1356 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1357 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1358
1359 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1360 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1361 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1362 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1363
1364 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1365 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1366 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1367 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1368
1369 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1370 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1371 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1372 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1373
1374 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID,
1375 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1376 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1377 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1378
1379 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1380 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1381 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1382 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1383
1384 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1385 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID,
1386 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1387 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1388
1389 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1390 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1391 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1392 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1393 };
1394 /*
1395 * The following two tables are used to encode crc32 and movbe
1396 * since they share the same opcodes.
1397 */
1398 const instable_t dis_op0F38F0[2] = {
1399 /* [00] */ TNS("crc32b",CRC32),
1400 TS("movbe",MOVBE),
1401 };
1402
1403 const instable_t dis_op0F38F1[2] = {
1404 /* [00] */ TS("crc32",CRC32),
1405 TS("movbe",MOVBE),
1406 };
1407
1408 const instable_t dis_op0F38[256] = {
1409 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
1410 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
1411 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
1412 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1413
1414 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID,
1415 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16),
1416 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1417 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
1418
1419 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
1420 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID,
1421 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
1422 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1423
1424 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
1425 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16),
1426 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
1427 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
1428
1429 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID,
1430 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1431 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1432 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1433
1434 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1435 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1436 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1437 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1438
1439 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1440 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1441 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1442 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1443
1444 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1445 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1446 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1447 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1448
1449 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),INVALID, INVALID,
1450 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1451 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1452 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1453
1454 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1455 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1456 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1457 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1458
1459 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1460 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1461 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1462 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1463
1464 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1465 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1466 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1467 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1468
1469 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1470 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1471 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1472 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1473
1474 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1475 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1476 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16),
1477 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
1478
1479 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1480 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1481 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1482 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1483 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
1484 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1485 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1486 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1487 };
1488
1489 const instable_t dis_opAVX660F38[256] = {
1490 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1491 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1492 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1493 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
1494
1495 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16),
1496 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16),
1497 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1498 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
1499
1500 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1501 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID,
1502 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1503 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
1504
1505 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
1506 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
1507 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
1508 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
1509
1510 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID,
1511 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
1512 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1513 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1514
1515 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1516 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1517 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
1518 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1519
1520 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1521 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1522 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1523 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1524
1525 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1526 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1527 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID,
1528 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1529
1530 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1531 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1532 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1533 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID,
1534
1535 /* XXX All of the gather things are a bit wrong. We're not properly changing the last character */
1536
1537 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
1538 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
1539 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
1540 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
1541
1542 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1543 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16),
1544 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
1545 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
1546
1547 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1548 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16),
1549 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
1550 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
1551
1552 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1553 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1554 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1555 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1556
1557 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1558 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1559 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16),
1560 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
1561
1562 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1563 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1564 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1565 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1566 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
1567 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5),
1568 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1569 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1570 };
1571
1572 const instable_t dis_op0F3A[256] = {
1573 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1574 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1575 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
1576 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
1577
1578 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1579 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
1580 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1581 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1582
1583 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
1584 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1585 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1586 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1587
1588 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1589 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1590 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1591 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1592
1593 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
1594 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID,
1595 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1596 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1597
1598 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1599 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1600 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1601 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1602
1603 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
1604 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1605 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1606 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1607
1608 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1609 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1610 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1611 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1612
1613 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1614 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1615 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1616 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1617
1618 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1619 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1620 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1621 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1622
1623 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1624 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1625 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1626 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1627
1628 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1629 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1630 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1631 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1632
1633 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1634 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1635 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1636 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1637
1638 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1639 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1640 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1641 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16),
1642
1643 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1644 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1645 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1646 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1647
1648 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1649 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1650 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1651 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1652 };
1653
1654 const instable_t dis_opAVX660F3A[256] = {
1655 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
1656 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1657 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1658 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1659
1660 /* [10] */ INVALID, INVALID, INVALID, INVALID,
1661 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1662 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID,
1663 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID,
1664
1665 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1666 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1667 /* [28] */ INVALID, INVALID, INVALID, INVALID,
1668 /* [2C] */ INVALID, INVALID, INVALID, INVALID,
1669
1670 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1671 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1672 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID,
1673 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1674
1675 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
1676 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID,
1677 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16),
1678 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID,
1679
1680 /* [50] */ INVALID, INVALID, INVALID, INVALID,
1681 /* [54] */ INVALID, INVALID, INVALID, INVALID,
1682 /* [58] */ INVALID, INVALID, INVALID, INVALID,
1683 /* [5C] */ INVALID, INVALID, INVALID, INVALID,
1684
1685 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
1686 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1687 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1688 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1689
1690 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1691 /* [74] */ INVALID, INVALID, INVALID, INVALID,
1692 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1693 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1694
1695 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1696 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1697 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1698 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1699
1700 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1701 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1702 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1703 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1704
1705 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1706 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1707 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1708 /* [AC] */ INVALID, INVALID, INVALID, INVALID,
1709
1710 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1711 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1712 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1713 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1714
1715 /* [C0] */ INVALID, INVALID, INVALID, INVALID,
1716 /* [C4] */ INVALID, INVALID, INVALID, INVALID,
1717 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1718 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1719
1720 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1721 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1722 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1723 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16),
1724
1725 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1726 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1727 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1728 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1729
1730 /* [F0] */ INVALID, INVALID, INVALID, INVALID,
1731 /* [F4] */ INVALID, INVALID, INVALID, INVALID,
1732 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1733 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1734 };
1735
1736 /*
1737 * Decode table for 0x0F opcodes
1738 */
1739
1740 const instable_t dis_op0F[16][16] = {
1741 {
1742 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR),
1743 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM),
1744 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM),
1745 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1746 }, {
1747 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
1748 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1749 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
1750 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw),
1751 }, {
1752 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
1753 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,
1754 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1755 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1756 }, {
1757 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM),
1758 /* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID,
1759 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1760 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1761 }, {
1762 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR),
1763 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR),
1764 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR),
1765 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR),
1766 }, {
1767 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
1768 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16),
1769 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
1770 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16),
1771 }, {
1772 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1773 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
1774 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1775 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
1776 }, {
1777 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR),
1778 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
1779 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID,
1780 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8),
1781 }, {
1782 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D),
1783 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D),
1784 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D),
1785 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D),
1786 }, {
1787 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb),
1788 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb),
1789 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb),
1790 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb),
1791 }, {
1792 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw),
1793 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID,
1794 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw),
1795 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw),
1796 }, {
1797 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw),
1798 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ),
1799 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw),
1800 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ),
1801 }, {
1802 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
1803 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
1804 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1805 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1806 }, {
1807 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8),
1808 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3),
1809 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8),
1810 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8),
1811 }, {
1812 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8),
1813 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8),
1814 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8),
1815 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8),
1816 }, {
1817 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8),
1818 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8),
1819 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8),
1820 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID,
1821 } };
1822
1823 const instable_t dis_opAVX0F[16][16] = {
1824 {
1825 /* [00] */ INVALID, INVALID, INVALID, INVALID,
1826 /* [04] */ INVALID, INVALID, INVALID, INVALID,
1827 /* [08] */ INVALID, INVALID, INVALID, INVALID,
1828 /* [0C] */ INVALID, INVALID, INVALID, INVALID,
1829 }, {
1830 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8),
1831 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
1832 /* [18] */ INVALID, INVALID, INVALID, INVALID,
1833 /* [1C] */ INVALID, INVALID, INVALID, INVALID,
1834 }, {
1835 /* [20] */ INVALID, INVALID, INVALID, INVALID,
1836 /* [24] */ INVALID, INVALID, INVALID, INVALID,
1837 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16),
1838 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4),
1839 }, {
1840 /* [30] */ INVALID, INVALID, INVALID, INVALID,
1841 /* [34] */ INVALID, INVALID, INVALID, INVALID,
1842 /* [38] */ INVALID, INVALID, INVALID, INVALID,
1843 /* [3C] */ INVALID, INVALID, INVALID, INVALID,
1844 }, {
1845 /* [40] */ INVALID, INVALID, INVALID, INVALID,
1846 /* [44] */ INVALID, INVALID, INVALID, INVALID,
1847 /* [48] */ INVALID, INVALID, INVALID, INVALID,
1848 /* [4C] */ INVALID, INVALID, INVALID, INVALID,
1849 }, {
1850 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
1851 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16),
1852 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
1853 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16),
1854 }, {
1855 /* [60] */ INVALID, INVALID, INVALID, INVALID,
1856 /* [64] */ INVALID, INVALID, INVALID, INVALID,
1857 /* [68] */ INVALID, INVALID, INVALID, INVALID,
1858 /* [6C] */ INVALID, INVALID, INVALID, INVALID,
1859 }, {
1860 /* [70] */ INVALID, INVALID, INVALID, INVALID,
1861 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE),
1862 /* [78] */ INVALID, INVALID, INVALID, INVALID,
1863 /* [7C] */ INVALID, INVALID, INVALID, INVALID,
1864 }, {
1865 /* [80] */ INVALID, INVALID, INVALID, INVALID,
1866 /* [84] */ INVALID, INVALID, INVALID, INVALID,
1867 /* [88] */ INVALID, INVALID, INVALID, INVALID,
1868 /* [8C] */ INVALID, INVALID, INVALID, INVALID,
1869 }, {
1870 /* [90] */ INVALID, INVALID, INVALID, INVALID,
1871 /* [94] */ INVALID, INVALID, INVALID, INVALID,
1872 /* [98] */ INVALID, INVALID, INVALID, INVALID,
1873 /* [9C] */ INVALID, INVALID, INVALID, INVALID,
1874 }, {
1875 /* [A0] */ INVALID, INVALID, INVALID, INVALID,
1876 /* [A4] */ INVALID, INVALID, INVALID, INVALID,
1877 /* [A8] */ INVALID, INVALID, INVALID, INVALID,
1878 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID,
1879 }, {
1880 /* [B0] */ INVALID, INVALID, INVALID, INVALID,
1881 /* [B4] */ INVALID, INVALID, INVALID, INVALID,
1882 /* [B8] */ INVALID, INVALID, INVALID, INVALID,
1883 /* [BC] */ INVALID, INVALID, INVALID, INVALID,
1884 }, {
1885 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID,
1886 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID,
1887 /* [C8] */ INVALID, INVALID, INVALID, INVALID,
1888 /* [CC] */ INVALID, INVALID, INVALID, INVALID,
1889 }, {
1890 /* [D0] */ INVALID, INVALID, INVALID, INVALID,
1891 /* [D4] */ INVALID, INVALID, INVALID, INVALID,
1892 /* [D8] */ INVALID, INVALID, INVALID, INVALID,
1893 /* [DC] */ INVALID, INVALID, INVALID, INVALID,
1894 }, {
1895 /* [E0] */ INVALID, INVALID, INVALID, INVALID,
1896 /* [E4] */ INVALID, INVALID, INVALID, INVALID,
1897 /* [E8] */ INVALID, INVALID, INVALID, INVALID,
1898 /* [EC] */ INVALID, INVALID, INVALID, INVALID,
1899 }, {
1900 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5),
1901 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5),
1902 /* [F8] */ INVALID, INVALID, INVALID, INVALID,
1903 /* [FC] */ INVALID, INVALID, INVALID, INVALID,
1904 } };
1905
1906 /*
1907 * Decode table for 0x80 opcodes
1908 */
1909
1910 const instable_t dis_op80[8] = {
1911
1912 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw),
1913 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw),
1914 };
1915
1916
1917 /*
1918 * Decode table for 0x81 opcodes.
1919 */
1920
1921 const instable_t dis_op81[8] = {
1922
1923 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw),
1924 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw),
1925 };
1926
1927
1928 /*
1929 * Decode table for 0x82 opcodes.
1930 */
1931
1932 const instable_t dis_op82[8] = {
1933
1934 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw),
1935 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw),
1936 };
1937 /*
1938 * Decode table for 0x83 opcodes.
1939 */
1940
1941 const instable_t dis_op83[8] = {
1942
1943 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw),
1944 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw),
1945 };
1946
1947 /*
1948 * Decode table for 0xC0 opcodes.
1949 */
1950
1951 const instable_t dis_opC0[8] = {
1952
1953 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI),
1954 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI),
1955 };
1956
1957 /*
1958 * Decode table for 0xD0 opcodes.
1959 */
1960
1961 const instable_t dis_opD0[8] = {
1962
1963 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
1964 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
1965 };
1966
1967 /*
1968 * Decode table for 0xC1 opcodes.
1969 * 186 instruction set
1970 */
1971
1972 const instable_t dis_opC1[8] = {
1973
1974 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI),
1975 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI),
1976 };
1977
1978 /*
1979 * Decode table for 0xD1 opcodes.
1980 */
1981
1982 const instable_t dis_opD1[8] = {
1983
1984 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
1985 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv),
1986 };
1987
1988
1989 /*
1990 * Decode table for 0xD2 opcodes.
1991 */
1992
1993 const instable_t dis_opD2[8] = {
1994
1995 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
1996 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
1997 };
1998 /*
1999 * Decode table for 0xD3 opcodes.
2000 */
2001
2002 const instable_t dis_opD3[8] = {
2003
2004 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
2005 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv),
2006 };
2007
2008
2009 /*
2010 * Decode table for 0xF6 opcodes.
2011 */
2012
2013 const instable_t dis_opF6[8] = {
2014
2015 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw),
2016 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA),
2017 };
2018
2019
2020 /*
2021 * Decode table for 0xF7 opcodes.
2022 */
2023
2024 const instable_t dis_opF7[8] = {
2025
2026 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw),
2027 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA),
2028 };
2029
2030
2031 /*
2032 * Decode table for 0xFE opcodes.
2033 */
2034
2035 const instable_t dis_opFE[8] = {
2036
2037 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID,
2038 /* [4] */ INVALID, INVALID, INVALID, INVALID,
2039 };
2040 /*
2041 * Decode table for 0xFF opcodes.
2042 */
2043
2044 const instable_t dis_opFF[8] = {
2045
2046 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM),
2047 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID,
2048 };
2049
2050 /* for 287 instructions, which are a mess to decode */
2051
2052 const instable_t dis_opFP1n2[8][8] = {
2053 {
2054 /* bit pattern: 1101 1xxx MODxx xR/M */
2055 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M),
2056 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M),
2057 }, {
2058 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M),
2059 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2),
2060 }, {
2061 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M),
2062 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M),
2063 }, {
2064 /* [3,0] */ TNS("fildl",M), INVALID, TNS("fistl",M), TNS("fistpl",M),
2065 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10),
2066 }, {
2067 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8),
2068 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8),
2069 }, {
2070 /* [5,0] */ TNSZ("fldl",M,8), INVALID, TNSZ("fstl",M,8), TNSZ("fstpl",M,8),
2071 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2),
2072 }, {
2073 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2),
2074 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2),
2075 }, {
2076 /* [7,0] */ TNSZ("fild",M,2), INVALID, TNSZ("fist",M,2), TNSZ("fistp",M,2),
2077 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8),
2078 } };
2079
2080 const instable_t dis_opFP3[8][8] = {
2081 {
2082 /* bit pattern: 1101 1xxx 11xx xREG */
2083 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
2084 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
2085 }, {
2086 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F),
2087 /* [1,4] */ INVALID, INVALID, INVALID, INVALID,
2088 }, {
2089 /* [2,0] */ INVALID, INVALID, INVALID, INVALID,
2090 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID,
2091 }, {
2092 /* [3,0] */ INVALID, INVALID, INVALID, INVALID,
2093 /* [3,4] */ INVALID, INVALID, INVALID, INVALID,
2094 }, {
2095 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
2096 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
2097 }, {
2098 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F),
2099 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID,
2100 }, {
2101 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM),
2102 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF),
2103 }, {
2104 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F),
2105 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID,
2106 } };
2107
2108 const instable_t dis_opFP4[4][8] = {
2109 {
2110 /* bit pattern: 1101 1001 111x xxxx */
2111 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID,
2112 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID,
2113 }, {
2114 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM),
2115 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID,
2116 }, {
2117 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM),
2118 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM),
2119 }, {
2120 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM),
2121 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM),
2122 } };
2123
2124 const instable_t dis_opFP5[8] = {
2125 /* bit pattern: 1101 1011 111x xxxx */
2126 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM),
2127 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID,
2128 };
2129
2130 const instable_t dis_opFP6[8] = {
2131 /* bit pattern: 1101 1011 11yy yxxx */
2132 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF),
2133 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID,
2134 };
2135
2136 const instable_t dis_opFP7[8] = {
2137 /* bit pattern: 1101 1010 11yy yxxx */
2138 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF),
2139 /* [04] */ INVALID, INVALID, INVALID, INVALID,
2140 };
2141
2142 /*
2143 * Main decode table for the op codes. The first two nibbles
2144 * will be used as an index into the table. If there is a
2145 * a need to further decode an instruction, the array to be
2146 * referenced is indicated with the other two entries being
2147 * empty.
2148 */
2149
2150 const instable_t dis_distable[16][16] = {
2151 {
2152 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw),
2153 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG),
2154 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw),
2155 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F),
2156 }, {
2157 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw),
2158 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG),
2159 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw),
2160 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG),
2161 }, {
2162 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw),
2163 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM),
2164 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw),
2165 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM),
2166 }, {
2167 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw),
2168 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM),
2169 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw),
2170 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM),
2171 }, {
2172 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
2173 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
2174 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
2175 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
2176 }, {
2177 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
2178 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
2179 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
2180 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
2181 }, {
2182 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw),
2183 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM),
2184 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL),
2185 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
2186 }, {
2187 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD),
2188 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD),
2189 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD),
2190 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD),
2191 }, {
2192 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83),
2193 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw),
2194 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw),
2195 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M),
2196 }, {
2197 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
2198 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
2199 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM),
2200 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNSx("sahf",NORM), TNSx("lahf",NORM),
2201 }, {
2202 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO),
2203 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD),
2204 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD),
2205 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD),
2206 }, {
2207 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2208 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2209 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
2210 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
2211 }, {
2212 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM),
2213 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw),
2214 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM),
2215 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM),
2216 }, {
2217 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3),
2218 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1),
2219
2220 /* 287 instructions. Note that although the indirect field */
2221 /* indicates opFP1n2 for further decoding, this is not necessarily */
2222 /* the case since the opFP arrays are not partitioned according to key1 */
2223 /* and key2. opFP1n2 is given only to indicate that we haven't */
2224 /* finished decoding the instruction. */
2225 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
2226 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
2227 }, {
2228 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD),
2229 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P),
2230 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD),
2231 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V),
2232 }, {
2233 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX),
2234 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7),
2235 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM),
2236 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF),
2237 } };
2238
2239 /* END CSTYLED */
2240
2241 /*
2242 * common functions to decode and disassemble an x86 or amd64 instruction
2243 */
2244
2245 /*
2246 * These are the individual fields of a REX prefix. Note that a REX
2247 * prefix with none of these set is still needed to:
2248 * - use the MOVSXD (sign extend 32 to 64 bits) instruction
2249 * - access the %sil, %dil, %bpl, %spl registers
2250 */
2251 #define REX_W 0x08 /* 64 bit operand size when set */
2252 #define REX_R 0x04 /* high order bit extension of ModRM reg field */
2253 #define REX_X 0x02 /* high order bit extension of SIB index field */
2254 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */
2255
2256 /*
2257 * These are the individual fields of a VEX prefix.
2258 */
2259 #define VEX_R 0x08 /* REX.R in 1's complement form */
2260 #define VEX_X 0x04 /* REX.X in 1's complement form */
2261 #define VEX_B 0x02 /* REX.B in 1's complement form */
2262 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
2263 #define VEX_L 0x04
2264 #define VEX_W 0x08 /* opcode specific, use like REX.W */
2265 #define VEX_m 0x1F /* VEX m-mmmm field */
2266 #define VEX_v 0x78 /* VEX register specifier */
2267 #define VEX_p 0x03 /* VEX pp field, opcode extension */
2268
2269 /* VEX m-mmmm field, only used by three bytes prefix */
2270 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */
2271 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
2272 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
2273
2274 /* VEX pp field, providing equivalent functionality of a SIMD prefix */
2275 #define VEX_p_66 0x01
2276 #define VEX_p_F3 0x02
2277 #define VEX_p_F2 0x03
2278
2279 /*
2280 * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
2281 */
2282 static int isize[] = {1, 2, 4, 4};
2283 static int isize64[] = {1, 2, 4, 8};
2284
2285 /*
2286 * Just a bunch of useful macros.
2287 */
2288 #define WBIT(x) (x & 0x1) /* to get w bit */
2289 #define REGNO(x) (x & 0x7) /* to get 3 bit register */
2290 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */
2291 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
2292 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
2293
2294 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */
2295
2296 #define BYTE_OPND 0 /* w-bit value indicating byte register */
2297 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */
2298 #define MM_OPND 2 /* "value" used to indicate a mmx reg */
2299 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */
2300 #define SEG_OPND 4 /* "value" used to indicate a segment reg */
2301 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */
2302 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */
2303 #define TEST_OPND 7 /* "value" used to indicate a test reg */
2304 #define WORD_OPND 8 /* w-bit value indicating word size reg */
2305 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */
2306
2307 /*
2308 * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
2309 * there's not really a consistent scheme that we can use to know what the mode
2310 * is supposed to be for a given type. Various instructions, like VPGATHERDD,
2311 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
2312 * some registers match VEX_L, but the VSIB is always XMM.
2313 *
2314 * The simplest way to deal with this is to just define a table based on the
2315 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
2316 * them.
2317 *
2318 * We further have to subdivide this based on the value of VEX_W and the value
2319 * of VEX_L. The array is constructed to be indexed as:
2320 * [opcode - 0x90][VEX_W][VEX_L].
2321 */
2322 /* w = 0, 0x90 */
2323 typedef struct dis_gather_regs {
2324 uint_t dgr_arg0; /* src reg */
2325 uint_t dgr_arg1; /* vsib reg */
2326 uint_t dgr_arg2; /* dst reg */
2327 char *dgr_suffix; /* suffix to append */
2328 } dis_gather_regs_t;
2329
2330 static dis_gather_regs_t dis_vgather[4][2][2] = {
2331 {
2332 /* op 0x90, W.0 */
2333 {
2334 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2335 { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2336 },
2337 /* op 0x90, W.1 */
2338 {
2339 { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2340 { YMM_OPND, XMM_OPND, YMM_OPND, "q" }
2341 }
2342 },
2343 {
2344 /* op 0x91, W.0 */
2345 {
2346 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2347 { XMM_OPND, YMM_OPND, XMM_OPND, "d" },
2348 },
2349 /* op 0x91, W.1 */
2350 {
2351 { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2352 { YMM_OPND, YMM_OPND, YMM_OPND, "q" },
2353 }
2354 },
2355 {
2356 /* op 0x92, W.0 */
2357 {
2358 { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2359 { YMM_OPND, YMM_OPND, YMM_OPND, "s" }
2360 },
2361 /* op 0x92, W.1 */
2362 {
2363 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2364 { YMM_OPND, XMM_OPND, YMM_OPND, "d" }
2365 }
2366 },
2367 {
2368 /* op 0x93, W.0 */
2369 {
2370 { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2371 { XMM_OPND, YMM_OPND, XMM_OPND, "s" }
2372 },
2373 /* op 0x93, W.1 */
2374 {
2375 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2376 { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2377 }
2378 }
2379 };
2380
2381 /*
2382 * Get the next byte and separate the op code into the high and low nibbles.
2383 */
2384 static int
dtrace_get_opcode(dis86_t * x,uint_t * high,uint_t * low)2385 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low)
2386 {
2387 int byte;
2388
2389 /*
2390 * x86 instructions have a maximum length of 15 bytes. Bail out if
2391 * we try to read more.
2392 */
2393 if (x->d86_len >= 15)
2394 return (x->d86_error = 1);
2395
2396 if (x->d86_error)
2397 return (1);
2398 byte = x->d86_get_byte(x->d86_data);
2399 if (byte < 0)
2400 return (x->d86_error = 1);
2401 x->d86_bytes[x->d86_len++] = byte;
2402 *low = byte & 0xf; /* ----xxxx low 4 bits */
2403 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */
2404 return (0);
2405 }
2406
2407 /*
2408 * Get and decode an SIB (scaled index base) byte
2409 */
2410 static void
dtrace_get_SIB(dis86_t * x,uint_t * ss,uint_t * index,uint_t * base)2411 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base)
2412 {
2413 int byte;
2414
2415 if (x->d86_error)
2416 return;
2417
2418 byte = x->d86_get_byte(x->d86_data);
2419 if (byte < 0) {
2420 x->d86_error = 1;
2421 return;
2422 }
2423 x->d86_bytes[x->d86_len++] = byte;
2424
2425 *base = byte & 0x7;
2426 *index = (byte >> 3) & 0x7;
2427 *ss = (byte >> 6) & 0x3;
2428 }
2429
2430 /*
2431 * Get the byte following the op code and separate it into the
2432 * mode, register, and r/m fields.
2433 */
2434 static void
dtrace_get_modrm(dis86_t * x,uint_t * mode,uint_t * reg,uint_t * r_m)2435 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)
2436 {
2437 if (x->d86_got_modrm == 0) {
2438 if (x->d86_rmindex == -1)
2439 x->d86_rmindex = x->d86_len;
2440 dtrace_get_SIB(x, mode, reg, r_m);
2441 x->d86_got_modrm = 1;
2442 }
2443 }
2444
2445 /*
2446 * Adjust register selection based on any REX prefix bits present.
2447 */
2448 /*ARGSUSED*/
2449 static void
dtrace_rex_adjust(uint_t rex_prefix,uint_t mode,uint_t * reg,uint_t * r_m)2450 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
2451 {
2452 if (reg != NULL && r_m == NULL) {
2453 if (rex_prefix & REX_B)
2454 *reg += 8;
2455 } else {
2456 if (reg != NULL && (REX_R & rex_prefix) != 0)
2457 *reg += 8;
2458 if (r_m != NULL && (REX_B & rex_prefix) != 0)
2459 *r_m += 8;
2460 }
2461 }
2462
2463 /*
2464 * Adjust register selection based on any VEX prefix bits present.
2465 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
2466 */
2467 /*ARGSUSED*/
2468 static void
dtrace_vex_adjust(uint_t vex_byte1,uint_t mode,uint_t * reg,uint_t * r_m)2469 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
2470 {
2471 if (reg != NULL && r_m == NULL) {
2472 if (!(vex_byte1 & VEX_B))
2473 *reg += 8;
2474 } else {
2475 if (reg != NULL && ((VEX_R & vex_byte1) == 0))
2476 *reg += 8;
2477 if (r_m != NULL && ((VEX_B & vex_byte1) == 0))
2478 *r_m += 8;
2479 }
2480 }
2481
2482 /*
2483 * Get an immediate operand of the given size, with sign extension.
2484 */
2485 static void
dtrace_imm_opnd(dis86_t * x,int wbit,int size,int opindex)2486 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
2487 {
2488 int i;
2489 int byte;
2490 int valsize;
2491
2492 if (x->d86_numopnds < opindex + 1)
2493 x->d86_numopnds = opindex + 1;
2494
2495 switch (wbit) {
2496 case BYTE_OPND:
2497 valsize = 1;
2498 break;
2499 case LONG_OPND:
2500 if (x->d86_opnd_size == SIZE16)
2501 valsize = 2;
2502 else if (x->d86_opnd_size == SIZE32)
2503 valsize = 4;
2504 else
2505 valsize = 8;
2506 break;
2507 case MM_OPND:
2508 case XMM_OPND:
2509 case YMM_OPND:
2510 case SEG_OPND:
2511 case CONTROL_OPND:
2512 case DEBUG_OPND:
2513 case TEST_OPND:
2514 valsize = size;
2515 break;
2516 case WORD_OPND:
2517 valsize = 2;
2518 break;
2519 }
2520 if (valsize < size)
2521 valsize = size;
2522
2523 if (x->d86_error)
2524 return;
2525 x->d86_opnd[opindex].d86_value = 0;
2526 for (i = 0; i < size; ++i) {
2527 byte = x->d86_get_byte(x->d86_data);
2528 if (byte < 0) {
2529 x->d86_error = 1;
2530 return;
2531 }
2532 x->d86_bytes[x->d86_len++] = byte;
2533 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8);
2534 }
2535 /* Do sign extension */
2536 if (x->d86_bytes[x->d86_len - 1] & 0x80) {
2537 for (; i < sizeof (uint64_t); i++)
2538 x->d86_opnd[opindex].d86_value |=
2539 (uint64_t)0xff << (i * 8);
2540 }
2541 #ifdef DIS_TEXT
2542 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2543 x->d86_opnd[opindex].d86_value_size = valsize;
2544 x->d86_imm_bytes += size;
2545 #endif
2546 }
2547
2548 /*
2549 * Get an ip relative operand of the given size, with sign extension.
2550 */
2551 static void
dtrace_disp_opnd(dis86_t * x,int wbit,int size,int opindex)2552 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex)
2553 {
2554 dtrace_imm_opnd(x, wbit, size, opindex);
2555 #ifdef DIS_TEXT
2556 x->d86_opnd[opindex].d86_mode = MODE_IPREL;
2557 #endif
2558 }
2559
2560 /*
2561 * Check to see if there is a segment override prefix pending.
2562 * If so, print it in the current 'operand' location and set
2563 * the override flag back to false.
2564 */
2565 /*ARGSUSED*/
2566 static void
dtrace_check_override(dis86_t * x,int opindex)2567 dtrace_check_override(dis86_t *x, int opindex)
2568 {
2569 #ifdef DIS_TEXT
2570 if (x->d86_seg_prefix) {
2571 (void) strlcat(x->d86_opnd[opindex].d86_prefix,
2572 x->d86_seg_prefix, PFIXLEN);
2573 }
2574 #endif
2575 x->d86_seg_prefix = NULL;
2576 }
2577
2578
2579 /*
2580 * Process a single instruction Register or Memory operand.
2581 *
2582 * mode = addressing mode from ModRM byte
2583 * r_m = r_m (or reg if mode == 3) field from ModRM byte
2584 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
2585 * o = index of operand that we are processing (0, 1 or 2)
2586 *
2587 * the value of reg or r_m must have already been adjusted for any REX prefix.
2588 */
2589 /*ARGSUSED*/
2590 static void
dtrace_get_operand(dis86_t * x,uint_t mode,uint_t r_m,int wbit,int opindex)2591 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
2592 {
2593 int have_SIB = 0; /* flag presence of scale-index-byte */
2594 uint_t ss; /* scale-factor from opcode */
2595 uint_t index; /* index register number */
2596 uint_t base; /* base register number */
2597 int dispsize; /* size of displacement in bytes */
2598 #ifdef DIS_TEXT
2599 char *opnd = x->d86_opnd[opindex].d86_opnd;
2600 #endif
2601
2602 if (x->d86_numopnds < opindex + 1)
2603 x->d86_numopnds = opindex + 1;
2604
2605 if (x->d86_error)
2606 return;
2607
2608 /*
2609 * first handle a simple register
2610 */
2611 if (mode == REG_ONLY) {
2612 #ifdef DIS_TEXT
2613 switch (wbit) {
2614 case MM_OPND:
2615 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN);
2616 break;
2617 case XMM_OPND:
2618 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
2619 break;
2620 case YMM_OPND:
2621 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN);
2622 break;
2623 case SEG_OPND:
2624 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
2625 break;
2626 case CONTROL_OPND:
2627 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN);
2628 break;
2629 case DEBUG_OPND:
2630 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN);
2631 break;
2632 case TEST_OPND:
2633 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN);
2634 break;
2635 case BYTE_OPND:
2636 if (x->d86_rex_prefix == 0)
2637 (void) strlcat(opnd, dis_REG8[r_m], OPLEN);
2638 else
2639 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN);
2640 break;
2641 case WORD_OPND:
2642 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2643 break;
2644 case LONG_OPND:
2645 if (x->d86_opnd_size == SIZE16)
2646 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2647 else if (x->d86_opnd_size == SIZE32)
2648 (void) strlcat(opnd, dis_REG32[r_m], OPLEN);
2649 else
2650 (void) strlcat(opnd, dis_REG64[r_m], OPLEN);
2651 break;
2652 }
2653 #endif /* DIS_TEXT */
2654 return;
2655 }
2656
2657 /*
2658 * if symbolic representation, skip override prefix, if any
2659 */
2660 dtrace_check_override(x, opindex);
2661
2662 /*
2663 * Handle 16 bit memory references first, since they decode
2664 * the mode values more simply.
2665 * mode 1 is r_m + 8 bit displacement
2666 * mode 2 is r_m + 16 bit displacement
2667 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
2668 */
2669 if (x->d86_addr_size == SIZE16) {
2670 if ((mode == 0 && r_m == 6) || mode == 2)
2671 dtrace_imm_opnd(x, WORD_OPND, 2, opindex);
2672 else if (mode == 1)
2673 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex);
2674 #ifdef DIS_TEXT
2675 if (mode == 0 && r_m == 6)
2676 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2677 else if (mode == 0)
2678 x->d86_opnd[opindex].d86_mode = MODE_NONE;
2679 else
2680 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2681 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN);
2682 #endif
2683 return;
2684 }
2685
2686 /*
2687 * 32 and 64 bit addressing modes are more complex since they
2688 * can involve an SIB (scaled index and base) byte to decode.
2689 */
2690 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) {
2691 have_SIB = 1;
2692 dtrace_get_SIB(x, &ss, &index, &base);
2693 if (x->d86_error)
2694 return;
2695 if (base != 5 || mode != 0)
2696 if (x->d86_rex_prefix & REX_B)
2697 base += 8;
2698 if (x->d86_rex_prefix & REX_X)
2699 index += 8;
2700 } else {
2701 base = r_m;
2702 }
2703
2704 /*
2705 * Compute the displacement size and get its bytes
2706 */
2707 dispsize = 0;
2708
2709 if (mode == 1)
2710 dispsize = 1;
2711 else if (mode == 2)
2712 dispsize = 4;
2713 else if ((r_m & 7) == EBP_REGNO ||
2714 (have_SIB && (base & 7) == EBP_REGNO))
2715 dispsize = 4;
2716
2717 if (dispsize > 0) {
2718 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND,
2719 dispsize, opindex);
2720 if (x->d86_error)
2721 return;
2722 }
2723
2724 #ifdef DIS_TEXT
2725 if (dispsize > 0)
2726 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2727
2728 if (have_SIB == 0) {
2729 if (x->d86_mode == SIZE32) {
2730 if (mode == 0)
2731 (void) strlcat(opnd, dis_addr32_mode0[r_m],
2732 OPLEN);
2733 else
2734 (void) strlcat(opnd, dis_addr32_mode12[r_m],
2735 OPLEN);
2736 } else {
2737 if (mode == 0) {
2738 (void) strlcat(opnd, dis_addr64_mode0[r_m],
2739 OPLEN);
2740 if (r_m == 5) {
2741 x->d86_opnd[opindex].d86_mode =
2742 MODE_RIPREL;
2743 }
2744 } else {
2745 (void) strlcat(opnd, dis_addr64_mode12[r_m],
2746 OPLEN);
2747 }
2748 }
2749 } else {
2750 uint_t need_paren = 0;
2751 char **regs;
2752 char **bregs;
2753 const char *const *sf;
2754 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
2755 regs = (char **)dis_REG32;
2756 else
2757 regs = (char **)dis_REG64;
2758
2759 if (x->d86_vsib != 0) {
2760 if (wbit == YMM_OPND) /* NOTE this is not addr_size! */
2761 bregs = (char **)dis_YMMREG;
2762 else
2763 bregs = (char **)dis_XMMREG;
2764 sf = dis_vscale_factor;
2765 } else {
2766 bregs = regs;
2767 sf = dis_scale_factor;
2768 }
2769
2770 /*
2771 * print the base (if any)
2772 */
2773 if (base == EBP_REGNO && mode == 0) {
2774 if (index != ESP_REGNO || x->d86_vsib != 0) {
2775 (void) strlcat(opnd, "(", OPLEN);
2776 need_paren = 1;
2777 }
2778 } else {
2779 (void) strlcat(opnd, "(", OPLEN);
2780 (void) strlcat(opnd, regs[base], OPLEN);
2781 need_paren = 1;
2782 }
2783
2784 /*
2785 * print the index (if any)
2786 */
2787 if (index != ESP_REGNO || x->d86_vsib) {
2788 (void) strlcat(opnd, ",", OPLEN);
2789 (void) strlcat(opnd, bregs[index], OPLEN);
2790 (void) strlcat(opnd, sf[ss], OPLEN);
2791 } else
2792 if (need_paren)
2793 (void) strlcat(opnd, ")", OPLEN);
2794 }
2795 #endif
2796 }
2797
2798 /*
2799 * Operand sequence for standard instruction involving one register
2800 * and one register/memory operand.
2801 * wbit indicates a byte(0) or opnd_size(1) operation
2802 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
2803 */
2804 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \
2805 dtrace_get_modrm(x, &mode, ®, &r_m); \
2806 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2807 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2808 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \
2809 }
2810
2811 /*
2812 * Similar to above, but allows for the two operands to be of different
2813 * classes (ie. wbit).
2814 * wbit is for the r_m operand
2815 * w2 is for the reg operand
2816 */
2817 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \
2818 dtrace_get_modrm(x, &mode, ®, &r_m); \
2819 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2820 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2821 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \
2822 }
2823
2824 /*
2825 * Similar, but for 2 operands plus an immediate.
2826 * vbit indicates direction
2827 * 0 for "opcode imm, r, r_m" or
2828 * 1 for "opcode imm, r_m, r"
2829 */
2830 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
2831 dtrace_get_modrm(x, &mode, ®, &r_m); \
2832 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2833 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \
2834 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \
2835 dtrace_imm_opnd(x, wbit, immsize, 0); \
2836 }
2837
2838 /*
2839 * Similar, but for 2 operands plus two immediates.
2840 */
2841 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
2842 dtrace_get_modrm(x, &mode, ®, &r_m); \
2843 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2844 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2845 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \
2846 dtrace_imm_opnd(x, wbit, immsize, 1); \
2847 dtrace_imm_opnd(x, wbit, immsize, 0); \
2848 }
2849
2850 /*
2851 * 1 operands plus two immediates.
2852 */
2853 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
2854 dtrace_get_modrm(x, &mode, ®, &r_m); \
2855 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2856 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2857 dtrace_imm_opnd(x, wbit, immsize, 1); \
2858 dtrace_imm_opnd(x, wbit, immsize, 0); \
2859 }
2860
2861 /*
2862 * Dissassemble a single x86 or amd64 instruction.
2863 *
2864 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
2865 * for interpreting instructions.
2866 *
2867 * returns non-zero for bad opcode
2868 */
2869 int
dtrace_disx86(dis86_t * x,uint_t cpu_mode)2870 dtrace_disx86(dis86_t *x, uint_t cpu_mode)
2871 {
2872 instable_t *dp; /* decode table being used */
2873 #ifdef DIS_TEXT
2874 uint_t i;
2875 #endif
2876 #ifdef DIS_MEM
2877 uint_t nomem = 0;
2878 #define NOMEM (nomem = 1)
2879 #else
2880 #define NOMEM /* nothing */
2881 #endif
2882 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */
2883 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */
2884 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */
2885 uint_t w2; /* wbit value for second operand */
2886 uint_t vbit;
2887 uint_t mode = 0; /* mode value from ModRM byte */
2888 uint_t reg; /* reg value from ModRM byte */
2889 uint_t r_m; /* r_m value from ModRM byte */
2890
2891 uint_t opcode1; /* high nibble of 1st byte */
2892 uint_t opcode2; /* low nibble of 1st byte */
2893 uint_t opcode3; /* extra opcode bits usually from ModRM byte */
2894 uint_t opcode4; /* high nibble of 2nd byte */
2895 uint_t opcode5; /* low nibble of 2nd byte */
2896 uint_t opcode6; /* high nibble of 3rd byte */
2897 uint_t opcode7; /* low nibble of 3rd byte */
2898 uint_t opcode_bytes = 1;
2899
2900 /*
2901 * legacy prefixes come in 5 flavors, you should have only one of each
2902 */
2903 uint_t opnd_size_prefix = 0;
2904 uint_t addr_size_prefix = 0;
2905 uint_t segment_prefix = 0;
2906 uint_t lock_prefix = 0;
2907 uint_t rep_prefix = 0;
2908 uint_t rex_prefix = 0; /* amd64 register extension prefix */
2909
2910 /*
2911 * Intel VEX instruction encoding prefix and fields
2912 */
2913
2914 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
2915 uint_t vex_prefix = 0;
2916
2917 /*
2918 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
2919 * (for 3 bytes prefix)
2920 */
2921 uint_t vex_byte1 = 0;
2922
2923 /*
2924 * For 32-bit mode, it should prefetch the next byte to
2925 * distinguish between AVX and les/lds
2926 */
2927 uint_t vex_prefetch = 0;
2928
2929 uint_t vex_m = 0;
2930 uint_t vex_v = 0;
2931 uint_t vex_p = 0;
2932 uint_t vex_R = 1;
2933 uint_t vex_X = 1;
2934 uint_t vex_B = 1;
2935 uint_t vex_W = 0;
2936 uint_t vex_L;
2937 dis_gather_regs_t *vreg;
2938
2939 #ifdef DIS_TEXT
2940 /* Instruction name for BLS* family of instructions */
2941 char *blsinstr;
2942 #endif
2943
2944 size_t off;
2945
2946 instable_t dp_mmx;
2947
2948 x->d86_len = 0;
2949 x->d86_rmindex = -1;
2950 x->d86_error = 0;
2951 #ifdef DIS_TEXT
2952 x->d86_numopnds = 0;
2953 x->d86_seg_prefix = NULL;
2954 x->d86_mnem[0] = 0;
2955 for (i = 0; i < 4; ++i) {
2956 x->d86_opnd[i].d86_opnd[0] = 0;
2957 x->d86_opnd[i].d86_prefix[0] = 0;
2958 x->d86_opnd[i].d86_value_size = 0;
2959 x->d86_opnd[i].d86_value = 0;
2960 x->d86_opnd[i].d86_mode = MODE_NONE;
2961 }
2962 #endif
2963 x->d86_rex_prefix = 0;
2964 x->d86_got_modrm = 0;
2965 x->d86_memsize = 0;
2966 x->d86_vsib = 0;
2967
2968 if (cpu_mode == SIZE16) {
2969 opnd_size = SIZE16;
2970 addr_size = SIZE16;
2971 } else if (cpu_mode == SIZE32) {
2972 opnd_size = SIZE32;
2973 addr_size = SIZE32;
2974 } else {
2975 opnd_size = SIZE32;
2976 addr_size = SIZE64;
2977 }
2978
2979 /*
2980 * Get one opcode byte and check for zero padding that follows
2981 * jump tables.
2982 */
2983 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
2984 goto error;
2985
2986 if (opcode1 == 0 && opcode2 == 0 &&
2987 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
2988 #ifdef DIS_TEXT
2989 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);
2990 #endif
2991 goto done;
2992 }
2993
2994 /*
2995 * Gather up legacy x86 prefix bytes.
2996 */
2997 for (;;) {
2998 uint_t *which_prefix = NULL;
2999
3000 dp = (instable_t *)&dis_distable[opcode1][opcode2];
3001
3002 switch (dp->it_adrmode) {
3003 case PREFIX:
3004 which_prefix = &rep_prefix;
3005 break;
3006 case LOCK:
3007 which_prefix = &lock_prefix;
3008 break;
3009 case OVERRIDE:
3010 which_prefix = &segment_prefix;
3011 #ifdef DIS_TEXT
3012 x->d86_seg_prefix = (char *)dp->it_name;
3013 #endif
3014 if (dp->it_invalid64 && cpu_mode == SIZE64)
3015 goto error;
3016 break;
3017 case AM:
3018 which_prefix = &addr_size_prefix;
3019 break;
3020 case DM:
3021 which_prefix = &opnd_size_prefix;
3022 break;
3023 }
3024 if (which_prefix == NULL)
3025 break;
3026 *which_prefix = (opcode1 << 4) | opcode2;
3027 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3028 goto error;
3029 }
3030
3031 /*
3032 * Handle amd64 mode PREFIX values.
3033 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
3034 * We might have a REX prefix (opcodes 0x40-0x4f)
3035 */
3036 if (cpu_mode == SIZE64) {
3037 if (segment_prefix != 0x64 && segment_prefix != 0x65)
3038 segment_prefix = 0;
3039
3040 if (opcode1 == 0x4) {
3041 rex_prefix = (opcode1 << 4) | opcode2;
3042 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3043 goto error;
3044 dp = (instable_t *)&dis_distable[opcode1][opcode2];
3045 } else if (opcode1 == 0xC &&
3046 (opcode2 == 0x4 || opcode2 == 0x5)) {
3047 /* AVX instructions */
3048 vex_prefix = (opcode1 << 4) | opcode2;
3049 x->d86_rex_prefix = 0x40;
3050 }
3051 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) {
3052 /* LDS, LES or AVX */
3053 dtrace_get_modrm(x, &mode, ®, &r_m);
3054 vex_prefetch = 1;
3055
3056 if (mode == REG_ONLY) {
3057 /* AVX */
3058 vex_prefix = (opcode1 << 4) | opcode2;
3059 x->d86_rex_prefix = 0x40;
3060 opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
3061 opcode4 = ((reg << 3) | r_m) & 0x0F;
3062 }
3063 }
3064
3065 if (vex_prefix == VEX_2bytes) {
3066 if (!vex_prefetch) {
3067 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3068 goto error;
3069 }
3070 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3;
3071 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2;
3072 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3;
3073 vex_p = opcode4 & VEX_p;
3074 /*
3075 * The vex.x and vex.b bits are not defined in two bytes
3076 * mode vex prefix, their default values are 1
3077 */
3078 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B;
3079
3080 if (vex_R == 0)
3081 x->d86_rex_prefix |= REX_R;
3082
3083 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3084 goto error;
3085
3086 switch (vex_p) {
3087 case VEX_p_66:
3088 dp = (instable_t *)
3089 &dis_opAVX660F[(opcode1 << 4) | opcode2];
3090 break;
3091 case VEX_p_F3:
3092 dp = (instable_t *)
3093 &dis_opAVXF30F[(opcode1 << 4) | opcode2];
3094 break;
3095 case VEX_p_F2:
3096 dp = (instable_t *)
3097 &dis_opAVXF20F [(opcode1 << 4) | opcode2];
3098 break;
3099 default:
3100 dp = (instable_t *)
3101 &dis_opAVX0F[opcode1][opcode2];
3102
3103 }
3104
3105 } else if (vex_prefix == VEX_3bytes) {
3106 if (!vex_prefetch) {
3107 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3108 goto error;
3109 }
3110 vex_R = (opcode3 & VEX_R) >> 3;
3111 vex_X = (opcode3 & VEX_X) >> 2;
3112 vex_B = (opcode3 & VEX_B) >> 1;
3113 vex_m = (((opcode3 << 4) | opcode4) & VEX_m);
3114 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B);
3115
3116 if (vex_R == 0)
3117 x->d86_rex_prefix |= REX_R;
3118 if (vex_X == 0)
3119 x->d86_rex_prefix |= REX_X;
3120 if (vex_B == 0)
3121 x->d86_rex_prefix |= REX_B;
3122
3123 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0)
3124 goto error;
3125 vex_W = (opcode5 & VEX_W) >> 3;
3126 vex_L = (opcode6 & VEX_L) >> 2;
3127 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3;
3128 vex_p = opcode6 & VEX_p;
3129
3130 if (vex_W)
3131 x->d86_rex_prefix |= REX_W;
3132
3133 /* Only these three vex_m values valid; others are reserved */
3134 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) &&
3135 (vex_m != VEX_m_0F3A))
3136 goto error;
3137
3138 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3139 goto error;
3140
3141 switch (vex_p) {
3142 case VEX_p_66:
3143 if (vex_m == VEX_m_0F) {
3144 dp = (instable_t *)
3145 &dis_opAVX660F
3146 [(opcode1 << 4) | opcode2];
3147 } else if (vex_m == VEX_m_0F38) {
3148 dp = (instable_t *)
3149 &dis_opAVX660F38
3150 [(opcode1 << 4) | opcode2];
3151 } else if (vex_m == VEX_m_0F3A) {
3152 dp = (instable_t *)
3153 &dis_opAVX660F3A
3154 [(opcode1 << 4) | opcode2];
3155 } else {
3156 goto error;
3157 }
3158 break;
3159 case VEX_p_F3:
3160 if (vex_m == VEX_m_0F) {
3161 dp = (instable_t *)
3162 &dis_opAVXF30F
3163 [(opcode1 << 4) | opcode2];
3164 } else if (vex_m == VEX_m_0F38) {
3165 dp = (instable_t *)
3166 &dis_opAVXF30F38
3167 [(opcode1 << 4) | opcode2];
3168 } else {
3169 goto error;
3170 }
3171 break;
3172 case VEX_p_F2:
3173 if (vex_m == VEX_m_0F) {
3174 dp = (instable_t *)
3175 &dis_opAVXF20F
3176 [(opcode1 << 4) | opcode2];
3177 } else if (vex_m == VEX_m_0F3A) {
3178 dp = (instable_t *)
3179 &dis_opAVXF20F3A
3180 [(opcode1 << 4) | opcode2];
3181 } else if (vex_m == VEX_m_0F38) {
3182 dp = (instable_t *)
3183 &dis_opAVXF20F38
3184 [(opcode1 << 4) | opcode2];
3185 } else {
3186 goto error;
3187 }
3188 break;
3189 default:
3190 dp = (instable_t *)
3191 &dis_opAVX0F[opcode1][opcode2];
3192
3193 }
3194 }
3195 if (vex_prefix) {
3196 if (dp->it_vexwoxmm) {
3197 wbit = LONG_OPND;
3198 } else {
3199 if (vex_L)
3200 wbit = YMM_OPND;
3201 else
3202 wbit = XMM_OPND;
3203 }
3204 }
3205
3206 /*
3207 * Deal with selection of operand and address size now.
3208 * Note that the REX.W bit being set causes opnd_size_prefix to be
3209 * ignored.
3210 */
3211 if (cpu_mode == SIZE64) {
3212 if ((rex_prefix & REX_W) || vex_W)
3213 opnd_size = SIZE64;
3214 else if (opnd_size_prefix)
3215 opnd_size = SIZE16;
3216
3217 if (addr_size_prefix)
3218 addr_size = SIZE32;
3219 } else if (cpu_mode == SIZE32) {
3220 if (opnd_size_prefix)
3221 opnd_size = SIZE16;
3222 if (addr_size_prefix)
3223 addr_size = SIZE16;
3224 } else {
3225 if (opnd_size_prefix)
3226 opnd_size = SIZE32;
3227 if (addr_size_prefix)
3228 addr_size = SIZE32;
3229 }
3230 /*
3231 * The pause instruction - a repz'd nop. This doesn't fit
3232 * with any of the other prefix goop added for SSE, so we'll
3233 * special-case it here.
3234 */
3235 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) {
3236 rep_prefix = 0;
3237 dp = (instable_t *)&dis_opPause;
3238 }
3239
3240 /*
3241 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
3242 * byte so we may need to perform a table indirection.
3243 */
3244 if (dp->it_indirect == (instable_t *)dis_op0F) {
3245 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
3246 goto error;
3247 opcode_bytes = 2;
3248 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) {
3249 uint_t subcode;
3250
3251 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3252 goto error;
3253 opcode_bytes = 3;
3254 subcode = ((opcode6 & 0x3) << 1) |
3255 ((opcode7 & 0x8) >> 3);
3256 dp = (instable_t *)&dis_op0F7123[opcode5][subcode];
3257 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) {
3258 dp = (instable_t *)&dis_op0FC8[0];
3259 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) {
3260 opcode_bytes = 3;
3261 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3262 goto error;
3263 if (opnd_size == SIZE16)
3264 opnd_size = SIZE32;
3265
3266 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7];
3267 #ifdef DIS_TEXT
3268 if (strcmp(dp->it_name, "INVALID") == 0)
3269 goto error;
3270 #endif
3271 switch (dp->it_adrmode) {
3272 case XMMP_66r:
3273 case XMMPRM_66r:
3274 case XMM3PM_66r:
3275 if (opnd_size_prefix == 0) {
3276 goto error;
3277 }
3278 break;
3279 case XMMP_66o:
3280 if (opnd_size_prefix == 0) {
3281 /* SSSE3 MMX instructions */
3282 dp_mmx = *dp;
3283 dp = &dp_mmx;
3284 dp->it_adrmode = MMOPM_66o;
3285 #ifdef DIS_MEM
3286 dp->it_size = 8;
3287 #endif
3288 }
3289 break;
3290 default:
3291 goto error;
3292 }
3293 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) {
3294 opcode_bytes = 3;
3295 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3296 goto error;
3297 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];
3298
3299 /*
3300 * Both crc32 and movbe have the same 3rd opcode
3301 * byte of either 0xF0 or 0xF1, so we use another
3302 * indirection to distinguish between the two.
3303 */
3304 if (dp->it_indirect == (instable_t *)dis_op0F38F0 ||
3305 dp->it_indirect == (instable_t *)dis_op0F38F1) {
3306
3307 dp = dp->it_indirect;
3308 if (rep_prefix != 0xF2) {
3309 /* It is movbe */
3310 dp++;
3311 }
3312 }
3313 #ifdef DIS_TEXT
3314 if (strcmp(dp->it_name, "INVALID") == 0)
3315 goto error;
3316 #endif
3317 switch (dp->it_adrmode) {
3318 case RM_66r:
3319 case XMM_66r:
3320 case XMMM_66r:
3321 if (opnd_size_prefix == 0) {
3322 goto error;
3323 }
3324 break;
3325 case XMM_66o:
3326 if (opnd_size_prefix == 0) {
3327 /* SSSE3 MMX instructions */
3328 dp_mmx = *dp;
3329 dp = &dp_mmx;
3330 dp->it_adrmode = MM;
3331 #ifdef DIS_MEM
3332 dp->it_size = 8;
3333 #endif
3334 }
3335 break;
3336 case CRC32:
3337 if (rep_prefix != 0xF2) {
3338 goto error;
3339 }
3340 rep_prefix = 0;
3341 break;
3342 case MOVBE:
3343 if (rep_prefix != 0x0) {
3344 goto error;
3345 }
3346 break;
3347 default:
3348 goto error;
3349 }
3350 } else {
3351 dp = (instable_t *)&dis_op0F[opcode4][opcode5];
3352 }
3353 }
3354
3355 /*
3356 * If still not at a TERM decode entry, then a ModRM byte
3357 * exists and its fields further decode the instruction.
3358 */
3359 x->d86_got_modrm = 0;
3360 if (dp->it_indirect != TERM) {
3361 dtrace_get_modrm(x, &mode, &opcode3, &r_m);
3362 if (x->d86_error)
3363 goto error;
3364 reg = opcode3;
3365
3366 /*
3367 * decode 287 instructions (D8-DF) from opcodeN
3368 */
3369 if (opcode1 == 0xD && opcode2 >= 0x8) {
3370 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4)
3371 dp = (instable_t *)&dis_opFP5[r_m];
3372 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4)
3373 dp = (instable_t *)&dis_opFP7[opcode3];
3374 else if (opcode2 == 0xB && mode == 0x3)
3375 dp = (instable_t *)&dis_opFP6[opcode3];
3376 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4)
3377 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m];
3378 else if (mode == 0x3)
3379 dp = (instable_t *)
3380 &dis_opFP3[opcode2 - 8][opcode3];
3381 else
3382 dp = (instable_t *)
3383 &dis_opFP1n2[opcode2 - 8][opcode3];
3384 } else {
3385 dp = (instable_t *)dp->it_indirect + opcode3;
3386 }
3387 }
3388
3389 /*
3390 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
3391 * (sign extend 32bit to 64 bit)
3392 */
3393 if ((vex_prefix == 0) && cpu_mode == SIZE64 &&
3394 opcode1 == 0x6 && opcode2 == 0x3)
3395 dp = (instable_t *)&dis_opMOVSLD;
3396
3397 /*
3398 * at this point we should have a correct (or invalid) opcode
3399 */
3400 if (cpu_mode == SIZE64 && dp->it_invalid64 ||
3401 cpu_mode != SIZE64 && dp->it_invalid32)
3402 goto error;
3403 if (dp->it_indirect != TERM)
3404 goto error;
3405
3406 /*
3407 * deal with MMX/SSE opcodes which are changed by prefixes
3408 */
3409 switch (dp->it_adrmode) {
3410 case MMO:
3411 case MMOIMPL:
3412 case MMO3P:
3413 case MMOM3:
3414 case MMOMS:
3415 case MMOPM:
3416 case MMOPRM:
3417 case MMOS:
3418 case XMMO:
3419 case XMMOM:
3420 case XMMOMS:
3421 case XMMOPM:
3422 case XMMOS:
3423 case XMMOMX:
3424 case XMMOX3:
3425 case XMMOXMM:
3426 /*
3427 * This is horrible. Some SIMD instructions take the
3428 * form 0x0F 0x?? ..., which is easily decoded using the
3429 * existing tables. Other SIMD instructions use various
3430 * prefix bytes to overload existing instructions. For
3431 * Example, addps is F0, 58, whereas addss is F3 (repz),
3432 * F0, 58. Presumably someone got a raise for this.
3433 *
3434 * If we see one of the instructions which can be
3435 * modified in this way (if we've got one of the SIMDO*
3436 * address modes), we'll check to see if the last prefix
3437 * was a repz. If it was, we strip the prefix from the
3438 * mnemonic, and we indirect using the dis_opSIMDrepz
3439 * table.
3440 */
3441
3442 /*
3443 * Calculate our offset in dis_op0F
3444 */
3445 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F))
3446 goto error;
3447
3448 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3449 sizeof (instable_t);
3450
3451 /*
3452 * Rewrite if this instruction used one of the magic prefixes.
3453 */
3454 if (rep_prefix) {
3455 if (rep_prefix == 0xf2)
3456 dp = (instable_t *)&dis_opSIMDrepnz[off];
3457 else
3458 dp = (instable_t *)&dis_opSIMDrepz[off];
3459 rep_prefix = 0;
3460 } else if (opnd_size_prefix) {
3461 dp = (instable_t *)&dis_opSIMDdata16[off];
3462 opnd_size_prefix = 0;
3463 if (opnd_size == SIZE16)
3464 opnd_size = SIZE32;
3465 }
3466 break;
3467
3468 case MG9:
3469 /*
3470 * More horribleness: the group 9 (0xF0 0xC7) instructions are
3471 * allowed an optional prefix of 0x66 or 0xF3. This is similar
3472 * to the SIMD business described above, but with a different
3473 * addressing mode (and an indirect table), so we deal with it
3474 * separately (if similarly).
3475 *
3476 * Intel further complicated this with the release of Ivy Bridge
3477 * where they overloaded these instructions based on the ModR/M
3478 * bytes. The VMX instructions have a mode of 0 since they are
3479 * memory instructions but rdrand instructions have a mode of
3480 * 0b11 (REG_ONLY) because they only operate on registers. While
3481 * there are different prefix formats, for now it is sufficient
3482 * to use a single different table.
3483 */
3484
3485 /*
3486 * Calculate our offset in dis_op0FC7 (the group 9 table)
3487 */
3488 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
3489 goto error;
3490
3491 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
3492 sizeof (instable_t);
3493
3494 /*
3495 * If we have a mode of 0b11 then we have to rewrite this.
3496 */
3497 dtrace_get_modrm(x, &mode, ®, &r_m);
3498 if (mode == REG_ONLY) {
3499 dp = (instable_t *)&dis_op0FC7m3[off];
3500 break;
3501 }
3502
3503 /*
3504 * Rewrite if this instruction used one of the magic prefixes.
3505 */
3506 if (rep_prefix) {
3507 if (rep_prefix == 0xf3)
3508 dp = (instable_t *)&dis_opF30FC7[off];
3509 else
3510 goto error;
3511 rep_prefix = 0;
3512 } else if (opnd_size_prefix) {
3513 dp = (instable_t *)&dis_op660FC7[off];
3514 opnd_size_prefix = 0;
3515 if (opnd_size == SIZE16)
3516 opnd_size = SIZE32;
3517 }
3518 break;
3519
3520
3521 case MMOSH:
3522 /*
3523 * As with the "normal" SIMD instructions, the MMX
3524 * shuffle instructions are overloaded. These
3525 * instructions, however, are special in that they use
3526 * an extra byte, and thus an extra table. As of this
3527 * writing, they only use the opnd_size prefix.
3528 */
3529
3530 /*
3531 * Calculate our offset in dis_op0F7123
3532 */
3533 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 >
3534 sizeof (dis_op0F7123))
3535 goto error;
3536
3537 if (opnd_size_prefix) {
3538 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) /
3539 sizeof (instable_t);
3540 dp = (instable_t *)&dis_opSIMD7123[off];
3541 opnd_size_prefix = 0;
3542 if (opnd_size == SIZE16)
3543 opnd_size = SIZE32;
3544 }
3545 break;
3546 case MRw:
3547 if (rep_prefix) {
3548 if (rep_prefix == 0xf3) {
3549
3550 /*
3551 * Calculate our offset in dis_op0F
3552 */
3553 if ((uintptr_t)dp - (uintptr_t)dis_op0F
3554 > sizeof (dis_op0F))
3555 goto error;
3556
3557 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3558 sizeof (instable_t);
3559
3560 dp = (instable_t *)&dis_opSIMDrepz[off];
3561 rep_prefix = 0;
3562 } else {
3563 goto error;
3564 }
3565 }
3566 break;
3567 }
3568
3569 /*
3570 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
3571 */
3572 if (cpu_mode == SIZE64)
3573 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop))
3574 opnd_size = SIZE64;
3575
3576 #ifdef DIS_TEXT
3577 /*
3578 * At this point most instructions can format the opcode mnemonic
3579 * including the prefixes.
3580 */
3581 if (lock_prefix)
3582 (void) strlcat(x->d86_mnem, "lock ", OPLEN);
3583
3584 if (rep_prefix == 0xf2)
3585 (void) strlcat(x->d86_mnem, "repnz ", OPLEN);
3586 else if (rep_prefix == 0xf3)
3587 (void) strlcat(x->d86_mnem, "repz ", OPLEN);
3588
3589 if (cpu_mode == SIZE64 && addr_size_prefix)
3590 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN);
3591
3592 if (dp->it_adrmode != CBW &&
3593 dp->it_adrmode != CWD &&
3594 dp->it_adrmode != XMMSFNC) {
3595 if (strcmp(dp->it_name, "INVALID") == 0)
3596 goto error;
3597 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN);
3598 if (dp->it_avxsuf && dp->it_suffix) {
3599 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d",
3600 OPLEN);
3601 } else if (dp->it_suffix) {
3602 char *types[] = {"", "w", "l", "q"};
3603 if (opcode_bytes == 2 && opcode4 == 4) {
3604 /* It's a cmovx.yy. Replace the suffix x */
3605 for (i = 5; i < OPLEN; i++) {
3606 if (x->d86_mnem[i] == '.')
3607 break;
3608 }
3609 x->d86_mnem[i - 1] = *types[opnd_size];
3610 } else if ((opnd_size == 2) && (opcode_bytes == 3) &&
3611 ((opcode6 == 1 && opcode7 == 6) ||
3612 (opcode6 == 2 && opcode7 == 2))) {
3613 /*
3614 * To handle PINSRD and PEXTRD
3615 */
3616 (void) strlcat(x->d86_mnem, "d", OPLEN);
3617 } else {
3618 (void) strlcat(x->d86_mnem, types[opnd_size],
3619 OPLEN);
3620 }
3621 }
3622 }
3623 #endif
3624
3625 /*
3626 * Process operands based on the addressing modes.
3627 */
3628 x->d86_mode = cpu_mode;
3629 /*
3630 * In vex mode the rex_prefix has no meaning
3631 */
3632 if (!vex_prefix)
3633 x->d86_rex_prefix = rex_prefix;
3634 x->d86_opnd_size = opnd_size;
3635 x->d86_addr_size = addr_size;
3636 vbit = 0; /* initialize for mem/reg -> reg */
3637 switch (dp->it_adrmode) {
3638 /*
3639 * amd64 instruction to sign extend 32 bit reg/mem operands
3640 * into 64 bit register values
3641 */
3642 case MOVSXZ:
3643 #ifdef DIS_TEXT
3644 if (rex_prefix == 0)
3645 (void) strncpy(x->d86_mnem, "movzld", OPLEN);
3646 #endif
3647 dtrace_get_modrm(x, &mode, ®, &r_m);
3648 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3649 x->d86_opnd_size = SIZE64;
3650 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3651 x->d86_opnd_size = opnd_size = SIZE32;
3652 wbit = LONG_OPND;
3653 dtrace_get_operand(x, mode, r_m, wbit, 0);
3654 break;
3655
3656 /*
3657 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
3658 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
3659 * wbit lives in 2nd byte, note that operands
3660 * are different sized
3661 */
3662 case MOVZ:
3663 if (rex_prefix & REX_W) {
3664 /* target register size = 64 bit */
3665 x->d86_mnem[5] = 'q';
3666 }
3667 dtrace_get_modrm(x, &mode, ®, &r_m);
3668 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3669 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3670 x->d86_opnd_size = opnd_size = SIZE16;
3671 wbit = WBIT(opcode5);
3672 dtrace_get_operand(x, mode, r_m, wbit, 0);
3673 break;
3674 case CRC32:
3675 opnd_size = SIZE32;
3676 if (rex_prefix & REX_W)
3677 opnd_size = SIZE64;
3678 x->d86_opnd_size = opnd_size;
3679
3680 dtrace_get_modrm(x, &mode, ®, &r_m);
3681 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3682 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3683 wbit = WBIT(opcode7);
3684 if (opnd_size_prefix)
3685 x->d86_opnd_size = opnd_size = SIZE16;
3686 dtrace_get_operand(x, mode, r_m, wbit, 0);
3687 break;
3688 case MOVBE:
3689 opnd_size = SIZE32;
3690 if (rex_prefix & REX_W)
3691 opnd_size = SIZE64;
3692 x->d86_opnd_size = opnd_size;
3693
3694 dtrace_get_modrm(x, &mode, ®, &r_m);
3695 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3696 wbit = WBIT(opcode7);
3697 if (opnd_size_prefix)
3698 x->d86_opnd_size = opnd_size = SIZE16;
3699 if (wbit) {
3700 /* reg -> mem */
3701 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
3702 dtrace_get_operand(x, mode, r_m, wbit, 1);
3703 } else {
3704 /* mem -> reg */
3705 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3706 dtrace_get_operand(x, mode, r_m, wbit, 0);
3707 }
3708 break;
3709
3710 /*
3711 * imul instruction, with either 8-bit or longer immediate
3712 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
3713 */
3714 case IMUL:
3715 wbit = LONG_OPND;
3716 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND,
3717 OPSIZE(opnd_size, opcode2 == 0x9), 1);
3718 break;
3719
3720 /* memory or register operand to register, with 'w' bit */
3721 case MRw:
3722 wbit = WBIT(opcode2);
3723 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3724 break;
3725
3726 /* register to memory or register operand, with 'w' bit */
3727 /* arpl happens to fit here also because it is odd */
3728 case RMw:
3729 if (opcode_bytes == 2)
3730 wbit = WBIT(opcode5);
3731 else
3732 wbit = WBIT(opcode2);
3733 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3734 break;
3735
3736 /* xaddb instruction */
3737 case XADDB:
3738 wbit = 0;
3739 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3740 break;
3741
3742 /* MMX register to memory or register operand */
3743 case MMS:
3744 case MMOS:
3745 #ifdef DIS_TEXT
3746 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
3747 #else
3748 wbit = LONG_OPND;
3749 #endif
3750 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3751 break;
3752
3753 /* MMX register to memory */
3754 case MMOMS:
3755 dtrace_get_modrm(x, &mode, ®, &r_m);
3756 if (mode == REG_ONLY)
3757 goto error;
3758 wbit = MM_OPND;
3759 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3760 break;
3761
3762 /* Double shift. Has immediate operand specifying the shift. */
3763 case DSHIFT:
3764 wbit = LONG_OPND;
3765 dtrace_get_modrm(x, &mode, ®, &r_m);
3766 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
3767 dtrace_get_operand(x, mode, r_m, wbit, 2);
3768 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3769 dtrace_imm_opnd(x, wbit, 1, 0);
3770 break;
3771
3772 /*
3773 * Double shift. With no immediate operand, specifies using %cl.
3774 */
3775 case DSHIFTcl:
3776 wbit = LONG_OPND;
3777 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3778 break;
3779
3780 /* immediate to memory or register operand */
3781 case IMlw:
3782 wbit = WBIT(opcode2);
3783 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3784 dtrace_get_operand(x, mode, r_m, wbit, 1);
3785 /*
3786 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
3787 */
3788 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0);
3789 break;
3790
3791 /* immediate to memory or register operand with the */
3792 /* 'w' bit present */
3793 case IMw:
3794 wbit = WBIT(opcode2);
3795 dtrace_get_modrm(x, &mode, ®, &r_m);
3796 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3797 dtrace_get_operand(x, mode, r_m, wbit, 1);
3798 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
3799 break;
3800
3801 /* immediate to register with register in low 3 bits */
3802 /* of op code */
3803 case IR:
3804 /* w-bit here (with regs) is bit 3 */
3805 wbit = opcode2 >>3 & 0x1;
3806 reg = REGNO(opcode2);
3807 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
3808 mode = REG_ONLY;
3809 r_m = reg;
3810 dtrace_get_operand(x, mode, r_m, wbit, 1);
3811 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0);
3812 break;
3813
3814 /* MMX immediate shift of register */
3815 case MMSH:
3816 case MMOSH:
3817 wbit = MM_OPND;
3818 goto mm_shift; /* in next case */
3819
3820 /* SIMD immediate shift of register */
3821 case XMMSH:
3822 wbit = XMM_OPND;
3823 mm_shift:
3824 reg = REGNO(opcode7);
3825 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
3826 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
3827 dtrace_imm_opnd(x, wbit, 1, 0);
3828 NOMEM;
3829 break;
3830
3831 /* accumulator to memory operand */
3832 case AO:
3833 vbit = 1;
3834 /*FALLTHROUGH*/
3835
3836 /* memory operand to accumulator */
3837 case OA:
3838 wbit = WBIT(opcode2);
3839 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit);
3840 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit);
3841 #ifdef DIS_TEXT
3842 x->d86_opnd[vbit].d86_mode = MODE_OFFSET;
3843 #endif
3844 break;
3845
3846
3847 /* segment register to memory or register operand */
3848 case SM:
3849 vbit = 1;
3850 /*FALLTHROUGH*/
3851
3852 /* memory or register operand to segment register */
3853 case MS:
3854 dtrace_get_modrm(x, &mode, ®, &r_m);
3855 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3856 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit);
3857 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit);
3858 break;
3859
3860 /*
3861 * rotate or shift instructions, which may shift by 1 or
3862 * consult the cl register, depending on the 'v' bit
3863 */
3864 case Mv:
3865 vbit = VBIT(opcode2);
3866 wbit = WBIT(opcode2);
3867 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3868 dtrace_get_operand(x, mode, r_m, wbit, 1);
3869 #ifdef DIS_TEXT
3870 if (vbit) {
3871 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN);
3872 } else {
3873 x->d86_opnd[0].d86_mode = MODE_SIGNED;
3874 x->d86_opnd[0].d86_value_size = 1;
3875 x->d86_opnd[0].d86_value = 1;
3876 }
3877 #endif
3878 break;
3879 /*
3880 * immediate rotate or shift instructions
3881 */
3882 case MvI:
3883 wbit = WBIT(opcode2);
3884 normal_imm_mem:
3885 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3886 dtrace_get_operand(x, mode, r_m, wbit, 1);
3887 dtrace_imm_opnd(x, wbit, 1, 0);
3888 break;
3889
3890 /* bit test instructions */
3891 case MIb:
3892 wbit = LONG_OPND;
3893 goto normal_imm_mem;
3894
3895 /* single memory or register operand with 'w' bit present */
3896 case Mw:
3897 wbit = WBIT(opcode2);
3898 just_mem:
3899 dtrace_get_modrm(x, &mode, ®, &r_m);
3900 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3901 dtrace_get_operand(x, mode, r_m, wbit, 0);
3902 break;
3903
3904 case SWAPGS_RDTSCP:
3905 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
3906 #ifdef DIS_TEXT
3907 (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
3908 #endif
3909 NOMEM;
3910 break;
3911 } else if (mode == 3 && r_m == 1) {
3912 #ifdef DIS_TEXT
3913 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN);
3914 #endif
3915 NOMEM;
3916 break;
3917 }
3918
3919 /*FALLTHROUGH*/
3920
3921 /* prefetch instruction - memory operand, but no memory acess */
3922 case PREF:
3923 NOMEM;
3924 /*FALLTHROUGH*/
3925
3926 /* single memory or register operand */
3927 case M:
3928 case MG9:
3929 wbit = LONG_OPND;
3930 goto just_mem;
3931
3932 /* single memory or register byte operand */
3933 case Mb:
3934 wbit = BYTE_OPND;
3935 goto just_mem;
3936
3937 case VMx:
3938 if (mode == 3) {
3939 #ifdef DIS_TEXT
3940 char *vminstr;
3941
3942 switch (r_m) {
3943 case 1:
3944 vminstr = "vmcall";
3945 break;
3946 case 2:
3947 vminstr = "vmlaunch";
3948 break;
3949 case 3:
3950 vminstr = "vmresume";
3951 break;
3952 case 4:
3953 vminstr = "vmxoff";
3954 break;
3955 default:
3956 goto error;
3957 }
3958
3959 (void) strncpy(x->d86_mnem, vminstr, OPLEN);
3960 #else
3961 if (r_m < 1 || r_m > 4)
3962 goto error;
3963 #endif
3964
3965 NOMEM;
3966 break;
3967 }
3968 /*FALLTHROUGH*/
3969 case SVM:
3970 if (mode == 3) {
3971 #if DIS_TEXT
3972 char *vinstr;
3973
3974 switch (r_m) {
3975 case 0:
3976 vinstr = "vmrun";
3977 break;
3978 case 1:
3979 vinstr = "vmmcall";
3980 break;
3981 case 2:
3982 vinstr = "vmload";
3983 break;
3984 case 3:
3985 vinstr = "vmsave";
3986 break;
3987 case 4:
3988 vinstr = "stgi";
3989 break;
3990 case 5:
3991 vinstr = "clgi";
3992 break;
3993 case 6:
3994 vinstr = "skinit";
3995 break;
3996 case 7:
3997 vinstr = "invlpga";
3998 break;
3999 }
4000
4001 (void) strncpy(x->d86_mnem, vinstr, OPLEN);
4002 #endif
4003 NOMEM;
4004 break;
4005 }
4006 /*FALLTHROUGH*/
4007 case MONITOR_MWAIT:
4008 if (mode == 3) {
4009 if (r_m == 0) {
4010 #ifdef DIS_TEXT
4011 (void) strncpy(x->d86_mnem, "monitor", OPLEN);
4012 #endif
4013 NOMEM;
4014 break;
4015 } else if (r_m == 1) {
4016 #ifdef DIS_TEXT
4017 (void) strncpy(x->d86_mnem, "mwait", OPLEN);
4018 #endif
4019 NOMEM;
4020 break;
4021 } else {
4022 goto error;
4023 }
4024 }
4025 /*FALLTHROUGH*/
4026 case XGETBV_XSETBV:
4027 if (mode == 3) {
4028 if (r_m == 0) {
4029 #ifdef DIS_TEXT
4030 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN);
4031 #endif
4032 NOMEM;
4033 break;
4034 } else if (r_m == 1) {
4035 #ifdef DIS_TEXT
4036 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN);
4037 #endif
4038 NOMEM;
4039 break;
4040 } else {
4041 goto error;
4042 }
4043
4044 }
4045 /*FALLTHROUGH*/
4046 case MO:
4047 /* Similar to M, but only memory (no direct registers) */
4048 wbit = LONG_OPND;
4049 dtrace_get_modrm(x, &mode, ®, &r_m);
4050 if (mode == 3)
4051 goto error;
4052 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4053 dtrace_get_operand(x, mode, r_m, wbit, 0);
4054 break;
4055
4056 /* move special register to register or reverse if vbit */
4057 case SREG:
4058 switch (opcode5) {
4059
4060 case 2:
4061 vbit = 1;
4062 /*FALLTHROUGH*/
4063 case 0:
4064 wbit = CONTROL_OPND;
4065 break;
4066
4067 case 3:
4068 vbit = 1;
4069 /*FALLTHROUGH*/
4070 case 1:
4071 wbit = DEBUG_OPND;
4072 break;
4073
4074 case 6:
4075 vbit = 1;
4076 /*FALLTHROUGH*/
4077 case 4:
4078 wbit = TEST_OPND;
4079 break;
4080
4081 }
4082 dtrace_get_modrm(x, &mode, ®, &r_m);
4083 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
4084 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit);
4085 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit);
4086 NOMEM;
4087 break;
4088
4089 /*
4090 * single register operand with register in the low 3
4091 * bits of op code
4092 */
4093 case R:
4094 if (opcode_bytes == 2)
4095 reg = REGNO(opcode5);
4096 else
4097 reg = REGNO(opcode2);
4098 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
4099 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
4100 NOMEM;
4101 break;
4102
4103 /*
4104 * register to accumulator with register in the low 3
4105 * bits of op code, xchg instructions
4106 */
4107 case RA:
4108 NOMEM;
4109 reg = REGNO(opcode2);
4110 dtrace_rex_adjust(rex_prefix, mode, ®, NULL);
4111 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
4112 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1);
4113 break;
4114
4115 /*
4116 * single segment register operand, with register in
4117 * bits 3-4 of op code byte
4118 */
4119 case SEG:
4120 NOMEM;
4121 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3;
4122 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
4123 break;
4124
4125 /*
4126 * single segment register operand, with register in
4127 * bits 3-5 of op code
4128 */
4129 case LSEG:
4130 NOMEM;
4131 /* long seg reg from opcode */
4132 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7;
4133 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
4134 break;
4135
4136 /* memory or register operand to register */
4137 case MR:
4138 if (vex_prefetch)
4139 x->d86_got_modrm = 1;
4140 wbit = LONG_OPND;
4141 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
4142 break;
4143
4144 case RM:
4145 case RM_66r:
4146 wbit = LONG_OPND;
4147 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
4148 break;
4149
4150 /* MMX/SIMD-Int memory or mm reg to mm reg */
4151 case MM:
4152 case MMO:
4153 #ifdef DIS_TEXT
4154 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
4155 #else
4156 wbit = LONG_OPND;
4157 #endif
4158 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
4159 break;
4160
4161 case MMOIMPL:
4162 #ifdef DIS_TEXT
4163 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
4164 #else
4165 wbit = LONG_OPND;
4166 #endif
4167 dtrace_get_modrm(x, &mode, ®, &r_m);
4168 if (mode != REG_ONLY)
4169 goto error;
4170
4171 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
4172 dtrace_get_operand(x, mode, r_m, wbit, 0);
4173 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1);
4174 mode = 0; /* change for memory access size... */
4175 break;
4176
4177 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */
4178 case MMO3P:
4179 wbit = MM_OPND;
4180 goto xmm3p;
4181 case XMM3P:
4182 wbit = XMM_OPND;
4183 xmm3p:
4184 dtrace_get_modrm(x, &mode, ®, &r_m);
4185 if (mode != REG_ONLY)
4186 goto error;
4187
4188 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1,
4189 1);
4190 NOMEM;
4191 break;
4192
4193 case XMM3PM_66r:
4194 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND,
4195 1, 0);
4196 break;
4197
4198 /* MMX/SIMD-Int predicated r32/mem to mm reg */
4199 case MMOPRM:
4200 wbit = LONG_OPND;
4201 w2 = MM_OPND;
4202 goto xmmprm;
4203 case XMMPRM:
4204 case XMMPRM_66r:
4205 wbit = LONG_OPND;
4206 w2 = XMM_OPND;
4207 xmmprm:
4208 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1);
4209 break;
4210
4211 /* MMX/SIMD-Int predicated mm/mem to mm reg */
4212 case MMOPM:
4213 case MMOPM_66o:
4214 wbit = w2 = MM_OPND;
4215 goto xmmprm;
4216
4217 /* MMX/SIMD-Int mm reg to r32 */
4218 case MMOM3:
4219 NOMEM;
4220 dtrace_get_modrm(x, &mode, ®, &r_m);
4221 if (mode != REG_ONLY)
4222 goto error;
4223 wbit = MM_OPND;
4224 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
4225 break;
4226
4227 /* SIMD memory or xmm reg operand to xmm reg */
4228 case XMM:
4229 case XMM_66o:
4230 case XMM_66r:
4231 case XMMO:
4232 case XMMXIMPL:
4233 wbit = XMM_OPND;
4234 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
4235
4236 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY)
4237 goto error;
4238
4239 #ifdef DIS_TEXT
4240 /*
4241 * movlps and movhlps share opcodes. They differ in the
4242 * addressing modes allowed for their operands.
4243 * movhps and movlhps behave similarly.
4244 */
4245 if (mode == REG_ONLY) {
4246 if (strcmp(dp->it_name, "movlps") == 0)
4247 (void) strncpy(x->d86_mnem, "movhlps", OPLEN);
4248 else if (strcmp(dp->it_name, "movhps") == 0)
4249 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
4250 }
4251 #endif
4252 if (dp->it_adrmode == XMMXIMPL)
4253 mode = 0; /* change for memory access size... */
4254 break;
4255
4256 /* SIMD xmm reg to memory or xmm reg */
4257 case XMMS:
4258 case XMMOS:
4259 case XMMMS:
4260 case XMMOMS:
4261 dtrace_get_modrm(x, &mode, ®, &r_m);
4262 #ifdef DIS_TEXT
4263 if ((strcmp(dp->it_name, "movlps") == 0 ||
4264 strcmp(dp->it_name, "movhps") == 0 ||
4265 strcmp(dp->it_name, "movntps") == 0) &&
4266 mode == REG_ONLY)
4267 goto error;
4268 #endif
4269 wbit = XMM_OPND;
4270 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
4271 break;
4272
4273 /* SIMD memory to xmm reg */
4274 case XMMM:
4275 case XMMM_66r:
4276 case XMMOM:
4277 wbit = XMM_OPND;
4278 dtrace_get_modrm(x, &mode, ®, &r_m);
4279 #ifdef DIS_TEXT
4280 if (mode == REG_ONLY) {
4281 if (strcmp(dp->it_name, "movhps") == 0)
4282 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
4283 else
4284 goto error;
4285 }
4286 #endif
4287 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4288 break;
4289
4290 /* SIMD memory or r32 to xmm reg */
4291 case XMM3MX:
4292 wbit = LONG_OPND;
4293 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4294 break;
4295
4296 case XMM3MXS:
4297 wbit = LONG_OPND;
4298 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
4299 break;
4300
4301 /* SIMD memory or mm reg to xmm reg */
4302 case XMMOMX:
4303 /* SIMD mm to xmm */
4304 case XMMMX:
4305 wbit = MM_OPND;
4306 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4307 break;
4308
4309 /* SIMD memory or xmm reg to mm reg */
4310 case XMMXMM:
4311 case XMMOXMM:
4312 case XMMXM:
4313 wbit = XMM_OPND;
4314 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
4315 break;
4316
4317
4318 /* SIMD memory or xmm reg to r32 */
4319 case XMMXM3:
4320 wbit = XMM_OPND;
4321 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
4322 break;
4323
4324 /* SIMD xmm to r32 */
4325 case XMMX3:
4326 case XMMOX3:
4327 dtrace_get_modrm(x, &mode, ®, &r_m);
4328 if (mode != REG_ONLY)
4329 goto error;
4330 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
4331 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
4332 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
4333 NOMEM;
4334 break;
4335
4336 /* SIMD predicated memory or xmm reg with/to xmm reg */
4337 case XMMP:
4338 case XMMP_66r:
4339 case XMMP_66o:
4340 case XMMOPM:
4341 wbit = XMM_OPND;
4342 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1,
4343 1);
4344
4345 #ifdef DIS_TEXT
4346 /*
4347 * cmpps and cmpss vary their instruction name based
4348 * on the value of imm8. Other XMMP instructions,
4349 * such as shufps, require explicit specification of
4350 * the predicate.
4351 */
4352 if (dp->it_name[0] == 'c' &&
4353 dp->it_name[1] == 'm' &&
4354 dp->it_name[2] == 'p' &&
4355 strlen(dp->it_name) == 5) {
4356 uchar_t pred = x->d86_opnd[0].d86_value & 0xff;
4357
4358 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *)))
4359 goto error;
4360
4361 (void) strncpy(x->d86_mnem, "cmp", OPLEN);
4362 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred],
4363 OPLEN);
4364 (void) strlcat(x->d86_mnem,
4365 dp->it_name + strlen(dp->it_name) - 2,
4366 OPLEN);
4367 x->d86_opnd[0] = x->d86_opnd[1];
4368 x->d86_opnd[1] = x->d86_opnd[2];
4369 x->d86_numopnds = 2;
4370 }
4371 #endif
4372 break;
4373
4374 case XMMX2I:
4375 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND,
4376 1);
4377 NOMEM;
4378 break;
4379
4380 case XMM2I:
4381 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1);
4382 NOMEM;
4383 break;
4384
4385 /* immediate operand to accumulator */
4386 case IA:
4387 wbit = WBIT(opcode2);
4388 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4389 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
4390 NOMEM;
4391 break;
4392
4393 /* memory or register operand to accumulator */
4394 case MA:
4395 wbit = WBIT(opcode2);
4396 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4397 dtrace_get_operand(x, mode, r_m, wbit, 0);
4398 break;
4399
4400 /* si register to di register used to reference memory */
4401 case SD:
4402 #ifdef DIS_TEXT
4403 dtrace_check_override(x, 0);
4404 x->d86_numopnds = 2;
4405 if (addr_size == SIZE64) {
4406 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4407 OPLEN);
4408 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4409 OPLEN);
4410 } else if (addr_size == SIZE32) {
4411 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4412 OPLEN);
4413 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4414 OPLEN);
4415 } else {
4416 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4417 OPLEN);
4418 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4419 OPLEN);
4420 }
4421 #endif
4422 wbit = LONG_OPND;
4423 break;
4424
4425 /* accumulator to di register */
4426 case AD:
4427 wbit = WBIT(opcode2);
4428 #ifdef DIS_TEXT
4429 dtrace_check_override(x, 1);
4430 x->d86_numopnds = 2;
4431 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0);
4432 if (addr_size == SIZE64)
4433 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4434 OPLEN);
4435 else if (addr_size == SIZE32)
4436 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4437 OPLEN);
4438 else
4439 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4440 OPLEN);
4441 #endif
4442 break;
4443
4444 /* si register to accumulator */
4445 case SA:
4446 wbit = WBIT(opcode2);
4447 #ifdef DIS_TEXT
4448 dtrace_check_override(x, 0);
4449 x->d86_numopnds = 2;
4450 if (addr_size == SIZE64)
4451 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4452 OPLEN);
4453 else if (addr_size == SIZE32)
4454 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4455 OPLEN);
4456 else
4457 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4458 OPLEN);
4459 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4460 #endif
4461 break;
4462
4463 /*
4464 * single operand, a 16/32 bit displacement
4465 */
4466 case D:
4467 wbit = LONG_OPND;
4468 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4469 NOMEM;
4470 break;
4471
4472 /* jmp/call indirect to memory or register operand */
4473 case INM:
4474 #ifdef DIS_TEXT
4475 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN);
4476 #endif
4477 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4478 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4479 wbit = LONG_OPND;
4480 break;
4481
4482 /*
4483 * for long jumps and long calls -- a new code segment
4484 * register and an offset in IP -- stored in object
4485 * code in reverse order. Note - not valid in amd64
4486 */
4487 case SO:
4488 dtrace_check_override(x, 1);
4489 wbit = LONG_OPND;
4490 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1);
4491 #ifdef DIS_TEXT
4492 x->d86_opnd[1].d86_mode = MODE_SIGNED;
4493 #endif
4494 /* will now get segment operand */
4495 dtrace_imm_opnd(x, wbit, 2, 0);
4496 break;
4497
4498 /*
4499 * jmp/call. single operand, 8 bit displacement.
4500 * added to current EIP in 'compofff'
4501 */
4502 case BD:
4503 dtrace_disp_opnd(x, BYTE_OPND, 1, 0);
4504 NOMEM;
4505 break;
4506
4507 /* single 32/16 bit immediate operand */
4508 case I:
4509 wbit = LONG_OPND;
4510 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4511 break;
4512
4513 /* single 8 bit immediate operand */
4514 case Ib:
4515 wbit = LONG_OPND;
4516 dtrace_imm_opnd(x, wbit, 1, 0);
4517 break;
4518
4519 case ENTER:
4520 wbit = LONG_OPND;
4521 dtrace_imm_opnd(x, wbit, 2, 0);
4522 dtrace_imm_opnd(x, wbit, 1, 1);
4523 switch (opnd_size) {
4524 case SIZE64:
4525 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8;
4526 break;
4527 case SIZE32:
4528 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4;
4529 break;
4530 case SIZE16:
4531 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2;
4532 break;
4533 }
4534
4535 break;
4536
4537 /* 16-bit immediate operand */
4538 case RET:
4539 wbit = LONG_OPND;
4540 dtrace_imm_opnd(x, wbit, 2, 0);
4541 break;
4542
4543 /* single 8 bit port operand */
4544 case P:
4545 dtrace_check_override(x, 0);
4546 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4547 NOMEM;
4548 break;
4549
4550 /* single operand, dx register (variable port instruction) */
4551 case V:
4552 x->d86_numopnds = 1;
4553 dtrace_check_override(x, 0);
4554 #ifdef DIS_TEXT
4555 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN);
4556 #endif
4557 NOMEM;
4558 break;
4559
4560 /*
4561 * The int instruction, which has two forms:
4562 * int 3 (breakpoint) or
4563 * int n, where n is indicated in the subsequent
4564 * byte (format Ib). The int 3 instruction (opcode 0xCC),
4565 * where, although the 3 looks like an operand,
4566 * it is implied by the opcode. It must be converted
4567 * to the correct base and output.
4568 */
4569 case INT3:
4570 #ifdef DIS_TEXT
4571 x->d86_numopnds = 1;
4572 x->d86_opnd[0].d86_mode = MODE_SIGNED;
4573 x->d86_opnd[0].d86_value_size = 1;
4574 x->d86_opnd[0].d86_value = 3;
4575 #endif
4576 NOMEM;
4577 break;
4578
4579 /* single 8 bit immediate operand */
4580 case INTx:
4581 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4582 NOMEM;
4583 break;
4584
4585 /* an unused byte must be discarded */
4586 case U:
4587 if (x->d86_get_byte(x->d86_data) < 0)
4588 goto error;
4589 x->d86_len++;
4590 NOMEM;
4591 break;
4592
4593 case CBW:
4594 #ifdef DIS_TEXT
4595 if (opnd_size == SIZE16)
4596 (void) strlcat(x->d86_mnem, "cbtw", OPLEN);
4597 else if (opnd_size == SIZE32)
4598 (void) strlcat(x->d86_mnem, "cwtl", OPLEN);
4599 else
4600 (void) strlcat(x->d86_mnem, "cltq", OPLEN);
4601 #endif
4602 wbit = LONG_OPND;
4603 NOMEM;
4604 break;
4605
4606 case CWD:
4607 #ifdef DIS_TEXT
4608 if (opnd_size == SIZE16)
4609 (void) strlcat(x->d86_mnem, "cwtd", OPLEN);
4610 else if (opnd_size == SIZE32)
4611 (void) strlcat(x->d86_mnem, "cltd", OPLEN);
4612 else
4613 (void) strlcat(x->d86_mnem, "cqtd", OPLEN);
4614 #endif
4615 wbit = LONG_OPND;
4616 NOMEM;
4617 break;
4618
4619 case XMMSFNC:
4620 /*
4621 * sfence is sfence if mode is REG_ONLY. If mode isn't
4622 * REG_ONLY, mnemonic should be 'clflush'.
4623 */
4624 dtrace_get_modrm(x, &mode, ®, &r_m);
4625
4626 /* sfence doesn't take operands */
4627 #ifdef DIS_TEXT
4628 if (mode == REG_ONLY) {
4629 (void) strlcat(x->d86_mnem, "sfence", OPLEN);
4630 } else {
4631 (void) strlcat(x->d86_mnem, "clflush", OPLEN);
4632 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
4633 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4634 NOMEM;
4635 }
4636 #else
4637 if (mode != REG_ONLY) {
4638 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
4639 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4640 NOMEM;
4641 }
4642 #endif
4643 break;
4644
4645 /*
4646 * no disassembly, the mnemonic was all there was so go on
4647 */
4648 case NORM:
4649 if (dp->it_invalid32 && cpu_mode != SIZE64)
4650 goto error;
4651 NOMEM;
4652 /*FALLTHROUGH*/
4653 case IMPLMEM:
4654 break;
4655
4656 case XMMFENCE:
4657 /*
4658 * XRSTOR and LFENCE share the same opcode but differ in mode
4659 */
4660 dtrace_get_modrm(x, &mode, ®, &r_m);
4661
4662 if (mode == REG_ONLY) {
4663 /*
4664 * Only the following exact byte sequences are allowed:
4665 *
4666 * 0f ae e8 lfence
4667 * 0f ae f0 mfence
4668 */
4669 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 &&
4670 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0)
4671 goto error;
4672 } else {
4673 #ifdef DIS_TEXT
4674 (void) strncpy(x->d86_mnem, "xrstor", OPLEN);
4675 #endif
4676 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m);
4677 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4678 }
4679 break;
4680
4681 /* float reg */
4682 case F:
4683 #ifdef DIS_TEXT
4684 x->d86_numopnds = 1;
4685 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN);
4686 x->d86_opnd[0].d86_opnd[4] = r_m + '0';
4687 #endif
4688 NOMEM;
4689 break;
4690
4691 /* float reg to float reg, with ret bit present */
4692 case FF:
4693 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */
4694 /*FALLTHROUGH*/
4695 case FFC: /* case for vbit always = 0 */
4696 #ifdef DIS_TEXT
4697 x->d86_numopnds = 2;
4698 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN);
4699 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN);
4700 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0';
4701 #endif
4702 NOMEM;
4703 break;
4704
4705 /* AVX instructions */
4706 case VEX_MO:
4707 /* op(ModR/M.r/m) */
4708 x->d86_numopnds = 1;
4709 dtrace_get_modrm(x, &mode, ®, &r_m);
4710 #ifdef DIS_TEXT
4711 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))
4712 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN);
4713 #endif
4714 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4715 dtrace_get_operand(x, mode, r_m, wbit, 0);
4716 break;
4717 case VEX_RMrX:
4718 case FMA:
4719 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
4720 x->d86_numopnds = 3;
4721 dtrace_get_modrm(x, &mode, ®, &r_m);
4722 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4723
4724 /*
4725 * In classic Intel fashion, the opcodes for all of the FMA
4726 * instructions all have two possible mnemonics which vary by
4727 * one letter, which is selected based on the value of the wbit.
4728 * When wbit is one, they have the 'd' suffix and when 'wbit' is
4729 * 0, they have the 's' suffix. Otherwise, the FMA instructions
4730 * are all a standard VEX_RMrX.
4731 */
4732 #ifdef DIS_TEXT
4733 if (dp->it_adrmode == FMA) {
4734 size_t len = strlen(dp->it_name);
4735 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
4736 if (len + 1 < OPLEN) {
4737 (void) strncpy(x->d86_mnem + len,
4738 vex_W != 0 ? "d" : "s", OPLEN - len);
4739 }
4740 }
4741 #endif
4742
4743 if (mode != REG_ONLY) {
4744 if ((dp == &dis_opAVXF20F[0x10]) ||
4745 (dp == &dis_opAVXF30F[0x10])) {
4746 /* vmovsd <m64>, <xmm> */
4747 /* or vmovss <m64>, <xmm> */
4748 x->d86_numopnds = 2;
4749 goto L_VEX_MX;
4750 }
4751 }
4752
4753 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4754 /*
4755 * VEX prefix uses the 1's complement form to encode the
4756 * XMM/YMM regs
4757 */
4758 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4759
4760 if ((dp == &dis_opAVXF20F[0x2A]) ||
4761 (dp == &dis_opAVXF30F[0x2A])) {
4762 /*
4763 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
4764 * <xmm>, <xmm>
4765 */
4766 wbit = LONG_OPND;
4767 }
4768 #ifdef DIS_TEXT
4769 else if ((mode == REG_ONLY) &&
4770 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */
4771 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN);
4772 } else if ((mode == REG_ONLY) &&
4773 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */
4774 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN);
4775 }
4776 #endif
4777 dtrace_get_operand(x, mode, r_m, wbit, 0);
4778
4779 break;
4780
4781 case VEX_VRMrX:
4782 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */
4783 x->d86_numopnds = 3;
4784 dtrace_get_modrm(x, &mode, ®, &r_m);
4785 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4786
4787 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4788 /*
4789 * VEX prefix uses the 1's complement form to encode the
4790 * XMM/YMM regs
4791 */
4792 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0);
4793
4794 dtrace_get_operand(x, mode, r_m, wbit, 1);
4795 break;
4796
4797 case VEX_SbVM:
4798 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */
4799 x->d86_numopnds = 3;
4800 x->d86_vsib = 1;
4801
4802 /*
4803 * All instructions that use VSIB are currently a mess. See the
4804 * comment around the dis_gather_regs_t structure definition.
4805 */
4806
4807 vreg = &dis_vgather[opcode2][vex_W][vex_L];
4808
4809 #ifdef DIS_TEXT
4810 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
4811 (void) strlcat(x->d86_mnem + strlen(dp->it_name),
4812 vreg->dgr_suffix, OPLEN - strlen(dp->it_name));
4813 #endif
4814
4815 dtrace_get_modrm(x, &mode, ®, &r_m);
4816 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4817
4818 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2);
4819 /*
4820 * VEX prefix uses the 1's complement form to encode the
4821 * XMM/YMM regs
4822 */
4823 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0,
4824 0);
4825 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1);
4826 break;
4827
4828 case VEX_RRX:
4829 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
4830 x->d86_numopnds = 3;
4831
4832 dtrace_get_modrm(x, &mode, ®, &r_m);
4833 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4834
4835 if (mode != REG_ONLY) {
4836 if ((dp == &dis_opAVXF20F[0x11]) ||
4837 (dp == &dis_opAVXF30F[0x11])) {
4838 /* vmovsd <xmm>, <m64> */
4839 /* or vmovss <xmm>, <m64> */
4840 x->d86_numopnds = 2;
4841 goto L_VEX_RM;
4842 }
4843 }
4844
4845 dtrace_get_operand(x, mode, r_m, wbit, 2);
4846 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4847 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
4848 break;
4849
4850 case VEX_RMRX:
4851 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
4852 x->d86_numopnds = 4;
4853
4854 dtrace_get_modrm(x, &mode, ®, &r_m);
4855 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4856 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
4857 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
4858 if (dp == &dis_opAVX660F3A[0x18]) {
4859 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
4860 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1);
4861 } else if ((dp == &dis_opAVX660F3A[0x20]) ||
4862 (dp == & dis_opAVX660F[0xC4])) {
4863 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
4864 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
4865 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4866 } else if (dp == &dis_opAVX660F3A[0x22]) {
4867 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
4868 #ifdef DIS_TEXT
4869 if (vex_W)
4870 x->d86_mnem[6] = 'q';
4871 #endif
4872 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4873 } else {
4874 dtrace_get_operand(x, mode, r_m, wbit, 1);
4875 }
4876
4877 /* one byte immediate number */
4878 dtrace_imm_opnd(x, wbit, 1, 0);
4879
4880 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
4881 if ((dp == &dis_opAVX660F3A[0x4A]) ||
4882 (dp == &dis_opAVX660F3A[0x4B]) ||
4883 (dp == &dis_opAVX660F3A[0x4C])) {
4884 #ifdef DIS_TEXT
4885 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4;
4886 #endif
4887 x->d86_opnd[0].d86_mode = MODE_NONE;
4888 #ifdef DIS_TEXT
4889 if (vex_L)
4890 (void) strncpy(x->d86_opnd[0].d86_opnd,
4891 dis_YMMREG[regnum], OPLEN);
4892 else
4893 (void) strncpy(x->d86_opnd[0].d86_opnd,
4894 dis_XMMREG[regnum], OPLEN);
4895 #endif
4896 }
4897 break;
4898
4899 case VEX_MX:
4900 /* ModR/M.reg := op(ModR/M.rm) */
4901 x->d86_numopnds = 2;
4902
4903 dtrace_get_modrm(x, &mode, ®, &r_m);
4904 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4905 L_VEX_MX:
4906
4907 if ((dp == &dis_opAVXF20F[0xE6]) ||
4908 (dp == &dis_opAVX660F[0x5A]) ||
4909 (dp == &dis_opAVX660F[0xE6])) {
4910 /* vcvtpd2dq <ymm>, <xmm> */
4911 /* or vcvtpd2ps <ymm>, <xmm> */
4912 /* or vcvttpd2dq <ymm>, <xmm> */
4913 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
4914 dtrace_get_operand(x, mode, r_m, wbit, 0);
4915 } else if ((dp == &dis_opAVXF30F[0xE6]) ||
4916 (dp == &dis_opAVX0F[0x5][0xA]) ||
4917 (dp == &dis_opAVX660F38[0x13]) ||
4918 (dp == &dis_opAVX660F38[0x18]) ||
4919 (dp == &dis_opAVX660F38[0x19]) ||
4920 (dp == &dis_opAVX660F38[0x58]) ||
4921 (dp == &dis_opAVX660F38[0x78]) ||
4922 (dp == &dis_opAVX660F38[0x79]) ||
4923 (dp == &dis_opAVX660F38[0x59])) {
4924 /* vcvtdq2pd <xmm>, <ymm> */
4925 /* or vcvtps2pd <xmm>, <ymm> */
4926 /* or vcvtph2ps <xmm>, <ymm> */
4927 /* or vbroadcasts* <xmm>, <ymm> */
4928 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4929 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
4930 } else if (dp == &dis_opAVX660F[0x6E]) {
4931 /* vmovd/q <reg/mem 32/64>, <xmm> */
4932 #ifdef DIS_TEXT
4933 if (vex_W)
4934 x->d86_mnem[4] = 'q';
4935 #endif
4936 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4937 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4938 } else {
4939 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
4940 dtrace_get_operand(x, mode, r_m, wbit, 0);
4941 }
4942
4943 break;
4944
4945 case VEX_MXI:
4946 /* ModR/M.reg := op(ModR/M.rm, imm8) */
4947 x->d86_numopnds = 3;
4948
4949 dtrace_get_modrm(x, &mode, ®, &r_m);
4950 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4951
4952 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4953 dtrace_get_operand(x, mode, r_m, wbit, 1);
4954
4955 /* one byte immediate number */
4956 dtrace_imm_opnd(x, wbit, 1, 0);
4957 break;
4958
4959 case VEX_XXI:
4960 /* VEX.vvvv := op(ModR/M.rm, imm8) */
4961 x->d86_numopnds = 3;
4962
4963 dtrace_get_modrm(x, &mode, ®, &r_m);
4964 #ifdef DIS_TEXT
4965 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],
4966 OPLEN);
4967 #endif
4968 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4969
4970 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
4971 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1);
4972
4973 /* one byte immediate number */
4974 dtrace_imm_opnd(x, wbit, 1, 0);
4975 break;
4976
4977 case VEX_MR:
4978 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
4979 if (dp == &dis_opAVX660F[0xC5]) {
4980 /* vpextrw <imm8>, <xmm>, <reg> */
4981 x->d86_numopnds = 2;
4982 vbit = 2;
4983 } else {
4984 x->d86_numopnds = 2;
4985 vbit = 1;
4986 }
4987
4988 dtrace_get_modrm(x, &mode, ®, &r_m);
4989 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
4990 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);
4991 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1);
4992
4993 if (vbit == 2)
4994 dtrace_imm_opnd(x, wbit, 1, 0);
4995
4996 break;
4997
4998 case VEX_RRI:
4999 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
5000 x->d86_numopnds = 2;
5001
5002 dtrace_get_modrm(x, &mode, ®, &r_m);
5003 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5004 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5005 dtrace_get_operand(x, mode, r_m, wbit, 0);
5006 break;
5007
5008 case VEX_RX:
5009 /* ModR/M.rm := op(ModR/M.reg) */
5010 /* vextractf128 || vcvtps2ph */
5011 if (dp == &dis_opAVX660F3A[0x19] ||
5012 dp == &dis_opAVX660F3A[0x1d]) {
5013 x->d86_numopnds = 3;
5014
5015 dtrace_get_modrm(x, &mode, ®, &r_m);
5016 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5017
5018 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
5019 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5020
5021 /* one byte immediate number */
5022 dtrace_imm_opnd(x, wbit, 1, 0);
5023 break;
5024 }
5025
5026 x->d86_numopnds = 2;
5027
5028 dtrace_get_modrm(x, &mode, ®, &r_m);
5029 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5030 dtrace_get_operand(x, mode, r_m, wbit, 1);
5031 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5032 break;
5033
5034 case VEX_RR:
5035 /* ModR/M.rm := op(ModR/M.reg) */
5036 x->d86_numopnds = 2;
5037
5038 dtrace_get_modrm(x, &mode, ®, &r_m);
5039 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5040
5041 if (dp == &dis_opAVX660F[0x7E]) {
5042 /* vmovd/q <reg/mem 32/64>, <xmm> */
5043 #ifdef DIS_TEXT
5044 if (vex_W)
5045 x->d86_mnem[4] = 'q';
5046 #endif
5047 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
5048 } else
5049 dtrace_get_operand(x, mode, r_m, wbit, 1);
5050
5051 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5052 break;
5053
5054 case VEX_RRi:
5055 /* ModR/M.rm := op(ModR/M.reg, imm) */
5056 x->d86_numopnds = 3;
5057
5058 dtrace_get_modrm(x, &mode, ®, &r_m);
5059 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5060
5061 #ifdef DIS_TEXT
5062 if (dp == &dis_opAVX660F3A[0x16]) {
5063 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
5064 if (vex_W)
5065 x->d86_mnem[6] = 'q';
5066 }
5067 #endif
5068 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
5069 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5070
5071 /* one byte immediate number */
5072 dtrace_imm_opnd(x, wbit, 1, 0);
5073 break;
5074 case VEX_RIM:
5075 /* ModR/M.rm := op(ModR/M.reg, imm) */
5076 x->d86_numopnds = 3;
5077
5078 dtrace_get_modrm(x, &mode, ®, &r_m);
5079 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5080
5081 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
5082 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5083 /* one byte immediate number */
5084 dtrace_imm_opnd(x, wbit, 1, 0);
5085 break;
5086
5087 case VEX_RM:
5088 /* ModR/M.rm := op(ModR/M.reg) */
5089 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */
5090 x->d86_numopnds = 3;
5091
5092 dtrace_get_modrm(x, &mode, ®, &r_m);
5093 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5094
5095 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
5096 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5097 /* one byte immediate number */
5098 dtrace_imm_opnd(x, wbit, 1, 0);
5099 break;
5100 }
5101 x->d86_numopnds = 2;
5102
5103 dtrace_get_modrm(x, &mode, ®, &r_m);
5104 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5105 L_VEX_RM:
5106 vbit = 1;
5107 dtrace_get_operand(x, mode, r_m, wbit, vbit);
5108 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);
5109
5110 break;
5111
5112 case VEX_RRM:
5113 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
5114 x->d86_numopnds = 3;
5115
5116 dtrace_get_modrm(x, &mode, ®, &r_m);
5117 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5118 dtrace_get_operand(x, mode, r_m, wbit, 2);
5119 /* VEX use the 1's complement form encode the XMM/YMM regs */
5120 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5121 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5122 break;
5123
5124 case VEX_RMX:
5125 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
5126 x->d86_numopnds = 3;
5127
5128 dtrace_get_modrm(x, &mode, ®, &r_m);
5129 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5130 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
5131 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5132 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0);
5133 break;
5134
5135 case VEX_NONE:
5136 #ifdef DIS_TEXT
5137 if (vex_L)
5138 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN);
5139 #endif
5140 break;
5141 case BLS: {
5142
5143 /*
5144 * The BLS instructions are VEX instructions that are based on
5145 * VEX.0F38.F3; however, they are considered special group 17
5146 * and like everything else, they use the bits in 3-5 of the
5147 * MOD R/M to determine the sub instruction. Unlike many others
5148 * like the VMX instructions, these are valid both for memory
5149 * and register forms.
5150 */
5151
5152 dtrace_get_modrm(x, &mode, ®, &r_m);
5153 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m);
5154
5155 switch (reg) {
5156 case 1:
5157 #ifdef DIS_TEXT
5158 blsinstr = "blsr";
5159 #endif
5160 break;
5161 case 2:
5162 #ifdef DIS_TEXT
5163 blsinstr = "blsmsk";
5164 #endif
5165 break;
5166 case 3:
5167 #ifdef DIS_TEXT
5168 blsinstr = "blsi";
5169 #endif
5170 break;
5171 default:
5172 goto error;
5173 }
5174
5175 x->d86_numopnds = 2;
5176 #ifdef DIS_TEXT
5177 (void) strncpy(x->d86_mnem, blsinstr, OPLEN);
5178 #endif
5179 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5180 dtrace_get_operand(x, mode, r_m, wbit, 0);
5181 break;
5182 }
5183 /* an invalid op code */
5184 case AM:
5185 case DM:
5186 case OVERRIDE:
5187 case PREFIX:
5188 case UNKNOWN:
5189 NOMEM;
5190 default:
5191 goto error;
5192 } /* end switch */
5193 if (x->d86_error)
5194 goto error;
5195
5196 done:
5197 #ifdef DIS_MEM
5198 /*
5199 * compute the size of any memory accessed by the instruction
5200 */
5201 if (x->d86_memsize != 0) {
5202 return (0);
5203 } else if (dp->it_stackop) {
5204 switch (opnd_size) {
5205 case SIZE16:
5206 x->d86_memsize = 2;
5207 break;
5208 case SIZE32:
5209 x->d86_memsize = 4;
5210 break;
5211 case SIZE64:
5212 x->d86_memsize = 8;
5213 break;
5214 }
5215 } else if (nomem || mode == REG_ONLY) {
5216 x->d86_memsize = 0;
5217
5218 } else if (dp->it_size != 0) {
5219 /*
5220 * In 64 bit mode descriptor table entries
5221 * go up to 10 bytes and popf/pushf are always 8 bytes
5222 */
5223 if (x->d86_mode == SIZE64 && dp->it_size == 6)
5224 x->d86_memsize = 10;
5225 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 &&
5226 (opcode2 == 0xc || opcode2 == 0xd))
5227 x->d86_memsize = 8;
5228 else
5229 x->d86_memsize = dp->it_size;
5230
5231 } else if (wbit == 0) {
5232 x->d86_memsize = 1;
5233
5234 } else if (wbit == LONG_OPND) {
5235 if (opnd_size == SIZE64)
5236 x->d86_memsize = 8;
5237 else if (opnd_size == SIZE32)
5238 x->d86_memsize = 4;
5239 else
5240 x->d86_memsize = 2;
5241
5242 } else if (wbit == SEG_OPND) {
5243 x->d86_memsize = 4;
5244
5245 } else {
5246 x->d86_memsize = 8;
5247 }
5248 #endif
5249 return (0);
5250
5251 error:
5252 #ifdef DIS_TEXT
5253 (void) strlcat(x->d86_mnem, "undef", OPLEN);
5254 #endif
5255 return (1);
5256 }
5257
5258 #ifdef DIS_TEXT
5259
5260 /*
5261 * Some instructions should have immediate operands printed
5262 * as unsigned integers. We compare against this table.
5263 */
5264 static char *unsigned_ops[] = {
5265 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp",
5266 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl",
5267 0
5268 };
5269
5270
5271 static int
isunsigned_op(char * opcode)5272 isunsigned_op(char *opcode)
5273 {
5274 char *where;
5275 int i;
5276 int is_unsigned = 0;
5277
5278 /*
5279 * Work back to start of last mnemonic, since we may have
5280 * prefixes on some opcodes.
5281 */
5282 where = opcode + strlen(opcode) - 1;
5283 while (where > opcode && *where != ' ')
5284 --where;
5285 if (*where == ' ')
5286 ++where;
5287
5288 for (i = 0; unsigned_ops[i]; ++i) {
5289 if (strncmp(where, unsigned_ops[i],
5290 strlen(unsigned_ops[i])))
5291 continue;
5292 is_unsigned = 1;
5293 break;
5294 }
5295 return (is_unsigned);
5296 }
5297
5298 /*
5299 * Print a numeric immediate into end of buf, maximum length buflen.
5300 * The immediate may be an address or a displacement. Mask is set
5301 * for address size. If the immediate is a "small negative", or
5302 * if it's a negative displacement of any magnitude, print as -<absval>.
5303 * Respect the "octal" flag. "Small negative" is defined as "in the
5304 * interval [NEG_LIMIT, 0)".
5305 *
5306 * Also, "isunsigned_op()" instructions never print negatives.
5307 *
5308 * Return whether we decided to print a negative value or not.
5309 */
5310
5311 #define NEG_LIMIT -255
5312 enum {IMM, DISP};
5313 enum {POS, TRY_NEG};
5314
5315 static int
print_imm(dis86_t * dis,uint64_t usv,uint64_t mask,char * buf,size_t buflen,int disp,int try_neg)5316 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf,
5317 size_t buflen, int disp, int try_neg)
5318 {
5319 int curlen;
5320 int64_t sv = (int64_t)usv;
5321 int octal = dis->d86_flags & DIS_F_OCTAL;
5322
5323 curlen = strlen(buf);
5324
5325 if (try_neg == TRY_NEG && sv < 0 &&
5326 (disp || sv >= NEG_LIMIT) &&
5327 !isunsigned_op(dis->d86_mnem)) {
5328 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5329 octal ? "-0%llo" : "-0x%llx", (-sv) & mask);
5330 return (1);
5331 } else {
5332 if (disp == DISP)
5333 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5334 octal ? "+0%llo" : "+0x%llx", usv & mask);
5335 else
5336 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5337 octal ? "0%llo" : "0x%llx", usv & mask);
5338 return (0);
5339
5340 }
5341 }
5342
5343
5344 static int
log2(int size)5345 log2(int size)
5346 {
5347 switch (size) {
5348 case 1: return (0);
5349 case 2: return (1);
5350 case 4: return (2);
5351 case 8: return (3);
5352 }
5353 return (0);
5354 }
5355
5356 /* ARGSUSED */
5357 void
dtrace_disx86_str(dis86_t * dis,uint_t mode,uint64_t pc,char * buf,size_t buflen)5358 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf,
5359 size_t buflen)
5360 {
5361 uint64_t reltgt = 0;
5362 uint64_t tgt = 0;
5363 int curlen;
5364 int (*lookup)(void *, uint64_t, char *, size_t);
5365 int i;
5366 int64_t sv;
5367 uint64_t usv, mask, save_mask, save_usv;
5368 static uint64_t masks[] =
5369 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL};
5370 save_usv = 0;
5371
5372 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem);
5373
5374 /*
5375 * For PC-relative jumps, the pc is really the next pc after executing
5376 * this instruction, so increment it appropriately.
5377 */
5378 pc += dis->d86_len;
5379
5380 for (i = 0; i < dis->d86_numopnds; i++) {
5381 d86opnd_t *op = &dis->d86_opnd[i];
5382
5383 if (i != 0)
5384 (void) strlcat(buf, ",", buflen);
5385
5386 (void) strlcat(buf, op->d86_prefix, buflen);
5387
5388 /*
5389 * sv is for the signed, possibly-truncated immediate or
5390 * displacement; usv retains the original size and
5391 * unsignedness for symbol lookup.
5392 */
5393
5394 sv = usv = op->d86_value;
5395
5396 /*
5397 * About masks: for immediates that represent
5398 * addresses, the appropriate display size is
5399 * the effective address size of the instruction.
5400 * This includes MODE_OFFSET, MODE_IPREL, and
5401 * MODE_RIPREL. Immediates that are simply
5402 * immediate values should display in the operand's
5403 * size, however, since they don't represent addresses.
5404 */
5405
5406 /* d86_addr_size is SIZEnn, which is log2(real size) */
5407 mask = masks[dis->d86_addr_size];
5408
5409 /* d86_value_size and d86_imm_bytes are in bytes */
5410 if (op->d86_mode == MODE_SIGNED ||
5411 op->d86_mode == MODE_IMPLIED)
5412 mask = masks[log2(op->d86_value_size)];
5413
5414 switch (op->d86_mode) {
5415
5416 case MODE_NONE:
5417
5418 (void) strlcat(buf, op->d86_opnd, buflen);
5419 break;
5420
5421 case MODE_SIGNED:
5422 case MODE_IMPLIED:
5423 case MODE_OFFSET:
5424
5425 tgt = usv;
5426
5427 if (dis->d86_seg_prefix)
5428 (void) strlcat(buf, dis->d86_seg_prefix,
5429 buflen);
5430
5431 if (op->d86_mode == MODE_SIGNED ||
5432 op->d86_mode == MODE_IMPLIED) {
5433 (void) strlcat(buf, "$", buflen);
5434 }
5435
5436 if (print_imm(dis, usv, mask, buf, buflen,
5437 IMM, TRY_NEG) &&
5438 (op->d86_mode == MODE_SIGNED ||
5439 op->d86_mode == MODE_IMPLIED)) {
5440
5441 /*
5442 * We printed a negative value for an
5443 * immediate that wasn't a
5444 * displacement. Note that fact so we can
5445 * print the positive value as an
5446 * annotation.
5447 */
5448
5449 save_usv = usv;
5450 save_mask = mask;
5451 }
5452 (void) strlcat(buf, op->d86_opnd, buflen);
5453
5454 break;
5455
5456 case MODE_IPREL:
5457 case MODE_RIPREL:
5458
5459 reltgt = pc + sv;
5460
5461 switch (mode) {
5462 case SIZE16:
5463 reltgt = (uint16_t)reltgt;
5464 break;
5465 case SIZE32:
5466 reltgt = (uint32_t)reltgt;
5467 break;
5468 }
5469
5470 (void) print_imm(dis, usv, mask, buf, buflen,
5471 DISP, TRY_NEG);
5472
5473 if (op->d86_mode == MODE_RIPREL)
5474 (void) strlcat(buf, "(%rip)", buflen);
5475 break;
5476 }
5477 }
5478
5479 /*
5480 * The symbol lookups may result in false positives,
5481 * particularly on object files, where small numbers may match
5482 * the 0-relative non-relocated addresses of symbols.
5483 */
5484
5485 lookup = dis->d86_sym_lookup;
5486 if (tgt != 0) {
5487 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 &&
5488 lookup(dis->d86_data, tgt, NULL, 0) == 0) {
5489 (void) strlcat(buf, "\t<", buflen);
5490 curlen = strlen(buf);
5491 lookup(dis->d86_data, tgt, buf + curlen,
5492 buflen - curlen);
5493 (void) strlcat(buf, ">", buflen);
5494 }
5495
5496 /*
5497 * If we printed a negative immediate above, print the
5498 * positive in case our heuristic was unhelpful
5499 */
5500 if (save_usv) {
5501 (void) strlcat(buf, "\t<", buflen);
5502 (void) print_imm(dis, save_usv, save_mask, buf, buflen,
5503 IMM, POS);
5504 (void) strlcat(buf, ">", buflen);
5505 }
5506 }
5507
5508 if (reltgt != 0) {
5509 /* Print symbol or effective address for reltgt */
5510
5511 (void) strlcat(buf, "\t<", buflen);
5512 curlen = strlen(buf);
5513 lookup(dis->d86_data, reltgt, buf + curlen,
5514 buflen - curlen);
5515 (void) strlcat(buf, ">", buflen);
5516 }
5517 }
5518
5519 #endif /* DIS_TEXT */
5520