1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Yunfei Dong <yunfei.dong@mediatek.com>
5 */
6
7 #ifndef _MTK_VCODEC_DEC_DRV_H_
8 #define _MTK_VCODEC_DEC_DRV_H_
9
10 #include "../common/mtk_vcodec_cmn_drv.h"
11 #include "../common/mtk_vcodec_dbgfs.h"
12 #include "../common/mtk_vcodec_fw_priv.h"
13 #include "../common/mtk_vcodec_util.h"
14 #include "vdec_msg_queue.h"
15
16 #define MTK_VCODEC_DEC_NAME "mtk-vcodec-dec"
17
18 #define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >= MTK_VDEC_LAT_SINGLE_CORE)
19 #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_RACING)
20
21 enum mtk_vcodec_dec_chip_name {
22 MTK_VDEC_INVAL = 0,
23 MTK_VDEC_MT8173 = 8173,
24 MTK_VDEC_MT8183 = 8183,
25 MTK_VDEC_MT8186 = 8186,
26 MTK_VDEC_MT8188 = 8188,
27 MTK_VDEC_MT8192 = 8192,
28 MTK_VDEC_MT8195 = 8195,
29 };
30
31 /*
32 * enum mtk_vdec_format_types - Structure used to get supported
33 * format types according to decoder capability
34 */
35 enum mtk_vdec_format_types {
36 MTK_VDEC_FORMAT_MM21 = 0x20,
37 MTK_VDEC_FORMAT_MT21C = 0x40,
38 MTK_VDEC_FORMAT_H264_SLICE = 0x100,
39 MTK_VDEC_FORMAT_VP8_FRAME = 0x200,
40 MTK_VDEC_FORMAT_VP9_FRAME = 0x400,
41 MTK_VDEC_FORMAT_AV1_FRAME = 0x800,
42 MTK_VDEC_FORMAT_HEVC_FRAME = 0x1000,
43 MTK_VCODEC_INNER_RACING = 0x20000,
44 MTK_VDEC_IS_SUPPORT_10BIT = 0x40000,
45 };
46
47 /*
48 * enum mtk_vdec_hw_count - Supported hardware count
49 */
50 enum mtk_vdec_hw_count {
51 MTK_VDEC_NO_HW = 0,
52 MTK_VDEC_ONE_CORE,
53 MTK_VDEC_ONE_LAT_ONE_CORE,
54 MTK_VDEC_MAX_HW_COUNT,
55 };
56
57 /*
58 * enum mtk_vdec_hw_arch - Used to separate different hardware architecture
59 */
60 enum mtk_vdec_hw_arch {
61 MTK_VDEC_PURE_SINGLE_CORE,
62 MTK_VDEC_LAT_SINGLE_CORE,
63 };
64
65 /**
66 * struct vdec_pic_info - picture size information
67 * @pic_w: picture width
68 * @pic_h: picture height
69 * @buf_w: picture buffer width (64 aligned up from pic_w)
70 * @buf_h: picture buffer height (64 aligned up from pic_h)
71 * @fb_sz: bitstream size of each plane
72 * E.g. suppose picture size is 176x144,
73 * buffer size will be aligned to 176x160.
74 * @cap_fourcc: fourcc number(may change on a resolution change)
75 * @reserved: align struct to 64-bit in order to adjust 32-bit and 64-bit os.
76 */
77 struct vdec_pic_info {
78 unsigned int pic_w;
79 unsigned int pic_h;
80 unsigned int buf_w;
81 unsigned int buf_h;
82 unsigned int fb_sz[VIDEO_MAX_PLANES];
83 unsigned int cap_fourcc;
84 unsigned int reserved;
85 };
86
87 /**
88 * struct mtk_vcodec_dec_pdata - compatible data for each IC
89 * @init_vdec_params: init vdec params
90 * @ctrls_setup: init vcodec dec ctrls
91 * @worker: worker to start a decode job
92 * @flush_decoder: function that flushes the decoder
93 * @get_cap_buffer: get capture buffer from capture queue
94 * @cap_to_disp: put capture buffer to disp list for lat and core arch
95 * @vdec_vb2_ops: struct vb2_ops
96 *
97 * @vdec_formats: supported video decoder formats
98 * @num_formats: count of video decoder formats
99 * @default_out_fmt: default output buffer format
100 * @default_cap_fmt: default capture buffer format
101 *
102 * @hw_arch: hardware arch is used to separate pure_sin_core and lat_sin_core
103 *
104 * @is_subdev_supported: whether support parent-node architecture(subdev)
105 * @uses_stateless_api: whether the decoder uses the stateless API with requests
106 */
107 struct mtk_vcodec_dec_pdata {
108 void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx);
109 int (*ctrls_setup)(struct mtk_vcodec_dec_ctx *ctx);
110 void (*worker)(struct work_struct *work);
111 int (*flush_decoder)(struct mtk_vcodec_dec_ctx *ctx);
112 struct vdec_fb *(*get_cap_buffer)(struct mtk_vcodec_dec_ctx *ctx);
113 void (*cap_to_disp)(struct mtk_vcodec_dec_ctx *ctx, int error,
114 struct media_request *src_buf_req);
115
116 const struct vb2_ops *vdec_vb2_ops;
117
118 const struct mtk_video_fmt *vdec_formats;
119 const int *num_formats;
120 const struct mtk_video_fmt *default_out_fmt;
121 const struct mtk_video_fmt *default_cap_fmt;
122
123 enum mtk_vdec_hw_arch hw_arch;
124
125 bool is_subdev_supported;
126 bool uses_stateless_api;
127 };
128
129 /**
130 * struct mtk_vcodec_dec_ctx - Context (instance) private data.
131 *
132 * @type: type of decoder instance
133 * @dev: pointer to the mtk_vcodec_dec_dev of the device
134 * @list: link to ctx_list of mtk_vcodec_dec_dev
135 *
136 * @fh: struct v4l2_fh
137 * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
138 * @q_data: store information of input and output queue of the context
139 * @id: index of the context that this structure describes
140 * @state: state of the context
141 *
142 * @dec_if: hooked decoder driver interface
143 * @drv_handle: driver handle for specific decode/encode instance
144 *
145 * @picinfo: store picture info after header parsing
146 * @dpb_size: store dpb count after header parsing
147 *
148 * @int_cond: variable used by the waitqueue
149 * @int_type: type of the last interrupt
150 * @queue: waitqueue that can be used to wait for this context to finish
151 * @irq_status: irq status
152 *
153 * @ctrl_hdl: handler for v4l2 framework
154 * @decode_work: worker for the decoding
155 * @last_decoded_picinfo: pic information get from latest decode
156 * @empty_flush_buf: a fake size-0 capture buffer that indicates flush. Used
157 * for stateful decoder.
158 * @is_flushing: set to true if flushing is in progress.
159 *
160 * @current_codec: current set input codec, in V4L2 pixel format
161 * @capture_fourcc: capture queue type in V4L2 pixel format
162 *
163 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
164 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
165 * @quantization: enum v4l2_quantization, colorspace quantization
166 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
167 *
168 * @decoded_frame_cnt: number of decoded frames
169 * @lock: protect variables accessed by V4L2 threads and worker thread such as
170 * mtk_video_dec_buf.
171 * @hw_id: hardware index used to identify different hardware.
172 *
173 * @msg_queue: msg queue used to store lat buffer information.
174 * @vpu_inst: vpu instance pointer.
175 *
176 * @is_10bit_bitstream: set to true if it's 10bit bitstream
177 */
178 struct mtk_vcodec_dec_ctx {
179 enum mtk_instance_type type;
180 struct mtk_vcodec_dec_dev *dev;
181 struct list_head list;
182
183 struct v4l2_fh fh;
184 struct v4l2_m2m_ctx *m2m_ctx;
185 struct mtk_q_data q_data[2];
186 int id;
187 enum mtk_instance_state state;
188
189 const struct vdec_common_if *dec_if;
190 void *drv_handle;
191
192 struct vdec_pic_info picinfo;
193 int dpb_size;
194
195 int int_cond[MTK_VDEC_HW_MAX];
196 int int_type[MTK_VDEC_HW_MAX];
197 wait_queue_head_t queue[MTK_VDEC_HW_MAX];
198 unsigned int irq_status;
199
200 struct v4l2_ctrl_handler ctrl_hdl;
201 struct work_struct decode_work;
202 struct vdec_pic_info last_decoded_picinfo;
203 struct v4l2_m2m_buffer empty_flush_buf;
204 bool is_flushing;
205
206 u32 current_codec;
207 u32 capture_fourcc;
208
209 enum v4l2_colorspace colorspace;
210 enum v4l2_ycbcr_encoding ycbcr_enc;
211 enum v4l2_quantization quantization;
212 enum v4l2_xfer_func xfer_func;
213
214 int decoded_frame_cnt;
215 struct mutex lock;
216 int hw_id;
217
218 struct vdec_msg_queue msg_queue;
219 void *vpu_inst;
220
221 bool is_10bit_bitstream;
222 };
223
224 /**
225 * struct mtk_vcodec_dec_dev - driver data
226 * @v4l2_dev: V4L2 device to register video devices for.
227 * @vfd_dec: Video device for decoder
228 * @mdev_dec: Media device for decoder
229 *
230 * @m2m_dev_dec: m2m device for decoder
231 * @plat_dev: platform device
232 * @ctx_list: list of struct mtk_vcodec_ctx
233 * @curr_ctx: The context that is waiting for codec hardware
234 *
235 * @reg_base: Mapped address of MTK Vcodec registers.
236 * @vdec_pdata: decoder IC-specific data
237 * @vdecsys_regmap: VDEC_SYS register space passed through syscon
238 *
239 * @fw_handler: used to communicate with the firmware.
240 * @id_counter: used to identify current opened instance
241 *
242 * @dec_mutex: decoder hardware lock
243 * @dev_mutex: video_device lock
244 * @dev_ctx_lock: the lock of context list
245 * @decode_workqueue: decode work queue
246 *
247 * @irqlock: protect data access by irq handler and work thread
248 * @dec_irq: decoder irq resource
249 *
250 * @pm: power management control
251 * @dec_capability: used to identify decode capability, ex: 4k
252 *
253 * @core_workqueue: queue used for core hardware decode
254 *
255 * @subdev_dev: subdev hardware device
256 * @subdev_prob_done: check whether all used hw device is prob done
257 * @subdev_bitmap: used to record hardware is ready or not
258 *
259 * @dec_active_cnt: used to mark whether need to record register value
260 * @vdec_racing_info: record register value
261 * @dec_racing_info_mutex: mutex lock used for inner racing mode
262 * @dbgfs: debug log related information
263 *
264 * @chip_name: used to distinguish platforms and select the correct codec configuration values
265 */
266 struct mtk_vcodec_dec_dev {
267 struct v4l2_device v4l2_dev;
268 struct video_device *vfd_dec;
269 struct media_device mdev_dec;
270
271 struct v4l2_m2m_dev *m2m_dev_dec;
272 struct platform_device *plat_dev;
273 struct list_head ctx_list;
274 struct mtk_vcodec_dec_ctx *curr_ctx;
275
276 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
277 const struct mtk_vcodec_dec_pdata *vdec_pdata;
278 struct regmap *vdecsys_regmap;
279
280 struct mtk_vcodec_fw *fw_handler;
281 u64 id_counter;
282
283 /* decoder hardware mutex lock */
284 struct mutex dec_mutex[MTK_VDEC_HW_MAX];
285 struct mutex dev_mutex;
286 struct mutex dev_ctx_lock;
287 struct workqueue_struct *decode_workqueue;
288
289 spinlock_t irqlock;
290 int dec_irq;
291
292 struct mtk_vcodec_pm pm;
293 unsigned int dec_capability;
294
295 struct workqueue_struct *core_workqueue;
296
297 void *subdev_dev[MTK_VDEC_HW_MAX];
298 int (*subdev_prob_done)(struct mtk_vcodec_dec_dev *vdec_dev);
299 DECLARE_BITMAP(subdev_bitmap, MTK_VDEC_HW_MAX);
300
301 atomic_t dec_active_cnt;
302 u32 vdec_racing_info[132];
303 /* Protects access to vdec_racing_info data */
304 struct mutex dec_racing_info_mutex;
305 struct mtk_vcodec_dbgfs dbgfs;
306
307 enum mtk_vcodec_dec_chip_name chip_name;
308 };
309
fh_to_dec_ctx(struct v4l2_fh * fh)310 static inline struct mtk_vcodec_dec_ctx *fh_to_dec_ctx(struct v4l2_fh *fh)
311 {
312 return container_of(fh, struct mtk_vcodec_dec_ctx, fh);
313 }
314
ctrl_to_dec_ctx(struct v4l2_ctrl * ctrl)315 static inline struct mtk_vcodec_dec_ctx *ctrl_to_dec_ctx(struct v4l2_ctrl *ctrl)
316 {
317 return container_of(ctrl->handler, struct mtk_vcodec_dec_ctx, ctrl_hdl);
318 }
319
320 /* Wake up context wait_queue */
321 static inline void
wake_up_dec_ctx(struct mtk_vcodec_dec_ctx * ctx,unsigned int reason,unsigned int hw_id)322 wake_up_dec_ctx(struct mtk_vcodec_dec_ctx *ctx, unsigned int reason, unsigned int hw_id)
323 {
324 ctx->int_cond[hw_id] = 1;
325 ctx->int_type[hw_id] = reason;
326 wake_up_interruptible(&ctx->queue[hw_id]);
327 }
328
329 #define mtk_vdec_err(ctx, fmt, args...) \
330 mtk_vcodec_err((ctx)->id, (ctx)->dev->plat_dev, fmt, ##args)
331
332 #define mtk_vdec_debug(ctx, fmt, args...) \
333 mtk_vcodec_debug((ctx)->id, (ctx)->dev->plat_dev, fmt, ##args)
334
335 #define mtk_v4l2_vdec_err(ctx, fmt, args...) mtk_v4l2_err((ctx)->dev->plat_dev, fmt, ##args)
336
337 #define mtk_v4l2_vdec_dbg(level, ctx, fmt, args...) \
338 mtk_v4l2_debug((ctx)->dev->plat_dev, level, fmt, ##args)
339
340 #endif /* _MTK_VCODEC_DEC_DRV_H_ */
341