1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Microsoft Corp. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _MANA_H 33 #define _MANA_H 34 35 #include <sys/types.h> 36 #include <sys/proc.h> 37 #include <sys/socket.h> 38 #include <sys/sysctl.h> 39 #include <sys/taskqueue.h> 40 #include <sys/counter.h> 41 42 #include <net/ethernet.h> 43 #include <net/if.h> 44 #include <net/if_media.h> 45 #include <netinet/tcp_lro.h> 46 47 #include "gdma.h" 48 #include "hw_channel.h" 49 50 51 /* Microsoft Azure Network Adapter (MANA)'s definitions 52 * 53 * Structures labeled with "HW DATA" are exchanged with the hardware. All of 54 * them are naturally aligned and hence don't need __packed. 55 */ 56 /* MANA protocol version */ 57 #define MANA_MAJOR_VERSION 0 58 #define MANA_MINOR_VERSION 1 59 #define MANA_MICRO_VERSION 1 60 61 #define DRV_MODULE_NAME "mana" 62 63 #ifndef DRV_MODULE_VERSION 64 #define DRV_MODULE_VERSION \ 65 __XSTRING(MANA_MAJOR_VERSION) "." \ 66 __XSTRING(MANA_MINOR_VERSION) "." \ 67 __XSTRING(MANA_MICRO_VERSION) 68 #endif 69 #define DEVICE_NAME "Microsoft Azure Network Adapter (MANA)" 70 #define DEVICE_DESC "MANA adapter" 71 72 /* 73 * Supported PCI vendor and devices IDs 74 */ 75 #ifndef PCI_VENDOR_ID_MICROSOFT 76 #define PCI_VENDOR_ID_MICROSOFT 0x1414 77 #endif 78 79 #define PCI_DEV_ID_MANA_VF 0x00ba 80 81 typedef struct _mana_vendor_id_t { 82 uint16_t vendor_id; 83 uint16_t device_id; 84 } mana_vendor_id_t; 85 86 typedef uint64_t mana_handle_t; 87 #define INVALID_MANA_HANDLE ((mana_handle_t)-1) 88 89 enum TRI_STATE { 90 TRI_STATE_UNKNOWN = -1, 91 TRI_STATE_FALSE = 0, 92 TRI_STATE_TRUE = 1 93 }; 94 95 /* Number of entries for hardware indirection table must be in power of 2 */ 96 #define MANA_INDIRECT_TABLE_SIZE 64 97 #define MANA_INDIRECT_TABLE_MASK (MANA_INDIRECT_TABLE_SIZE - 1) 98 99 /* The Toeplitz hash key's length in bytes: should be multiple of 8 */ 100 #define MANA_HASH_KEY_SIZE 40 101 102 #define COMP_ENTRY_SIZE 64 103 104 #define MIN_FRAME_SIZE 146 105 #define ADAPTER_MTU_SIZE 1500 106 #define DEFAULT_FRAME_SIZE (ADAPTER_MTU_SIZE + 14) 107 #define MAX_FRAME_SIZE 4096 108 109 /* Unit number of RX buffers. Must be power of two 110 * Higher number could fail at allocation. 111 */ 112 #define MAX_RX_BUFFERS_PER_QUEUE 8192 113 #define DEF_RX_BUFFERS_PER_QUEUE 1024 114 #define MIN_RX_BUFFERS_PER_QUEUE 128 115 116 /* Unit number of TX buffers. Must be power of two 117 * Higher number could fail at allocation. 118 * The max value is derived as the maximum 119 * allocatable pages supported on host per guest 120 * through testing. TX buffer size beyond this 121 * value is rejected by the hardware. 122 */ 123 #define MAX_SEND_BUFFERS_PER_QUEUE 16384 124 #define DEF_SEND_BUFFERS_PER_QUEUE 1024 125 #define MIN_SEND_BUFFERS_PER_QUEUE 128 126 127 #define EQ_SIZE (8 * PAGE_SIZE) 128 #define LOG2_EQ_THROTTLE 3 129 130 #define MAX_PORTS_IN_MANA_DEV 8 131 132 struct mana_send_buf_info { 133 struct mbuf *mbuf; 134 bus_dmamap_t dma_map; 135 136 /* Required to store the result of mana_gd_post_work_request. 137 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 138 * work queue when the WQE is consumed. 139 */ 140 struct gdma_posted_wqe_info wqe_inf; 141 }; 142 143 struct mana_stats { 144 counter_u64_t packets; /* rx, tx */ 145 counter_u64_t bytes; /* rx, tx */ 146 counter_u64_t stop; /* tx */ 147 counter_u64_t wakeup; /* tx */ 148 counter_u64_t collapse; /* tx */ 149 counter_u64_t collapse_err; /* tx */ 150 counter_u64_t dma_mapping_err; /* rx, tx */ 151 counter_u64_t mbuf_alloc_fail; /* rx */ 152 counter_u64_t partial_refill; /* rx */ 153 counter_u64_t alt_chg; /* tx */ 154 counter_u64_t alt_reset; /* tx */ 155 counter_u64_t cqe_err; /* tx */ 156 counter_u64_t cqe_unknown_type; /* tx */ 157 }; 158 159 struct mana_txq { 160 struct gdma_queue *gdma_sq; 161 162 union { 163 uint32_t gdma_txq_id; 164 struct { 165 uint32_t reserved1 :10; 166 uint32_t vsq_frame :14; 167 uint32_t reserved2 :8; 168 }; 169 }; 170 171 uint16_t vp_offset; 172 173 if_t ndev; 174 /* Store index to the array of tx_qp in port structure */ 175 int idx; 176 /* The alternative txq idx when this txq is under heavy load */ 177 int alt_txq_idx; 178 179 /* The mbufs are sent to the HW and we are waiting for the CQEs. */ 180 struct mana_send_buf_info *tx_buf_info; 181 uint16_t next_to_use; 182 uint16_t next_to_complete; 183 184 atomic_t pending_sends; 185 186 struct buf_ring *txq_br; 187 struct mtx txq_mtx; 188 char txq_mtx_name[16]; 189 190 uint64_t tso_pkts; 191 uint64_t tso_bytes; 192 193 struct task enqueue_task; 194 struct taskqueue *enqueue_tq; 195 196 struct mana_stats stats; 197 }; 198 199 200 /* 201 * Max WQE size is 512B. The first 8B is for GDMA Out of Band (OOB), 202 * next is the Client OOB can be either 8B or 24B. Thus, the max 203 * space for SGL entries in a singel WQE is 512 - 8 - 8 = 496B. Since each 204 * SGL is 16B in size, the max number of SGLs in a WQE is 496/16 = 31. 205 * Save one for emergency use, set the MAX_MBUF_FRAGS allowed to 30. 206 */ 207 #define MAX_MBUF_FRAGS 30 208 #define MANA_TSO_MAXSEG_SZ PAGE_SIZE 209 #define MANA_TSO_MAX_SZ IP_MAXPACKET 210 211 /* mbuf data and frags dma mappings */ 212 struct mana_mbuf_head { 213 bus_addr_t dma_handle[MAX_MBUF_FRAGS + 1]; 214 215 uint32_t size[MAX_MBUF_FRAGS + 1]; 216 }; 217 218 #define MANA_HEADROOM sizeof(struct mana_mbuf_head) 219 220 enum mana_tx_pkt_format { 221 MANA_SHORT_PKT_FMT = 0, 222 MANA_LONG_PKT_FMT = 1, 223 }; 224 225 struct mana_tx_short_oob { 226 uint32_t pkt_fmt :2; 227 uint32_t is_outer_ipv4 :1; 228 uint32_t is_outer_ipv6 :1; 229 uint32_t comp_iphdr_csum :1; 230 uint32_t comp_tcp_csum :1; 231 uint32_t comp_udp_csum :1; 232 uint32_t supress_txcqe_gen :1; 233 uint32_t vcq_num :24; 234 235 uint32_t trans_off :10; /* Transport header offset */ 236 uint32_t vsq_frame :14; 237 uint32_t short_vp_offset :8; 238 }; /* HW DATA */ 239 240 struct mana_tx_long_oob { 241 uint32_t is_encap :1; 242 uint32_t inner_is_ipv6 :1; 243 uint32_t inner_tcp_opt :1; 244 uint32_t inject_vlan_pri_tag :1; 245 uint32_t reserved1 :12; 246 uint32_t pcp :3; /* 802.1Q */ 247 uint32_t dei :1; /* 802.1Q */ 248 uint32_t vlan_id :12; /* 802.1Q */ 249 250 uint32_t inner_frame_offset :10; 251 uint32_t inner_ip_rel_offset :6; 252 uint32_t long_vp_offset :12; 253 uint32_t reserved2 :4; 254 255 uint32_t reserved3; 256 uint32_t reserved4; 257 }; /* HW DATA */ 258 259 struct mana_tx_oob { 260 struct mana_tx_short_oob s_oob; 261 struct mana_tx_long_oob l_oob; 262 }; /* HW DATA */ 263 264 enum mana_cq_type { 265 MANA_CQ_TYPE_RX, 266 MANA_CQ_TYPE_TX, 267 }; 268 269 enum mana_cqe_type { 270 CQE_INVALID = 0, 271 CQE_RX_OKAY = 1, 272 CQE_RX_COALESCED_4 = 2, 273 CQE_RX_OBJECT_FENCE = 3, 274 CQE_RX_TRUNCATED = 4, 275 276 CQE_TX_OKAY = 32, 277 CQE_TX_SA_DROP = 33, 278 CQE_TX_MTU_DROP = 34, 279 CQE_TX_INVALID_OOB = 35, 280 CQE_TX_INVALID_ETH_TYPE = 36, 281 CQE_TX_HDR_PROCESSING_ERROR = 37, 282 CQE_TX_VF_DISABLED = 38, 283 CQE_TX_VPORT_IDX_OUT_OF_RANGE = 39, 284 CQE_TX_VPORT_DISABLED = 40, 285 CQE_TX_VLAN_TAGGING_VIOLATION = 41, 286 }; 287 288 #define MANA_CQE_COMPLETION 1 289 290 struct mana_cqe_header { 291 uint32_t cqe_type :6; 292 uint32_t client_type :2; 293 uint32_t vendor_err :24; 294 }; /* HW DATA */ 295 296 /* NDIS HASH Types */ 297 #define NDIS_HASH_IPV4 BIT(0) 298 #define NDIS_HASH_TCP_IPV4 BIT(1) 299 #define NDIS_HASH_UDP_IPV4 BIT(2) 300 #define NDIS_HASH_IPV6 BIT(3) 301 #define NDIS_HASH_TCP_IPV6 BIT(4) 302 #define NDIS_HASH_UDP_IPV6 BIT(5) 303 #define NDIS_HASH_IPV6_EX BIT(6) 304 #define NDIS_HASH_TCP_IPV6_EX BIT(7) 305 #define NDIS_HASH_UDP_IPV6_EX BIT(8) 306 307 #define MANA_HASH_L3 (NDIS_HASH_IPV4 | NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 308 #define MANA_HASH_L4 \ 309 (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4 | NDIS_HASH_TCP_IPV6 | \ 310 NDIS_HASH_UDP_IPV6 | NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 311 312 #define NDIS_HASH_IPV4_L3_MASK (NDIS_HASH_IPV4) 313 #define NDIS_HASH_IPV4_L4_MASK (NDIS_HASH_TCP_IPV4 | NDIS_HASH_UDP_IPV4) 314 #define NDIS_HASH_IPV6_L3_MASK (NDIS_HASH_IPV6 | NDIS_HASH_IPV6_EX) 315 #define NDIS_HASH_IPV6_L4_MASK \ 316 (NDIS_HASH_TCP_IPV6 | NDIS_HASH_UDP_IPV6 | \ 317 NDIS_HASH_TCP_IPV6_EX | NDIS_HASH_UDP_IPV6_EX) 318 #define NDIS_HASH_IPV4_MASK \ 319 (NDIS_HASH_IPV4_L3_MASK | NDIS_HASH_IPV4_L4_MASK) 320 #define NDIS_HASH_IPV6_MASK \ 321 (NDIS_HASH_IPV6_L3_MASK | NDIS_HASH_IPV6_L4_MASK) 322 323 324 struct mana_rxcomp_perpkt_info { 325 uint32_t pkt_len :16; 326 uint32_t reserved1 :16; 327 uint32_t reserved2; 328 uint32_t pkt_hash; 329 }; /* HW DATA */ 330 331 #define MANA_RXCOMP_OOB_NUM_PPI 4 332 333 /* Receive completion OOB */ 334 struct mana_rxcomp_oob { 335 struct mana_cqe_header cqe_hdr; 336 337 uint32_t rx_vlan_id :12; 338 uint32_t rx_vlantag_present :1; 339 uint32_t rx_outer_iphdr_csum_succeed :1; 340 uint32_t rx_outer_iphdr_csum_fail :1; 341 uint32_t reserved1 :1; 342 uint32_t rx_hashtype :9; 343 uint32_t rx_iphdr_csum_succeed :1; 344 uint32_t rx_iphdr_csum_fail :1; 345 uint32_t rx_tcp_csum_succeed :1; 346 uint32_t rx_tcp_csum_fail :1; 347 uint32_t rx_udp_csum_succeed :1; 348 uint32_t rx_udp_csum_fail :1; 349 uint32_t reserved2 :1; 350 351 struct mana_rxcomp_perpkt_info ppi[MANA_RXCOMP_OOB_NUM_PPI]; 352 353 uint32_t rx_wqe_offset; 354 }; /* HW DATA */ 355 356 struct mana_tx_comp_oob { 357 struct mana_cqe_header cqe_hdr; 358 359 uint32_t tx_data_offset; 360 361 uint32_t tx_sgl_offset :5; 362 uint32_t tx_wqe_offset :27; 363 364 uint32_t reserved[12]; 365 }; /* HW DATA */ 366 367 struct mana_rxq; 368 369 #define CQE_POLLING_BUFFER 512 370 371 struct mana_cq { 372 struct gdma_queue *gdma_cq; 373 374 /* Cache the CQ id (used to verify if each CQE comes to the right CQ. */ 375 uint32_t gdma_id; 376 377 /* Type of the CQ: TX or RX */ 378 enum mana_cq_type type; 379 380 /* Pointer to the mana_rxq that is pushing RX CQEs to the queue. 381 * Only and must be non-NULL if type is MANA_CQ_TYPE_RX. 382 */ 383 struct mana_rxq *rxq; 384 385 /* Pointer to the mana_txq that is pushing TX CQEs to the queue. 386 * Only and must be non-NULL if type is MANA_CQ_TYPE_TX. 387 */ 388 struct mana_txq *txq; 389 390 /* Taskqueue and related structs */ 391 struct task cleanup_task; 392 struct taskqueue *cleanup_tq; 393 int cpu; 394 bool do_not_ring_db; 395 396 /* Budget for one cleanup task */ 397 int work_done; 398 int budget; 399 400 /* Buffer which the CQ handler can copy the CQE's into. */ 401 struct gdma_comp gdma_comp_buf[CQE_POLLING_BUFFER]; 402 }; 403 404 struct mana_recv_buf_oob { 405 /* A valid GDMA work request representing the data buffer. */ 406 struct gdma_wqe_request wqe_req; 407 408 struct mbuf *mbuf; 409 bus_dmamap_t dma_map; 410 411 /* SGL of the buffer going to be sent as part of the work request. */ 412 uint32_t num_sge; 413 struct gdma_sge sgl[MAX_RX_WQE_SGL_ENTRIES]; 414 415 /* Required to store the result of mana_gd_post_work_request. 416 * gdma_posted_wqe_info.wqe_size_in_bu is required for progressing the 417 * work queue when the WQE is consumed. 418 */ 419 struct gdma_posted_wqe_info wqe_inf; 420 }; 421 422 struct mana_rxq { 423 struct gdma_queue *gdma_rq; 424 /* Cache the gdma receive queue id */ 425 uint32_t gdma_id; 426 427 /* Index of RQ in the vPort, not gdma receive queue id */ 428 uint32_t rxq_idx; 429 430 uint32_t datasize; 431 432 mana_handle_t rxobj; 433 434 struct completion fence_event; 435 436 struct mana_cq rx_cq; 437 438 if_t ndev; 439 struct lro_ctrl lro; 440 441 /* Total number of receive buffers to be allocated */ 442 uint32_t num_rx_buf; 443 444 uint32_t buf_index; 445 uint32_t next_to_refill; 446 uint32_t refill_thresh; 447 448 uint64_t lro_tried; 449 uint64_t lro_failed; 450 struct mana_stats stats; 451 452 /* MUST BE THE LAST MEMBER: 453 * Each receive buffer has an associated mana_recv_buf_oob. 454 */ 455 struct mana_recv_buf_oob rx_oobs[]; 456 }; 457 458 struct mana_tx_qp { 459 struct mana_txq txq; 460 461 struct mana_cq tx_cq; 462 463 mana_handle_t tx_object; 464 }; 465 466 struct mana_port_stats { 467 counter_u64_t rx_packets; 468 counter_u64_t tx_packets; 469 470 counter_u64_t rx_bytes; 471 counter_u64_t tx_bytes; 472 473 counter_u64_t rx_drops; 474 counter_u64_t tx_drops; 475 476 counter_u64_t stop_queue; 477 counter_u64_t wake_queue; 478 }; 479 480 struct mana_context { 481 struct gdma_dev *gdma_dev; 482 483 uint16_t num_ports; 484 485 struct mana_eq *eqs; 486 487 if_t ports[MAX_PORTS_IN_MANA_DEV]; 488 }; 489 490 struct mana_port_context { 491 struct mana_context *ac; 492 if_t ndev; 493 struct ifmedia media; 494 495 struct sx apc_lock; 496 497 /* DMA tag used for queue bufs of the entire port */ 498 bus_dma_tag_t rx_buf_tag; 499 bus_dma_tag_t tx_buf_tag; 500 501 uint8_t mac_addr[ETHER_ADDR_LEN]; 502 503 enum TRI_STATE rss_state; 504 505 mana_handle_t default_rxobj; 506 bool tx_shortform_allowed; 507 uint16_t tx_vp_offset; 508 509 struct mana_tx_qp *tx_qp; 510 511 /* Indirection Table for RX & TX. The values are queue indexes */ 512 uint32_t indir_table[MANA_INDIRECT_TABLE_SIZE]; 513 514 /* Indirection table containing RxObject Handles */ 515 mana_handle_t rxobj_table[MANA_INDIRECT_TABLE_SIZE]; 516 517 /* Hash key used by the NIC */ 518 uint8_t hashkey[MANA_HASH_KEY_SIZE]; 519 520 /* This points to an array of num_queues of RQ pointers. */ 521 struct mana_rxq **rxqs; 522 523 /* Create num_queues EQs, SQs, SQ-CQs, RQs and RQ-CQs, respectively. */ 524 unsigned int max_queues; 525 unsigned int num_queues; 526 527 unsigned int tx_queue_size; 528 unsigned int rx_queue_size; 529 530 mana_handle_t port_handle; 531 532 int vport_use_count; 533 534 uint16_t port_idx; 535 536 uint16_t frame_size; 537 538 bool port_is_up; 539 bool port_st_save; /* Saved port state */ 540 541 bool enable_tx_altq; 542 543 bool bind_cleanup_thread_cpu; 544 int last_tx_cq_bind_cpu; 545 int last_rx_cq_bind_cpu; 546 547 struct mana_port_stats port_stats; 548 549 struct sysctl_oid_list *port_list; 550 struct sysctl_ctx_list que_sysctl_ctx; 551 }; 552 553 #define MANA_APC_LOCK_INIT(apc) \ 554 sx_init(&(apc)->apc_lock, "MANA port lock") 555 #define MANA_APC_LOCK_DESTROY(apc) sx_destroy(&(apc)->apc_lock) 556 #define MANA_APC_LOCK_LOCK(apc) sx_xlock(&(apc)->apc_lock) 557 #define MANA_APC_LOCK_UNLOCK(apc) sx_unlock(&(apc)->apc_lock) 558 559 int mana_config_rss(struct mana_port_context *ac, enum TRI_STATE rx, 560 bool update_hash, bool update_tab); 561 562 int mana_alloc_queues(if_t ndev); 563 int mana_attach(if_t ndev); 564 int mana_detach(if_t ndev); 565 566 int mana_probe(struct gdma_dev *gd); 567 void mana_remove(struct gdma_dev *gd); 568 569 struct mana_obj_spec { 570 uint32_t queue_index; 571 uint64_t gdma_region; 572 uint32_t queue_size; 573 uint32_t attached_eq; 574 uint32_t modr_ctx_id; 575 }; 576 577 enum mana_command_code { 578 MANA_QUERY_DEV_CONFIG = 0x20001, 579 MANA_QUERY_GF_STAT = 0x20002, 580 MANA_CONFIG_VPORT_TX = 0x20003, 581 MANA_CREATE_WQ_OBJ = 0x20004, 582 MANA_DESTROY_WQ_OBJ = 0x20005, 583 MANA_FENCE_RQ = 0x20006, 584 MANA_CONFIG_VPORT_RX = 0x20007, 585 MANA_QUERY_VPORT_CONFIG = 0x20008, 586 }; 587 588 /* Query Device Configuration */ 589 struct mana_query_device_cfg_req { 590 struct gdma_req_hdr hdr; 591 592 /* Driver Capability flags */ 593 uint64_t drv_cap_flags1; 594 uint64_t drv_cap_flags2; 595 uint64_t drv_cap_flags3; 596 uint64_t drv_cap_flags4; 597 598 uint32_t proto_major_ver; 599 uint32_t proto_minor_ver; 600 uint32_t proto_micro_ver; 601 602 uint32_t reserved; 603 }; /* HW DATA */ 604 605 struct mana_query_device_cfg_resp { 606 struct gdma_resp_hdr hdr; 607 608 uint64_t pf_cap_flags1; 609 uint64_t pf_cap_flags2; 610 uint64_t pf_cap_flags3; 611 uint64_t pf_cap_flags4; 612 613 uint16_t max_num_vports; 614 uint16_t reserved; 615 uint32_t max_num_eqs; 616 }; /* HW DATA */ 617 618 /* Query vPort Configuration */ 619 struct mana_query_vport_cfg_req { 620 struct gdma_req_hdr hdr; 621 uint32_t vport_index; 622 }; /* HW DATA */ 623 624 struct mana_query_vport_cfg_resp { 625 struct gdma_resp_hdr hdr; 626 uint32_t max_num_sq; 627 uint32_t max_num_rq; 628 uint32_t num_indirection_ent; 629 uint32_t reserved1; 630 uint8_t mac_addr[6]; 631 uint8_t reserved2[2]; 632 mana_handle_t vport; 633 }; /* HW DATA */ 634 635 /* Configure vPort */ 636 struct mana_config_vport_req { 637 struct gdma_req_hdr hdr; 638 mana_handle_t vport; 639 uint32_t pdid; 640 uint32_t doorbell_pageid; 641 }; /* HW DATA */ 642 643 struct mana_config_vport_resp { 644 struct gdma_resp_hdr hdr; 645 uint16_t tx_vport_offset; 646 uint8_t short_form_allowed; 647 uint8_t reserved; 648 }; /* HW DATA */ 649 650 /* Create WQ Object */ 651 struct mana_create_wqobj_req { 652 struct gdma_req_hdr hdr; 653 mana_handle_t vport; 654 uint32_t wq_type; 655 uint32_t reserved; 656 uint64_t wq_gdma_region; 657 uint64_t cq_gdma_region; 658 uint32_t wq_size; 659 uint32_t cq_size; 660 uint32_t cq_moderation_ctx_id; 661 uint32_t cq_parent_qid; 662 }; /* HW DATA */ 663 664 struct mana_create_wqobj_resp { 665 struct gdma_resp_hdr hdr; 666 uint32_t wq_id; 667 uint32_t cq_id; 668 mana_handle_t wq_obj; 669 }; /* HW DATA */ 670 671 /* Destroy WQ Object */ 672 struct mana_destroy_wqobj_req { 673 struct gdma_req_hdr hdr; 674 uint32_t wq_type; 675 uint32_t reserved; 676 mana_handle_t wq_obj_handle; 677 }; /* HW DATA */ 678 679 struct mana_destroy_wqobj_resp { 680 struct gdma_resp_hdr hdr; 681 }; /* HW DATA */ 682 683 /* Fence RQ */ 684 struct mana_fence_rq_req { 685 struct gdma_req_hdr hdr; 686 mana_handle_t wq_obj_handle; 687 }; /* HW DATA */ 688 689 struct mana_fence_rq_resp { 690 struct gdma_resp_hdr hdr; 691 }; /* HW DATA */ 692 693 /* Configure vPort Rx Steering */ 694 struct mana_cfg_rx_steer_req { 695 struct gdma_req_hdr hdr; 696 mana_handle_t vport; 697 uint16_t num_indir_entries; 698 uint16_t indir_tab_offset; 699 uint32_t rx_enable; 700 uint32_t rss_enable; 701 uint8_t update_default_rxobj; 702 uint8_t update_hashkey; 703 uint8_t update_indir_tab; 704 uint8_t reserved; 705 mana_handle_t default_rxobj; 706 uint8_t hashkey[MANA_HASH_KEY_SIZE]; 707 }; /* HW DATA */ 708 709 struct mana_cfg_rx_steer_resp { 710 struct gdma_resp_hdr hdr; 711 }; /* HW DATA */ 712 713 #define MANA_MAX_NUM_QUEUES 16 714 715 #define MANA_SHORT_VPORT_OFFSET_MAX ((1U << 8) - 1) 716 717 #define MANA_IDX_NEXT(idx, size) (((idx) + 1) & ((size) - 1)) 718 #define MANA_GET_SPACE(start_idx, end_idx, size) \ 719 (((end_idx) >= (start_idx)) ? \ 720 ((end_idx) - (start_idx)) : ((size) - (start_idx) + (end_idx))) 721 722 #define MANA_RX_REFILL_THRESH 256 723 724 struct mana_tx_package { 725 struct gdma_wqe_request wqe_req; 726 struct gdma_sge sgl_array[MAX_MBUF_FRAGS]; 727 728 struct mana_tx_oob tx_oob; 729 730 struct gdma_posted_wqe_info wqe_info; 731 }; 732 733 int mana_restart(struct mana_port_context *apc); 734 735 int mana_create_wq_obj(struct mana_port_context *apc, 736 mana_handle_t vport, 737 uint32_t wq_type, struct mana_obj_spec *wq_spec, 738 struct mana_obj_spec *cq_spec, 739 mana_handle_t *wq_obj); 740 741 void mana_destroy_wq_obj(struct mana_port_context *apc, uint32_t wq_type, 742 mana_handle_t wq_obj); 743 744 int mana_cfg_vport(struct mana_port_context *apc, uint32_t protection_dom_id, 745 uint32_t doorbell_pg_id); 746 747 void mana_uncfg_vport(struct mana_port_context *apc); 748 #endif /* _MANA_H */ 749