1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/vmalloc.h>
28 #include <drm/display/drm_dp_helper.h>
29 #include <drm/display/drm_dp_mst_helper.h>
30 #include <drm/drm_atomic.h>
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_fixed.h>
33 #include <drm/drm_edid.h>
34 #include "dm_services.h"
35 #include "amdgpu.h"
36 #include "amdgpu_dm.h"
37 #include "amdgpu_dm_mst_types.h"
38 #include "amdgpu_dm_hdcp.h"
39
40 #include "dc.h"
41 #include "dm_helpers.h"
42
43 #include "ddc_service_types.h"
44 #include "dpcd_defs.h"
45
46 #include "dmub_cmd.h"
47 #if defined(CONFIG_DEBUG_FS)
48 #include "amdgpu_dm_debugfs.h"
49 #endif
50
51 #include "dc/resource/dcn20/dcn20_resource.h"
52
53 #define PEAK_FACTOR_X1000 1006
54
55 /*
56 * This function handles both native AUX and I2C-Over-AUX transactions.
57 */
dm_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)58 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
59 struct drm_dp_aux_msg *msg)
60 {
61 ssize_t result = 0;
62 struct aux_payload payload;
63 enum aux_return_code_type operation_result;
64 struct amdgpu_device *adev;
65 struct ddc_service *ddc;
66 uint8_t copy[16];
67
68 if (WARN_ON(msg->size > 16))
69 return -E2BIG;
70
71 payload.address = msg->address;
72 payload.data = msg->buffer;
73 payload.length = msg->size;
74 payload.reply = &msg->reply;
75 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
76 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
77 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
78 payload.write_status_update =
79 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
80 payload.defer_delay = 0;
81
82 if (payload.write) {
83 memcpy(copy, msg->buffer, msg->size);
84 payload.data = copy;
85 }
86
87 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
88 &operation_result);
89
90 /*
91 * w/a on certain intel platform where hpd is unexpected to pull low during
92 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
93 * aux transaction is succuess in such case, therefore bypass the error
94 */
95 ddc = TO_DM_AUX(aux)->ddc_service;
96 adev = ddc->ctx->driver_context;
97 if (adev->dm.aux_hpd_discon_quirk) {
98 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
99 operation_result == AUX_RET_ERROR_HPD_DISCON) {
100 result = msg->size;
101 operation_result = AUX_RET_SUCCESS;
102 }
103 }
104
105 /*
106 * result equals to 0 includes the cases of AUX_DEFER/I2C_DEFER
107 */
108 if (payload.write && result >= 0) {
109 if (result) {
110 /*one byte indicating partially written bytes*/
111 drm_dbg_dp(adev_to_drm(adev), "AUX partially written\n");
112 result = payload.data[0];
113 } else if (!payload.reply[0])
114 /*I2C_ACK|AUX_ACK*/
115 result = msg->size;
116 }
117
118 if (result < 0) {
119 switch (operation_result) {
120 case AUX_RET_SUCCESS:
121 break;
122 case AUX_RET_ERROR_HPD_DISCON:
123 case AUX_RET_ERROR_UNKNOWN:
124 case AUX_RET_ERROR_INVALID_OPERATION:
125 case AUX_RET_ERROR_PROTOCOL_ERROR:
126 result = -EIO;
127 break;
128 case AUX_RET_ERROR_INVALID_REPLY:
129 case AUX_RET_ERROR_ENGINE_ACQUIRE:
130 result = -EBUSY;
131 break;
132 case AUX_RET_ERROR_TIMEOUT:
133 result = -ETIMEDOUT;
134 break;
135 }
136
137 drm_dbg_dp(adev_to_drm(adev), "DP AUX transfer fail:%d\n", operation_result);
138 }
139
140 if (payload.reply[0])
141 drm_dbg_dp(adev_to_drm(adev), "AUX reply command not ACK: 0x%02x.",
142 payload.reply[0]);
143
144 return result;
145 }
146
147 static void
dm_dp_mst_connector_destroy(struct drm_connector * connector)148 dm_dp_mst_connector_destroy(struct drm_connector *connector)
149 {
150 struct amdgpu_dm_connector *aconnector =
151 to_amdgpu_dm_connector(connector);
152
153 if (aconnector->dc_sink) {
154 dc_link_remove_remote_sink(aconnector->dc_link,
155 aconnector->dc_sink);
156 dc_sink_release(aconnector->dc_sink);
157 }
158
159 drm_edid_free(aconnector->drm_edid);
160
161 drm_connector_cleanup(connector);
162 drm_dp_mst_put_port_malloc(aconnector->mst_output_port);
163 kfree(aconnector);
164 }
165
166 static int
amdgpu_dm_mst_connector_late_register(struct drm_connector * connector)167 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
168 {
169 struct amdgpu_dm_connector *amdgpu_dm_connector =
170 to_amdgpu_dm_connector(connector);
171 int r;
172
173 r = drm_dp_mst_connector_late_register(connector,
174 amdgpu_dm_connector->mst_output_port);
175 if (r < 0)
176 return r;
177
178 #if defined(CONFIG_DEBUG_FS)
179 connector_debugfs_init(amdgpu_dm_connector);
180 #endif
181
182 return 0;
183 }
184
185
186 static inline void
amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector * aconnector)187 amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector)
188 {
189 aconnector->drm_edid = NULL;
190 aconnector->dsc_aux = NULL;
191 aconnector->mst_output_port->passthrough_aux = NULL;
192 aconnector->mst_local_bw = 0;
193 aconnector->vc_full_pbn = 0;
194 }
195
196 static void
amdgpu_dm_mst_connector_early_unregister(struct drm_connector * connector)197 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
198 {
199 struct amdgpu_dm_connector *aconnector =
200 to_amdgpu_dm_connector(connector);
201 struct drm_dp_mst_port *port = aconnector->mst_output_port;
202 struct amdgpu_dm_connector *root = aconnector->mst_root;
203 struct dc_link *dc_link = aconnector->dc_link;
204 struct dc_sink *dc_sink = aconnector->dc_sink;
205
206 drm_dp_mst_connector_early_unregister(connector, port);
207
208 /*
209 * Release dc_sink for connector which its attached port is
210 * no longer in the mst topology
211 */
212 drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
213 if (dc_sink) {
214 if (dc_link->sink_count)
215 dc_link_remove_remote_sink(dc_link, dc_sink);
216
217 drm_dbg_dp(connector->dev,
218 "DM_MST: remove remote sink 0x%p, %d remaining\n",
219 dc_sink, dc_link->sink_count);
220
221 dc_sink_release(dc_sink);
222 aconnector->dc_sink = NULL;
223 amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
224 }
225
226 aconnector->mst_status = MST_STATUS_DEFAULT;
227 drm_modeset_unlock(&root->mst_mgr.base.lock);
228 }
229
230 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
231 .fill_modes = drm_helper_probe_single_connector_modes,
232 .destroy = dm_dp_mst_connector_destroy,
233 .reset = amdgpu_dm_connector_funcs_reset,
234 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
235 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
236 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
237 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
238 .late_register = amdgpu_dm_mst_connector_late_register,
239 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
240 };
241
needs_dsc_aux_workaround(struct dc_link * link)242 bool needs_dsc_aux_workaround(struct dc_link *link)
243 {
244 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
245 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
246 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
247 return true;
248
249 return false;
250 }
251
252 #if defined(CONFIG_DRM_AMD_DC_FP)
is_synaptics_cascaded_panamera(struct dc_link * link,struct drm_dp_mst_port * port)253 static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)
254 {
255 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F
256
257 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) {
258 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
259 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) {
260 DRM_INFO("Synaptics Cascaded MST hub\n");
261 return true;
262 }
263 }
264
265 return false;
266 }
267
validate_dsc_caps_on_connector(struct amdgpu_dm_connector * aconnector)268 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
269 {
270 struct dc_sink *dc_sink = aconnector->dc_sink;
271 struct drm_dp_mst_port *port = aconnector->mst_output_port;
272 u8 dsc_caps[16] = { 0 };
273 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
274 u8 *dsc_branch_dec_caps = NULL;
275
276 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
277
278 /*
279 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
280 * because it only check the dsc/fec caps of the "port variable" and not the dock
281 *
282 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
283 *
284 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
285 *
286 */
287 if (!aconnector->dsc_aux && !port->parent->port_parent &&
288 needs_dsc_aux_workaround(aconnector->dc_link))
289 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux;
290
291 /* synaptics cascaded MST hub case */
292 if (is_synaptics_cascaded_panamera(aconnector->dc_link, port))
293 aconnector->dsc_aux = port->mgr->aux;
294
295 if (!aconnector->dsc_aux)
296 return false;
297
298 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
299 return false;
300
301 if (drm_dp_dpcd_read(aconnector->dsc_aux,
302 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
303 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
304
305 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
306 dsc_caps, dsc_branch_dec_caps,
307 &dc_sink->dsc_caps.dsc_dec_caps))
308 return false;
309
310 return true;
311 }
312 #endif
313
retrieve_downstream_port_device(struct amdgpu_dm_connector * aconnector)314 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
315 {
316 union dp_downstream_port_present ds_port_present;
317
318 if (!aconnector->dsc_aux)
319 return false;
320
321 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) {
322 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n");
323 return false;
324 }
325
326 aconnector->mst_downstream_port_present = ds_port_present;
327 DRM_INFO("Downstream port present %d, type %d\n",
328 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE);
329
330 return true;
331 }
332
retrieve_branch_specific_data(struct amdgpu_dm_connector * aconnector)333 static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector)
334 {
335 struct drm_connector *connector = &aconnector->base;
336 struct drm_dp_mst_port *port = aconnector->mst_output_port;
337 struct drm_dp_mst_port *port_parent;
338 struct drm_dp_aux *immediate_upstream_aux;
339 struct drm_dp_desc branch_desc;
340
341 if (!port->parent)
342 return false;
343
344 port_parent = port->parent->port_parent;
345
346 immediate_upstream_aux = port_parent ? &port_parent->aux : port->mgr->aux;
347
348 if (drm_dp_read_desc(immediate_upstream_aux, &branch_desc, true))
349 return false;
350
351 aconnector->branch_ieee_oui = (branch_desc.ident.oui[0] << 16) +
352 (branch_desc.ident.oui[1] << 8) +
353 (branch_desc.ident.oui[2]);
354
355 drm_dbg_dp(port->aux.drm_dev, "MST branch oui 0x%x detected at %s\n",
356 aconnector->branch_ieee_oui, connector->name);
357
358 return true;
359 }
360
dm_dp_mst_get_modes(struct drm_connector * connector)361 static int dm_dp_mst_get_modes(struct drm_connector *connector)
362 {
363 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
364 int ret = 0;
365
366 if (!aconnector)
367 return drm_add_edid_modes(connector, NULL);
368
369 if (!aconnector->drm_edid) {
370 const struct drm_edid *drm_edid;
371
372 drm_edid = drm_dp_mst_edid_read(connector,
373 &aconnector->mst_root->mst_mgr,
374 aconnector->mst_output_port);
375
376 if (!drm_edid) {
377 amdgpu_dm_set_mst_status(&aconnector->mst_status,
378 MST_REMOTE_EDID, false);
379
380 drm_edid_connector_update(
381 &aconnector->base,
382 NULL);
383
384 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
385 if (!aconnector->dc_sink) {
386 struct dc_sink *dc_sink;
387 struct dc_sink_init_data init_params = {
388 .link = aconnector->dc_link,
389 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
390
391 dc_sink = dc_link_add_remote_sink(
392 aconnector->dc_link,
393 NULL,
394 0,
395 &init_params);
396
397 if (!dc_sink) {
398 DRM_ERROR("Unable to add a remote sink\n");
399 return 0;
400 }
401
402 drm_dbg_dp(connector->dev,
403 "DM_MST: add remote sink 0x%p, %d remaining\n",
404 dc_sink,
405 aconnector->dc_link->sink_count);
406
407 dc_sink->priv = aconnector;
408 aconnector->dc_sink = dc_sink;
409 }
410
411 return ret;
412 }
413
414 aconnector->drm_edid = drm_edid;
415 amdgpu_dm_set_mst_status(&aconnector->mst_status,
416 MST_REMOTE_EDID, true);
417 }
418
419 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
420 dc_sink_release(aconnector->dc_sink);
421 aconnector->dc_sink = NULL;
422 }
423
424 if (!aconnector->dc_sink) {
425 struct dc_sink *dc_sink;
426 struct dc_sink_init_data init_params = {
427 .link = aconnector->dc_link,
428 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
429 const struct edid *edid;
430
431 edid = drm_edid_raw(aconnector->drm_edid); // FIXME: Get rid of drm_edid_raw()
432 dc_sink = dc_link_add_remote_sink(
433 aconnector->dc_link,
434 (uint8_t *)edid,
435 (edid->extensions + 1) * EDID_LENGTH,
436 &init_params);
437
438 if (!dc_sink) {
439 DRM_ERROR("Unable to add a remote sink\n");
440 return 0;
441 }
442
443 drm_dbg_dp(connector->dev,
444 "DM_MST: add remote sink 0x%p, %d remaining\n",
445 dc_sink, aconnector->dc_link->sink_count);
446
447 dc_sink->priv = aconnector;
448 /* dc_link_add_remote_sink returns a new reference */
449 aconnector->dc_sink = dc_sink;
450
451 /* when display is unplugged from mst hub, connctor will be
452 * destroyed within dm_dp_mst_connector_destroy. connector
453 * hdcp perperties, like type, undesired, desired, enabled,
454 * will be lost. So, save hdcp properties into hdcp_work within
455 * amdgpu_dm_atomic_commit_tail. if the same display is
456 * plugged back with same display index, its hdcp properties
457 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
458 */
459 if (aconnector->dc_sink && connector->state) {
460 struct drm_device *dev = connector->dev;
461 struct amdgpu_device *adev = drm_to_adev(dev);
462
463 if (adev->dm.hdcp_workqueue) {
464 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
465 struct hdcp_workqueue *hdcp_w =
466 &hdcp_work[aconnector->dc_link->link_index];
467
468 connector->state->hdcp_content_type =
469 hdcp_w->hdcp_content_type[connector->index];
470 connector->state->content_protection =
471 hdcp_w->content_protection[connector->index];
472 }
473 }
474
475 if (aconnector->dc_sink) {
476 amdgpu_dm_update_freesync_caps(
477 connector, aconnector->drm_edid);
478
479 #if defined(CONFIG_DRM_AMD_DC_FP)
480 if (!validate_dsc_caps_on_connector(aconnector))
481 memset(&aconnector->dc_sink->dsc_caps,
482 0, sizeof(aconnector->dc_sink->dsc_caps));
483 #endif
484
485 if (!retrieve_downstream_port_device(aconnector))
486 memset(&aconnector->mst_downstream_port_present,
487 0, sizeof(aconnector->mst_downstream_port_present));
488 }
489 }
490
491 drm_edid_connector_update(&aconnector->base, aconnector->drm_edid);
492
493 ret = drm_edid_connector_add_modes(connector);
494
495 return ret;
496 }
497
498 static struct drm_encoder *
dm_mst_atomic_best_encoder(struct drm_connector * connector,struct drm_atomic_state * state)499 dm_mst_atomic_best_encoder(struct drm_connector *connector,
500 struct drm_atomic_state *state)
501 {
502 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
503 connector);
504 struct amdgpu_device *adev = drm_to_adev(connector->dev);
505 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
506
507 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
508 }
509
510 static int
dm_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)511 dm_dp_mst_detect(struct drm_connector *connector,
512 struct drm_modeset_acquire_ctx *ctx, bool force)
513 {
514 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
515 struct amdgpu_dm_connector *master = aconnector->mst_root;
516 struct drm_dp_mst_port *port = aconnector->mst_output_port;
517 int connection_status;
518
519 if (drm_connector_is_unregistered(connector))
520 return connector_status_disconnected;
521
522 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
523 aconnector->mst_output_port);
524
525 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
526 uint8_t dpcd_rev;
527 int ret;
528
529 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
530
531 if (ret == 1) {
532 port->dpcd_rev = dpcd_rev;
533
534 /* Could be DP1.2 DP Rx case*/
535 if (!dpcd_rev) {
536 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
537
538 if (ret == 1)
539 port->dpcd_rev = dpcd_rev;
540 }
541
542 if (!dpcd_rev)
543 DRM_DEBUG_KMS("Can't decide DPCD revision number!");
544 }
545
546 /*
547 * Could be legacy sink, logical port etc on DP1.2.
548 * Will get Nack under these cases when issue remote
549 * DPCD read.
550 */
551 if (ret != 1)
552 DRM_DEBUG_KMS("Can't access DPCD");
553 } else if (port->pdt == DP_PEER_DEVICE_NONE) {
554 port->dpcd_rev = 0;
555 }
556
557 /*
558 * Release dc_sink for connector which unplug event is notified by CSN msg
559 */
560 if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
561 if (aconnector->dc_link->sink_count)
562 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
563
564 drm_dbg_dp(connector->dev,
565 "DM_MST: remove remote sink 0x%p, %d remaining\n",
566 aconnector->dc_link,
567 aconnector->dc_link->sink_count);
568
569 dc_sink_release(aconnector->dc_sink);
570 aconnector->dc_sink = NULL;
571 amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
572
573 amdgpu_dm_set_mst_status(&aconnector->mst_status,
574 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
575 false);
576 }
577
578 return connection_status;
579 }
580
dm_dp_mst_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)581 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
582 struct drm_atomic_state *state)
583 {
584 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
585 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr;
586 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port;
587
588 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
589 }
590
591 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
592 .get_modes = dm_dp_mst_get_modes,
593 .mode_valid = amdgpu_dm_connector_mode_valid,
594 .atomic_best_encoder = dm_mst_atomic_best_encoder,
595 .detect_ctx = dm_dp_mst_detect,
596 .atomic_check = dm_dp_mst_atomic_check,
597 };
598
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)599 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
600 {
601 drm_encoder_cleanup(encoder);
602 }
603
604 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
605 .destroy = amdgpu_dm_encoder_destroy,
606 };
607
608 void
dm_dp_create_fake_mst_encoders(struct amdgpu_device * adev)609 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
610 {
611 struct drm_device *dev = adev_to_drm(adev);
612 int i;
613
614 for (i = 0; i < adev->dm.display_indexes_num; i++) {
615 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
616 struct drm_encoder *encoder = &amdgpu_encoder->base;
617
618 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
619
620 drm_encoder_init(
621 dev,
622 &amdgpu_encoder->base,
623 &amdgpu_dm_encoder_funcs,
624 DRM_MODE_ENCODER_DPMST,
625 NULL);
626
627 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
628 }
629 }
630
631 static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)632 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
633 struct drm_dp_mst_port *port,
634 const char *pathprop)
635 {
636 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
637 struct drm_device *dev = master->base.dev;
638 struct amdgpu_device *adev = drm_to_adev(dev);
639 struct amdgpu_dm_connector *aconnector;
640 struct drm_connector *connector;
641 int i;
642
643 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
644 if (!aconnector)
645 return NULL;
646
647 DRM_DEBUG_DRIVER("%s: Create aconnector 0x%p for port 0x%p\n", __func__, aconnector, port);
648
649 connector = &aconnector->base;
650 aconnector->mst_output_port = port;
651 aconnector->mst_root = master;
652 amdgpu_dm_set_mst_status(&aconnector->mst_status,
653 MST_PROBE, true);
654
655 if (drm_connector_dynamic_init(
656 dev,
657 connector,
658 &dm_dp_mst_connector_funcs,
659 DRM_MODE_CONNECTOR_DisplayPort,
660 NULL)) {
661 kfree(aconnector);
662 return NULL;
663 }
664 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
665
666 amdgpu_dm_connector_init_helper(
667 &adev->dm,
668 aconnector,
669 DRM_MODE_CONNECTOR_DisplayPort,
670 master->dc_link,
671 master->connector_id);
672
673 for (i = 0; i < adev->dm.display_indexes_num; i++) {
674 drm_connector_attach_encoder(&aconnector->base,
675 &adev->dm.mst_encoders[i].base);
676 }
677
678 connector->max_bpc_property = master->base.max_bpc_property;
679 if (connector->max_bpc_property)
680 drm_connector_attach_max_bpc_property(connector, 8, 16);
681
682 connector->vrr_capable_property = master->base.vrr_capable_property;
683 if (connector->vrr_capable_property)
684 drm_connector_attach_vrr_capable_property(connector);
685
686 drm_object_attach_property(
687 &connector->base,
688 dev->mode_config.path_property,
689 0);
690 drm_object_attach_property(
691 &connector->base,
692 dev->mode_config.tile_property,
693 0);
694 connector->colorspace_property = master->base.colorspace_property;
695 if (connector->colorspace_property)
696 drm_connector_attach_colorspace_property(connector);
697
698 drm_connector_set_path_property(connector, pathprop);
699
700 if (!retrieve_branch_specific_data(aconnector))
701 aconnector->branch_ieee_oui = 0;
702
703 /*
704 * Initialize connector state before adding the connectror to drm and
705 * framebuffer lists
706 */
707 amdgpu_dm_connector_funcs_reset(connector);
708
709 drm_dp_mst_get_port_malloc(port);
710
711 return connector;
712 }
713
dm_handle_mst_sideband_msg_ready_event(struct drm_dp_mst_topology_mgr * mgr,enum mst_msg_ready_type msg_rdy_type)714 void dm_handle_mst_sideband_msg_ready_event(
715 struct drm_dp_mst_topology_mgr *mgr,
716 enum mst_msg_ready_type msg_rdy_type)
717 {
718 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
719 uint8_t dret;
720 bool new_irq_handled = false;
721 int dpcd_addr;
722 uint8_t dpcd_bytes_to_read;
723 const uint8_t max_process_count = 30;
724 uint8_t process_count = 0;
725 u8 retry;
726 struct amdgpu_dm_connector *aconnector =
727 container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
728
729
730 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
731
732 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
733 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
734 /* DPCD 0x200 - 0x201 for downstream IRQ */
735 dpcd_addr = DP_SINK_COUNT;
736 } else {
737 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
738 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
739 dpcd_addr = DP_SINK_COUNT_ESI;
740 }
741
742 mutex_lock(&aconnector->handle_mst_msg_ready);
743
744 while (process_count < max_process_count) {
745 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
746
747 process_count++;
748
749 dret = drm_dp_dpcd_read(
750 &aconnector->dm_dp_aux.aux,
751 dpcd_addr,
752 esi,
753 dpcd_bytes_to_read);
754
755 if (dret != dpcd_bytes_to_read) {
756 DRM_DEBUG_KMS("DPCD read and acked number is not as expected!");
757 break;
758 }
759
760 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
761
762 switch (msg_rdy_type) {
763 case DOWN_REP_MSG_RDY_EVENT:
764 /* Only handle DOWN_REP_MSG_RDY case*/
765 esi[1] &= DP_DOWN_REP_MSG_RDY;
766 break;
767 case UP_REQ_MSG_RDY_EVENT:
768 /* Only handle UP_REQ_MSG_RDY case*/
769 esi[1] &= DP_UP_REQ_MSG_RDY;
770 break;
771 default:
772 /* Handle both cases*/
773 esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
774 break;
775 }
776
777 if (!esi[1])
778 break;
779
780 /* handle MST irq */
781 if (aconnector->mst_mgr.mst_state)
782 drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
783 esi,
784 ack,
785 &new_irq_handled);
786
787 if (new_irq_handled) {
788 /* ACK at DPCD to notify down stream */
789 for (retry = 0; retry < 3; retry++) {
790 ssize_t wret;
791
792 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
793 dpcd_addr + 1,
794 ack[1]);
795 if (wret == 1)
796 break;
797 }
798
799 if (retry == 3) {
800 DRM_ERROR("Failed to ack MST event.\n");
801 break;
802 }
803
804 drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
805
806 new_irq_handled = false;
807 } else {
808 break;
809 }
810 }
811
812 mutex_unlock(&aconnector->handle_mst_msg_ready);
813
814 if (process_count == max_process_count)
815 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
816 }
817
dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr * mgr)818 static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr)
819 {
820 dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT);
821 }
822
823 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
824 .add_connector = dm_dp_add_mst_connector,
825 .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready,
826 };
827
amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int link_index)828 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
829 struct amdgpu_dm_connector *aconnector,
830 int link_index)
831 {
832 struct dc_link_settings max_link_enc_cap = {0};
833
834 aconnector->dm_dp_aux.aux.name =
835 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
836 link_index);
837 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
838 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
839 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
840
841 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
842 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
843 &aconnector->base);
844 drm_dp_dpcd_set_probe(&aconnector->dm_dp_aux.aux, false);
845
846 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
847 return;
848
849 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
850 aconnector->mst_mgr.cbs = &dm_mst_cbs;
851 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
852 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
853
854 drm_connector_attach_dp_subconnector_property(&aconnector->base);
855 }
856
dm_mst_get_pbn_divider(struct dc_link * link)857 uint32_t dm_mst_get_pbn_divider(struct dc_link *link)
858 {
859 uint32_t pbn_div_x100;
860 uint64_t dividend, divisor;
861
862 if (!link)
863 return 0;
864
865 dividend = (uint64_t)dc_link_bandwidth_kbps(link, dc_link_get_link_cap(link)) * 100;
866 divisor = 8 * 1000 * 54;
867
868 pbn_div_x100 = div64_u64(dividend, divisor);
869
870 return dfixed_const(pbn_div_x100) / 100;
871 }
872
873 struct dsc_mst_fairness_params {
874 struct dc_crtc_timing *timing;
875 struct dc_sink *sink;
876 struct dc_dsc_bw_range bw_range;
877 bool compression_possible;
878 struct drm_dp_mst_port *port;
879 enum dsc_clock_force_state clock_force_enable;
880 uint32_t num_slices_h;
881 uint32_t num_slices_v;
882 uint32_t bpp_overwrite;
883 struct amdgpu_dm_connector *aconnector;
884 };
885
886 #if defined(CONFIG_DRM_AMD_DC_FP)
kbps_to_pbn(int kbps,bool is_peak_pbn)887 static uint64_t kbps_to_pbn(int kbps, bool is_peak_pbn)
888 {
889 uint64_t effective_kbps = (uint64_t)kbps;
890
891 if (is_peak_pbn) { // add 0.6% (1006/1000) overhead into effective kbps
892 effective_kbps *= 1006;
893 effective_kbps = div_u64(effective_kbps, 1000);
894 }
895
896 return (uint64_t) DIV64_U64_ROUND_UP(effective_kbps * 64, (54 * 8 * 1000));
897 }
898
pbn_to_kbps(unsigned int pbn,bool with_margin)899 static uint32_t pbn_to_kbps(unsigned int pbn, bool with_margin)
900 {
901 uint64_t pbn_effective = (uint64_t)pbn;
902
903 if (with_margin) // deduct 0.6% (994/1000) overhead from effective pbn
904 pbn_effective *= (1000000 / PEAK_FACTOR_X1000);
905 else
906 pbn_effective *= 1000;
907
908 return DIV_U64_ROUND_UP(pbn_effective * 8 * 54, 64);
909 }
910
set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)911 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
912 struct dsc_mst_fairness_vars *vars,
913 int count,
914 int k)
915 {
916 struct drm_connector *drm_connector;
917 int i;
918 struct dc_dsc_config_options dsc_options = {0};
919
920 for (i = 0; i < count; i++) {
921 drm_connector = ¶ms[i].aconnector->base;
922
923 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options);
924 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
925
926 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
927 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
928 params[i].sink->ctx->dc->res_pool->dscs[0],
929 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
930 &dsc_options,
931 0,
932 params[i].timing,
933 dc_link_get_highest_encoding_format(params[i].aconnector->dc_link),
934 ¶ms[i].timing->dsc_cfg)) {
935 params[i].timing->flags.DSC = 1;
936
937 if (params[i].bpp_overwrite)
938 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
939 else
940 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
941
942 if (params[i].num_slices_h)
943 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
944
945 if (params[i].num_slices_v)
946 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
947 } else {
948 params[i].timing->flags.DSC = 0;
949 }
950 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
951 }
952
953 for (i = 0; i < count; i++) {
954 if (params[i].sink) {
955 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
956 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
957 DRM_DEBUG_DRIVER("MST_DSC %s i=%d dispname=%s\n", __func__, i,
958 params[i].sink->edid_caps.display_name);
959 }
960
961 DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n",
962 params[i].timing->flags.DSC,
963 params[i].timing->dsc_cfg.bits_per_pixel,
964 vars[i + k].pbn);
965 }
966 }
967
bpp_x16_from_pbn(struct dsc_mst_fairness_params param,int pbn)968 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
969 {
970 struct dc_dsc_config dsc_config;
971 u64 kbps;
972
973 struct drm_connector *drm_connector = ¶m.aconnector->base;
974 struct dc_dsc_config_options dsc_options = {0};
975
976 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options);
977 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
978
979 kbps = pbn_to_kbps(pbn, false);
980 dc_dsc_compute_config(
981 param.sink->ctx->dc->res_pool->dscs[0],
982 ¶m.sink->dsc_caps.dsc_dec_caps,
983 &dsc_options,
984 (int) kbps, param.timing,
985 dc_link_get_highest_encoding_format(param.aconnector->dc_link),
986 &dsc_config);
987
988 return dsc_config.bits_per_pixel;
989 }
990
increase_dsc_bpp(struct drm_atomic_state * state,struct drm_dp_mst_topology_state * mst_state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)991 static int increase_dsc_bpp(struct drm_atomic_state *state,
992 struct drm_dp_mst_topology_state *mst_state,
993 struct dc_link *dc_link,
994 struct dsc_mst_fairness_params *params,
995 struct dsc_mst_fairness_vars *vars,
996 int count,
997 int k)
998 {
999 int i;
1000 bool bpp_increased[MAX_PIPES];
1001 int initial_slack[MAX_PIPES];
1002 int min_initial_slack;
1003 int next_index;
1004 int remaining_to_increase = 0;
1005 int link_timeslots_used;
1006 int fair_pbn_alloc;
1007 int ret = 0;
1008
1009 for (i = 0; i < count; i++) {
1010 if (vars[i + k].dsc_enabled) {
1011 initial_slack[i] =
1012 kbps_to_pbn(params[i].bw_range.max_kbps, false) - vars[i + k].pbn;
1013 bpp_increased[i] = false;
1014 remaining_to_increase += 1;
1015 } else {
1016 initial_slack[i] = 0;
1017 bpp_increased[i] = true;
1018 }
1019 }
1020
1021 while (remaining_to_increase) {
1022 next_index = -1;
1023 min_initial_slack = -1;
1024 for (i = 0; i < count; i++) {
1025 if (!bpp_increased[i]) {
1026 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
1027 min_initial_slack = initial_slack[i];
1028 next_index = i;
1029 }
1030 }
1031 }
1032
1033 if (next_index == -1)
1034 break;
1035
1036 link_timeslots_used = 0;
1037
1038 for (i = 0; i < count; i++)
1039 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div));
1040
1041 fair_pbn_alloc =
1042 (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div);
1043
1044 if (initial_slack[next_index] > fair_pbn_alloc) {
1045 vars[next_index].pbn += fair_pbn_alloc;
1046 ret = drm_dp_atomic_find_time_slots(state,
1047 params[next_index].port->mgr,
1048 params[next_index].port,
1049 vars[next_index].pbn);
1050 if (ret < 0)
1051 return ret;
1052
1053 ret = drm_dp_mst_atomic_check(state);
1054 if (ret == 0) {
1055 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
1056 } else {
1057 vars[next_index].pbn -= fair_pbn_alloc;
1058 ret = drm_dp_atomic_find_time_slots(state,
1059 params[next_index].port->mgr,
1060 params[next_index].port,
1061 vars[next_index].pbn);
1062 if (ret < 0)
1063 return ret;
1064 }
1065 } else {
1066 vars[next_index].pbn += initial_slack[next_index];
1067 ret = drm_dp_atomic_find_time_slots(state,
1068 params[next_index].port->mgr,
1069 params[next_index].port,
1070 vars[next_index].pbn);
1071 if (ret < 0)
1072 return ret;
1073
1074 ret = drm_dp_mst_atomic_check(state);
1075 if (ret == 0) {
1076 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
1077 } else {
1078 vars[next_index].pbn -= initial_slack[next_index];
1079 ret = drm_dp_atomic_find_time_slots(state,
1080 params[next_index].port->mgr,
1081 params[next_index].port,
1082 vars[next_index].pbn);
1083 if (ret < 0)
1084 return ret;
1085 }
1086 }
1087
1088 bpp_increased[next_index] = true;
1089 remaining_to_increase--;
1090 }
1091 return 0;
1092 }
1093
try_disable_dsc(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count,int k)1094 static int try_disable_dsc(struct drm_atomic_state *state,
1095 struct dc_link *dc_link,
1096 struct dsc_mst_fairness_params *params,
1097 struct dsc_mst_fairness_vars *vars,
1098 int count,
1099 int k)
1100 {
1101 int i;
1102 bool tried[MAX_PIPES];
1103 int kbps_increase[MAX_PIPES];
1104 int max_kbps_increase;
1105 int next_index;
1106 int remaining_to_try = 0;
1107 int ret;
1108 int var_pbn;
1109
1110 for (i = 0; i < count; i++) {
1111 if (vars[i + k].dsc_enabled
1112 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
1113 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
1114 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
1115 tried[i] = false;
1116 remaining_to_try += 1;
1117 } else {
1118 kbps_increase[i] = 0;
1119 tried[i] = true;
1120 }
1121 }
1122
1123 while (remaining_to_try) {
1124 next_index = -1;
1125 max_kbps_increase = -1;
1126 for (i = 0; i < count; i++) {
1127 if (!tried[i]) {
1128 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
1129 max_kbps_increase = kbps_increase[i];
1130 next_index = i;
1131 }
1132 }
1133 }
1134
1135 if (next_index == -1)
1136 break;
1137
1138 DRM_DEBUG_DRIVER("MST_DSC index #%d, try no compression\n", next_index);
1139 var_pbn = vars[next_index].pbn;
1140 vars[next_index].pbn = kbps_to_pbn(params[next_index].bw_range.stream_kbps, true);
1141 ret = drm_dp_atomic_find_time_slots(state,
1142 params[next_index].port->mgr,
1143 params[next_index].port,
1144 vars[next_index].pbn);
1145 if (ret < 0) {
1146 DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",
1147 __func__, __LINE__, next_index, ret);
1148 vars[next_index].pbn = var_pbn;
1149 return ret;
1150 }
1151
1152 ret = drm_dp_mst_atomic_check(state);
1153 if (ret == 0) {
1154 DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index);
1155 vars[next_index].dsc_enabled = false;
1156 vars[next_index].bpp_x16 = 0;
1157 } else {
1158 DRM_DEBUG_DRIVER("MST_DSC index #%d, restore optimized pbn value\n", next_index);
1159 vars[next_index].pbn = var_pbn;
1160 ret = drm_dp_atomic_find_time_slots(state,
1161 params[next_index].port->mgr,
1162 params[next_index].port,
1163 vars[next_index].pbn);
1164 if (ret < 0) {
1165 DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n",
1166 __func__, __LINE__, next_index, ret);
1167 return ret;
1168 }
1169 }
1170
1171 tried[next_index] = true;
1172 remaining_to_try--;
1173 }
1174 return 0;
1175 }
1176
log_dsc_params(int count,struct dsc_mst_fairness_vars * vars,int k)1177 static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k)
1178 {
1179 int i;
1180
1181 for (i = 0; i < count; i++)
1182 DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n",
1183 i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn);
1184 }
1185
compute_mst_dsc_configs_for_link(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link,struct dsc_mst_fairness_vars * vars,struct drm_dp_mst_topology_mgr * mgr,int * link_vars_start_index)1186 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
1187 struct dc_state *dc_state,
1188 struct dc_link *dc_link,
1189 struct dsc_mst_fairness_vars *vars,
1190 struct drm_dp_mst_topology_mgr *mgr,
1191 int *link_vars_start_index)
1192 {
1193 struct dc_stream_state *stream;
1194 struct dsc_mst_fairness_params params[MAX_PIPES];
1195 struct amdgpu_dm_connector *aconnector;
1196 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
1197 int count = 0;
1198 int i, k, ret;
1199 bool debugfs_overwrite = false;
1200 struct drm_connector_state *new_conn_state;
1201
1202 memset(params, 0, sizeof(params));
1203
1204 if (IS_ERR(mst_state))
1205 return PTR_ERR(mst_state);
1206
1207 /* Set up params */
1208 DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state->stream_count);
1209 for (i = 0; i < dc_state->stream_count; i++) {
1210 struct dc_dsc_policy dsc_policy = {0};
1211
1212 stream = dc_state->streams[i];
1213
1214 if (stream->link != dc_link)
1215 continue;
1216
1217 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1218 if (!aconnector)
1219 continue;
1220
1221 if (!aconnector->mst_output_port)
1222 continue;
1223
1224 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1225
1226 if (!new_conn_state) {
1227 DRM_DEBUG_DRIVER("%s:%d MST_DSC Skip the stream 0x%p with invalid new_conn_state\n",
1228 __func__, __LINE__, stream);
1229 continue;
1230 }
1231
1232 stream->timing.flags.DSC = 0;
1233
1234 params[count].timing = &stream->timing;
1235 params[count].sink = stream->sink;
1236 params[count].aconnector = aconnector;
1237 params[count].port = aconnector->mst_output_port;
1238 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
1239 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
1240 debugfs_overwrite = true;
1241 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
1242 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
1243 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
1244 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
1245 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
1246 if (!dc_dsc_compute_bandwidth_range(
1247 stream->sink->ctx->dc->res_pool->dscs[0],
1248 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1249 dsc_policy.min_target_bpp * 16,
1250 dsc_policy.max_target_bpp * 16,
1251 &stream->sink->dsc_caps.dsc_dec_caps,
1252 &stream->timing,
1253 dc_link_get_highest_encoding_format(dc_link),
1254 ¶ms[count].bw_range))
1255 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
1256 dc_link_get_highest_encoding_format(dc_link));
1257
1258 DRM_DEBUG_DRIVER("MST_DSC #%d stream 0x%p - max_kbps = %u, min_kbps = %u, uncompressed_kbps = %u\n",
1259 count, stream, params[count].bw_range.max_kbps, params[count].bw_range.min_kbps,
1260 params[count].bw_range.stream_kbps);
1261 count++;
1262 }
1263
1264 DRM_DEBUG_DRIVER("%s: MST_DSC Params set up for %d streams\n", __func__, count);
1265
1266 if (count == 0) {
1267 ASSERT(0);
1268 return 0;
1269 }
1270
1271 /* k is start index of vars for current phy link used by mst hub */
1272 k = *link_vars_start_index;
1273 /* set vars start index for next mst hub phy link */
1274 *link_vars_start_index += count;
1275
1276 /* Try no compression */
1277 DRM_DEBUG_DRIVER("MST_DSC Try no compression\n");
1278 for (i = 0; i < count; i++) {
1279 vars[i + k].aconnector = params[i].aconnector;
1280 vars[i + k].pbn = kbps_to_pbn(params[i].bw_range.stream_kbps, false);
1281 vars[i + k].dsc_enabled = false;
1282 vars[i + k].bpp_x16 = 0;
1283 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
1284 vars[i + k].pbn);
1285 if (ret < 0)
1286 return ret;
1287 }
1288 ret = drm_dp_mst_atomic_check(state);
1289 if (ret == 0 && !debugfs_overwrite) {
1290 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1291 return 0;
1292 } else if (ret != -ENOSPC) {
1293 return ret;
1294 }
1295
1296 log_dsc_params(count, vars, k);
1297
1298 /* Try max compression */
1299 DRM_DEBUG_DRIVER("MST_DSC Try max compression\n");
1300 for (i = 0; i < count; i++) {
1301 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
1302 vars[i + k].pbn = kbps_to_pbn(params[i].bw_range.min_kbps, false);
1303 vars[i + k].dsc_enabled = true;
1304 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
1305 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1306 params[i].port, vars[i + k].pbn);
1307 if (ret < 0)
1308 return ret;
1309 } else {
1310 vars[i + k].pbn = kbps_to_pbn(params[i].bw_range.stream_kbps, false);
1311 vars[i + k].dsc_enabled = false;
1312 vars[i + k].bpp_x16 = 0;
1313 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1314 params[i].port, vars[i + k].pbn);
1315 if (ret < 0)
1316 return ret;
1317 }
1318 }
1319 ret = drm_dp_mst_atomic_check(state);
1320 if (ret != 0)
1321 return ret;
1322
1323 log_dsc_params(count, vars, k);
1324
1325 /* Optimize degree of compression */
1326 DRM_DEBUG_DRIVER("MST_DSC Try optimize compression\n");
1327 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
1328 if (ret < 0) {
1329 DRM_DEBUG_DRIVER("MST_DSC Failed to optimize compression\n");
1330 return ret;
1331 }
1332
1333 log_dsc_params(count, vars, k);
1334
1335 DRM_DEBUG_DRIVER("MST_DSC Try disable compression\n");
1336 ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1337 if (ret < 0) {
1338 DRM_DEBUG_DRIVER("MST_DSC Failed to disable compression\n");
1339 return ret;
1340 }
1341
1342 log_dsc_params(count, vars, k);
1343
1344 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1345
1346 return 0;
1347 }
1348
is_dsc_need_re_compute(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link)1349 static bool is_dsc_need_re_compute(
1350 struct drm_atomic_state *state,
1351 struct dc_state *dc_state,
1352 struct dc_link *dc_link)
1353 {
1354 int i, j;
1355 bool is_dsc_need_re_compute = false;
1356 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
1357 int new_stream_on_link_num = 0;
1358 struct amdgpu_dm_connector *aconnector;
1359 struct dc_stream_state *stream;
1360 const struct dc *dc = dc_link->dc;
1361
1362 /* only check phy used by dsc mst branch */
1363 if (dc_link->type != dc_connection_mst_branch)
1364 goto out;
1365
1366 /* add a check for older MST DSC with no virtual DPCDs */
1367 if (needs_dsc_aux_workaround(dc_link) &&
1368 (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1369 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)))
1370 goto out;
1371
1372 for (i = 0; i < MAX_PIPES; i++)
1373 stream_on_link[i] = NULL;
1374
1375 DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in new dc_state\n", __func__, dc_state->stream_count);
1376
1377 /* check if there is mode change in new request */
1378 for (i = 0; i < dc_state->stream_count; i++) {
1379 struct drm_crtc_state *new_crtc_state;
1380 struct drm_connector_state *new_conn_state;
1381
1382 stream = dc_state->streams[i];
1383 if (!stream)
1384 continue;
1385
1386 DRM_DEBUG_DRIVER("%s:%d MST_DSC checking #%d stream 0x%p\n", __func__, __LINE__, i, stream);
1387
1388 /* check if stream using the same link for mst */
1389 if (stream->link != dc_link)
1390 continue;
1391
1392 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1393 if (!aconnector)
1394 continue;
1395
1396 stream_on_link[new_stream_on_link_num] = aconnector;
1397 new_stream_on_link_num++;
1398
1399 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1400 if (!new_conn_state) {
1401 DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_conn_state for stream 0x%p, aconnector 0x%p\n",
1402 __func__, __LINE__, stream, aconnector);
1403 continue;
1404 }
1405
1406 if (IS_ERR(new_conn_state))
1407 continue;
1408
1409 if (!new_conn_state->crtc)
1410 continue;
1411
1412 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1413 if (!new_crtc_state) {
1414 DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_crtc_state for crtc of stream 0x%p, aconnector 0x%p\n",
1415 __func__, __LINE__, stream, aconnector);
1416 continue;
1417 }
1418
1419 if (IS_ERR(new_crtc_state))
1420 continue;
1421
1422 if (new_crtc_state->enable && new_crtc_state->active) {
1423 if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1424 new_crtc_state->connectors_changed) {
1425 DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."
1426 "stream 0x%p in new dc_state\n",
1427 __func__, __LINE__, stream);
1428 is_dsc_need_re_compute = true;
1429 goto out;
1430 }
1431 }
1432 }
1433
1434 if (new_stream_on_link_num == 0) {
1435 DRM_DEBUG_DRIVER("%s:%d MST_DSC no mode change request for streams in new dc_state\n",
1436 __func__, __LINE__);
1437 is_dsc_need_re_compute = false;
1438 goto out;
1439 }
1440
1441 DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in current dc_state\n",
1442 __func__, dc->current_state->stream_count);
1443
1444 /* check current_state if there stream on link but it is not in
1445 * new request state
1446 */
1447 for (i = 0; i < dc->current_state->stream_count; i++) {
1448 stream = dc->current_state->streams[i];
1449 /* only check stream on the mst hub */
1450 if (stream->link != dc_link)
1451 continue;
1452
1453 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1454 if (!aconnector)
1455 continue;
1456
1457 for (j = 0; j < new_stream_on_link_num; j++) {
1458 if (stream_on_link[j]) {
1459 if (aconnector == stream_on_link[j])
1460 break;
1461 }
1462 }
1463
1464 if (j == new_stream_on_link_num) {
1465 /* not in new state */
1466 DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required."
1467 "stream 0x%p in current dc_state but not in new dc_state\n",
1468 __func__, __LINE__, stream);
1469 is_dsc_need_re_compute = true;
1470 break;
1471 }
1472 }
1473
1474 out:
1475 DRM_DEBUG_DRIVER("%s: MST_DSC dsc recompute %s\n",
1476 __func__, is_dsc_need_re_compute ? "required" : "not required");
1477
1478 return is_dsc_need_re_compute;
1479 }
1480
compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1481 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1482 struct dc_state *dc_state,
1483 struct dsc_mst_fairness_vars *vars)
1484 {
1485 int i, j;
1486 struct dc_stream_state *stream;
1487 bool computed_streams[MAX_PIPES];
1488 struct amdgpu_dm_connector *aconnector;
1489 struct drm_dp_mst_topology_mgr *mst_mgr;
1490 struct resource_pool *res_pool;
1491 int link_vars_start_index = 0;
1492 int ret = 0;
1493
1494 for (i = 0; i < dc_state->stream_count; i++)
1495 computed_streams[i] = false;
1496
1497 for (i = 0; i < dc_state->stream_count; i++) {
1498 stream = dc_state->streams[i];
1499 res_pool = stream->ctx->dc->res_pool;
1500
1501 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1502 continue;
1503
1504 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1505
1506 DRM_DEBUG_DRIVER("%s: MST_DSC compute mst dsc configs for stream 0x%p, aconnector 0x%p\n",
1507 __func__, stream, aconnector);
1508
1509 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1510 continue;
1511
1512 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1513 continue;
1514
1515 if (computed_streams[i])
1516 continue;
1517
1518 if (res_pool->funcs->remove_stream_from_ctx &&
1519 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1520 return -EINVAL;
1521
1522 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1523 continue;
1524
1525 mst_mgr = aconnector->mst_output_port->mgr;
1526 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1527 &link_vars_start_index);
1528 if (ret != 0)
1529 return ret;
1530
1531 for (j = 0; j < dc_state->stream_count; j++) {
1532 if (dc_state->streams[j]->link == stream->link)
1533 computed_streams[j] = true;
1534 }
1535 }
1536
1537 for (i = 0; i < dc_state->stream_count; i++) {
1538 stream = dc_state->streams[i];
1539
1540 if (stream->timing.flags.DSC == 1)
1541 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) {
1542 DRM_DEBUG_DRIVER("%s:%d MST_DSC Failed to request dsc hw resource for stream 0x%p\n",
1543 __func__, __LINE__, stream);
1544 return -EINVAL;
1545 }
1546 }
1547
1548 return ret;
1549 }
1550
pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state,struct dsc_mst_fairness_vars * vars)1551 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1552 struct dc_state *dc_state,
1553 struct dsc_mst_fairness_vars *vars)
1554 {
1555 int i, j;
1556 struct dc_stream_state *stream;
1557 bool computed_streams[MAX_PIPES];
1558 struct amdgpu_dm_connector *aconnector;
1559 struct drm_dp_mst_topology_mgr *mst_mgr;
1560 int link_vars_start_index = 0;
1561 int ret = 0;
1562
1563 for (i = 0; i < dc_state->stream_count; i++)
1564 computed_streams[i] = false;
1565
1566 for (i = 0; i < dc_state->stream_count; i++) {
1567 stream = dc_state->streams[i];
1568
1569 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1570 continue;
1571
1572 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1573
1574 DRM_DEBUG_DRIVER("MST_DSC pre compute mst dsc configs for #%d stream 0x%p, aconnector 0x%p\n",
1575 i, stream, aconnector);
1576
1577 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1578 continue;
1579
1580 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1581 continue;
1582
1583 if (computed_streams[i])
1584 continue;
1585
1586 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1587 continue;
1588
1589 mst_mgr = aconnector->mst_output_port->mgr;
1590 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1591 &link_vars_start_index);
1592 if (ret != 0)
1593 return ret;
1594
1595 for (j = 0; j < dc_state->stream_count; j++) {
1596 if (dc_state->streams[j]->link == stream->link)
1597 computed_streams[j] = true;
1598 }
1599 }
1600
1601 return ret;
1602 }
1603
find_crtc_index_in_state_by_stream(struct drm_atomic_state * state,struct dc_stream_state * stream)1604 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
1605 struct dc_stream_state *stream)
1606 {
1607 int i;
1608 struct drm_crtc *crtc;
1609 struct drm_crtc_state *new_state, *old_state;
1610
1611 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
1612 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
1613
1614 if (dm_state->stream == stream)
1615 return i;
1616 }
1617 return -1;
1618 }
1619
is_link_to_dschub(struct dc_link * dc_link)1620 static bool is_link_to_dschub(struct dc_link *dc_link)
1621 {
1622 union dpcd_dsc_basic_capabilities *dsc_caps =
1623 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1624
1625 /* only check phy used by dsc mst branch */
1626 if (dc_link->type != dc_connection_mst_branch)
1627 return false;
1628
1629 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1630 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1631 return false;
1632 return true;
1633 }
1634
is_dsc_precompute_needed(struct drm_atomic_state * state)1635 static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
1636 {
1637 int i;
1638 struct drm_crtc *crtc;
1639 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1640 bool ret = false;
1641
1642 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1643 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
1644
1645 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1646 ret = false;
1647 break;
1648 }
1649 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1650 if (is_link_to_dschub(dm_crtc_state->stream->link))
1651 ret = true;
1652 }
1653 return ret;
1654 }
1655
pre_validate_dsc(struct drm_atomic_state * state,struct dm_atomic_state ** dm_state_ptr,struct dsc_mst_fairness_vars * vars)1656 int pre_validate_dsc(struct drm_atomic_state *state,
1657 struct dm_atomic_state **dm_state_ptr,
1658 struct dsc_mst_fairness_vars *vars)
1659 {
1660 int i;
1661 struct dm_atomic_state *dm_state;
1662 struct dc_state *local_dc_state = NULL;
1663 int ret = 0;
1664
1665 if (!is_dsc_precompute_needed(state)) {
1666 DRM_INFO_ONCE("%s:%d MST_DSC dsc precompute is not needed\n", __func__, __LINE__);
1667 return 0;
1668 }
1669 ret = dm_atomic_get_state(state, dm_state_ptr);
1670 if (ret != 0) {
1671 DRM_INFO_ONCE("%s:%d MST_DSC dm_atomic_get_state() failed\n", __func__, __LINE__);
1672 return ret;
1673 }
1674 dm_state = *dm_state_ptr;
1675
1676 /*
1677 * create local vailable for dc_state. copy content of streams of dm_state->context
1678 * to local variable. make sure stream pointer of local variable not the same as stream
1679 * from dm_state->context.
1680 */
1681
1682 local_dc_state = vmalloc(sizeof(struct dc_state));
1683 if (!local_dc_state)
1684 return -ENOMEM;
1685 memcpy(local_dc_state, dm_state->context, sizeof(struct dc_state));
1686
1687 for (i = 0; i < local_dc_state->stream_count; i++) {
1688 struct dc_stream_state *stream = dm_state->context->streams[i];
1689 int ind = find_crtc_index_in_state_by_stream(state, stream);
1690
1691 if (ind >= 0) {
1692 struct drm_connector *connector;
1693 struct drm_connector_state *drm_new_conn_state;
1694 struct dm_connector_state *dm_new_conn_state;
1695 struct dm_crtc_state *dm_old_crtc_state;
1696
1697 connector =
1698 amdgpu_dm_find_first_crtc_matching_connector(state,
1699 state->crtcs[ind].ptr);
1700 if (!connector)
1701 continue;
1702
1703 drm_new_conn_state =
1704 drm_atomic_get_new_connector_state(state,
1705 connector);
1706 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
1707 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
1708
1709 local_dc_state->streams[i] =
1710 create_validate_stream_for_sink(connector,
1711 &state->crtcs[ind].new_state->mode,
1712 dm_new_conn_state,
1713 dm_old_crtc_state->stream);
1714 if (local_dc_state->streams[i] == NULL) {
1715 ret = -EINVAL;
1716 break;
1717 }
1718 }
1719 }
1720
1721 if (ret != 0)
1722 goto clean_exit;
1723
1724 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);
1725 if (ret != 0) {
1726 DRM_INFO_ONCE("%s:%d MST_DSC dsc pre_compute_mst_dsc_configs_for_state() failed\n",
1727 __func__, __LINE__);
1728 ret = -EINVAL;
1729 goto clean_exit;
1730 }
1731
1732 /*
1733 * compare local_streams -> timing with dm_state->context,
1734 * if the same set crtc_state->mode-change = 0;
1735 */
1736 for (i = 0; i < local_dc_state->stream_count; i++) {
1737 struct dc_stream_state *stream = dm_state->context->streams[i];
1738
1739 if (local_dc_state->streams[i] &&
1740 dc_is_timing_changed(stream, local_dc_state->streams[i])) {
1741 DRM_INFO_ONCE("%s:%d MST_DSC crtc[%d] needs mode_change\n", __func__, __LINE__, i);
1742 } else {
1743 int ind = find_crtc_index_in_state_by_stream(state, stream);
1744
1745 if (ind >= 0) {
1746 DRM_INFO_ONCE("%s:%d MST_DSC no mode changed for stream 0x%p\n",
1747 __func__, __LINE__, stream);
1748 state->crtcs[ind].new_state->mode_changed = 0;
1749 }
1750 }
1751 }
1752 clean_exit:
1753 for (i = 0; i < local_dc_state->stream_count; i++) {
1754 struct dc_stream_state *stream = dm_state->context->streams[i];
1755
1756 if (local_dc_state->streams[i] != stream)
1757 dc_stream_release(local_dc_state->streams[i]);
1758 }
1759
1760 vfree(local_dc_state);
1761
1762 return ret;
1763 }
1764
is_dsc_common_config_possible(struct dc_stream_state * stream,struct dc_dsc_bw_range * bw_range)1765 static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1766 struct dc_dsc_bw_range *bw_range)
1767 {
1768 struct dc_dsc_policy dsc_policy = {0};
1769 bool is_dsc_possible;
1770
1771 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link));
1772 is_dsc_possible = dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1773 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1774 dsc_policy.min_target_bpp * 16,
1775 dsc_policy.max_target_bpp * 16,
1776 &stream->sink->dsc_caps.dsc_dec_caps,
1777 &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);
1778
1779 return is_dsc_possible;
1780 }
1781 #endif
1782
1783 #if defined(CONFIG_DRM_AMD_DC_FP)
dp_get_link_current_set_bw(struct drm_dp_aux * aux,uint32_t * cur_link_bw)1784 static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw)
1785 {
1786 uint32_t total_data_bw_efficiency_x10000 = 0;
1787 uint32_t link_rate_per_lane_kbps = 0;
1788 enum dc_link_rate link_rate;
1789 union lane_count_set lane_count;
1790 u8 dp_link_encoding;
1791 u8 link_bw_set = 0;
1792 u8 data[16] = {0};
1793
1794 *cur_link_bw = 0;
1795
1796 if (drm_dp_dpcd_read(aux, DP_LINK_BW_SET, data, 16) != 16)
1797 return false;
1798
1799 dp_link_encoding = data[DP_MAIN_LINK_CHANNEL_CODING_SET - DP_LINK_BW_SET];
1800 link_bw_set = data[DP_LINK_BW_SET - DP_LINK_BW_SET];
1801 lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET];
1802
1803 drm_dbg_dp(aux->drm_dev, "MST_DSC downlink setting: %d, 0x%x x %d\n",
1804 dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET);
1805
1806 switch (dp_link_encoding) {
1807 case DP_8b_10b_ENCODING:
1808 link_rate = link_bw_set;
1809 link_rate_per_lane_kbps = link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
1810 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
1811 total_data_bw_efficiency_x10000 /= 100;
1812 total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
1813 break;
1814 case DP_128b_132b_ENCODING:
1815 switch (link_bw_set) {
1816 case DP_LINK_BW_10:
1817 link_rate = LINK_RATE_UHBR10;
1818 break;
1819 case DP_LINK_BW_13_5:
1820 link_rate = LINK_RATE_UHBR13_5;
1821 break;
1822 case DP_LINK_BW_20:
1823 link_rate = LINK_RATE_UHBR20;
1824 break;
1825 default:
1826 return false;
1827 }
1828
1829 link_rate_per_lane_kbps = link_rate * 10000;
1830 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
1831 break;
1832 default:
1833 return false;
1834 }
1835
1836 *cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_efficiency_x10000;
1837 return true;
1838 }
1839 #endif
1840
dm_dp_mst_is_port_support_mode(struct amdgpu_dm_connector * aconnector,struct dc_stream_state * stream)1841 enum dc_status dm_dp_mst_is_port_support_mode(
1842 struct amdgpu_dm_connector *aconnector,
1843 struct dc_stream_state *stream)
1844 {
1845 #if defined(CONFIG_DRM_AMD_DC_FP)
1846 int branch_max_throughput_mps = 0;
1847 struct dc_link_settings cur_link_settings;
1848 uint32_t end_to_end_bw_in_kbps = 0;
1849 uint32_t root_link_bw_in_kbps = 0;
1850 uint32_t virtual_channel_bw_in_kbps = 0;
1851 struct dc_dsc_bw_range bw_range = {0};
1852 struct dc_dsc_config_options dsc_options = {0};
1853 uint32_t stream_kbps;
1854
1855 /* DSC unnecessary case
1856 * Check if timing could be supported within end-to-end BW
1857 */
1858 stream_kbps =
1859 dc_bandwidth_in_kbps_from_timing(&stream->timing,
1860 dc_link_get_highest_encoding_format(stream->link));
1861 cur_link_settings = stream->link->verified_link_cap;
1862 root_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, &cur_link_settings);
1863 virtual_channel_bw_in_kbps = pbn_to_kbps(aconnector->mst_output_port->full_pbn, true);
1864
1865 /* pick the end to end bw bottleneck */
1866 end_to_end_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
1867
1868 if (stream_kbps <= end_to_end_bw_in_kbps) {
1869 DRM_DEBUG_DRIVER("MST_DSC no dsc required. End-to-end bw sufficient\n");
1870 return DC_OK;
1871 }
1872
1873 /*DSC necessary case*/
1874 if (!aconnector->dsc_aux)
1875 return DC_FAIL_BANDWIDTH_VALIDATE;
1876
1877 if (is_dsc_common_config_possible(stream, &bw_range)) {
1878
1879 /*capable of dsc passthough. dsc bitstream along the entire path*/
1880 if (aconnector->mst_output_port->passthrough_aux) {
1881 if (bw_range.min_kbps > end_to_end_bw_in_kbps) {
1882 DRM_DEBUG_DRIVER("MST_DSC dsc passthrough and decode at endpoint"
1883 "Max dsc compression bw can't fit into end-to-end bw\n");
1884 return DC_FAIL_BANDWIDTH_VALIDATE;
1885 }
1886 } else {
1887 /*dsc bitstream decoded at the dp last link*/
1888 struct drm_dp_mst_port *immediate_upstream_port = NULL;
1889 uint32_t end_link_bw = 0;
1890
1891 /*Get last DP link BW capability. Mode shall be supported by Legacy peer*/
1892 if (aconnector->mst_output_port->pdt != DP_PEER_DEVICE_DP_LEGACY_CONV &&
1893 aconnector->mst_output_port->pdt != DP_PEER_DEVICE_NONE) {
1894 if (aconnector->vc_full_pbn != aconnector->mst_output_port->full_pbn) {
1895 dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw);
1896 aconnector->vc_full_pbn = aconnector->mst_output_port->full_pbn;
1897 aconnector->mst_local_bw = end_link_bw;
1898 } else {
1899 end_link_bw = aconnector->mst_local_bw;
1900 }
1901
1902 if (end_link_bw > 0 &&
1903 stream_kbps > end_link_bw &&
1904 aconnector->branch_ieee_oui != DP_BRANCH_DEVICE_ID_90CC24) {
1905 DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link. "
1906 "Mode required bw can't fit into last link\n");
1907 return DC_FAIL_BANDWIDTH_VALIDATE;
1908 }
1909 }
1910
1911 /*Get virtual channel bandwidth between source and the link before the last link*/
1912 if (aconnector->mst_output_port->parent->port_parent)
1913 immediate_upstream_port = aconnector->mst_output_port->parent->port_parent;
1914
1915 if (immediate_upstream_port) {
1916 virtual_channel_bw_in_kbps = pbn_to_kbps(immediate_upstream_port->full_pbn, true);
1917 virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
1918 } else {
1919 /* For topology LCT 1 case - only one mstb*/
1920 virtual_channel_bw_in_kbps = root_link_bw_in_kbps;
1921 }
1922
1923 if (bw_range.min_kbps > virtual_channel_bw_in_kbps) {
1924 DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
1925 "Max dsc compression can't fit into MST available bw\n");
1926 return DC_FAIL_BANDWIDTH_VALIDATE;
1927 }
1928 }
1929
1930 /*Confirm if we can obtain dsc config*/
1931 dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);
1932 dsc_options.max_target_bpp_limit_override_x16 = aconnector->base.display_info.max_dsc_bpp * 16;
1933 if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],
1934 &stream->sink->dsc_caps.dsc_dec_caps,
1935 &dsc_options,
1936 end_to_end_bw_in_kbps,
1937 &stream->timing,
1938 dc_link_get_highest_encoding_format(stream->link),
1939 &stream->timing.dsc_cfg)) {
1940 stream->timing.flags.DSC = 1;
1941 DRM_DEBUG_DRIVER("MST_DSC require dsc and dsc config found\n");
1942 } else {
1943 DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find appropriate dsc config\n");
1944 return DC_FAIL_BANDWIDTH_VALIDATE;
1945 }
1946
1947 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
1948 switch (stream->timing.pixel_encoding) {
1949 case PIXEL_ENCODING_RGB:
1950 case PIXEL_ENCODING_YCBCR444:
1951 branch_max_throughput_mps =
1952 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
1953 break;
1954 case PIXEL_ENCODING_YCBCR422:
1955 case PIXEL_ENCODING_YCBCR420:
1956 branch_max_throughput_mps =
1957 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
1958 break;
1959 default:
1960 break;
1961 }
1962
1963 if (branch_max_throughput_mps != 0 &&
1964 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) {
1965 DRM_DEBUG_DRIVER("MST_DSC require dsc but max throughput mps fails\n");
1966 return DC_FAIL_BANDWIDTH_VALIDATE;
1967 }
1968 } else {
1969 DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n");
1970 return DC_FAIL_BANDWIDTH_VALIDATE;
1971 }
1972 #endif
1973 return DC_OK;
1974 }
1975