1 /*- 2 * Broadcom NetXtreme-C/E network driver. 3 * 4 * Copyright (c) 2016 Broadcom, All Rights Reserved. 5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #ifndef _BNXT_H 31 #define _BNXT_H 32 33 #include <sys/param.h> 34 #include <sys/socket.h> 35 #include <sys/sysctl.h> 36 #include <sys/taskqueue.h> 37 #include <sys/bitstring.h> 38 39 #include <machine/bus.h> 40 41 #include <net/ethernet.h> 42 #include <net/if.h> 43 #include <net/if_var.h> 44 #include <net/iflib.h> 45 #include <linux/types.h> 46 47 #include "hsi_struct_def.h" 48 #include "bnxt_dcb.h" 49 #include "bnxt_auxbus_compat.h" 50 #include "bnxt_sriov.h" 51 52 #define DFLT_HWRM_CMD_TIMEOUT 500 53 54 /* PCI IDs */ 55 #define BROADCOM_VENDOR_ID 0x14E4 56 57 #define BCM57301 0x16c8 58 #define BCM57302 0x16c9 59 #define BCM57304 0x16ca 60 #define BCM57311 0x16ce 61 #define BCM57312 0x16cf 62 #define BCM57314 0x16df 63 #define BCM57402 0x16d0 64 #define BCM57402_NPAR 0x16d4 65 #define BCM57404 0x16d1 66 #define BCM57404_NPAR 0x16e7 67 #define BCM57406 0x16d2 68 #define BCM57406_NPAR 0x16e8 69 #define BCM57407 0x16d5 70 #define BCM57407_NPAR 0x16ea 71 #define BCM57407_SFP 0x16e9 72 #define BCM57412 0x16d6 73 #define BCM57412_NPAR1 0x16de 74 #define BCM57412_NPAR2 0x16eb 75 #define BCM57414 0x16d7 76 #define BCM57414_NPAR1 0x16ec 77 #define BCM57414_NPAR2 0x16ed 78 #define BCM57416 0x16d8 79 #define BCM57416_NPAR1 0x16ee 80 #define BCM57416_NPAR2 0x16ef 81 #define BCM57416_SFP 0x16e3 82 #define BCM57417 0x16d9 83 #define BCM57417_NPAR1 0x16c0 84 #define BCM57417_NPAR2 0x16cc 85 #define BCM57417_SFP 0x16e2 86 #define BCM57454 0x1614 87 #define BCM58700 0x16cd 88 #define BCM57508 0x1750 89 #define BCM57504 0x1751 90 #define BCM57504_NPAR 0x1801 91 #define BCM57502 0x1752 92 #define BCM57608 0x1760 93 #define BCM57604 0x1761 94 #define BCM57602 0x1762 95 #define BCM57601 0x1763 96 #define NETXTREME_C_VF1 0x16cb 97 #define NETXTREME_C_VF2 0x16e1 98 #define NETXTREME_C_VF3 0x16e5 99 100 #define NETXTREME_E_VF1 0x1606 101 #define NETXTREME_E_VF2 0x1609 102 #define NETXTREME_E_VF3 0x16c1 103 #define NETXTREME_E_VF4 0x16d3 104 #define NETXTREME_E_VF5 0x16dc 105 106 #define NETXTREME_E_P5_VF1 0x1806 107 #define NETXTREME_E_P5_VF2 0x1807 108 #define NETXTREME_E_P5_VF_HV1 0x1808 109 #define NETXTREME_E_P5_VF_HV2 0x1809 110 #define E_P7_VF 0x1819 111 112 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \ 113 (((data1) & \ 114 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ 115 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL) 116 117 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ 118 (((data1) & \ 119 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >> \ 120 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) 121 122 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \ 123 (((data2) & \ 124 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >> \ 125 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT) 126 127 #define BNXT_EVENT_DBR_EPOCH(data) \ 128 (((data) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK) >> \ 129 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT) 130 131 #define BNXT_EVENT_THERMAL_THRESHOLD_TEMP(data2) \ 132 (((data2) & \ 133 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK) >> \ 134 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT) 135 136 #define EVENT_DATA2_NVM_ERR_ADDR(data2) \ 137 (((data2) & \ 138 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK) >> \ 139 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT) 140 141 #define EVENT_DATA1_THERMAL_THRESHOLD_DIR_INCREASING(data1) \ 142 (((data1) & \ 143 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR) == \ 144 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING) 145 146 #define EVENT_DATA1_NVM_ERR_TYPE_WRITE(data1) \ 147 (((data1) & \ 148 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ 149 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE) 150 151 #define EVENT_DATA1_NVM_ERR_TYPE_ERASE(data1) \ 152 (((data1) & \ 153 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ 154 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE) 155 156 #define EVENT_DATA1_THERMAL_THRESHOLD_TYPE(data1) \ 157 ((data1) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK) 158 159 #define BNXT_EVENT_THERMAL_CURRENT_TEMP(data2) \ 160 ((data2) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK) 161 162 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \ 163 (((data1) & \ 164 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ 165 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION) 166 167 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \ 168 ((data2) & \ 169 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK) 170 171 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \ 172 !!((data1) & \ 173 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED) 174 175 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \ 176 !!((data1) & \ 177 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC) 178 179 #define INVALID_STATS_CTX_ID -1 180 181 /* Maximum numbers of RX and TX descriptors. iflib requires this to be a power 182 * of two. The hardware has no particular limitation. */ 183 #define BNXT_MAX_RXD ((INT32_MAX >> 1) + 1) 184 #define BNXT_MAX_TXD ((INT32_MAX >> 1) + 1) 185 186 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 187 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 188 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 189 190 #define BNXT_MAX_MTU 9600 191 192 #define BNXT_RSS_HASH_TYPE_TCPV4 0 193 #define BNXT_RSS_HASH_TYPE_UDPV4 1 194 #define BNXT_RSS_HASH_TYPE_IPV4 2 195 #define BNXT_RSS_HASH_TYPE_TCPV6 3 196 #define BNXT_RSS_HASH_TYPE_UDPV6 4 197 #define BNXT_RSS_HASH_TYPE_IPV6 5 198 #define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F) 199 200 #define BNXT_NO_MORE_WOL_FILTERS 0xFFFF 201 #define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \ 202 ((softc)->flags & BNXT_FLAG_WOL_CAP )) 203 /* 64-bit doorbell */ 204 #define DBR_INDEX_MASK 0x0000000000ffffffULL 205 #define DBR_PI_LO_MASK 0xff000000UL 206 #define DBR_PI_LO_SFT 24 207 #define DBR_EPOCH_MASK 0x01000000UL 208 #define DBR_EPOCH_SFT 24 209 #define DBR_TOGGLE_MASK 0x06000000UL 210 #define DBR_TOGGLE_SFT 25 211 #define DBR_XID_MASK 0x000fffff00000000ULL 212 #define DBR_XID_SFT 32 213 #define DBR_PI_HI_MASK 0xf0000000000000ULL 214 #define DBR_PI_HI_SFT 52 215 #define DBR_PATH_L2 (0x1ULL << 56) 216 #define DBR_VALID (0x1ULL << 58) 217 #define DBR_TYPE_SQ (0x0ULL << 60) 218 #define DBR_TYPE_RQ (0x1ULL << 60) 219 #define DBR_TYPE_SRQ (0x2ULL << 60) 220 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) 221 #define DBR_TYPE_CQ (0x4ULL << 60) 222 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) 223 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) 224 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) 225 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) 226 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) 227 #define DBR_TYPE_NQ (0xaULL << 60) 228 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 229 #define DBR_TYPE_PUSH_START (0xcULL << 60) 230 #define DBR_TYPE_PUSH_END (0xdULL << 60) 231 #define DBR_TYPE_NQ_MASK (0xeULL << 60) 232 #define DBR_TYPE_NULL (0xfULL << 60) 233 234 #define BNXT_MAX_L2_QUEUES 128 235 #define BNXT_ROCE_IRQ_COUNT 9 236 237 #define BNXT_MAX_NUM_QUEUES (BNXT_MAX_L2_QUEUES + BNXT_ROCE_IRQ_COUNT) 238 239 /* Completion related defines */ 240 #define CMP_VALID(cmp, v_bit) \ 241 ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) ) 242 243 /* Chip class phase 5 */ 244 #define BNXT_CHIP_P5(sc) ((sc->flags & BNXT_FLAG_CHIP_P5)) 245 246 /* Chip class phase 7 */ 247 #define BNXT_CHIP_P7(sc) ((sc->flags & BNXT_FLAG_CHIP_P7)) 248 249 /* Chip class phase 5 plus */ 250 #define BNXT_CHIP_P5_PLUS(sc) \ 251 (BNXT_CHIP_P5(sc) || BNXT_CHIP_P7(sc)) 252 253 #define DB_PF_OFFSET_P5 0x10000 254 #define DB_VF_OFFSET_P5 0x4000 255 #define NQ_VALID(cmp, v_bit) \ 256 ((!!(((nq_cn_t *)(cmp))->v & htole32(NQ_CN_V))) == !!(v_bit) ) 257 258 #ifndef DIV_ROUND_UP 259 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 260 #endif 261 #ifndef roundup 262 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 263 #endif 264 265 #define NEXT_CP_CONS_V(ring, cons, v_bit) do { \ 266 if (__predict_false(++(cons) == (ring)->ring_size)) \ 267 ((cons) = 0, (v_bit) = !v_bit); \ 268 } while (0) 269 270 #define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \ 271 0 : idx + 1) 272 273 #define CMPL_PREFETCH_NEXT(cpr, idx) \ 274 __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\ 275 (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \ 276 ((cpr)->ring.ring_size - 1)]) 277 278 /* Lock macros */ 279 #define BNXT_HWRM_LOCK_INIT(_softc, _name) \ 280 mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF) 281 #define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock) 282 #define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock) 283 #define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock) 284 #define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ 285 MA_OWNED) 286 #define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \ 287 ((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \ 288 (link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \ 289 (link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg)) 290 291 /* Chip info */ 292 #define BNXT_TSO_SIZE UINT16_MAX 293 294 #define min_t(type, x, y) ({ \ 295 type __min1 = (x); \ 296 type __min2 = (y); \ 297 __min1 < __min2 ? __min1 : __min2; }) 298 299 #define max_t(type, x, y) ({ \ 300 type __max1 = (x); \ 301 type __max2 = (y); \ 302 __max1 > __max2 ? __max1 : __max2; }) 303 304 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 305 306 #define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \ 307 if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \ 308 ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \ 309 } while(0) 310 311 #define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */ 312 313 #define BNXT_RX_STATS_EXT_OFFSET(counter) \ 314 (offsetof(struct rx_port_stats_ext, counter) / 8) 315 316 #define BNXT_RX_STATS_EXT_NUM_LEGACY \ 317 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks) 318 319 #define BNXT_TX_STATS_EXT_OFFSET(counter) \ 320 (offsetof(struct tx_port_stats_ext, counter) / 8) 321 322 extern const char bnxt_driver_version[]; 323 typedef void (*bnxt_doorbell_tx)(void *, uint16_t idx); 324 typedef void (*bnxt_doorbell_rx)(void *, uint16_t idx); 325 typedef void (*bnxt_doorbell_rx_cq)(void *, bool); 326 typedef void (*bnxt_doorbell_tx_cq)(void *, bool); 327 typedef void (*bnxt_doorbell_nq)(void *, bool); 328 329 typedef struct bnxt_doorbell_ops { 330 bnxt_doorbell_tx bnxt_db_tx; 331 bnxt_doorbell_rx bnxt_db_rx; 332 bnxt_doorbell_rx_cq bnxt_db_rx_cq; 333 bnxt_doorbell_tx_cq bnxt_db_tx_cq; 334 bnxt_doorbell_nq bnxt_db_nq; 335 } bnxt_dooorbell_ops_t; 336 /* NVRAM access */ 337 enum bnxt_nvm_directory_type { 338 BNX_DIR_TYPE_UNUSED = 0, 339 BNX_DIR_TYPE_PKG_LOG = 1, 340 BNX_DIR_TYPE_UPDATE = 2, 341 BNX_DIR_TYPE_CHIMP_PATCH = 3, 342 BNX_DIR_TYPE_BOOTCODE = 4, 343 BNX_DIR_TYPE_VPD = 5, 344 BNX_DIR_TYPE_EXP_ROM_MBA = 6, 345 BNX_DIR_TYPE_AVS = 7, 346 BNX_DIR_TYPE_PCIE = 8, 347 BNX_DIR_TYPE_PORT_MACRO = 9, 348 BNX_DIR_TYPE_APE_FW = 10, 349 BNX_DIR_TYPE_APE_PATCH = 11, 350 BNX_DIR_TYPE_KONG_FW = 12, 351 BNX_DIR_TYPE_KONG_PATCH = 13, 352 BNX_DIR_TYPE_BONO_FW = 14, 353 BNX_DIR_TYPE_BONO_PATCH = 15, 354 BNX_DIR_TYPE_TANG_FW = 16, 355 BNX_DIR_TYPE_TANG_PATCH = 17, 356 BNX_DIR_TYPE_BOOTCODE_2 = 18, 357 BNX_DIR_TYPE_CCM = 19, 358 BNX_DIR_TYPE_PCI_CFG = 20, 359 BNX_DIR_TYPE_TSCF_UCODE = 21, 360 BNX_DIR_TYPE_ISCSI_BOOT = 22, 361 BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, 362 BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, 363 BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, 364 BNX_DIR_TYPE_EXT_PHY = 27, 365 BNX_DIR_TYPE_SHARED_CFG = 40, 366 BNX_DIR_TYPE_PORT_CFG = 41, 367 BNX_DIR_TYPE_FUNC_CFG = 42, 368 BNX_DIR_TYPE_MGMT_CFG = 48, 369 BNX_DIR_TYPE_MGMT_DATA = 49, 370 BNX_DIR_TYPE_MGMT_WEB_DATA = 50, 371 BNX_DIR_TYPE_MGMT_WEB_META = 51, 372 BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, 373 BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 374 }; 375 376 enum bnxnvm_pkglog_field_index { 377 BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, 378 BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, 379 BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, 380 BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, 381 BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, 382 BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, 383 BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 384 }; 385 386 #define BNX_DIR_ORDINAL_FIRST 0 387 #define BNX_DIR_EXT_NONE 0 388 389 struct bnxt_bar_info { 390 struct resource *res; 391 bus_space_tag_t tag; 392 bus_space_handle_t handle; 393 bus_size_t size; 394 int rid; 395 }; 396 397 struct bnxt_flow_ctrl { 398 bool rx; 399 bool tx; 400 bool autoneg; 401 }; 402 403 struct bnxt_link_info { 404 uint8_t media_type; 405 uint8_t transceiver; 406 uint8_t phy_addr; 407 uint8_t phy_link_status; 408 uint8_t wire_speed; 409 uint8_t loop_back; 410 uint8_t link_up; 411 uint8_t last_link_up; 412 uint8_t duplex; 413 uint8_t last_duplex; 414 uint8_t last_phy_type; 415 struct bnxt_flow_ctrl flow_ctrl; 416 struct bnxt_flow_ctrl last_flow_ctrl; 417 uint8_t duplex_setting; 418 uint8_t auto_mode; 419 #define PHY_VER_LEN 3 420 uint8_t phy_ver[PHY_VER_LEN]; 421 uint8_t phy_type; 422 #define BNXT_PHY_STATE_ENABLED 0 423 #define BNXT_PHY_STATE_DISABLED 1 424 uint8_t phy_state; 425 426 uint16_t link_speed; 427 uint16_t support_speeds; 428 uint16_t support_speeds2; 429 uint16_t support_pam4_speeds; 430 uint16_t auto_link_speeds; 431 uint16_t auto_link_speeds2; 432 uint16_t auto_pam4_link_speeds; 433 uint16_t force_link_speed; 434 uint16_t force_link_speeds2; 435 uint16_t force_pam4_link_speed; 436 437 bool force_pam4_speed; 438 bool force_speed2_nrz; 439 bool force_pam4_56_speed2; 440 bool force_pam4_112_speed2; 441 442 uint16_t advertising; 443 uint16_t advertising_pam4; 444 445 uint32_t preemphasis; 446 uint16_t support_auto_speeds; 447 uint16_t support_force_speeds; 448 uint16_t support_pam4_auto_speeds; 449 uint16_t support_pam4_force_speeds; 450 uint16_t support_auto_speeds2; 451 uint16_t support_force_speeds2; 452 #define BNXT_SIG_MODE_NRZ HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ 453 #define BNXT_SIG_MODE_PAM4 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 454 #define BNXT_SIG_MODE_PAM4_112 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112 455 uint8_t req_signal_mode; 456 457 uint8_t active_fec_sig_mode; 458 uint8_t sig_mode; 459 460 /* copy of requested setting */ 461 uint8_t autoneg; 462 #define BNXT_AUTONEG_SPEED 1 463 #define BNXT_AUTONEG_FLOW_CTRL 2 464 uint8_t req_duplex; 465 uint16_t req_link_speed; 466 uint8_t module_status; 467 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 468 uint8_t active_lanes; 469 }; 470 471 enum bnxt_phy_type { 472 BNXT_MEDIA_CR = 0, 473 BNXT_MEDIA_LR, 474 BNXT_MEDIA_SR, 475 BNXT_MEDIA_ER, 476 BNXT_MEDIA_KR, 477 BNXT_MEDIA_AC, 478 BNXT_MEDIA_BASECX, 479 BNXT_MEDIA_BASET, 480 BNXT_MEDIA_BASEKX, 481 BNXT_MEDIA_BASESGMII, 482 BNXT_MEDIA_END 483 }; 484 485 enum bnxt_cp_type { 486 BNXT_DEFAULT, 487 BNXT_TX, 488 BNXT_RX, 489 BNXT_SHARED 490 }; 491 492 struct bnxt_queue_info { 493 uint8_t queue_id; 494 uint8_t queue_profile; 495 }; 496 497 struct bnxt_func_info { 498 uint32_t fw_fid; 499 uint8_t mac_addr[ETHER_ADDR_LEN]; 500 uint16_t max_rsscos_ctxs; 501 uint16_t max_cp_rings; 502 uint16_t max_tx_rings; 503 uint16_t max_rx_rings; 504 uint16_t max_hw_ring_grps; 505 uint16_t max_irqs; 506 uint16_t max_l2_ctxs; 507 uint16_t max_vnics; 508 uint16_t max_stat_ctxs; 509 }; 510 511 struct bnxt_pf_info { 512 #define BNXT_FIRST_PF_FID 1 513 #define BNXT_FIRST_VF_FID 128 514 uint8_t port_id; 515 uint32_t first_vf_id; 516 uint16_t active_vfs; 517 uint16_t registered_vfs; 518 uint16_t max_vfs; 519 uint16_t max_msix_vfs; 520 uint32_t max_encap_records; 521 uint32_t max_decap_records; 522 uint32_t max_tx_em_flows; 523 uint32_t max_tx_wm_flows; 524 uint32_t max_rx_em_flows; 525 uint32_t max_rx_wm_flows; 526 unsigned long *vf_event_bmap; 527 uint16_t hwrm_cmd_req_pages; 528 void *hwrm_cmd_req_addr[4]; 529 bus_addr_t hwrm_cmd_req_dma_addr[4]; 530 uint16_t fw_fid; 531 uint8_t mac_addr[ETHER_ADDR_LEN]; 532 uint8_t vf_resv_strategy; 533 uint8_t num_vfs; 534 struct bnxt_vf_info *vf; 535 uint16_t vf_hwrm_cmd_req_page_shift; 536 struct sysctl_ctx_list sysctl_ctx; 537 struct sysctl_oid *sysctl_node; 538 }; 539 540 #define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF)) 541 #define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) 542 543 struct bnxt_vlan_tag { 544 SLIST_ENTRY(bnxt_vlan_tag) next; 545 uint64_t filter_id; 546 uint16_t tag; 547 }; 548 549 struct bnxt_vnic_info { 550 uint16_t id; 551 uint16_t def_ring_grp; 552 uint16_t cos_rule; 553 uint16_t lb_rule; 554 uint16_t mru; 555 556 uint32_t rx_mask; 557 struct iflib_dma_info mc_list; 558 int mc_list_count; 559 #define BNXT_MAX_MC_ADDRS 16 560 561 uint32_t flags; 562 #define BNXT_VNIC_FLAG_DEFAULT 0x01 563 #define BNXT_VNIC_FLAG_BD_STALL 0x02 564 #define BNXT_VNIC_FLAG_VLAN_STRIP 0x04 565 566 uint64_t filter_id; 567 568 uint16_t rss_id; 569 uint32_t rss_hash_type; 570 uint8_t rss_hash_key[HW_HASH_KEY_SIZE]; 571 struct iflib_dma_info rss_hash_key_tbl; 572 struct iflib_dma_info rss_grp_tbl; 573 SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags; 574 struct iflib_dma_info vlan_tag_list; 575 }; 576 577 struct bnxt_grp_info { 578 uint16_t stats_ctx; 579 uint16_t grp_id; 580 uint16_t rx_ring_id; 581 uint16_t cp_ring_id; 582 uint16_t ag_ring_id; 583 }; 584 585 #define EPOCH_ARR_SZ 4096 586 587 struct bnxt_ring { 588 uint64_t paddr; 589 vm_offset_t doorbell; 590 caddr_t vaddr; 591 struct bnxt_softc *softc; 592 uint32_t ring_size; /* Must be a power of two */ 593 uint16_t id; /* Logical ID */ 594 uint16_t phys_id; 595 uint16_t idx; 596 struct bnxt_full_tpa_start *tpa_start; 597 union { 598 u64 db_key64; 599 u32 db_key32; 600 }; 601 uint32_t db_ring_mask; 602 uint32_t db_epoch_mask; 603 uint8_t db_epoch_shift; 604 605 uint64_t epoch_arr[EPOCH_ARR_SZ]; 606 bool epoch_bit; 607 608 }; 609 610 struct bnxt_cp_ring { 611 struct bnxt_ring ring; 612 struct if_irq irq; 613 uint32_t cons; 614 uint32_t raw_cons; 615 bool v_bit; /* Value of valid bit */ 616 struct ctx_hw_stats *stats; 617 uint32_t stats_ctx_id; 618 uint32_t last_idx; /* Used by RX rings only 619 * set to the last read pidx 620 */ 621 uint64_t int_count; 622 uint8_t toggle; 623 uint8_t type; 624 #define Q_TYPE_TX 1 625 #define Q_TYPE_RX 2 626 }; 627 628 struct bnxt_full_tpa_start { 629 struct rx_tpa_start_cmpl low; 630 struct rx_tpa_start_cmpl_hi high; 631 }; 632 633 /* All the version information for the part */ 634 #define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */ 635 #define BNXT_NAME_SIZE 17 636 #define FW_VER_STR_LEN 32 637 #define BC_HWRM_STR_LEN 21 638 struct bnxt_ver_info { 639 uint8_t hwrm_if_major; 640 uint8_t hwrm_if_minor; 641 uint8_t hwrm_if_update; 642 char hwrm_if_ver[BNXT_VERSTR_SIZE]; 643 char driver_hwrm_if_ver[BNXT_VERSTR_SIZE]; 644 char mgmt_fw_ver[FW_VER_STR_LEN]; 645 char netctrl_fw_ver[FW_VER_STR_LEN]; 646 char roce_fw_ver[FW_VER_STR_LEN]; 647 char fw_ver_str[FW_VER_STR_LEN]; 648 char phy_ver[BNXT_VERSTR_SIZE]; 649 char pkg_ver[64]; 650 651 char hwrm_fw_name[BNXT_NAME_SIZE]; 652 char mgmt_fw_name[BNXT_NAME_SIZE]; 653 char netctrl_fw_name[BNXT_NAME_SIZE]; 654 char roce_fw_name[BNXT_NAME_SIZE]; 655 char phy_vendor[BNXT_NAME_SIZE]; 656 char phy_partnumber[BNXT_NAME_SIZE]; 657 658 uint16_t chip_num; 659 uint8_t chip_rev; 660 uint8_t chip_metal; 661 uint8_t chip_bond_id; 662 uint8_t chip_type; 663 664 uint8_t hwrm_min_major; 665 uint8_t hwrm_min_minor; 666 uint8_t hwrm_min_update; 667 uint64_t fw_ver_code; 668 #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \ 669 ((uint64_t)(maj) << 48 | (uint64_t)(min) << 32 | (uint64_t)(bld) << 16 | (rsv)) 670 #define BNXT_FW_MAJ(softc) ((softc)->ver_info->fw_ver_code >> 48) 671 #define BNXT_FW_MIN(softc) (((softc)->ver_info->fw_ver_code >> 32) & 0xffff) 672 #define BNXT_FW_BLD(softc) (((softc)->ver_info->fw_ver_code >> 16) & 0xffff) 673 #define BNXT_FW_RSV(softc) (((softc)->ver_info->fw_ver_code) & 0xffff) 674 675 struct sysctl_ctx_list ver_ctx; 676 struct sysctl_oid *ver_oid; 677 }; 678 679 struct bnxt_nvram_info { 680 uint16_t mfg_id; 681 uint16_t device_id; 682 uint32_t sector_size; 683 uint32_t size; 684 uint32_t reserved_size; 685 uint32_t available_size; 686 687 struct sysctl_ctx_list nvm_ctx; 688 struct sysctl_oid *nvm_oid; 689 }; 690 691 struct bnxt_func_qcfg { 692 uint16_t alloc_completion_rings; 693 uint16_t alloc_tx_rings; 694 uint16_t alloc_rx_rings; 695 uint16_t alloc_vnics; 696 uint16_t alloc_rss_ctx; 697 uint16_t alloc_l2_ctx; 698 uint16_t alloc_vfs; 699 uint16_t alloc_hw_ring_grps; 700 uint16_t alloc_stat_ctx; 701 uint16_t alloc_msix; 702 }; 703 704 struct bnxt_hw_lro { 705 uint16_t enable; 706 uint16_t is_mode_gro; 707 uint16_t max_agg_segs; 708 uint16_t max_aggs; 709 uint32_t min_agg_len; 710 }; 711 712 /* The hardware supports certain page sizes. Use the supported page sizes 713 * to allocate the rings. 714 */ 715 #if (PAGE_SHIFT < 12) 716 #define BNXT_PAGE_SHIFT 12 717 #elif (PAGE_SHIFT <= 13) 718 #define BNXT_PAGE_SHIFT PAGE_SHIFT 719 #elif (PAGE_SHIFT < 16) 720 #define BNXT_PAGE_SHIFT 13 721 #else 722 #define BNXT_PAGE_SHIFT 16 723 #endif 724 725 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 726 727 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 728 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) 729 730 struct bnxt_ring_mem_info { 731 int nr_pages; 732 int page_size; 733 uint16_t flags; 734 #define BNXT_RMEM_VALID_PTE_FLAG 1 735 #define BNXT_RMEM_RING_PTE_FLAG 2 736 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 737 uint16_t depth; 738 struct bnxt_ctx_mem_type *ctx_mem; 739 740 struct iflib_dma_info *pg_arr; 741 struct iflib_dma_info pg_tbl; 742 743 int vmem_size; 744 void **vmem; 745 }; 746 747 struct bnxt_ctx_pg_info { 748 uint32_t entries; 749 uint32_t nr_pages; 750 struct iflib_dma_info ctx_arr[MAX_CTX_PAGES]; 751 struct bnxt_ring_mem_info ring_mem; 752 struct bnxt_ctx_pg_info **ctx_pg_tbl; 753 }; 754 755 #define BNXT_MAX_TQM_SP_RINGS 1 756 #define BNXT_MAX_TQM_FP_LEGACY_RINGS 8 757 #define BNXT_MAX_TQM_FP_RINGS 9 758 #define BNXT_MAX_TQM_LEGACY_RINGS \ 759 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS) 760 #define BNXT_MAX_TQM_RINGS \ 761 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 762 763 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 764 #define BNXT_BACKING_STORE_CFG_LEN \ 765 sizeof(struct hwrm_func_backing_store_cfg_input) 766 767 #define BNXT_SET_CTX_PAGE_ATTR(attr) \ 768 do { \ 769 if (BNXT_PAGE_SIZE == 0x2000) \ 770 attr = HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K; \ 771 else if (BNXT_PAGE_SIZE == 0x10000) \ 772 attr = HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K; \ 773 else \ 774 attr = HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K; \ 775 } while (0) 776 777 struct bnxt_ctx_mem_type { 778 u16 type; 779 u16 entry_size; 780 u32 flags; 781 #define BNXT_CTX_MEM_TYPE_VALID HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID 782 u32 instance_bmap; 783 u8 init_value; 784 u8 entry_multiple; 785 u16 init_offset; 786 #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff 787 u32 max_entries; 788 u32 min_entries; 789 u8 last:1; 790 u8 mem_valid:1; 791 u8 split_entry_cnt; 792 #define BNXT_MAX_SPLIT_ENTRY 4 793 union { 794 struct { 795 u32 qp_l2_entries; 796 u32 qp_qp1_entries; 797 }; 798 u32 srq_l2_entries; 799 u32 cq_l2_entries; 800 u32 vnic_entries; 801 struct { 802 u32 mrav_av_entries; 803 u32 mrav_num_entries_units; 804 }; 805 u32 split[BNXT_MAX_SPLIT_ENTRY]; 806 }; 807 struct bnxt_ctx_pg_info *pg_info; 808 }; 809 810 #define BNXT_CTX_QP HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP 811 #define BNXT_CTX_SRQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ 812 #define BNXT_CTX_CQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ 813 #define BNXT_CTX_VNIC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC 814 #define BNXT_CTX_STAT HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT 815 #define BNXT_CTX_STQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING 816 #define BNXT_CTX_FTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING 817 #define BNXT_CTX_MRAV HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV 818 #define BNXT_CTX_TIM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM 819 #define BNXT_CTX_TKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC 820 #define BNXT_CTX_RKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC 821 #define BNXT_CTX_MTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING 822 #define BNXT_CTX_SQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW 823 #define BNXT_CTX_RQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW 824 #define BNXT_CTX_SRQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW 825 #define BNXT_CTX_CQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW 826 #define BNXT_CTX_QTKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC 827 #define BNXT_CTX_QRKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC 828 #define BNXT_CTX_MAX (BNXT_CTX_TIM + 1) 829 #define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1) 830 831 #define BNXT_CTX_V2_MAX (HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE + 1) 832 833 #define BNXT_CTX_SRT_TRACE \ 834 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT_TRACE 835 836 #define BNXT_CTX_SRT2_TRACE \ 837 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT2_TRACE 838 839 #define BNXT_CTX_CRT_TRACE \ 840 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT_TRACE 841 842 #define BNXT_CTX_CRT2_TRACE \ 843 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT2_TRACE 844 845 #define BNXT_CTX_RIGP0_TRACE \ 846 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RIGP0_TRACE 847 848 #define BNXT_CTX_L2_HWRM_TRACE \ 849 HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_L2_HWRM_TRACE 850 851 #define BNXT_CTX_ROCE_HWRM_TRACE \ 852 HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE 853 854 #define BNXT_CTX_INV ((u16)-1) 855 856 #define BNXT_CTX_TRACE_BUF_COUNT \ 857 (BNXT_CTX_ROCE_HWRM_TRACE - BNXT_CTX_SRT_TRACE + 1) 858 859 860 struct bnxt_ctx_mem_info { 861 u8 tqm_fp_rings_count; 862 863 u32 flags; 864 #define BNXT_CTX_FLAG_INITED 0x01 865 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX]; 866 }; 867 868 struct bnxt_hw_resc { 869 uint16_t min_rsscos_ctxs; 870 uint16_t max_rsscos_ctxs; 871 uint16_t min_cp_rings; 872 uint16_t max_cp_rings; 873 uint16_t resv_cp_rings; 874 uint16_t min_tx_rings; 875 uint16_t max_tx_rings; 876 uint16_t resv_tx_rings; 877 uint16_t max_tx_sch_inputs; 878 uint16_t min_rx_rings; 879 uint16_t max_rx_rings; 880 uint16_t resv_rx_rings; 881 uint16_t min_hw_ring_grps; 882 uint16_t max_hw_ring_grps; 883 uint16_t resv_hw_ring_grps; 884 uint16_t min_l2_ctxs; 885 uint16_t max_l2_ctxs; 886 uint16_t min_vnics; 887 uint16_t max_vnics; 888 uint16_t resv_vnics; 889 uint16_t min_stat_ctxs; 890 uint16_t max_stat_ctxs; 891 uint16_t resv_stat_ctxs; 892 uint16_t max_nqs; 893 uint16_t max_irqs; 894 uint16_t resv_irqs; 895 }; 896 897 enum bnxt_type_ets { 898 BNXT_TYPE_ETS_TSA = 0, 899 BNXT_TYPE_ETS_PRI2TC, 900 BNXT_TYPE_ETS_TCBW, 901 BNXT_TYPE_ETS_MAX 902 }; 903 904 static const char *const BNXT_ETS_TYPE_STR[] = { 905 "tsa", 906 "pri2tc", 907 "tcbw", 908 }; 909 910 static const char *const BNXT_ETS_HELP_STR[] = { 911 "X is 1 (strict), 0 (ets)", 912 "TC values for pri 0 to 7", 913 "TC BW values for pri 0 to 7, Sum should be 100", 914 }; 915 916 #define BNXT_HWRM_MAX_REQ_LEN (softc->hwrm_max_req_len) 917 918 struct bnxt_softc_list { 919 SLIST_ENTRY(bnxt_softc_list) next; 920 struct bnxt_softc *softc; 921 }; 922 923 #ifndef BIT_ULL 924 #define BIT_ULL(nr) (1ULL << (nr)) 925 #endif 926 927 struct bnxt_aux_dev { 928 struct auxiliary_device aux_dev; 929 struct bnxt_en_dev *edev; 930 int id; 931 }; 932 933 struct bnxt_msix_tbl { 934 uint32_t entry; 935 uint32_t vector; 936 }; 937 938 enum bnxt_health_severity { 939 SEVERITY_NORMAL = 0, 940 SEVERITY_WARNING, 941 SEVERITY_RECOVERABLE, 942 SEVERITY_FATAL, 943 }; 944 945 enum bnxt_health_remedy { 946 REMEDY_DEVLINK_RECOVER, 947 REMEDY_POWER_CYCLE_DEVICE, 948 REMEDY_POWER_CYCLE_HOST, 949 REMEDY_FW_UPDATE, 950 REMEDY_HW_REPLACE, 951 }; 952 953 struct bnxt_fw_health { 954 u32 flags; 955 u32 polling_dsecs; 956 u32 master_func_wait_dsecs; 957 u32 normal_func_wait_dsecs; 958 u32 post_reset_wait_dsecs; 959 u32 post_reset_max_wait_dsecs; 960 u32 regs[4]; 961 u32 mapped_regs[4]; 962 #define BNXT_FW_HEALTH_REG 0 963 #define BNXT_FW_HEARTBEAT_REG 1 964 #define BNXT_FW_RESET_CNT_REG 2 965 #define BNXT_FW_RESET_INPROG_REG 3 966 u32 fw_reset_inprog_reg_mask; 967 u32 last_fw_heartbeat; 968 u32 last_fw_reset_cnt; 969 u8 enabled:1; 970 u8 primary:1; 971 u8 status_reliable:1; 972 u8 resets_reliable:1; 973 u8 tmr_multiplier; 974 u8 tmr_counter; 975 u8 fw_reset_seq_cnt; 976 u32 fw_reset_seq_regs[16]; 977 u32 fw_reset_seq_vals[16]; 978 u32 fw_reset_seq_delay_msec[16]; 979 u32 echo_req_data1; 980 u32 echo_req_data2; 981 struct devlink_health_reporter *fw_reporter; 982 struct mutex lock; 983 enum bnxt_health_severity severity; 984 enum bnxt_health_remedy remedy; 985 u32 arrests; 986 u32 discoveries; 987 u32 survivals; 988 u32 fatalities; 989 u32 diagnoses; 990 }; 991 992 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3 993 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0 994 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1 995 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2 996 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3 997 998 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK) 999 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK) 1000 1001 #define BNXT_FW_HEALTH_WIN_BASE 0x3000 1002 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8 1003 1004 #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \ 1005 ((reg) & BNXT_GRC_OFFSET_MASK)) 1006 1007 #define BNXT_FW_STATUS_HEALTH_MSK 0xffff 1008 #define BNXT_FW_STATUS_HEALTHY 0x8000 1009 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 1010 #define BNXT_FW_STATUS_RECOVERING 0x400000 1011 1012 #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\ 1013 BNXT_FW_STATUS_HEALTHY) 1014 1015 #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \ 1016 BNXT_FW_STATUS_HEALTHY) 1017 1018 #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \ 1019 BNXT_FW_STATUS_HEALTHY) 1020 1021 #define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \ 1022 ((sts) & BNXT_FW_STATUS_RECOVERING)) 1023 1024 #define BNXT_FW_RETRY 5 1025 #define BNXT_FW_IF_RETRY 10 1026 #define BNXT_FW_SLOT_RESET_RETRY 4 1027 1028 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0 1029 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 1030 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 1031 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 1032 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ 0x488 1033 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_MSK 0xffffffUL 1034 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_SFT 0 1035 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_MSK 0x1f000000UL 1036 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_SFT 24 1037 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_MSK 0x20000000UL 1038 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_SFT 29 1039 1040 #define BNXT_GRC_REG_STATUS_P5 0x520 1041 1042 #define BNXT_GRCPF_REG_KONG_COMM 0xA00 1043 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00 1044 1045 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 1046 #define BNXT_CAG_REG_BASE 0x300000 1047 1048 #define BNXT_GRC_REG_CHIP_NUM 0x48 1049 #define BNXT_GRC_REG_BASE 0x260000 1050 1051 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c 1052 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810 1053 1054 #define BNXT_GRC_BASE_MASK 0xfffff000 1055 #define BNXT_GRC_OFFSET_MASK 0x00000ffc 1056 1057 #define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK) 1058 #define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \ 1059 NQ_CN_TOGGLE_SFT) 1060 1061 #define DB_EPOCH(ring, idx) (((idx) & (ring)->db_epoch_mask) << \ 1062 ((ring)->db_epoch_shift)) 1063 1064 #define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT) 1065 1066 #define DB_RING_IDX_CMP(ring, idx) (((idx) & (ring)->db_ring_mask) | \ 1067 DB_EPOCH(ring, idx)) 1068 1069 #define DB_RING_IDX(ring, idx, bit) (((idx) & (ring)->db_ring_mask) | \ 1070 ((bit) << (24))) 1071 1072 struct bnxt_bs_trace_info { 1073 u8 *magic_byte; 1074 #define BNXT_TRACE_BUF_MAGIC_BYTE ((uint8_t)0xBC) 1075 u32 last_offset; 1076 u8 wrapped:1; 1077 u16 ctx_type; 1078 u16 trace_type; 1079 }; 1080 1081 struct bnxt_logger; 1082 1083 struct bnxt_softc { 1084 device_t dev; 1085 if_ctx_t ctx; 1086 if_softc_ctx_t scctx; 1087 if_shared_ctx_t sctx; 1088 if_t ifp; 1089 uint32_t domain; 1090 uint32_t bus; 1091 uint32_t slot; 1092 uint32_t function; 1093 uint32_t dev_fn; 1094 struct ifmedia *media; 1095 struct bnxt_ctx_mem_info *ctx_mem; 1096 struct bnxt_hw_resc hw_resc; 1097 struct bnxt_softc_list list; 1098 1099 struct bnxt_bar_info hwrm_bar; 1100 struct bnxt_bar_info doorbell_bar; 1101 struct bnxt_link_info link_info; 1102 #define BNXT_FLAG_VF 0x0001 1103 #define BNXT_FLAG_NPAR 0x0002 1104 #define BNXT_FLAG_WOL_CAP 0x0004 1105 #define BNXT_FLAG_SHORT_CMD 0x0008 1106 #define BNXT_FLAG_FW_CAP_NEW_RM 0x0010 1107 #define BNXT_FLAG_CHIP_P5 0x0020 1108 #define BNXT_FLAG_TPA 0x0040 1109 #define BNXT_FLAG_FW_CAP_EXT_STATS 0x0080 1110 #define BNXT_FLAG_MULTI_HOST 0x0100 1111 #define BNXT_FLAG_MULTI_ROOT 0x0200 1112 #define BNXT_FLAG_ROCEV1_CAP 0x0400 1113 #define BNXT_FLAG_ROCEV2_CAP 0x0800 1114 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | BNXT_FLAG_ROCEV2_CAP) 1115 #define BNXT_FLAG_CHIP_P7 0x1000 1116 uint32_t flags; 1117 #define BNXT_STATE_LINK_CHANGE (0) 1118 #define BNXT_STATE_MAX (BNXT_STATE_LINK_CHANGE + 1) 1119 bitstr_t *state_bv; 1120 1121 uint32_t total_irqs; 1122 struct bnxt_msix_tbl *irq_tbl; 1123 1124 struct bnxt_func_info func; 1125 struct bnxt_func_qcfg fn_qcfg; 1126 struct bnxt_pf_info pf; 1127 struct bnxt_vf_info vf; 1128 struct hwrm_func_vf_resource_cfg_input vf_resc_cfg_input; 1129 1130 uint16_t hwrm_cmd_seq; 1131 uint32_t hwrm_cmd_timeo; /* milliseconds */ 1132 1133 /* DDR Crash Dump Support */ 1134 struct bnxt_ctx_pg_info *fw_crash_mem; 1135 uint32_t fw_crash_len; 1136 uint32_t fw_dbg_cap; 1137 #define BNXT_FW_DBG_CAP_CRASHDUMP_SOC 0x00000001 1138 #define BNXT_FW_DBG_CAP_CRASHDUMP_HOST 0x00000002 1139 uint16_t dump_flag; 1140 #define BNXT_DUMP_LIVE 0 1141 #define BNXT_DUMP_CRASH 1 1142 #define BNXT_DUMP_DRIVER 2 1143 #define BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE 3 1144 struct iflib_dma_info hwrm_cmd_resp; 1145 struct iflib_dma_info hwrm_short_cmd_req_addr; 1146 /* Interrupt info for HWRM */ 1147 struct if_irq irq; 1148 struct mtx hwrm_lock; 1149 struct mtx sriov_lock; 1150 uint16_t hwrm_max_req_len; 1151 uint16_t hwrm_max_ext_req_len; 1152 uint32_t hwrm_spec_code; 1153 1154 #define BNXT_MAX_QUEUE 8 1155 uint8_t max_tc; 1156 uint8_t max_lltc; 1157 struct bnxt_queue_info tx_q_info[BNXT_MAX_QUEUE]; 1158 struct bnxt_queue_info rx_q_info[BNXT_MAX_QUEUE]; 1159 uint8_t tc_to_qidx[BNXT_MAX_QUEUE]; 1160 uint8_t tx_q_ids[BNXT_MAX_QUEUE]; 1161 uint8_t rx_q_ids[BNXT_MAX_QUEUE]; 1162 uint8_t tx_max_q; 1163 uint8_t rx_max_q; 1164 uint8_t is_asym_q; 1165 1166 struct bnxt_ieee_ets *ieee_ets; 1167 struct bnxt_ieee_pfc *ieee_pfc; 1168 uint8_t dcbx_cap; 1169 uint8_t default_pri; 1170 uint8_t max_dscp_value; 1171 1172 uint64_t admin_ticks; 1173 struct iflib_dma_info hw_rx_port_stats; 1174 struct iflib_dma_info hw_tx_port_stats; 1175 struct rx_port_stats *rx_port_stats; 1176 struct tx_port_stats *tx_port_stats; 1177 1178 struct iflib_dma_info hw_tx_port_stats_ext; 1179 struct iflib_dma_info hw_rx_port_stats_ext; 1180 struct tx_port_stats_ext *tx_port_stats_ext; 1181 struct rx_port_stats_ext *rx_port_stats_ext; 1182 1183 uint16_t fw_rx_stats_ext_size; 1184 uint16_t fw_tx_stats_ext_size; 1185 uint16_t hw_ring_stats_size; 1186 1187 uint8_t tx_pri2cos_idx[8]; 1188 uint8_t rx_pri2cos_idx[8]; 1189 bool pri2cos_valid; 1190 1191 uint64_t tx_bytes_pri[8]; 1192 uint64_t tx_packets_pri[8]; 1193 uint64_t rx_bytes_pri[8]; 1194 uint64_t rx_packets_pri[8]; 1195 1196 uint8_t port_count; 1197 int num_cp_rings; 1198 1199 struct bnxt_cp_ring *nq_rings; 1200 1201 struct bnxt_ring *tx_rings; 1202 struct bnxt_cp_ring *tx_cp_rings; 1203 struct iflib_dma_info tx_stats[BNXT_MAX_NUM_QUEUES]; 1204 int ntxqsets; 1205 1206 struct bnxt_vnic_info vnic_info; 1207 struct bnxt_ring *ag_rings; 1208 struct bnxt_ring *rx_rings; 1209 struct bnxt_cp_ring *rx_cp_rings; 1210 struct bnxt_grp_info *grp_info; 1211 struct iflib_dma_info rx_stats[BNXT_MAX_NUM_QUEUES]; 1212 int nrxqsets; 1213 uint16_t rx_buf_size; 1214 1215 struct bnxt_cp_ring def_cp_ring; 1216 struct bnxt_cp_ring def_nq_ring; 1217 struct iflib_dma_info def_cp_ring_mem; 1218 struct iflib_dma_info def_nq_ring_mem; 1219 struct task def_cp_task; 1220 int db_size; 1221 int db_offset; 1222 int legacy_db_size; 1223 struct bnxt_doorbell_ops db_ops; 1224 1225 struct sysctl_ctx_list hw_stats; 1226 struct sysctl_oid *hw_stats_oid; 1227 struct sysctl_ctx_list hw_lro_ctx; 1228 struct sysctl_oid *hw_lro_oid; 1229 struct sysctl_ctx_list flow_ctrl_ctx; 1230 struct sysctl_oid *flow_ctrl_oid; 1231 struct sysctl_ctx_list dcb_ctx; 1232 struct sysctl_oid *dcb_oid; 1233 1234 struct bnxt_ver_info *ver_info; 1235 struct hwrm_ver_get_output ver_resp; 1236 struct bnxt_nvram_info *nvm_info; 1237 bool wol; 1238 bool is_dev_init; 1239 struct bnxt_hw_lro hw_lro; 1240 uint8_t wol_filter_id; 1241 uint16_t rx_coal_usecs; 1242 uint16_t rx_coal_usecs_irq; 1243 uint16_t rx_coal_frames; 1244 uint16_t rx_coal_frames_irq; 1245 uint16_t tx_coal_usecs; 1246 uint16_t tx_coal_usecs_irq; 1247 uint16_t tx_coal_frames; 1248 uint16_t tx_coal_frames_irq; 1249 1250 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) 1251 #define BNXT_DEF_STATS_COAL_TICKS 1000000 1252 #define BNXT_MIN_STATS_COAL_TICKS 250000 1253 #define BNXT_MAX_STATS_COAL_TICKS 1000000 1254 1255 uint64_t fw_cap; 1256 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0) 1257 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1) 1258 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2) 1259 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3) 1260 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4) 1261 #define BNXT_FW_CAP_LINK_ADMIN BIT_ULL(5) 1262 #define BNXT_FW_CAP_VF_RES_MIN_GUARANTEED BIT_ULL(6) 1263 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7) 1264 #define BNXT_FW_CAP_ADMIN_MTU BIT_ULL(8) 1265 #define BNXT_FW_CAP_ADMIN_PF BIT_ULL(9) 1266 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10) 1267 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11) 1268 #define BNXT_FW_CAP_VF_VNIC_NOTIFY BIT_ULL(12) 1269 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13) 1270 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14) 1271 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15) 1272 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16) 1273 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17) 1274 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18) 1275 #define BNXT_FW_CAP_SECURE_MODE BIT_ULL(19) 1276 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20) 1277 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21) 1278 #define BNXT_FW_CAP_CRASHDUMP BIT_ULL(23) 1279 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24) 1280 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25) 1281 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26) 1282 #define BNXT_FW_CAP_CFA_EEM BIT_ULL(27) 1283 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(29) 1284 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30) 1285 #define BNXT_FW_CAP_ECN_STATS BIT_ULL(31) 1286 #define BNXT_FW_CAP_TRUFLOW BIT_ULL(32) 1287 #define BNXT_FW_CAP_VF_CFG_FOR_PF BIT_ULL(33) 1288 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(34) 1289 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(35) 1290 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(36) 1291 #define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(37) 1292 #define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(38) 1293 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(39) 1294 #define BNXT_FW_CAP_TRUFLOW_EN BIT_ULL(40) 1295 #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN) 1296 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(41) 1297 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(42) 1298 #define BNXT_FW_CAP_DBR_SUPPORTED BIT_ULL(43) 1299 #define BNXT_FW_CAP_GENERIC_STATS BIT_ULL(44) 1300 #define BNXT_FW_CAP_DBR_PACING_SUPPORTED BIT_ULL(45) 1301 #define BNXT_FW_CAP_PTP_PTM BIT_ULL(46) 1302 #define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(47) 1303 #define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(48) 1304 #define BNXT_FW_CAP_RSS_TCAM BIT_ULL(49) 1305 1306 #define BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS BIT_ULL(61) 1307 #define BNXT_SW_RES_LMT(bp) ((bp)->fw_cap & BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS) 1308 1309 uint32_t lpi_tmr_lo; 1310 uint32_t lpi_tmr_hi; 1311 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */ 1312 uint16_t phy_flags; 1313 #define BNXT_PHY_FL_EEE_CAP HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED 1314 #define BNXT_PHY_FL_EXT_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED 1315 #define BNXT_PHY_FL_AN_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED 1316 #define BNXT_PHY_FL_SHARED_PORT_CFG HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED 1317 #define BNXT_PHY_FL_PORT_STATS_NO_RESET HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 1318 #define BNXT_PHY_FL_NO_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 1319 #define BNXT_PHY_FL_FW_MANAGED_LKDN HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN 1320 #define BNXT_PHY_FL_NO_FCS HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS 1321 #define BNXT_PHY_FL_NO_PAUSE (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED << 8) 1322 #define BNXT_PHY_FL_NO_PFC (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED << 8) 1323 #define BNXT_PHY_FL_BANK_SEL (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED << 8) 1324 #define BNXT_PHY_FL_SPEEDS2 (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_SPEEDS2_SUPPORTED << 8) 1325 struct bnxt_aux_dev *aux_dev; 1326 struct net_device *net_dev; 1327 struct mtx en_ops_lock; 1328 uint8_t port_partition_type; 1329 struct bnxt_en_dev *edev; 1330 unsigned long state; 1331 #define BNXT_STATE_OPEN 0 1332 #define BNXT_STATE_IN_SP_TASK 1 1333 #define BNXT_STATE_READ_STATS 2 1334 #define BNXT_STATE_FW_RESET_DET 3 1335 #define BNXT_STATE_IN_FW_RESET 4 1336 #define BNXT_STATE_ABORT_ERR 5 1337 #define BNXT_STATE_FW_FATAL_COND 6 1338 #define BNXT_STATE_DRV_REGISTERED 7 1339 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8 1340 #define BNXT_STATE_NAPI_DISABLED 9 1341 #define BNXT_STATE_L2_FILTER_RETRY 10 1342 #define BNXT_STATE_FW_ACTIVATE 11 1343 #define BNXT_STATE_RECOVER 12 1344 #define BNXT_STATE_FW_NON_FATAL_COND 13 1345 #define BNXT_STATE_FW_ACTIVATE_RESET 14 1346 #define BNXT_STATE_HALF_OPEN 15 1347 #define BNXT_NO_FW_ACCESS(bp) \ 1348 test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) 1349 struct pci_dev *pdev; 1350 1351 struct work_struct sp_task; 1352 unsigned long sp_event; 1353 #define BNXT_RX_MASK_SP_EVENT 0 1354 #define BNXT_RX_NTP_FLTR_SP_EVENT 1 1355 #define BNXT_LINK_CHNG_SP_EVENT 2 1356 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 1357 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 1358 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 1359 #define BNXT_RESET_TASK_SP_EVENT 6 1360 #define BNXT_RST_RING_SP_EVENT 7 1361 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 1362 #define BNXT_PERIODIC_STATS_SP_EVENT 9 1363 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 1364 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 1365 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 1366 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 1367 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 1368 #define BNXT_FLOW_STATS_SP_EVENT 15 1369 #define BNXT_UPDATE_PHY_SP_EVENT 16 1370 #define BNXT_RING_COAL_NOW_SP_EVENT 17 1371 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18 1372 #define BNXT_FW_EXCEPTION_SP_EVENT 19 1373 #define BNXT_VF_VNIC_CHANGE_SP_EVENT 20 1374 #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21 1375 #define BNXT_PTP_CURRENT_TIME_EVENT 22 1376 #define BNXT_FW_ECHO_REQUEST_SP_EVENT 23 1377 #define BNXT_VF_CFG_CHNG_SP_EVENT 24 1378 1379 struct delayed_work fw_reset_task; 1380 int fw_reset_state; 1381 #define BNXT_FW_RESET_STATE_POLL_VF 1 1382 #define BNXT_FW_RESET_STATE_RESET_FW 2 1383 #define BNXT_FW_RESET_STATE_ENABLE_DEV 3 1384 #define BNXT_FW_RESET_STATE_POLL_FW 4 1385 #define BNXT_FW_RESET_STATE_OPENING 5 1386 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6 1387 u16 fw_reset_min_dsecs; 1388 #define BNXT_DFLT_FW_RST_MIN_DSECS 20 1389 u16 fw_reset_max_dsecs; 1390 #define BNXT_DFLT_FW_RST_MAX_DSECS 60 1391 unsigned long fw_reset_timestamp; 1392 1393 struct bnxt_fw_health *fw_health; 1394 char board_partno[64]; 1395 TAILQ_HEAD(, bnxt_logger) loggers_list; 1396 void *debug_buf; 1397 struct mtx log_lock; /* logging ops lock */ 1398 struct callout time_sync_callout; 1399 struct bnxt_bs_trace_info bs_trace[BNXT_CTX_TRACE_BUF_COUNT]; 1400 1401 #define MAX_NUM_DMA_INDICATIONS 10 1402 struct iflib_dma_info mgmt_dma_data[MAX_NUM_DMA_INDICATIONS]; 1403 }; 1404 1405 struct bnxt_filter_info { 1406 STAILQ_ENTRY(bnxt_filter_info) next; 1407 uint64_t fw_l2_filter_id; 1408 #define INVALID_MAC_INDEX ((uint16_t)-1) 1409 uint16_t mac_index; 1410 1411 /* Filter Characteristics */ 1412 uint32_t flags; 1413 uint32_t enables; 1414 uint8_t l2_addr[ETHER_ADDR_LEN]; 1415 uint8_t l2_addr_mask[ETHER_ADDR_LEN]; 1416 uint16_t l2_ovlan; 1417 uint16_t l2_ovlan_mask; 1418 uint16_t l2_ivlan; 1419 uint16_t l2_ivlan_mask; 1420 uint8_t t_l2_addr[ETHER_ADDR_LEN]; 1421 uint8_t t_l2_addr_mask[ETHER_ADDR_LEN]; 1422 uint16_t t_l2_ovlan; 1423 uint16_t t_l2_ovlan_mask; 1424 uint16_t t_l2_ivlan; 1425 uint16_t t_l2_ivlan_mask; 1426 uint8_t tunnel_type; 1427 uint16_t mirror_vnic_id; 1428 uint32_t vni; 1429 uint8_t pri_hint; 1430 uint64_t l2_filter_id_hint; 1431 }; 1432 1433 #define I2C_DEV_ADDR_A0 0xa0 1434 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1435 1436 /* Function declarations */ 1437 void bnxt_report_link(struct bnxt_softc *softc); 1438 bool bnxt_check_hwrm_version(struct bnxt_softc *softc); 1439 struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *name); 1440 int bnxt_read_sfp_module_eeprom_info(struct bnxt_softc *bp, uint16_t i2c_addr, 1441 uint16_t page_number, uint8_t bank, bool bank_sel_en, uint16_t start_addr, 1442 uint16_t data_length, uint8_t *buf); 1443 void bnxt_dcb_init(struct bnxt_softc *softc); 1444 void bnxt_dcb_free(struct bnxt_softc *softc); 1445 uint8_t bnxt_dcb_setdcbx(struct bnxt_softc *softc, uint8_t mode); 1446 uint8_t bnxt_dcb_getdcbx(struct bnxt_softc *softc); 1447 int bnxt_dcb_ieee_getets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); 1448 int bnxt_dcb_ieee_setets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); 1449 uint8_t get_phy_type(struct bnxt_softc *softc); 1450 int bnxt_dcb_ieee_getpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); 1451 int bnxt_dcb_ieee_setpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); 1452 int bnxt_dcb_ieee_setapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); 1453 int bnxt_dcb_ieee_delapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); 1454 int bnxt_dcb_ieee_listapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app, 1455 size_t nitems, int *num_inputs); 1456 void bnxt_set_flags_by_devid(struct bnxt_softc *softc); 1457 int bnxt_hwrm_reserve_rings(struct bnxt_softc *softc); 1458 void bnxt_free_ctx_pg_tbls(struct bnxt_softc *softc, 1459 struct bnxt_ctx_pg_info *ctx_pg); 1460 int bnxt_alloc_ctx_pg_tbls(struct bnxt_softc *softc, 1461 struct bnxt_ctx_pg_info *ctx_pg, 1462 uint32_t mem_size, uint8_t depth, 1463 struct bnxt_ctx_mem_type *ctxm); 1464 #endif /* _BNXT_H */ 1465