1 //===- DetectDeadLanes.h - SubRegister Lane Usage Analysis --*- C++ -*-----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// Analysis that tracks defined/used subregister lanes across COPY instructions 11 /// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE, 12 /// INSERT_SUBREG, EXTRACT_SUBREG). 13 /// The information is used to detect dead definitions and the usage of 14 /// (completely) undefined values and mark the operands as such. 15 /// This pass is necessary because the dead/undef status is not obvious anymore 16 /// when subregisters are involved. 17 /// 18 /// Example: 19 /// %0 = some definition 20 /// %1 = IMPLICIT_DEF 21 /// %2 = REG_SEQUENCE %0, sub0, %1, sub1 22 /// %3 = EXTRACT_SUBREG %2, sub1 23 /// = use %3 24 /// The %0 definition is dead and %3 contains an undefined value. 25 // 26 //===----------------------------------------------------------------------===// 27 28 #ifndef LLVM_CODEGEN_DETECTDEADLANES_H 29 #define LLVM_CODEGEN_DETECTDEADLANES_H 30 31 #include "llvm/ADT/BitVector.h" 32 #include "llvm/CodeGen/MachinePassManager.h" 33 #include "llvm/MC/LaneBitmask.h" 34 #include <deque> 35 36 namespace llvm { 37 38 class MachineInstr; 39 class MachineOperand; 40 class MachineRegisterInfo; 41 class Register; 42 class TargetRegisterInfo; 43 44 class DeadLaneDetector { 45 public: 46 /// Contains a bitmask of which lanes of a given virtual register are 47 /// defined and which ones are actually used. 48 struct VRegInfo { 49 LaneBitmask UsedLanes; 50 LaneBitmask DefinedLanes; 51 }; 52 53 DeadLaneDetector(const MachineRegisterInfo *MRI, 54 const TargetRegisterInfo *TRI); 55 56 /// Update the \p DefinedLanes and the \p UsedLanes for all virtual registers. 57 void computeSubRegisterLaneBitInfo(); 58 getVRegInfo(unsigned RegIdx)59 const VRegInfo &getVRegInfo(unsigned RegIdx) const { 60 return VRegInfos[RegIdx]; 61 } 62 isDefinedByCopy(unsigned RegIdx)63 bool isDefinedByCopy(unsigned RegIdx) const { 64 return DefinedByCopy.test(RegIdx); 65 } 66 67 private: 68 /// Add used lane bits on the register used by operand \p MO. This translates 69 /// the bitmask based on the operands subregister, and puts the register into 70 /// the worklist if any new bits were added. 71 void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes); 72 73 /// Given a bitmask \p UsedLanes for the used lanes on a def output of a 74 /// COPY-like instruction determine the lanes used on the use operands 75 /// and call addUsedLanesOnOperand() for them. 76 void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes); 77 78 /// Given a use regiser operand \p Use and a mask of defined lanes, check 79 /// if the operand belongs to a lowersToCopies() instruction, transfer the 80 /// mask to the def and put the instruction into the worklist. 81 void transferDefinedLanesStep(const MachineOperand &Use, 82 LaneBitmask DefinedLanes); 83 84 public: 85 /// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum 86 /// of COPY-like instruction, determine which lanes are defined at the output 87 /// operand \p Def. 88 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum, 89 LaneBitmask DefinedLanes) const; 90 91 /// Given a mask \p UsedLanes used from the output of instruction \p MI 92 /// determine which lanes are used from operand \p MO of this instruction. 93 LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes, 94 const MachineOperand &MO) const; 95 96 private: 97 LaneBitmask determineInitialDefinedLanes(Register Reg); 98 LaneBitmask determineInitialUsedLanes(Register Reg); 99 100 const MachineRegisterInfo *MRI; 101 const TargetRegisterInfo *TRI; 102 PutInWorklist(unsigned RegIdx)103 void PutInWorklist(unsigned RegIdx) { 104 if (WorklistMembers.test(RegIdx)) 105 return; 106 WorklistMembers.set(RegIdx); 107 Worklist.push_back(RegIdx); 108 } 109 110 std::unique_ptr<VRegInfo[]> VRegInfos; 111 /// Worklist containing virtreg indexes. 112 std::deque<unsigned> Worklist; 113 BitVector WorklistMembers; 114 /// This bitvector is set for each vreg index where the vreg is defined 115 /// by an instruction where lowersToCopies()==true. 116 BitVector DefinedByCopy; 117 }; 118 119 class DetectDeadLanesPass : public PassInfoMixin<DetectDeadLanesPass> { 120 public: 121 PreservedAnalyses run(MachineFunction &MF, 122 MachineFunctionAnalysisManager &MFAM); isRequired()123 static bool isRequired() { return true; } 124 }; 125 126 } // end namespace llvm 127 128 #endif // LLVM_CODEGEN_DETECTDEADLANES_H 129