1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_IRQ_H
3 #define _LINUX_IRQ_H
4
5 /*
6 * Please do not include this file in generic code. There is currently
7 * no requirement for any architecture to implement anything held
8 * within this file.
9 *
10 * Thanks. --rmk
11 */
12
13 #include <linux/cache.h>
14 #include <linux/spinlock.h>
15 #include <linux/cpumask.h>
16 #include <linux/irqhandler.h>
17 #include <linux/irqreturn.h>
18 #include <linux/irqnr.h>
19 #include <linux/topology.h>
20 #include <linux/io.h>
21 #include <linux/slab.h>
22
23 #include <asm/irq.h>
24 #include <asm/ptrace.h>
25 #include <asm/irq_regs.h>
26
27 struct seq_file;
28 struct module;
29 struct msi_msg;
30 struct irq_affinity_desc;
31 enum irqchip_irq_state;
32
33 /*
34 * IRQ line status.
35 *
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
37 *
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
47 * to setup the HW to a sane default (used
48 * by irqdomain map() callbacks to synchronize
49 * the HW state and SW flags for a newly
50 * allocated descriptor).
51 *
52 * IRQ_TYPE_PROBE - Special flag for probing in progress
53 *
54 * Bits which can be modified via irq_set/clear/modify_status_flags()
55 * IRQ_LEVEL - Interrupt is level type. Will be also
56 * updated in the code when the above trigger
57 * bits are modified via irq_set_irq_type()
58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 * it from affinity setting
60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 * IRQ_NOREQUEST - Interrupt cannot be requested via
62 * request_irq()
63 * IRQ_NOTHREAD - Interrupt cannot be threaded
64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
65 * request/setup_irq()
66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 * IRQ_NESTED_THREAD - Interrupt nests into another thread
68 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
69 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
70 * it from the spurious interrupt detection
71 * mechanism and from core side polling.
72 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
73 * IRQ_HIDDEN - Don't show up in /proc/interrupts
74 * IRQ_NO_DEBUG - Exclude from note_interrupt() debugging
75 */
76 enum {
77 IRQ_TYPE_NONE = 0x00000000,
78 IRQ_TYPE_EDGE_RISING = 0x00000001,
79 IRQ_TYPE_EDGE_FALLING = 0x00000002,
80 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
81 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
82 IRQ_TYPE_LEVEL_LOW = 0x00000008,
83 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
84 IRQ_TYPE_SENSE_MASK = 0x0000000f,
85 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
86
87 IRQ_TYPE_PROBE = 0x00000010,
88
89 IRQ_LEVEL = (1 << 8),
90 IRQ_PER_CPU = (1 << 9),
91 IRQ_NOPROBE = (1 << 10),
92 IRQ_NOREQUEST = (1 << 11),
93 IRQ_NOAUTOEN = (1 << 12),
94 IRQ_NO_BALANCING = (1 << 13),
95 IRQ_NESTED_THREAD = (1 << 15),
96 IRQ_NOTHREAD = (1 << 16),
97 IRQ_PER_CPU_DEVID = (1 << 17),
98 IRQ_IS_POLLED = (1 << 18),
99 IRQ_DISABLE_UNLAZY = (1 << 19),
100 IRQ_HIDDEN = (1 << 20),
101 IRQ_NO_DEBUG = (1 << 21),
102 };
103
104 #define IRQF_MODIFY_MASK \
105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
106 IRQ_NOAUTOEN | IRQ_LEVEL | IRQ_NO_BALANCING | \
107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
108 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
109
110 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
111
112 /*
113 * Return value for chip->irq_set_affinity()
114 *
115 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
116 * IRQ_SET_MASK_NOCOPY - OK, chip did update irq_common_data.affinity
117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
118 * support stacked irqchips, which indicates skipping
119 * all descendant irqchips.
120 */
121 enum {
122 IRQ_SET_MASK_OK = 0,
123 IRQ_SET_MASK_OK_NOCOPY,
124 IRQ_SET_MASK_OK_DONE,
125 };
126
127 struct msi_desc;
128 struct irq_domain;
129
130 /**
131 * struct irq_common_data - per irq data shared by all irqchips
132 * @state_use_accessors: status information for irq chip functions.
133 * Use accessor functions to deal with it
134 * @node: node index useful for balancing
135 * @handler_data: per-IRQ data for the irq_chip methods
136 * @affinity: IRQ affinity on SMP. If this is an IPI
137 * related irq, then this is the mask of the
138 * CPUs to which an IPI can be sent.
139 * @effective_affinity: The effective IRQ affinity on SMP as some irq
140 * chips do not allow multi CPU destinations.
141 * A subset of @affinity.
142 * @msi_desc: MSI descriptor
143 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
144 */
145 struct irq_common_data {
146 unsigned int __private state_use_accessors;
147 #ifdef CONFIG_NUMA
148 unsigned int node;
149 #endif
150 void *handler_data;
151 struct msi_desc *msi_desc;
152 #ifdef CONFIG_SMP
153 cpumask_var_t affinity;
154 #endif
155 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
156 cpumask_var_t effective_affinity;
157 #endif
158 #ifdef CONFIG_GENERIC_IRQ_IPI
159 unsigned int ipi_offset;
160 #endif
161 };
162
163 /**
164 * struct irq_data - per irq chip data passed down to chip functions
165 * @mask: precomputed bitmask for accessing the chip registers
166 * @irq: interrupt number
167 * @hwirq: hardware interrupt number, local to the interrupt domain
168 * @common: point to data shared by all irqchips
169 * @chip: low level interrupt hardware access
170 * @domain: Interrupt translation domain; responsible for mapping
171 * between hwirq number and linux irq number.
172 * @parent_data: pointer to parent struct irq_data to support hierarchy
173 * irq_domain
174 * @chip_data: platform-specific per-chip private data for the chip
175 * methods, to allow shared chip implementations
176 */
177 struct irq_data {
178 u32 mask;
179 unsigned int irq;
180 irq_hw_number_t hwirq;
181 struct irq_common_data *common;
182 struct irq_chip *chip;
183 struct irq_domain *domain;
184 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
185 struct irq_data *parent_data;
186 #endif
187 void *chip_data;
188 };
189
190 /*
191 * Bit masks for irq_common_data.state_use_accessors
192 *
193 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
194 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
195 * IRQD_ACTIVATED - Interrupt has already been activated
196 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
197 * IRQD_PER_CPU - Interrupt is per cpu
198 * IRQD_AFFINITY_SET - Interrupt affinity was set
199 * IRQD_LEVEL - Interrupt is level triggered
200 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
201 * from suspend
202 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
203 * IRQD_IRQ_MASKED - Masked state of the interrupt
204 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
205 * IRQD_WAKEUP_ARMED - Wakeup mode armed
206 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
207 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
208 * IRQD_IRQ_STARTED - Startup state of the interrupt
209 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
210 * mask. Applies only to affinity managed irqs.
211 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
212 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
213 * IRQD_CAN_RESERVE - Can use reservation mode
214 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked
215 * from actual interrupt context.
216 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call
217 * irq_chip::irq_set_affinity() when deactivated.
218 * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if
219 * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set.
220 * IRQD_RESEND_WHEN_IN_PROGRESS - Interrupt may fire when already in progress in which
221 * case it must be resent at the next available opportunity.
222 */
223 enum {
224 IRQD_TRIGGER_MASK = 0xf,
225 IRQD_SETAFFINITY_PENDING = BIT(8),
226 IRQD_ACTIVATED = BIT(9),
227 IRQD_NO_BALANCING = BIT(10),
228 IRQD_PER_CPU = BIT(11),
229 IRQD_AFFINITY_SET = BIT(12),
230 IRQD_LEVEL = BIT(13),
231 IRQD_WAKEUP_STATE = BIT(14),
232 IRQD_IRQ_DISABLED = BIT(16),
233 IRQD_IRQ_MASKED = BIT(17),
234 IRQD_IRQ_INPROGRESS = BIT(18),
235 IRQD_WAKEUP_ARMED = BIT(19),
236 IRQD_FORWARDED_TO_VCPU = BIT(20),
237 IRQD_AFFINITY_MANAGED = BIT(21),
238 IRQD_IRQ_STARTED = BIT(22),
239 IRQD_MANAGED_SHUTDOWN = BIT(23),
240 IRQD_SINGLE_TARGET = BIT(24),
241 IRQD_DEFAULT_TRIGGER_SET = BIT(25),
242 IRQD_CAN_RESERVE = BIT(26),
243 IRQD_HANDLE_ENFORCE_IRQCTX = BIT(27),
244 IRQD_AFFINITY_ON_ACTIVATE = BIT(28),
245 IRQD_IRQ_ENABLED_ON_SUSPEND = BIT(29),
246 IRQD_RESEND_WHEN_IN_PROGRESS = BIT(30),
247 };
248
249 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
250
irqd_is_setaffinity_pending(struct irq_data * d)251 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
252 {
253 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
254 }
255
irqd_is_per_cpu(struct irq_data * d)256 static inline bool irqd_is_per_cpu(struct irq_data *d)
257 {
258 return __irqd_to_state(d) & IRQD_PER_CPU;
259 }
260
irqd_can_balance(struct irq_data * d)261 static inline bool irqd_can_balance(struct irq_data *d)
262 {
263 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
264 }
265
irqd_affinity_was_set(struct irq_data * d)266 static inline bool irqd_affinity_was_set(struct irq_data *d)
267 {
268 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
269 }
270
irqd_mark_affinity_was_set(struct irq_data * d)271 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
272 {
273 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
274 }
275
irqd_trigger_type_was_set(struct irq_data * d)276 static inline bool irqd_trigger_type_was_set(struct irq_data *d)
277 {
278 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
279 }
280
irqd_get_trigger_type(struct irq_data * d)281 static inline u32 irqd_get_trigger_type(struct irq_data *d)
282 {
283 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
284 }
285
286 /*
287 * Must only be called inside irq_chip.irq_set_type() functions or
288 * from the DT/ACPI setup code.
289 */
irqd_set_trigger_type(struct irq_data * d,u32 type)290 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
291 {
292 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
293 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
294 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
295 }
296
irqd_is_level_type(struct irq_data * d)297 static inline bool irqd_is_level_type(struct irq_data *d)
298 {
299 return __irqd_to_state(d) & IRQD_LEVEL;
300 }
301
302 /*
303 * Must only be called of irqchip.irq_set_affinity() or low level
304 * hierarchy domain allocation functions.
305 */
irqd_set_single_target(struct irq_data * d)306 static inline void irqd_set_single_target(struct irq_data *d)
307 {
308 __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
309 }
310
irqd_is_single_target(struct irq_data * d)311 static inline bool irqd_is_single_target(struct irq_data *d)
312 {
313 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
314 }
315
irqd_set_handle_enforce_irqctx(struct irq_data * d)316 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
317 {
318 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX;
319 }
320
irqd_is_handle_enforce_irqctx(struct irq_data * d)321 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
322 {
323 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
324 }
325
irqd_is_enabled_on_suspend(struct irq_data * d)326 static inline bool irqd_is_enabled_on_suspend(struct irq_data *d)
327 {
328 return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND;
329 }
330
irqd_is_wakeup_set(struct irq_data * d)331 static inline bool irqd_is_wakeup_set(struct irq_data *d)
332 {
333 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
334 }
335
irqd_irq_disabled(struct irq_data * d)336 static inline bool irqd_irq_disabled(struct irq_data *d)
337 {
338 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
339 }
340
irqd_irq_masked(struct irq_data * d)341 static inline bool irqd_irq_masked(struct irq_data *d)
342 {
343 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
344 }
345
irqd_irq_inprogress(struct irq_data * d)346 static inline bool irqd_irq_inprogress(struct irq_data *d)
347 {
348 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
349 }
350
irqd_is_wakeup_armed(struct irq_data * d)351 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
352 {
353 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
354 }
355
irqd_is_forwarded_to_vcpu(struct irq_data * d)356 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
357 {
358 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
359 }
360
irqd_set_forwarded_to_vcpu(struct irq_data * d)361 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
362 {
363 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
364 }
365
irqd_clr_forwarded_to_vcpu(struct irq_data * d)366 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
367 {
368 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
369 }
370
irqd_affinity_is_managed(struct irq_data * d)371 static inline bool irqd_affinity_is_managed(struct irq_data *d)
372 {
373 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
374 }
375
irqd_is_activated(struct irq_data * d)376 static inline bool irqd_is_activated(struct irq_data *d)
377 {
378 return __irqd_to_state(d) & IRQD_ACTIVATED;
379 }
380
irqd_set_activated(struct irq_data * d)381 static inline void irqd_set_activated(struct irq_data *d)
382 {
383 __irqd_to_state(d) |= IRQD_ACTIVATED;
384 }
385
irqd_clr_activated(struct irq_data * d)386 static inline void irqd_clr_activated(struct irq_data *d)
387 {
388 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
389 }
390
irqd_is_started(struct irq_data * d)391 static inline bool irqd_is_started(struct irq_data *d)
392 {
393 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
394 }
395
irqd_is_managed_and_shutdown(struct irq_data * d)396 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
397 {
398 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
399 }
400
irqd_set_can_reserve(struct irq_data * d)401 static inline void irqd_set_can_reserve(struct irq_data *d)
402 {
403 __irqd_to_state(d) |= IRQD_CAN_RESERVE;
404 }
405
irqd_clr_can_reserve(struct irq_data * d)406 static inline void irqd_clr_can_reserve(struct irq_data *d)
407 {
408 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
409 }
410
irqd_can_reserve(struct irq_data * d)411 static inline bool irqd_can_reserve(struct irq_data *d)
412 {
413 return __irqd_to_state(d) & IRQD_CAN_RESERVE;
414 }
415
irqd_set_affinity_on_activate(struct irq_data * d)416 static inline void irqd_set_affinity_on_activate(struct irq_data *d)
417 {
418 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE;
419 }
420
irqd_affinity_on_activate(struct irq_data * d)421 static inline bool irqd_affinity_on_activate(struct irq_data *d)
422 {
423 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE;
424 }
425
irqd_set_resend_when_in_progress(struct irq_data * d)426 static inline void irqd_set_resend_when_in_progress(struct irq_data *d)
427 {
428 __irqd_to_state(d) |= IRQD_RESEND_WHEN_IN_PROGRESS;
429 }
430
irqd_needs_resend_when_in_progress(struct irq_data * d)431 static inline bool irqd_needs_resend_when_in_progress(struct irq_data *d)
432 {
433 return __irqd_to_state(d) & IRQD_RESEND_WHEN_IN_PROGRESS;
434 }
435
436 #undef __irqd_to_state
437
irqd_to_hwirq(struct irq_data * d)438 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
439 {
440 return d->hwirq;
441 }
442
443 /**
444 * struct irq_chip - hardware interrupt chip descriptor
445 *
446 * @name: name for /proc/interrupts
447 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
448 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
449 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
450 * @irq_disable: disable the interrupt
451 * @irq_ack: start of a new interrupt
452 * @irq_mask: mask an interrupt source
453 * @irq_mask_ack: ack and mask an interrupt source
454 * @irq_unmask: unmask an interrupt source
455 * @irq_eoi: end of interrupt
456 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
457 * argument is true, it tells the driver to
458 * unconditionally apply the affinity setting. Sanity
459 * checks against the supplied affinity mask are not
460 * required. This is used for CPU hotplug where the
461 * target CPU is not yet set in the cpu_online_mask.
462 * @irq_retrigger: resend an IRQ to the CPU
463 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
464 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
465 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
466 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
467 * @irq_cpu_online: configure an interrupt source for a secondary CPU
468 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
469 * @irq_suspend: function called from core code on suspend once per
470 * chip, when one or more interrupts are installed
471 * @irq_resume: function called from core code on resume once per chip,
472 * when one ore more interrupts are installed
473 * @irq_pm_shutdown: function called from core code on shutdown once per chip
474 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
475 * @irq_print_chip: optional to print special chip info in show_interrupts
476 * @irq_request_resources: optional to request resources before calling
477 * any other callback related to this irq
478 * @irq_release_resources: optional to release resources acquired with
479 * irq_request_resources
480 * @irq_compose_msi_msg: optional to compose message content for MSI
481 * @irq_write_msi_msg: optional to write message content for MSI
482 * @irq_get_irqchip_state: return the internal state of an interrupt
483 * @irq_set_irqchip_state: set the internal state of a interrupt
484 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
485 * @ipi_send_single: send a single IPI to destination cpus
486 * @ipi_send_mask: send an IPI to destination cpus in cpumask
487 * @irq_nmi_setup: function called from core code before enabling an NMI
488 * @irq_nmi_teardown: function called from core code after disabling an NMI
489 * @irq_force_complete_move: optional function to force complete pending irq move
490 * @flags: chip specific flags
491 */
492 struct irq_chip {
493 const char *name;
494 unsigned int (*irq_startup)(struct irq_data *data);
495 void (*irq_shutdown)(struct irq_data *data);
496 void (*irq_enable)(struct irq_data *data);
497 void (*irq_disable)(struct irq_data *data);
498
499 void (*irq_ack)(struct irq_data *data);
500 void (*irq_mask)(struct irq_data *data);
501 void (*irq_mask_ack)(struct irq_data *data);
502 void (*irq_unmask)(struct irq_data *data);
503 void (*irq_eoi)(struct irq_data *data);
504
505 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
506 int (*irq_retrigger)(struct irq_data *data);
507 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
508 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
509
510 void (*irq_bus_lock)(struct irq_data *data);
511 void (*irq_bus_sync_unlock)(struct irq_data *data);
512
513 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE
514 void (*irq_cpu_online)(struct irq_data *data);
515 void (*irq_cpu_offline)(struct irq_data *data);
516 #endif
517 void (*irq_suspend)(struct irq_data *data);
518 void (*irq_resume)(struct irq_data *data);
519 void (*irq_pm_shutdown)(struct irq_data *data);
520
521 void (*irq_calc_mask)(struct irq_data *data);
522
523 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
524 int (*irq_request_resources)(struct irq_data *data);
525 void (*irq_release_resources)(struct irq_data *data);
526
527 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
528 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
529
530 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
531 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
532
533 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
534
535 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
536 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
537
538 int (*irq_nmi_setup)(struct irq_data *data);
539 void (*irq_nmi_teardown)(struct irq_data *data);
540
541 void (*irq_force_complete_move)(struct irq_data *data);
542
543 unsigned long flags;
544 };
545
546 /*
547 * irq_chip specific flags
548 *
549 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
550 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
551 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
552 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
553 * when irq enabled
554 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
555 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
556 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
557 * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs
558 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
559 * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs
560 * in the suspend path if they are in disabled state
561 * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup
562 * IRQCHIP_IMMUTABLE: Don't ever change anything in this chip
563 * IRQCHIP_MOVE_DEFERRED: Move the interrupt in actual interrupt context
564 */
565 enum {
566 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
567 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
568 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
569 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
570 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
571 IRQCHIP_ONESHOT_SAFE = (1 << 5),
572 IRQCHIP_EOI_THREADED = (1 << 6),
573 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
574 IRQCHIP_SUPPORTS_NMI = (1 << 8),
575 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9),
576 IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10),
577 IRQCHIP_IMMUTABLE = (1 << 11),
578 IRQCHIP_MOVE_DEFERRED = (1 << 12),
579 };
580
581 #include <linux/irqdesc.h>
582
583 /*
584 * Pick up the arch-dependent methods:
585 */
586 #include <asm/hw_irq.h>
587
588 #ifndef NR_IRQS_LEGACY
589 # define NR_IRQS_LEGACY 0
590 #endif
591
592 #ifndef ARCH_IRQ_INIT_FLAGS
593 # define ARCH_IRQ_INIT_FLAGS 0
594 #endif
595
596 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
597
598 struct irqaction;
599 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
600
601 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE
602 extern void irq_cpu_online(void);
603 extern void irq_cpu_offline(void);
604 #endif
605 extern int irq_set_affinity_locked(struct irq_data *data,
606 const struct cpumask *cpumask, bool force);
607 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
608
609 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
610 extern void irq_migrate_all_off_this_cpu(void);
611 extern int irq_affinity_online_cpu(unsigned int cpu);
612 #else
613 # define irq_affinity_online_cpu NULL
614 #endif
615
616 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
617 bool irq_can_move_in_process_context(struct irq_data *data);
618 void __irq_move_irq(struct irq_data *data);
irq_move_irq(struct irq_data * data)619 static inline void irq_move_irq(struct irq_data *data)
620 {
621 if (unlikely(irqd_is_setaffinity_pending(data)))
622 __irq_move_irq(data);
623 }
624 void irq_move_masked_irq(struct irq_data *data);
625 #else
irq_can_move_in_process_context(struct irq_data * data)626 static inline bool irq_can_move_in_process_context(struct irq_data *data) { return true; }
irq_move_irq(struct irq_data * data)627 static inline void irq_move_irq(struct irq_data *data) { }
irq_move_masked_irq(struct irq_data * data)628 static inline void irq_move_masked_irq(struct irq_data *data) { }
629 #endif
630
631 extern int no_irq_affinity;
632
633 #ifdef CONFIG_HARDIRQS_SW_RESEND
634 int irq_set_parent(int irq, int parent_irq);
635 #else
irq_set_parent(int irq,int parent_irq)636 static inline int irq_set_parent(int irq, int parent_irq)
637 {
638 return 0;
639 }
640 #endif
641
642 /*
643 * Built-in IRQ handlers for various IRQ types,
644 * callable via desc->handle_irq()
645 */
646 extern void handle_level_irq(struct irq_desc *desc);
647 extern void handle_fasteoi_irq(struct irq_desc *desc);
648 extern void handle_edge_irq(struct irq_desc *desc);
649 extern void handle_edge_eoi_irq(struct irq_desc *desc);
650 extern void handle_simple_irq(struct irq_desc *desc);
651 extern void handle_untracked_irq(struct irq_desc *desc);
652 extern void handle_percpu_irq(struct irq_desc *desc);
653 extern void handle_percpu_devid_irq(struct irq_desc *desc);
654 extern void handle_bad_irq(struct irq_desc *desc);
655 extern void handle_nested_irq(unsigned int irq);
656
657 extern void handle_fasteoi_nmi(struct irq_desc *desc);
658 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc);
659
660 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
661 extern int irq_chip_pm_get(struct irq_data *data);
662 extern int irq_chip_pm_put(struct irq_data *data);
663 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
664 extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
665 extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
666 extern int irq_chip_set_parent_state(struct irq_data *data,
667 enum irqchip_irq_state which,
668 bool val);
669 extern int irq_chip_get_parent_state(struct irq_data *data,
670 enum irqchip_irq_state which,
671 bool *state);
672 extern void irq_chip_enable_parent(struct irq_data *data);
673 extern void irq_chip_disable_parent(struct irq_data *data);
674 extern void irq_chip_ack_parent(struct irq_data *data);
675 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
676 extern void irq_chip_mask_parent(struct irq_data *data);
677 extern void irq_chip_mask_ack_parent(struct irq_data *data);
678 extern void irq_chip_unmask_parent(struct irq_data *data);
679 extern void irq_chip_eoi_parent(struct irq_data *data);
680 extern int irq_chip_set_affinity_parent(struct irq_data *data,
681 const struct cpumask *dest,
682 bool force);
683 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
684 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
685 void *vcpu_info);
686 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
687 extern int irq_chip_request_resources_parent(struct irq_data *data);
688 extern void irq_chip_release_resources_parent(struct irq_data *data);
689 #endif
690
691 /* Disable or mask interrupts during a kernel kexec */
692 extern void machine_kexec_mask_interrupts(void);
693
694 /* Handling of unhandled and spurious interrupts: */
695 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
696
697
698 /* Enable/disable irq debugging output: */
699 extern int noirqdebug_setup(char *str);
700
701 /* Checks whether the interrupt can be requested by request_irq(): */
702 extern bool can_request_irq(unsigned int irq, unsigned long irqflags);
703
704 /* Dummy irq-chip implementations: */
705 extern struct irq_chip no_irq_chip;
706 extern struct irq_chip dummy_irq_chip;
707
708 extern void
709 irq_set_chip_and_handler_name(unsigned int irq, const struct irq_chip *chip,
710 irq_flow_handler_t handle, const char *name);
711
irq_set_chip_and_handler(unsigned int irq,const struct irq_chip * chip,irq_flow_handler_t handle)712 static inline void irq_set_chip_and_handler(unsigned int irq,
713 const struct irq_chip *chip,
714 irq_flow_handler_t handle)
715 {
716 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
717 }
718
719 extern int irq_set_percpu_devid(unsigned int irq);
720 extern int irq_set_percpu_devid_partition(unsigned int irq,
721 const struct cpumask *affinity);
722 extern int irq_get_percpu_devid_partition(unsigned int irq,
723 struct cpumask *affinity);
724
725 extern void
726 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
727 const char *name);
728
729 static inline void
irq_set_handler(unsigned int irq,irq_flow_handler_t handle)730 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
731 {
732 __irq_set_handler(irq, handle, 0, NULL);
733 }
734
735 /*
736 * Set a highlevel chained flow handler for a given IRQ.
737 * (a chained handler is automatically enabled and set to
738 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
739 */
740 static inline void
irq_set_chained_handler(unsigned int irq,irq_flow_handler_t handle)741 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
742 {
743 __irq_set_handler(irq, handle, 1, NULL);
744 }
745
746 /*
747 * Set a highlevel chained flow handler and its data for a given IRQ.
748 * (a chained handler is automatically enabled and set to
749 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
750 */
751 void
752 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
753 void *data);
754
755 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
756
irq_set_status_flags(unsigned int irq,unsigned long set)757 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
758 {
759 irq_modify_status(irq, 0, set);
760 }
761
irq_clear_status_flags(unsigned int irq,unsigned long clr)762 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
763 {
764 irq_modify_status(irq, clr, 0);
765 }
766
irq_set_noprobe(unsigned int irq)767 static inline void irq_set_noprobe(unsigned int irq)
768 {
769 irq_modify_status(irq, 0, IRQ_NOPROBE);
770 }
771
irq_set_probe(unsigned int irq)772 static inline void irq_set_probe(unsigned int irq)
773 {
774 irq_modify_status(irq, IRQ_NOPROBE, 0);
775 }
776
irq_set_nothread(unsigned int irq)777 static inline void irq_set_nothread(unsigned int irq)
778 {
779 irq_modify_status(irq, 0, IRQ_NOTHREAD);
780 }
781
irq_set_thread(unsigned int irq)782 static inline void irq_set_thread(unsigned int irq)
783 {
784 irq_modify_status(irq, IRQ_NOTHREAD, 0);
785 }
786
irq_set_nested_thread(unsigned int irq,bool nest)787 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
788 {
789 if (nest)
790 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
791 else
792 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
793 }
794
irq_set_percpu_devid_flags(unsigned int irq)795 static inline void irq_set_percpu_devid_flags(unsigned int irq)
796 {
797 irq_set_status_flags(irq,
798 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
799 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
800 }
801
802 /* Set/get chip/data for an IRQ: */
803 extern int irq_set_chip(unsigned int irq, const struct irq_chip *chip);
804 extern int irq_set_handler_data(unsigned int irq, void *data);
805 extern int irq_set_chip_data(unsigned int irq, void *data);
806 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
807 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
808 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
809 struct msi_desc *entry);
810 extern struct irq_data *irq_get_irq_data(unsigned int irq);
811
irq_get_chip(unsigned int irq)812 static inline struct irq_chip *irq_get_chip(unsigned int irq)
813 {
814 struct irq_data *d = irq_get_irq_data(irq);
815 return d ? d->chip : NULL;
816 }
817
irq_data_get_irq_chip(struct irq_data * d)818 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
819 {
820 return d->chip;
821 }
822
irq_get_chip_data(unsigned int irq)823 static inline void *irq_get_chip_data(unsigned int irq)
824 {
825 struct irq_data *d = irq_get_irq_data(irq);
826 return d ? d->chip_data : NULL;
827 }
828
irq_data_get_irq_chip_data(struct irq_data * d)829 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
830 {
831 return d->chip_data;
832 }
833
irq_get_handler_data(unsigned int irq)834 static inline void *irq_get_handler_data(unsigned int irq)
835 {
836 struct irq_data *d = irq_get_irq_data(irq);
837 return d ? d->common->handler_data : NULL;
838 }
839
irq_data_get_irq_handler_data(struct irq_data * d)840 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
841 {
842 return d->common->handler_data;
843 }
844
irq_get_msi_desc(unsigned int irq)845 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
846 {
847 struct irq_data *d = irq_get_irq_data(irq);
848 return d ? d->common->msi_desc : NULL;
849 }
850
irq_data_get_msi_desc(struct irq_data * d)851 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
852 {
853 return d->common->msi_desc;
854 }
855
irq_get_trigger_type(unsigned int irq)856 static inline u32 irq_get_trigger_type(unsigned int irq)
857 {
858 struct irq_data *d = irq_get_irq_data(irq);
859 return d ? irqd_get_trigger_type(d) : 0;
860 }
861
irq_common_data_get_node(struct irq_common_data * d)862 static inline int irq_common_data_get_node(struct irq_common_data *d)
863 {
864 #ifdef CONFIG_NUMA
865 return d->node;
866 #else
867 return 0;
868 #endif
869 }
870
irq_data_get_node(struct irq_data * d)871 static inline int irq_data_get_node(struct irq_data *d)
872 {
873 return irq_common_data_get_node(d->common);
874 }
875
876 static inline
irq_data_get_affinity_mask(struct irq_data * d)877 const struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
878 {
879 #ifdef CONFIG_SMP
880 return d->common->affinity;
881 #else
882 return cpumask_of(0);
883 #endif
884 }
885
irq_data_update_affinity(struct irq_data * d,const struct cpumask * m)886 static inline void irq_data_update_affinity(struct irq_data *d,
887 const struct cpumask *m)
888 {
889 #ifdef CONFIG_SMP
890 cpumask_copy(d->common->affinity, m);
891 #endif
892 }
893
irq_get_affinity_mask(int irq)894 static inline const struct cpumask *irq_get_affinity_mask(int irq)
895 {
896 struct irq_data *d = irq_get_irq_data(irq);
897
898 return d ? irq_data_get_affinity_mask(d) : NULL;
899 }
900
901 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
902 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)903 const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
904 {
905 return d->common->effective_affinity;
906 }
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)907 static inline void irq_data_update_effective_affinity(struct irq_data *d,
908 const struct cpumask *m)
909 {
910 cpumask_copy(d->common->effective_affinity, m);
911 }
912 #else
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)913 static inline void irq_data_update_effective_affinity(struct irq_data *d,
914 const struct cpumask *m)
915 {
916 }
917 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)918 const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
919 {
920 return irq_data_get_affinity_mask(d);
921 }
922 #endif
923
924 static inline
irq_get_effective_affinity_mask(unsigned int irq)925 const struct cpumask *irq_get_effective_affinity_mask(unsigned int irq)
926 {
927 struct irq_data *d = irq_get_irq_data(irq);
928
929 return d ? irq_data_get_effective_affinity_mask(d) : NULL;
930 }
931
932 unsigned int arch_dynirq_lower_bound(unsigned int from);
933
934 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
935 struct module *owner,
936 const struct irq_affinity_desc *affinity);
937
938 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
939 unsigned int cnt, int node, struct module *owner,
940 const struct irq_affinity_desc *affinity);
941
942 /* use macros to avoid needing export.h for THIS_MODULE */
943 #define irq_alloc_descs(irq, from, cnt, node) \
944 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
945
946 #define irq_alloc_desc(node) \
947 irq_alloc_descs(-1, 1, 1, node)
948
949 #define irq_alloc_desc_at(at, node) \
950 irq_alloc_descs(at, at, 1, node)
951
952 #define irq_alloc_desc_from(from, node) \
953 irq_alloc_descs(-1, from, 1, node)
954
955 #define irq_alloc_descs_from(from, cnt, node) \
956 irq_alloc_descs(-1, from, cnt, node)
957
958 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
959 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
960
961 #define devm_irq_alloc_desc(dev, node) \
962 devm_irq_alloc_descs(dev, -1, 1, 1, node)
963
964 #define devm_irq_alloc_desc_at(dev, at, node) \
965 devm_irq_alloc_descs(dev, at, at, 1, node)
966
967 #define devm_irq_alloc_desc_from(dev, from, node) \
968 devm_irq_alloc_descs(dev, -1, from, 1, node)
969
970 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
971 devm_irq_alloc_descs(dev, -1, from, cnt, node)
972
973 void irq_free_descs(unsigned int irq, unsigned int cnt);
irq_free_desc(unsigned int irq)974 static inline void irq_free_desc(unsigned int irq)
975 {
976 irq_free_descs(irq, 1);
977 }
978
979 #ifdef CONFIG_GENERIC_IRQ_LEGACY
980 void irq_init_desc(unsigned int irq);
981 #endif
982
983 /**
984 * struct irq_chip_regs - register offsets for struct irq_gci
985 * @enable: Enable register offset to reg_base
986 * @disable: Disable register offset to reg_base
987 * @mask: Mask register offset to reg_base
988 * @ack: Ack register offset to reg_base
989 * @eoi: Eoi register offset to reg_base
990 * @type: Type configuration register offset to reg_base
991 */
992 struct irq_chip_regs {
993 unsigned long enable;
994 unsigned long disable;
995 unsigned long mask;
996 unsigned long ack;
997 unsigned long eoi;
998 unsigned long type;
999 };
1000
1001 /**
1002 * struct irq_chip_type - Generic interrupt chip instance for a flow type
1003 * @chip: The real interrupt chip which provides the callbacks
1004 * @regs: Register offsets for this chip
1005 * @handler: Flow handler associated with this chip
1006 * @type: Chip can handle these flow types
1007 * @mask_cache_priv: Cached mask register private to the chip type
1008 * @mask_cache: Pointer to cached mask register
1009 *
1010 * A irq_generic_chip can have several instances of irq_chip_type when
1011 * it requires different functions and register offsets for different
1012 * flow types.
1013 */
1014 struct irq_chip_type {
1015 struct irq_chip chip;
1016 struct irq_chip_regs regs;
1017 irq_flow_handler_t handler;
1018 u32 type;
1019 u32 mask_cache_priv;
1020 u32 *mask_cache;
1021 };
1022
1023 /**
1024 * struct irq_chip_generic - Generic irq chip data structure
1025 * @lock: Lock to protect register and cache data access
1026 * @reg_base: Register base address (virtual)
1027 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
1028 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
1029 * @suspend: Function called from core code on suspend once per
1030 * chip; can be useful instead of irq_chip::suspend to
1031 * handle chip details even when no interrupts are in use
1032 * @resume: Function called from core code on resume once per chip;
1033 * can be useful instead of irq_chip::suspend to handle
1034 * chip details even when no interrupts are in use
1035 * @irq_base: Interrupt base nr for this chip
1036 * @irq_cnt: Number of interrupts handled by this chip
1037 * @mask_cache: Cached mask register shared between all chip types
1038 * @wake_enabled: Interrupt can wakeup from suspend
1039 * @wake_active: Interrupt is marked as an wakeup from suspend source
1040 * @num_ct: Number of available irq_chip_type instances (usually 1)
1041 * @private: Private data for non generic chip callbacks
1042 * @installed: bitfield to denote installed interrupts
1043 * @unused: bitfield to denote unused interrupts
1044 * @domain: irq domain pointer
1045 * @list: List head for keeping track of instances
1046 * @chip_types: Array of interrupt irq_chip_types
1047 *
1048 * Note, that irq_chip_generic can have multiple irq_chip_type
1049 * implementations which can be associated to a particular irq line of
1050 * an irq_chip_generic instance. That allows to share and protect
1051 * state in an irq_chip_generic instance when we need to implement
1052 * different flow mechanisms (level/edge) for it.
1053 */
1054 struct irq_chip_generic {
1055 raw_spinlock_t lock;
1056 void __iomem *reg_base;
1057 u32 (*reg_readl)(void __iomem *addr);
1058 void (*reg_writel)(u32 val, void __iomem *addr);
1059 void (*suspend)(struct irq_chip_generic *gc);
1060 void (*resume)(struct irq_chip_generic *gc);
1061 unsigned int irq_base;
1062 unsigned int irq_cnt;
1063 u32 mask_cache;
1064 u32 wake_enabled;
1065 u32 wake_active;
1066 unsigned int num_ct;
1067 void *private;
1068 unsigned long installed;
1069 unsigned long unused;
1070 struct irq_domain *domain;
1071 struct list_head list;
1072 struct irq_chip_type chip_types[];
1073 };
1074
1075 /**
1076 * enum irq_gc_flags - Initialization flags for generic irq chips
1077 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1078 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1079 * irq chips which need to call irq_set_wake() on
1080 * the parent irq. Usually GPIO implementations
1081 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
1082 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1083 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1084 */
1085 enum irq_gc_flags {
1086 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
1087 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
1088 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
1089 IRQ_GC_NO_MASK = 1 << 3,
1090 IRQ_GC_BE_IO = 1 << 4,
1091 };
1092
1093 /*
1094 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1095 * @irqs_per_chip: Number of interrupts per chip
1096 * @num_chips: Number of chips
1097 * @irq_flags_to_set: IRQ* flags to set on irq setup
1098 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1099 * @gc_flags: Generic chip specific setup flags
1100 * @exit: Function called on each chip when they are destroyed.
1101 * @gc: Array of pointers to generic interrupt chips
1102 */
1103 struct irq_domain_chip_generic {
1104 unsigned int irqs_per_chip;
1105 unsigned int num_chips;
1106 unsigned int irq_flags_to_clear;
1107 unsigned int irq_flags_to_set;
1108 enum irq_gc_flags gc_flags;
1109 void (*exit)(struct irq_chip_generic *gc);
1110 struct irq_chip_generic *gc[];
1111 };
1112
1113 /**
1114 * struct irq_domain_chip_generic_info - Generic chip information structure
1115 * @name: Name of the generic interrupt chip
1116 * @handler: Interrupt handler used by the generic interrupt chip
1117 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
1118 * @num_ct: Number of irq_chip_type instances associated with each
1119 * chip
1120 * @irq_flags_to_clear: IRQ_* bits to clear in the mapping function
1121 * @irq_flags_to_set: IRQ_* bits to set in the mapping function
1122 * @gc_flags: Generic chip specific setup flags
1123 * @init: Function called on each chip when they are created.
1124 * Allow to do some additional chip initialisation.
1125 * @exit: Function called on each chip when they are destroyed.
1126 * Allow to do some chip cleanup operation.
1127 */
1128 struct irq_domain_chip_generic_info {
1129 const char *name;
1130 irq_flow_handler_t handler;
1131 unsigned int irqs_per_chip;
1132 unsigned int num_ct;
1133 unsigned int irq_flags_to_clear;
1134 unsigned int irq_flags_to_set;
1135 enum irq_gc_flags gc_flags;
1136 int (*init)(struct irq_chip_generic *gc);
1137 void (*exit)(struct irq_chip_generic *gc);
1138 };
1139
1140 /* Generic chip callback functions */
1141 void irq_gc_noop(struct irq_data *d);
1142 void irq_gc_mask_disable_reg(struct irq_data *d);
1143 void irq_gc_mask_set_bit(struct irq_data *d);
1144 void irq_gc_mask_clr_bit(struct irq_data *d);
1145 void irq_gc_unmask_enable_reg(struct irq_data *d);
1146 void irq_gc_ack_set_bit(struct irq_data *d);
1147 void irq_gc_ack_clr_bit(struct irq_data *d);
1148 void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
1149 void irq_gc_eoi(struct irq_data *d);
1150 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1151
1152 /* Setup functions for irq_chip_generic */
1153 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1154 irq_hw_number_t hw_irq);
1155 void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq);
1156 struct irq_chip_generic *
1157 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1158 void __iomem *reg_base, irq_flow_handler_t handler);
1159 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1160 enum irq_gc_flags flags, unsigned int clr,
1161 unsigned int set);
1162 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1163 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1164 unsigned int clr, unsigned int set);
1165
1166 struct irq_chip_generic *
1167 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1168 unsigned int irq_base, void __iomem *reg_base,
1169 irq_flow_handler_t handler);
1170 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1171 u32 msk, enum irq_gc_flags flags,
1172 unsigned int clr, unsigned int set);
1173
1174 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1175
1176 #ifdef CONFIG_GENERIC_IRQ_CHIP
1177 int irq_domain_alloc_generic_chips(struct irq_domain *d,
1178 const struct irq_domain_chip_generic_info *info);
1179 void irq_domain_remove_generic_chips(struct irq_domain *d);
1180 #else
1181 static inline int
irq_domain_alloc_generic_chips(struct irq_domain * d,const struct irq_domain_chip_generic_info * info)1182 irq_domain_alloc_generic_chips(struct irq_domain *d,
1183 const struct irq_domain_chip_generic_info *info)
1184 {
1185 return -EINVAL;
1186 }
irq_domain_remove_generic_chips(struct irq_domain * d)1187 static inline void irq_domain_remove_generic_chips(struct irq_domain *d) { }
1188 #endif /* CONFIG_GENERIC_IRQ_CHIP */
1189
1190 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1191 int num_ct, const char *name,
1192 irq_flow_handler_t handler,
1193 unsigned int clr, unsigned int set,
1194 enum irq_gc_flags flags);
1195
1196 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1197 handler, clr, set, flags) \
1198 ({ \
1199 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1200 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1201 handler, clr, set, flags); \
1202 })
1203
irq_free_generic_chip(struct irq_chip_generic * gc)1204 static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1205 {
1206 kfree(gc);
1207 }
1208
irq_destroy_generic_chip(struct irq_chip_generic * gc,u32 msk,unsigned int clr,unsigned int set)1209 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1210 u32 msk, unsigned int clr,
1211 unsigned int set)
1212 {
1213 irq_remove_generic_chip(gc, msk, clr, set);
1214 irq_free_generic_chip(gc);
1215 }
1216
irq_data_get_chip_type(struct irq_data * d)1217 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1218 {
1219 return container_of(d->chip, struct irq_chip_type, chip);
1220 }
1221
1222 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1223
irq_reg_writel(struct irq_chip_generic * gc,u32 val,int reg_offset)1224 static inline void irq_reg_writel(struct irq_chip_generic *gc,
1225 u32 val, int reg_offset)
1226 {
1227 if (gc->reg_writel)
1228 gc->reg_writel(val, gc->reg_base + reg_offset);
1229 else
1230 writel(val, gc->reg_base + reg_offset);
1231 }
1232
irq_reg_readl(struct irq_chip_generic * gc,int reg_offset)1233 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1234 int reg_offset)
1235 {
1236 if (gc->reg_readl)
1237 return gc->reg_readl(gc->reg_base + reg_offset);
1238 else
1239 return readl(gc->reg_base + reg_offset);
1240 }
1241
1242 struct irq_matrix;
1243 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1244 unsigned int alloc_start,
1245 unsigned int alloc_end);
1246 void irq_matrix_online(struct irq_matrix *m);
1247 void irq_matrix_offline(struct irq_matrix *m);
1248 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1249 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1250 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
1251 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
1252 unsigned int *mapped_cpu);
1253 void irq_matrix_reserve(struct irq_matrix *m);
1254 void irq_matrix_remove_reserved(struct irq_matrix *m);
1255 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1256 bool reserved, unsigned int *mapped_cpu);
1257 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1258 unsigned int bit, bool managed);
1259 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1260 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1261 unsigned int irq_matrix_allocated(struct irq_matrix *m);
1262 unsigned int irq_matrix_reserved(struct irq_matrix *m);
1263 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1264
1265 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1266 #define INVALID_HWIRQ (~0UL)
1267 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1268 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1269 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1270 int ipi_send_single(unsigned int virq, unsigned int cpu);
1271 int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1272
1273 void ipi_mux_process(void);
1274 int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu));
1275
1276 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1277 /*
1278 * Registers a generic IRQ handling function as the top-level IRQ handler in
1279 * the system, which is generally the first C code called from an assembly
1280 * architecture-specific interrupt handler.
1281 *
1282 * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1283 * registered.
1284 */
1285 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1286
1287 /*
1288 * Allows interrupt handlers to find the irqchip that's been registered as the
1289 * top-level IRQ handler.
1290 */
1291 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1292 asmlinkage void generic_handle_arch_irq(struct pt_regs *regs);
1293 #else
1294 #ifndef set_handle_irq
1295 #define set_handle_irq(handle_irq) \
1296 do { \
1297 (void)handle_irq; \
1298 WARN_ON(1); \
1299 } while (0)
1300 #endif
1301 #endif
1302
1303 #endif /* _LINUX_IRQ_H */
1304