1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
6 */
7
8 /* Common definitions for all Efx net driver code */
9
10 #ifndef EFX_NET_DRIVER_H
11 #define EFX_NET_DRIVER_H
12
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/if_vlan.h>
17 #include <linux/timer.h>
18 #include <linux/mii.h>
19 #include <linux/list.h>
20 #include <linux/pci.h>
21 #include <linux/device.h>
22 #include <linux/highmem.h>
23 #include <linux/workqueue.h>
24 #include <linux/mutex.h>
25 #include <linux/rwsem.h>
26 #include <linux/vmalloc.h>
27 #include <linux/mtd/mtd.h>
28 #include <net/busy_poll.h>
29 #include <net/xdp.h>
30 #include <net/netevent.h>
31
32 #include "enum.h"
33 #include "bitfield.h"
34 #include "filter.h"
35
36 /**************************************************************************
37 *
38 * Build definitions
39 *
40 **************************************************************************/
41
42 #ifdef DEBUG
43 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
44 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
45 #else
46 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
47 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
48 #endif
49
50 /**************************************************************************
51 *
52 * Efx data structures
53 *
54 **************************************************************************/
55
56 #define EFX_MAX_CHANNELS 32U
57 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
58 #define EFX_EXTRA_CHANNEL_IOV 0
59 #define EFX_EXTRA_CHANNEL_PTP 1
60 #define EFX_EXTRA_CHANNEL_TC 2
61 #define EFX_MAX_EXTRA_CHANNELS 3U
62
63 /* Checksum generation is a per-queue option in hardware, so each
64 * queue visible to the networking core is backed by two hardware TX
65 * queues. */
66 #define EFX_MAX_TX_TC 2
67 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
68 #define EFX_TXQ_TYPE_OUTER_CSUM 1 /* Outer checksum offload */
69 #define EFX_TXQ_TYPE_INNER_CSUM 2 /* Inner checksum offload */
70 #define EFX_TXQ_TYPES 4
71 #define EFX_MAX_TXQ_PER_CHANNEL 4
72 #define EFX_MAX_TX_QUEUES (EFX_MAX_TXQ_PER_CHANNEL * EFX_MAX_CHANNELS)
73
74 /* Maximum possible MTU the driver supports */
75 #define EFX_MAX_MTU (9 * 1024)
76
77 /* Minimum MTU, from RFC791 (IP) */
78 #define EFX_MIN_MTU 68
79
80 /* Maximum total header length for TSOv2 */
81 #define EFX_TSO2_MAX_HDRLEN 208
82
83 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
84 * and should be a multiple of the cache line size.
85 */
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
87
88 /* If possible, we should ensure cache line alignment at start and end
89 * of every buffer. Otherwise, we just need to ensure 4-byte
90 * alignment of the network header.
91 */
92 #if NET_IP_ALIGN == 0
93 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
94 #else
95 #define EFX_RX_BUF_ALIGNMENT 4
96 #endif
97
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
99 * still fit two standard MTU size packets into a single 4K page.
100 */
101 #define EFX_XDP_HEADROOM 128
102 #define EFX_XDP_TAILROOM SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
103
104 /* Forward declare Precision Time Protocol (PTP) support structure. */
105 struct efx_ptp_data;
106 struct hwtstamp_config;
107
108 struct efx_self_tests;
109
110 /**
111 * struct efx_buffer - A general-purpose DMA buffer
112 * @addr: host base address of the buffer
113 * @dma_addr: DMA base address of the buffer
114 * @len: Buffer length, in bytes
115 *
116 * The NIC uses these buffers for its interrupt status registers and
117 * MAC stats dumps.
118 */
119 struct efx_buffer {
120 void *addr;
121 dma_addr_t dma_addr;
122 unsigned int len;
123 };
124
125 /**
126 * struct efx_tx_buffer - buffer state for a TX descriptor
127 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
128 * freed when descriptor completes
129 * @xdpf: When @flags & %EFX_TX_BUF_XDP, the XDP frame information; its @data
130 * member is the associated buffer to drop a page reference on.
131 * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
132 * descriptor.
133 * @dma_addr: DMA address of the fragment.
134 * @flags: Flags for allocation and DMA mapping type
135 * @len: Length of this fragment.
136 * This field is zero when the queue slot is empty.
137 * @unmap_len: Length of this fragment to unmap
138 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
139 * Only valid if @unmap_len != 0.
140 */
141 struct efx_tx_buffer {
142 union {
143 const struct sk_buff *skb;
144 struct xdp_frame *xdpf;
145 };
146 union {
147 efx_qword_t option; /* EF10 */
148 dma_addr_t dma_addr;
149 };
150 unsigned short flags;
151 unsigned short len;
152 unsigned short unmap_len;
153 unsigned short dma_offset;
154 };
155 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
156 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
157 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
158 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
159 #define EFX_TX_BUF_XDP 0x20 /* buffer was sent with XDP */
160 #define EFX_TX_BUF_TSO_V3 0x40 /* empty buffer for a TSO_V3 descriptor */
161 #define EFX_TX_BUF_EFV 0x100 /* buffer was sent from representor */
162
163 /**
164 * struct efx_tx_queue - An Efx TX queue
165 *
166 * This is a ring buffer of TX fragments.
167 * Since the TX completion path always executes on the same
168 * CPU and the xmit path can operate on different CPUs,
169 * performance is increased by ensuring that the completion
170 * path and the xmit path operate on different cache lines.
171 * This is particularly important if the xmit path is always
172 * executing on one CPU which is different from the completion
173 * path. There is also a cache line for members which are
174 * read but not written on the fast path.
175 *
176 * @efx: The associated Efx NIC
177 * @queue: DMA queue number
178 * @label: Label for TX completion events.
179 * Is our index within @channel->tx_queue array.
180 * @type: configuration type of this TX queue. A bitmask of %EFX_TXQ_TYPE_* flags.
181 * @tso_version: Version of TSO in use for this queue.
182 * @tso_encap: Is encapsulated TSO supported? Supported in TSOv2 on 8000 series.
183 * @channel: The associated channel
184 * @core_txq: The networking core TX queue structure
185 * @buffer: The software buffer ring
186 * @cb_page: Array of pages of copy buffers. Carved up according to
187 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
188 * @txd: The hardware descriptor ring
189 * @ptr_mask: The size of the ring minus 1.
190 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
191 * Size of the region is efx_piobuf_size.
192 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
193 * @initialised: Has hardware queue been initialised?
194 * @timestamping: Is timestamping enabled for this channel?
195 * @xdp_tx: Is this an XDP tx queue?
196 * @old_complete_packets: Value of @complete_packets as of last
197 * efx_init_tx_queue()
198 * @old_complete_bytes: Value of @complete_bytes as of last
199 * efx_init_tx_queue()
200 * @old_tso_bursts: Value of @tso_bursts as of last efx_init_tx_queue()
201 * @old_tso_packets: Value of @tso_packets as of last efx_init_tx_queue()
202 * @read_count: Current read pointer.
203 * This is the number of buffers that have been removed from both rings.
204 * @old_write_count: The value of @write_count when last checked.
205 * This is here for performance reasons. The xmit path will
206 * only get the up-to-date value of @write_count if this
207 * variable indicates that the queue is empty. This is to
208 * avoid cache-line ping-pong between the xmit path and the
209 * completion path.
210 * @merge_events: Number of TX merged completion events
211 * @bytes_compl: Number of bytes completed during this NAPI poll
212 * (efx_process_channel()). For BQL.
213 * @pkts_compl: Number of packets completed during this NAPI poll.
214 * @complete_packets: Number of packets completed since this struct was
215 * created. Only counts SKB packets, not XDP TX (it accumulates
216 * the same values that are reported to BQL).
217 * @complete_bytes: Number of bytes completed since this struct was
218 * created. For TSO, counts the superframe size, not the sizes of
219 * generated frames on the wire (i.e. the headers are only counted
220 * once)
221 * @complete_xdp_packets: Number of XDP TX packets completed since this
222 * struct was created.
223 * @complete_xdp_bytes: Number of XDP TX bytes completed since this
224 * struct was created.
225 * @completed_timestamp_major: Top part of the most recent tx timestamp.
226 * @completed_timestamp_minor: Low part of the most recent tx timestamp.
227 * @insert_count: Current insert pointer
228 * This is the number of buffers that have been added to the
229 * software ring.
230 * @write_count: Current write pointer
231 * This is the number of buffers that have been added to the
232 * hardware ring.
233 * @packet_write_count: Completable write pointer
234 * This is the write pointer of the last packet written.
235 * Normally this will equal @write_count, but as option descriptors
236 * don't produce completion events, they won't update this.
237 * Filled in iff @efx->type->option_descriptors; only used for PIO.
238 * Thus, this is only written and used on EF10.
239 * @old_read_count: The value of read_count when last checked.
240 * This is here for performance reasons. The xmit path will
241 * only get the up-to-date value of read_count if this
242 * variable indicates that the queue is full. This is to
243 * avoid cache-line ping-pong between the xmit path and the
244 * completion path.
245 * @tso_bursts: Number of times TSO xmit invoked by kernel
246 * @tso_long_headers: Number of packets with headers too long for standard
247 * blocks
248 * @tso_packets: Number of packets via the TSO xmit path
249 * @tso_fallbacks: Number of times TSO fallback used
250 * @pushes: Number of times the TX push feature has been used
251 * @pio_packets: Number of times the TX PIO feature has been used
252 * @xmit_pending: Are any packets waiting to be pushed to the NIC
253 * @cb_packets: Number of times the TX copybreak feature has been used
254 * @notify_count: Count of notified descriptors to the NIC
255 * @tx_packets: Number of packets sent since this struct was created
256 * @empty_read_count: If the completion path has seen the queue as empty
257 * and the transmission path has not yet checked this, the value of
258 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
259 */
260 struct efx_tx_queue {
261 /* Members which don't change on the fast path */
262 struct efx_nic *efx ____cacheline_aligned_in_smp;
263 unsigned int queue;
264 unsigned int label;
265 unsigned int type;
266 unsigned int tso_version;
267 bool tso_encap;
268 struct efx_channel *channel;
269 struct netdev_queue *core_txq;
270 struct efx_tx_buffer *buffer;
271 struct efx_buffer *cb_page;
272 struct efx_buffer txd;
273 unsigned int ptr_mask;
274 void __iomem *piobuf;
275 unsigned int piobuf_offset;
276 bool initialised;
277 bool timestamping;
278 bool xdp_tx;
279 unsigned long old_complete_packets;
280 unsigned long old_complete_bytes;
281 unsigned int old_tso_bursts;
282 unsigned int old_tso_packets;
283
284 /* Members used mainly on the completion path */
285 unsigned int read_count ____cacheline_aligned_in_smp;
286 unsigned int old_write_count;
287 unsigned int merge_events;
288 unsigned int bytes_compl;
289 unsigned int pkts_compl;
290 unsigned long complete_packets;
291 unsigned long complete_bytes;
292 unsigned long complete_xdp_packets;
293 unsigned long complete_xdp_bytes;
294 u32 completed_timestamp_major;
295 u32 completed_timestamp_minor;
296
297 /* Members used only on the xmit path */
298 unsigned int insert_count ____cacheline_aligned_in_smp;
299 unsigned int write_count;
300 unsigned int packet_write_count;
301 unsigned int old_read_count;
302 unsigned int tso_bursts;
303 unsigned int tso_long_headers;
304 unsigned int tso_packets;
305 unsigned int tso_fallbacks;
306 unsigned int pushes;
307 unsigned int pio_packets;
308 bool xmit_pending;
309 unsigned int cb_packets;
310 unsigned int notify_count;
311 /* Statistics to supplement MAC stats */
312 unsigned long tx_packets;
313
314 /* Members shared between paths and sometimes updated */
315 unsigned int empty_read_count ____cacheline_aligned_in_smp;
316 #define EFX_EMPTY_COUNT_VALID 0x80000000
317 atomic_t flush_outstanding;
318 };
319
320 #define EFX_TX_CB_ORDER 7
321 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
322
323 /**
324 * struct efx_rx_buffer - An Efx RX data buffer
325 * @dma_addr: DMA base address of the buffer
326 * @page: The associated page buffer.
327 * Will be %NULL if the buffer slot is currently free.
328 * @page_offset: If pending: offset in @page of DMA base address.
329 * If completed: offset in @page of Ethernet header.
330 * @len: If pending: length for DMA descriptor.
331 * If completed: received length, excluding hash prefix.
332 * @flags: Flags for buffer and packet state. These are only set on the
333 * first buffer of a scattered packet.
334 */
335 struct efx_rx_buffer {
336 dma_addr_t dma_addr;
337 struct page *page;
338 u16 page_offset;
339 u16 len;
340 u16 flags;
341 };
342 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
343 #define EFX_RX_PKT_CSUMMED 0x0002
344 #define EFX_RX_PKT_DISCARD 0x0004
345 #define EFX_RX_PKT_TCP 0x0040
346 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
347 #define EFX_RX_PKT_CSUM_LEVEL 0x0200
348
349 /**
350 * struct efx_rx_page_state - Page-based rx buffer state
351 *
352 * Inserted at the start of every page allocated for receive buffers.
353 * Used to facilitate sharing dma mappings between recycled rx buffers
354 * and those passed up to the kernel.
355 *
356 * @dma_addr: The dma address of this page.
357 */
358 struct efx_rx_page_state {
359 dma_addr_t dma_addr;
360
361 unsigned int __pad[] ____cacheline_aligned;
362 };
363
364 /**
365 * struct efx_rx_queue - An Efx RX queue
366 * @efx: The associated Efx NIC
367 * @core_index: Index of network core RX queue. Will be >= 0 iff this
368 * is associated with a real RX queue.
369 * @buffer: The software buffer ring
370 * @rxd: The hardware descriptor ring
371 * @ptr_mask: The size of the ring minus 1.
372 * @refill_enabled: Enable refill whenever fill level is low
373 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
374 * @rxq_flush_pending.
375 * @grant_credits: Posted RX descriptors need to be granted to the MAE with
376 * %MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS. For %EFX_EXTRA_CHANNEL_TC,
377 * and only supported on EF100.
378 * @added_count: Number of buffers added to the receive queue.
379 * @notified_count: Number of buffers given to NIC (<= @added_count).
380 * @granted_count: Number of buffers granted to the MAE (<= @notified_count).
381 * @removed_count: Number of buffers removed from the receive queue.
382 * @scatter_n: Used by NIC specific receive code.
383 * @scatter_len: Used by NIC specific receive code.
384 * @page_ring: The ring to store DMA mapped pages for reuse.
385 * @page_add: Counter to calculate the write pointer for the recycle ring.
386 * @page_remove: Counter to calculate the read pointer for the recycle ring.
387 * @page_recycle_count: The number of pages that have been recycled.
388 * @page_recycle_failed: The number of pages that couldn't be recycled because
389 * the kernel still held a reference to them.
390 * @page_recycle_full: The number of pages that were released because the
391 * recycle ring was full.
392 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
393 * @max_fill: RX descriptor maximum fill level (<= ring size)
394 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
395 * (<= @max_fill)
396 * @min_fill: RX descriptor minimum non-zero fill level.
397 * This records the minimum fill level observed when a ring
398 * refill was triggered.
399 * @recycle_count: RX buffer recycle counter.
400 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
401 * @grant_work: workitem used to grant credits to the MAE if @grant_credits
402 * @rx_packets: Number of packets received since this struct was created
403 * @rx_bytes: Number of bytes received since this struct was created
404 * @old_rx_packets: Value of @rx_packets as of last efx_init_rx_queue()
405 * @old_rx_bytes: Value of @rx_bytes as of last efx_init_rx_queue()
406 * @xdp_rxq_info: XDP specific RX queue information.
407 * @xdp_rxq_info_valid: Is xdp_rxq_info valid data?.
408 */
409 struct efx_rx_queue {
410 struct efx_nic *efx;
411 int core_index;
412 struct efx_rx_buffer *buffer;
413 struct efx_buffer rxd;
414 unsigned int ptr_mask;
415 bool refill_enabled;
416 bool flush_pending;
417 bool grant_credits;
418
419 unsigned int added_count;
420 unsigned int notified_count;
421 unsigned int granted_count;
422 unsigned int removed_count;
423 unsigned int scatter_n;
424 unsigned int scatter_len;
425 struct page **page_ring;
426 unsigned int page_add;
427 unsigned int page_remove;
428 unsigned int page_recycle_count;
429 unsigned int page_recycle_failed;
430 unsigned int page_recycle_full;
431 unsigned int page_ptr_mask;
432 unsigned int max_fill;
433 unsigned int fast_fill_trigger;
434 unsigned int min_fill;
435 unsigned int min_overfill;
436 unsigned int recycle_count;
437 struct timer_list slow_fill;
438 unsigned int slow_fill_count;
439 struct work_struct grant_work;
440 /* Statistics to supplement MAC stats */
441 unsigned long rx_packets;
442 unsigned long rx_bytes;
443 unsigned long old_rx_packets;
444 unsigned long old_rx_bytes;
445 struct xdp_rxq_info xdp_rxq_info;
446 bool xdp_rxq_info_valid;
447 };
448
449 enum efx_sync_events_state {
450 SYNC_EVENTS_DISABLED = 0,
451 SYNC_EVENTS_QUIESCENT,
452 SYNC_EVENTS_REQUESTED,
453 SYNC_EVENTS_VALID,
454 };
455
456 /**
457 * struct efx_channel - An Efx channel
458 *
459 * A channel comprises an event queue, at least one TX queue, at least
460 * one RX queue, and an associated tasklet for processing the event
461 * queue.
462 *
463 * @efx: Associated Efx NIC
464 * @channel: Channel instance number
465 * @type: Channel type definition
466 * @eventq_init: Event queue initialised flag
467 * @enabled: Channel enabled indicator
468 * @irq: IRQ number (MSI and MSI-X only)
469 * @irq_moderation_us: IRQ moderation value (in microseconds)
470 * @napi_dev: Net device used with NAPI
471 * @napi_str: NAPI control structure
472 * @state: state for NAPI vs busy polling
473 * @state_lock: lock protecting @state
474 * @eventq: Event queue buffer
475 * @eventq_mask: Event queue pointer mask
476 * @eventq_read_ptr: Event queue read pointer
477 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
478 * @irq_count: Number of IRQs since last adaptive moderation decision
479 * @irq_mod_score: IRQ moderation score
480 * @rfs_filter_count: number of accelerated RFS filters currently in place;
481 * equals the count of @rps_flow_id slots filled
482 * @rfs_last_expiry: value of jiffies last time some accelerated RFS filters
483 * were checked for expiry
484 * @rfs_expire_index: next accelerated RFS filter ID to check for expiry
485 * @n_rfs_succeeded: number of successful accelerated RFS filter insertions
486 * @n_rfs_failed: number of failed accelerated RFS filter insertions
487 * @filter_work: Work item for efx_filter_rfs_expire()
488 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
489 * indexed by filter ID
490 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
491 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
492 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
493 * @n_rx_overlength: Count of RX_OVERLENGTH errors
494 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
495 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
496 * lack of descriptors
497 * @n_rx_merge_events: Number of RX merged completion events
498 * @n_rx_merge_packets: Number of RX packets completed by merged events
499 * @n_rx_xdp_drops: Count of RX packets intentionally dropped due to XDP
500 * @n_rx_xdp_bad_drops: Count of RX packets dropped due to XDP errors
501 * @n_rx_xdp_tx: Count of RX packets retransmitted due to XDP
502 * @n_rx_xdp_redirect: Count of RX packets redirected to a different NIC by XDP
503 * @n_rx_mport_bad: Count of RX packets dropped because their ingress mport was
504 * not recognised
505 * @old_n_rx_hw_drops: Count of all RX packets dropped for any reason as of last
506 * efx_start_channels()
507 * @old_n_rx_hw_drop_overruns: Value of @n_rx_nodesc_trunc as of last
508 * efx_start_channels()
509 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
510 * __efx_rx_packet(), or zero if there is none
511 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
512 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
513 * @rx_list: list of SKBs from current RX, awaiting processing
514 * @rx_queue: RX queue for this channel
515 * @tx_queue: TX queues for this channel
516 * @tx_queue_by_type: pointers into @tx_queue, or %NULL, indexed by txq type
517 * @sync_events_state: Current state of sync events on this channel
518 * @sync_timestamp_major: Major part of the last ptp sync event
519 * @sync_timestamp_minor: Minor part of the last ptp sync event
520 */
521 struct efx_channel {
522 struct efx_nic *efx;
523 int channel;
524 const struct efx_channel_type *type;
525 bool eventq_init;
526 bool enabled;
527 int irq;
528 unsigned int irq_moderation_us;
529 struct net_device *napi_dev;
530 struct napi_struct napi_str;
531 #ifdef CONFIG_NET_RX_BUSY_POLL
532 unsigned long busy_poll_state;
533 #endif
534 struct efx_buffer eventq;
535 unsigned int eventq_mask;
536 unsigned int eventq_read_ptr;
537 int event_test_cpu;
538
539 unsigned int irq_count;
540 unsigned int irq_mod_score;
541 #ifdef CONFIG_RFS_ACCEL
542 unsigned int rfs_filter_count;
543 unsigned int rfs_last_expiry;
544 unsigned int rfs_expire_index;
545 unsigned int n_rfs_succeeded;
546 unsigned int n_rfs_failed;
547 struct delayed_work filter_work;
548 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF
549 u32 *rps_flow_id;
550 #endif
551
552 unsigned int n_rx_ip_hdr_chksum_err;
553 unsigned int n_rx_tcp_udp_chksum_err;
554 unsigned int n_rx_outer_ip_hdr_chksum_err;
555 unsigned int n_rx_outer_tcp_udp_chksum_err;
556 unsigned int n_rx_inner_ip_hdr_chksum_err;
557 unsigned int n_rx_inner_tcp_udp_chksum_err;
558 unsigned int n_rx_eth_crc_err;
559 unsigned int n_rx_frm_trunc;
560 unsigned int n_rx_overlength;
561 unsigned int n_skbuff_leaks;
562 unsigned int n_rx_nodesc_trunc;
563 unsigned int n_rx_merge_events;
564 unsigned int n_rx_merge_packets;
565 unsigned int n_rx_xdp_drops;
566 unsigned int n_rx_xdp_bad_drops;
567 unsigned int n_rx_xdp_tx;
568 unsigned int n_rx_xdp_redirect;
569 unsigned int n_rx_mport_bad;
570
571 unsigned int old_n_rx_hw_drops;
572 unsigned int old_n_rx_hw_drop_overruns;
573
574 unsigned int rx_pkt_n_frags;
575 unsigned int rx_pkt_index;
576
577 struct list_head *rx_list;
578
579 struct efx_rx_queue rx_queue;
580 struct efx_tx_queue tx_queue[EFX_MAX_TXQ_PER_CHANNEL];
581 struct efx_tx_queue *tx_queue_by_type[EFX_TXQ_TYPES];
582
583 enum efx_sync_events_state sync_events_state;
584 u32 sync_timestamp_major;
585 u32 sync_timestamp_minor;
586 };
587
588 /**
589 * struct efx_msi_context - Context for each MSI
590 * @efx: The associated NIC
591 * @index: Index of the channel/IRQ
592 * @name: Name of the channel/IRQ
593 *
594 * Unlike &struct efx_channel, this is never reallocated and is always
595 * safe for the IRQ handler to access.
596 */
597 struct efx_msi_context {
598 struct efx_nic *efx;
599 unsigned int index;
600 char name[IFNAMSIZ + 6];
601 };
602
603 /**
604 * struct efx_channel_type - distinguishes traffic and extra channels
605 * @handle_no_channel: Handle failure to allocate an extra channel
606 * @pre_probe: Set up extra state prior to initialisation
607 * @start: called early in efx_start_channels()
608 * @stop: called early in efx_stop_channels()
609 * @post_remove: Tear down extra state after finalisation, if allocated.
610 * May be called on channels that have not been probed.
611 * @get_name: Generate the channel's name (used for its IRQ handler)
612 * @copy: Copy the channel state prior to reallocation. May be %NULL if
613 * reallocation is not supported.
614 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
615 * @receive_raw: Handle an RX buffer ready to be passed to __efx_rx_packet()
616 * @want_txqs: Determine whether this channel should have TX queues
617 * created. If %NULL, TX queues are not created.
618 * @keep_eventq: Flag for whether event queue should be kept initialised
619 * while the device is stopped
620 * @want_pio: Flag for whether PIO buffers should be linked to this
621 * channel's TX queues.
622 */
623 struct efx_channel_type {
624 void (*handle_no_channel)(struct efx_nic *);
625 int (*pre_probe)(struct efx_channel *);
626 int (*start)(struct efx_channel *);
627 void (*stop)(struct efx_channel *);
628 void (*post_remove)(struct efx_channel *);
629 void (*get_name)(struct efx_channel *, char *buf, size_t len);
630 struct efx_channel *(*copy)(const struct efx_channel *);
631 bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
632 bool (*receive_raw)(struct efx_rx_queue *, u32);
633 bool (*want_txqs)(struct efx_channel *);
634 bool keep_eventq;
635 bool want_pio;
636 };
637
638 enum efx_led_mode {
639 EFX_LED_OFF = 0,
640 EFX_LED_ON = 1,
641 EFX_LED_DEFAULT = 2
642 };
643
644 #define STRING_TABLE_LOOKUP(val, member) \
645 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
646
647 extern const char *const efx_loopback_mode_names[];
648 extern const unsigned int efx_loopback_mode_max;
649 #define LOOPBACK_MODE(efx) \
650 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
651
652 enum efx_int_mode {
653 /* Be careful if altering to correct macro below */
654 EFX_INT_MODE_MSIX = 0,
655 EFX_INT_MODE_MSI = 1,
656 EFX_INT_MODE_LEGACY = 2,
657 EFX_INT_MODE_MAX /* Insert any new items before this */
658 };
659 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
660
661 enum nic_state {
662 STATE_UNINIT = 0, /* device being probed/removed */
663 STATE_PROBED, /* hardware probed */
664 STATE_NET_DOWN, /* netdev registered */
665 STATE_NET_UP, /* ready for traffic */
666 STATE_DISABLED, /* device disabled due to hardware errors */
667
668 STATE_RECOVERY = 0x100,/* recovering from PCI error */
669 STATE_FROZEN = 0x200, /* frozen by power management */
670 };
671
efx_net_active(enum nic_state state)672 static inline bool efx_net_active(enum nic_state state)
673 {
674 return state == STATE_NET_DOWN || state == STATE_NET_UP;
675 }
676
efx_frozen(enum nic_state state)677 static inline bool efx_frozen(enum nic_state state)
678 {
679 return state & STATE_FROZEN;
680 }
681
efx_recovering(enum nic_state state)682 static inline bool efx_recovering(enum nic_state state)
683 {
684 return state & STATE_RECOVERY;
685 }
686
efx_freeze(enum nic_state state)687 static inline enum nic_state efx_freeze(enum nic_state state)
688 {
689 WARN_ON(!efx_net_active(state));
690 return state | STATE_FROZEN;
691 }
692
efx_thaw(enum nic_state state)693 static inline enum nic_state efx_thaw(enum nic_state state)
694 {
695 WARN_ON(!efx_frozen(state));
696 return state & ~STATE_FROZEN;
697 }
698
efx_recover(enum nic_state state)699 static inline enum nic_state efx_recover(enum nic_state state)
700 {
701 WARN_ON(!efx_net_active(state));
702 return state | STATE_RECOVERY;
703 }
704
efx_recovered(enum nic_state state)705 static inline enum nic_state efx_recovered(enum nic_state state)
706 {
707 WARN_ON(!efx_recovering(state));
708 return state & ~STATE_RECOVERY;
709 }
710
711 /* Forward declaration */
712 struct efx_nic;
713
714 /* Pseudo bit-mask flow control field */
715 #define EFX_FC_RX FLOW_CTRL_RX
716 #define EFX_FC_TX FLOW_CTRL_TX
717 #define EFX_FC_AUTO 4
718
719 /**
720 * struct efx_link_state - Current state of the link
721 * @up: Link is up
722 * @fd: Link is full-duplex
723 * @fc: Actual flow control flags
724 * @speed: Link speed (Mbps)
725 */
726 struct efx_link_state {
727 bool up;
728 bool fd;
729 u8 fc;
730 unsigned int speed;
731 };
732
efx_link_state_equal(const struct efx_link_state * left,const struct efx_link_state * right)733 static inline bool efx_link_state_equal(const struct efx_link_state *left,
734 const struct efx_link_state *right)
735 {
736 return left->up == right->up && left->fd == right->fd &&
737 left->fc == right->fc && left->speed == right->speed;
738 }
739
740 /**
741 * enum efx_phy_mode - PHY operating mode flags
742 * @PHY_MODE_NORMAL: on and should pass traffic
743 * @PHY_MODE_TX_DISABLED: on with TX disabled
744 * @PHY_MODE_LOW_POWER: set to low power through MDIO
745 * @PHY_MODE_OFF: switched off through external control
746 * @PHY_MODE_SPECIAL: on but will not pass traffic
747 */
748 enum efx_phy_mode {
749 PHY_MODE_NORMAL = 0,
750 PHY_MODE_TX_DISABLED = 1,
751 PHY_MODE_LOW_POWER = 2,
752 PHY_MODE_OFF = 4,
753 PHY_MODE_SPECIAL = 8,
754 };
755
efx_phy_mode_disabled(enum efx_phy_mode mode)756 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
757 {
758 return !!(mode & ~PHY_MODE_TX_DISABLED);
759 }
760
761 /**
762 * struct efx_hw_stat_desc - Description of a hardware statistic
763 * @name: Name of the statistic as visible through ethtool, or %NULL if
764 * it should not be exposed
765 * @dma_width: Width in bits (0 for non-DMA statistics)
766 * @offset: Offset within stats (ignored for non-DMA statistics)
767 */
768 struct efx_hw_stat_desc {
769 const char *name;
770 u16 dma_width;
771 u16 offset;
772 };
773
774 struct vfdi_status;
775
776 /* The reserved RSS context value */
777 #define EFX_MCDI_RSS_CONTEXT_INVALID 0xffffffff
778 /**
779 * struct efx_rss_context_priv - driver private data for an RSS context
780 * @context_id: the RSS_CONTEXT_ID returned by MC firmware, or
781 * %EFX_MCDI_RSS_CONTEXT_INVALID if this context is not present on the NIC.
782 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
783 */
784 struct efx_rss_context_priv {
785 u32 context_id;
786 bool rx_hash_udp_4tuple;
787 };
788
789 /**
790 * struct efx_rss_context - an RSS context
791 * @priv: hardware-specific state
792 * @rx_hash_key: Toeplitz hash key for this RSS context
793 * @indir_table: Indirection table for this RSS context
794 */
795 struct efx_rss_context {
796 struct efx_rss_context_priv priv;
797 u8 rx_hash_key[40];
798 u32 rx_indir_table[128];
799 };
800
801 #ifdef CONFIG_RFS_ACCEL
802 /* Order of these is important, since filter_id >= %EFX_ARFS_FILTER_ID_PENDING
803 * is used to test if filter does or will exist.
804 */
805 #define EFX_ARFS_FILTER_ID_PENDING -1
806 #define EFX_ARFS_FILTER_ID_ERROR -2
807 #define EFX_ARFS_FILTER_ID_REMOVING -3
808 /**
809 * struct efx_arfs_rule - record of an ARFS filter and its IDs
810 * @node: linkage into hash table
811 * @spec: details of the filter (used as key for hash table). Use efx->type to
812 * determine which member to use.
813 * @rxq_index: channel to which the filter will steer traffic.
814 * @arfs_id: filter ID which was returned to ARFS
815 * @filter_id: index in software filter table. May be
816 * %EFX_ARFS_FILTER_ID_PENDING if filter was not inserted yet,
817 * %EFX_ARFS_FILTER_ID_ERROR if filter insertion failed, or
818 * %EFX_ARFS_FILTER_ID_REMOVING if expiry is currently removing the filter.
819 */
820 struct efx_arfs_rule {
821 struct hlist_node node;
822 struct efx_filter_spec spec;
823 u16 rxq_index;
824 u16 arfs_id;
825 s32 filter_id;
826 };
827
828 /* Size chosen so that the table is one page (4kB) */
829 #define EFX_ARFS_HASH_TABLE_SIZE 512
830
831 /**
832 * struct efx_async_filter_insertion - Request to asynchronously insert a filter
833 * @net_dev: Reference to the netdevice
834 * @net_dev_tracker: reference tracker entry for @net_dev
835 * @spec: The filter to insert
836 * @work: Workitem for this request
837 * @rxq_index: Identifies the channel for which this request was made
838 * @flow_id: Identifies the kernel-side flow for which this request was made
839 */
840 struct efx_async_filter_insertion {
841 struct net_device *net_dev;
842 netdevice_tracker net_dev_tracker;
843 struct efx_filter_spec spec;
844 struct work_struct work;
845 u16 rxq_index;
846 u32 flow_id;
847 };
848
849 /* Maximum number of ARFS workitems that may be in flight on an efx_nic */
850 #define EFX_RPS_MAX_IN_FLIGHT 8
851 #endif /* CONFIG_RFS_ACCEL */
852
853 enum efx_xdp_tx_queues_mode {
854 EFX_XDP_TX_QUEUES_DEDICATED, /* one queue per core, locking not needed */
855 EFX_XDP_TX_QUEUES_SHARED, /* each queue used by more than 1 core */
856 EFX_XDP_TX_QUEUES_BORROWED /* queues borrowed from net stack */
857 };
858
859 struct efx_mae;
860
861 /**
862 * struct efx_nic - an Efx NIC
863 * @name: Device name (net device name or bus id before net device registered)
864 * @pci_dev: The PCI device
865 * @node: List node for maintaning primary/secondary function lists
866 * @primary: &struct efx_nic instance for the primary function of this
867 * controller. May be the same structure, and may be %NULL if no
868 * primary function is bound. Serialised by rtnl_lock.
869 * @secondary_list: List of &struct efx_nic instances for the secondary PCI
870 * functions of the controller, if this is for the primary function.
871 * Serialised by rtnl_lock.
872 * @type: Controller type attributes
873 * @legacy_irq: IRQ number
874 * @workqueue: Workqueue for port reconfigures and the HW monitor.
875 * Work items do not hold and must not acquire RTNL.
876 * @workqueue_name: Name of workqueue
877 * @reset_work: Scheduled reset workitem
878 * @membase_phys: Memory BAR value as physical address
879 * @membase: Memory BAR value
880 * @vi_stride: step between per-VI registers / memory regions
881 * @interrupt_mode: Interrupt mode
882 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
883 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds
884 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
885 * @irqs_hooked: Channel interrupts are hooked
886 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
887 * @irq_rx_moderation_us: IRQ moderation time for RX event queues
888 * @msg_enable: Log message enable flags
889 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
890 * @reset_pending: Bitmask for pending resets
891 * @tx_queue: TX DMA queues
892 * @rx_queue: RX DMA queues
893 * @channel: Channels
894 * @msi_context: Context for each MSI
895 * @extra_channel_types: Types of extra (non-traffic) channels that
896 * should be allocated for this NIC
897 * @mae: Details of the Match Action Engine
898 * @xdp_tx_queue_count: Number of entries in %xdp_tx_queues.
899 * @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit.
900 * @xdp_txq_queues_mode: XDP TX queues sharing strategy.
901 * @rxq_entries: Size of receive queues requested by user.
902 * @txq_entries: Size of transmit queues requested by user.
903 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
904 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
905 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
906 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
907 * @sram_lim_qw: Qword address limit of SRAM
908 * @n_channels: Number of channels in use
909 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
910 * @n_tx_channels: Number of channels used for TX
911 * @n_extra_tx_channels: Number of extra channels with TX queues
912 * @tx_queues_per_channel: number of TX queues probed on each channel
913 * @n_xdp_channels: Number of channels used for XDP TX
914 * @xdp_channel_offset: Offset of zeroth channel used for XPD TX.
915 * @xdp_tx_per_channel: Max number of TX queues on an XDP TX channel.
916 * @rx_ip_align: RX DMA address offset to have IP header aligned in
917 * in accordance with NET_IP_ALIGN
918 * @rx_dma_len: Current maximum RX DMA length
919 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
920 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
921 * for use in sk_buff::truesize
922 * @rx_prefix_size: Size of RX prefix before packet data
923 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
924 * (valid only if @rx_prefix_size != 0; always negative)
925 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
926 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
927 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
928 * (valid only if channel->sync_timestamps_enabled; always negative)
929 * @rx_scatter: Scatter mode enabled for receives
930 * @rss_context: Main RSS context.
931 * @vport_id: The function's vport ID, only relevant for PFs
932 * @int_error_count: Number of internal errors seen recently
933 * @int_error_expire: Time at which error count will be expired
934 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
935 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
936 * acknowledge but do nothing else.
937 * @irq_status: Interrupt status buffer
938 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
939 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
940 * @selftest_work: Work item for asynchronous self-test
941 * @mtd_list: List of MTDs attached to the NIC
942 * @nic_data: Hardware dependent state
943 * @mcdi: Management-Controller-to-Driver Interface state
944 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
945 * efx_monitor() and efx_reconfigure_port()
946 * @port_enabled: Port enabled indicator.
947 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
948 * efx_mac_work() with kernel interfaces. Safe to read under any
949 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
950 * be held to modify it.
951 * @port_initialized: Port initialized?
952 * @net_dev: Operating system network device. Consider holding the rtnl lock
953 * @fixed_features: Features which cannot be turned off
954 * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS
955 * field of %MC_CMD_GET_CAPABILITIES_V4 response, or %MC_CMD_MAC_NSTATS)
956 * @stats_buffer: DMA buffer for statistics
957 * @phy_type: PHY type
958 * @phy_data: PHY private data (including PHY-specific stats)
959 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
960 * @link_advertising: Autonegotiation advertising flags
961 * @fec_config: Forward Error Correction configuration flags. For bit positions
962 * see &enum ethtool_fec_config_bits.
963 * @link_state: Current state of the link
964 * @n_link_state_changes: Number of times the link has changed state
965 * @wanted_fc: Wanted flow control flags
966 * @fc_disable: When non-zero flow control is disabled. Typically used to
967 * ensure that network back pressure doesn't delay dma queue flushes.
968 * Serialised by the rtnl lock.
969 * @mac_work: Work item for changing MAC promiscuity and multicast hash
970 * @loopback_mode: Loopback status
971 * @loopback_modes: Supported loopback mode bitmask
972 * @loopback_selftest: Offline self-test private state
973 * @xdp_prog: Current XDP programme for this interface
974 * @filter_sem: Filter table rw_semaphore, protects existence of @filter_state
975 * @filter_state: Architecture-dependent filter table state
976 * @rps_mutex: Protects RPS state of all channels
977 * @rps_slot_map: bitmap of in-flight entries in @rps_slot
978 * @rps_slot: array of ARFS insertion requests for efx_filter_rfs_work()
979 * @rps_hash_lock: Protects ARFS filter mapping state (@rps_hash_table and
980 * @rps_next_id).
981 * @rps_hash_table: Mapping between ARFS filters and their various IDs
982 * @rps_next_id: next arfs_id for an ARFS filter
983 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
984 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
985 * Decremented when the efx_flush_rx_queue() is called.
986 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
987 * completed (either success or failure). Not used when MCDI is used to
988 * flush receive queues.
989 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
990 * @vf_count: Number of VFs intended to be enabled.
991 * @vf_init_count: Number of VFs that have been fully initialised.
992 * @vi_scale: log2 number of vnics per VF.
993 * @vf_reps_lock: Protects vf_reps list
994 * @vf_reps: local VF reps
995 * @ptp_data: PTP state data
996 * @ptp_warned: has this NIC seen and warned about unexpected PTP events?
997 * @vpd_sn: Serial number read from VPD
998 * @xdp_rxq_info_failed: Have any of the rx queues failed to initialise their
999 * xdp_rxq_info structures?
1000 * @netdev_notifier: Netdevice notifier.
1001 * @netevent_notifier: Netevent notifier (for neighbour updates).
1002 * @tc: state for TC offload (EF100).
1003 * @devlink: reference to devlink structure owned by this device
1004 * @dl_port: devlink port associated with the PF
1005 * @mem_bar: The BAR that is mapped into membase.
1006 * @reg_base: Offset from the start of the bar to the function control window.
1007 * @reflash_mutex: Mutex for serialising firmware reflash operations.
1008 * @monitor_work: Hardware monitor workitem
1009 * @biu_lock: BIU (bus interface unit) lock
1010 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
1011 * field is used by efx_test_interrupts() to verify that an
1012 * interrupt has occurred.
1013 * @stats_lock: Statistics update lock. Must be held when calling
1014 * efx_nic_type::{update,start,stop}_stats.
1015 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
1016 *
1017 * This is stored in the private area of the &struct net_device.
1018 */
1019 struct efx_nic {
1020 /* The following fields should be written very rarely */
1021
1022 char name[IFNAMSIZ];
1023 struct list_head node;
1024 struct efx_nic *primary;
1025 struct list_head secondary_list;
1026 struct pci_dev *pci_dev;
1027 unsigned int port_num;
1028 const struct efx_nic_type *type;
1029 int legacy_irq;
1030 bool eeh_disabled_legacy_irq;
1031 struct workqueue_struct *workqueue;
1032 char workqueue_name[16];
1033 struct work_struct reset_work;
1034 resource_size_t membase_phys;
1035 void __iomem *membase;
1036
1037 unsigned int vi_stride;
1038
1039 enum efx_int_mode interrupt_mode;
1040 unsigned int timer_quantum_ns;
1041 unsigned int timer_max_ns;
1042 bool irq_rx_adaptive;
1043 bool irqs_hooked;
1044 unsigned int irq_mod_step_us;
1045 unsigned int irq_rx_moderation_us;
1046 u32 msg_enable;
1047
1048 enum nic_state state;
1049 unsigned long reset_pending;
1050
1051 struct efx_channel *channel[EFX_MAX_CHANNELS];
1052 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
1053 const struct efx_channel_type *
1054 extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
1055 struct efx_mae *mae;
1056
1057 unsigned int xdp_tx_queue_count;
1058 struct efx_tx_queue **xdp_tx_queues;
1059 enum efx_xdp_tx_queues_mode xdp_txq_queues_mode;
1060
1061 unsigned rxq_entries;
1062 unsigned txq_entries;
1063 unsigned int txq_stop_thresh;
1064 unsigned int txq_wake_thresh;
1065
1066 unsigned tx_dc_base;
1067 unsigned rx_dc_base;
1068 unsigned sram_lim_qw;
1069
1070 unsigned int max_channels;
1071 unsigned int max_vis;
1072 unsigned int max_tx_channels;
1073 unsigned n_channels;
1074 unsigned n_rx_channels;
1075 unsigned rss_spread;
1076 unsigned tx_channel_offset;
1077 unsigned n_tx_channels;
1078 unsigned n_extra_tx_channels;
1079 unsigned int tx_queues_per_channel;
1080 unsigned int n_xdp_channels;
1081 unsigned int xdp_channel_offset;
1082 unsigned int xdp_tx_per_channel;
1083 unsigned int rx_ip_align;
1084 unsigned int rx_dma_len;
1085 unsigned int rx_buffer_order;
1086 unsigned int rx_buffer_truesize;
1087 unsigned int rx_page_buf_step;
1088 unsigned int rx_bufs_per_page;
1089 unsigned int rx_pages_per_batch;
1090 unsigned int rx_prefix_size;
1091 int rx_packet_hash_offset;
1092 int rx_packet_len_offset;
1093 int rx_packet_ts_offset;
1094 bool rx_scatter;
1095 struct efx_rss_context rss_context;
1096 u32 vport_id;
1097
1098 unsigned int_error_count;
1099 unsigned long int_error_expire;
1100
1101 bool must_realloc_vis;
1102 bool irq_soft_enabled;
1103 struct efx_buffer irq_status;
1104 unsigned irq_zero_count;
1105 unsigned irq_level;
1106 struct delayed_work selftest_work;
1107
1108 #ifdef CONFIG_SFC_MTD
1109 struct list_head mtd_list;
1110 #endif
1111
1112 void *nic_data;
1113 struct efx_mcdi_data *mcdi;
1114
1115 struct mutex mac_lock;
1116 struct work_struct mac_work;
1117 bool port_enabled;
1118
1119 bool mc_bist_for_other_fn;
1120 bool port_initialized;
1121 struct net_device *net_dev;
1122
1123 netdev_features_t fixed_features;
1124
1125 u16 num_mac_stats;
1126 struct efx_buffer stats_buffer;
1127 u64 rx_nodesc_drops_total;
1128 u64 rx_nodesc_drops_while_down;
1129 bool rx_nodesc_drops_prev_state;
1130
1131 unsigned int phy_type;
1132 void *phy_data;
1133 enum efx_phy_mode phy_mode;
1134
1135 __ETHTOOL_DECLARE_LINK_MODE_MASK(link_advertising);
1136 u32 fec_config;
1137 struct efx_link_state link_state;
1138 unsigned int n_link_state_changes;
1139
1140 u8 wanted_fc;
1141 unsigned fc_disable;
1142
1143 atomic_t rx_reset;
1144 enum efx_loopback_mode loopback_mode;
1145 u64 loopback_modes;
1146
1147 void *loopback_selftest;
1148 /* We access loopback_selftest immediately before running XDP,
1149 * so we want them next to each other.
1150 */
1151 struct bpf_prog __rcu *xdp_prog;
1152
1153 struct rw_semaphore filter_sem;
1154 void *filter_state;
1155 #ifdef CONFIG_RFS_ACCEL
1156 struct mutex rps_mutex;
1157 unsigned long rps_slot_map;
1158 struct efx_async_filter_insertion rps_slot[EFX_RPS_MAX_IN_FLIGHT];
1159 spinlock_t rps_hash_lock;
1160 struct hlist_head *rps_hash_table;
1161 u32 rps_next_id;
1162 #endif
1163
1164 atomic_t active_queues;
1165 atomic_t rxq_flush_pending;
1166 atomic_t rxq_flush_outstanding;
1167 wait_queue_head_t flush_wq;
1168
1169 #ifdef CONFIG_SFC_SRIOV
1170 unsigned vf_count;
1171 unsigned vf_init_count;
1172 unsigned vi_scale;
1173 #endif
1174 spinlock_t vf_reps_lock;
1175 struct list_head vf_reps;
1176
1177 struct efx_ptp_data *ptp_data;
1178 bool ptp_warned;
1179
1180 char *vpd_sn;
1181 bool xdp_rxq_info_failed;
1182
1183 struct notifier_block netdev_notifier;
1184 struct notifier_block netevent_notifier;
1185 struct efx_tc_state *tc;
1186
1187 struct devlink *devlink;
1188 struct devlink_port *dl_port;
1189 unsigned int mem_bar;
1190 u32 reg_base;
1191 struct mutex reflash_mutex;
1192
1193 /* The following fields may be written more often */
1194
1195 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1196 spinlock_t biu_lock;
1197 int last_irq_cpu;
1198 spinlock_t stats_lock;
1199 atomic_t n_rx_noskb_drops;
1200 };
1201
1202 /**
1203 * struct efx_probe_data - State after hardware probe
1204 * @pci_dev: The PCI device
1205 * @efx: Efx NIC details
1206 */
1207 struct efx_probe_data {
1208 struct pci_dev *pci_dev;
1209 struct efx_nic efx;
1210 };
1211
efx_netdev_priv(struct net_device * dev)1212 static inline struct efx_nic *efx_netdev_priv(struct net_device *dev)
1213 {
1214 struct efx_probe_data **probe_ptr = netdev_priv(dev);
1215 struct efx_probe_data *probe_data = *probe_ptr;
1216
1217 return &probe_data->efx;
1218 }
1219
efx_dev_registered(struct efx_nic * efx)1220 static inline int efx_dev_registered(struct efx_nic *efx)
1221 {
1222 return efx->net_dev->reg_state == NETREG_REGISTERED;
1223 }
1224
efx_port_num(struct efx_nic * efx)1225 static inline unsigned int efx_port_num(struct efx_nic *efx)
1226 {
1227 return efx->port_num;
1228 }
1229
1230 struct efx_mtd_partition {
1231 struct list_head node;
1232 struct mtd_info mtd;
1233 const char *dev_type_name;
1234 const char *type_name;
1235 char name[IFNAMSIZ + 20];
1236 };
1237
1238 struct efx_udp_tunnel {
1239 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID 0xffff
1240 u16 type; /* TUNNEL_ENCAP_UDP_PORT_ENTRY_foo, see mcdi_pcol.h */
1241 __be16 port;
1242 };
1243
1244 /**
1245 * struct efx_nic_type - Efx device type definition
1246 * @mem_bar: Get the memory BAR
1247 * @mem_map_size: Get memory BAR mapped size
1248 * @probe: Probe the controller
1249 * @remove: Free resources allocated by probe()
1250 * @init: Initialise the controller
1251 * @dimension_resources: Dimension controller resources (buffer table,
1252 * and VIs once the available interrupt resources are clear)
1253 * @fini: Shut down the controller
1254 * @monitor: Periodic function for polling link state and hardware monitor
1255 * @map_reset_reason: Map ethtool reset reason to a reset method
1256 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1257 * @reset: Reset the controller hardware and possibly the PHY. This will
1258 * be called while the controller is uninitialised.
1259 * @probe_port: Probe the MAC and PHY
1260 * @remove_port: Free resources allocated by probe_port()
1261 * @handle_global_event: Handle a "global" event (may be %NULL)
1262 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1263 * @prepare_flr: Prepare for an FLR
1264 * @finish_flr: Clean up after an FLR
1265 * @describe_stats: Describe statistics for ethtool
1266 * @update_stats: Update statistics not provided by event handling.
1267 * Either argument may be %NULL.
1268 * @update_stats_atomic: Update statistics while in atomic context, if that
1269 * is more limiting than @update_stats. Otherwise, leave %NULL and
1270 * driver core will call @update_stats.
1271 * @start_stats: Start the regular fetching of statistics
1272 * @pull_stats: Pull stats from the NIC and wait until they arrive.
1273 * @stop_stats: Stop the regular fetching of statistics
1274 * @push_irq_moderation: Apply interrupt moderation value
1275 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1276 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1277 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1278 * to the hardware. Serialised by the mac_lock.
1279 * @check_mac_fault: Check MAC fault state. True if fault present.
1280 * @get_wol: Get WoL configuration from driver state
1281 * @set_wol: Push WoL configuration to the NIC
1282 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1283 * @get_fec_stats: Get standard FEC statistics.
1284 * @test_chip: Test registers. This is expected to reset the NIC.
1285 * @test_nvram: Test validity of NVRAM contents
1286 * @mcdi_request: Send an MCDI request with the given header and SDU.
1287 * The SDU length may be any value from 0 up to the protocol-
1288 * defined maximum, but its buffer will be padded to a multiple
1289 * of 4 bytes.
1290 * @mcdi_poll_response: Test whether an MCDI response is available.
1291 * @mcdi_read_response: Read the MCDI response PDU. The offset will
1292 * be a multiple of 4. The length may not be, but the buffer
1293 * will be padded so it is safe to round up.
1294 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
1295 * return an appropriate error code for aborting any current
1296 * request; otherwise return 0.
1297 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1298 * be separately enabled after this.
1299 * @irq_test_generate: Generate a test IRQ
1300 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1301 * queue must be separately disabled before this.
1302 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1303 * a pointer to the &struct efx_msi_context for the channel.
1304 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1305 * is a pointer to the &struct efx_nic.
1306 * @tx_probe: Allocate resources for TX queue (and select TXQ type)
1307 * @tx_init: Initialise TX queue on the NIC
1308 * @tx_remove: Free resources for TX queue
1309 * @tx_write: Write TX descriptors and doorbell
1310 * @tx_enqueue: Add an SKB to TX queue
1311 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1312 * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC
1313 * @rx_push_rss_context_config: Write RSS hash key and indirection table for
1314 * user RSS context to the NIC
1315 * @rx_pull_rss_context_config: Read RSS hash key and indirection table for user
1316 * RSS context back from the NIC
1317 * @rx_probe: Allocate resources for RX queue
1318 * @rx_init: Initialise RX queue on the NIC
1319 * @rx_remove: Free resources for RX queue
1320 * @rx_write: Write RX descriptors and doorbell
1321 * @rx_defer_refill: Generate a refill reminder event
1322 * @rx_packet: Receive the queued RX buffer on a channel
1323 * @rx_buf_hash_valid: Determine whether the RX prefix contains a valid hash
1324 * @ev_probe: Allocate resources for event queue
1325 * @ev_init: Initialise event queue on the NIC
1326 * @ev_fini: Deinitialise event queue on the NIC
1327 * @ev_remove: Free resources for event queue
1328 * @ev_process: Process events for a queue, up to the given NAPI quota
1329 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1330 * @ev_test_generate: Generate a test event
1331 * @filter_table_probe: Probe filter capabilities and set up filter software state
1332 * @filter_table_restore: Restore filters removed from hardware
1333 * @filter_table_remove: Remove filters from hardware and tear down software state
1334 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1335 * @filter_insert: add or replace a filter
1336 * @filter_remove_safe: remove a filter by ID, carefully
1337 * @filter_get_safe: retrieve a filter by ID, carefully
1338 * @filter_clear_rx: Remove all RX filters whose priority is less than or
1339 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1340 * @filter_count_rx_used: Get the number of filters in use at a given priority
1341 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1342 * @filter_get_rx_ids: Get list of RX filters at a given priority
1343 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1344 * This must check whether the specified table entry is used by RFS
1345 * and that rps_may_expire_flow() returns true for it.
1346 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1347 * using efx_mtd_add()
1348 * @mtd_rename: Set an MTD partition name using the net device name
1349 * @mtd_read: Read from an MTD partition
1350 * @mtd_erase: Erase part of an MTD partition
1351 * @mtd_write: Write to an MTD partition
1352 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1353 * also notifies the driver that a writer has finished using this
1354 * partition.
1355 * @ptp_write_host_time: Send host time to MC as part of sync protocol
1356 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1357 * timestamping, possibly only temporarily for the purposes of a reset.
1358 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1359 * and tx_type will already have been validated but this operation
1360 * must validate and update rx_filter.
1361 * @get_phys_port_id: Get the underlying physical port id.
1362 * @set_mac_address: Set the MAC address of the device
1363 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1364 * If %NULL, then device does not support any TSO version.
1365 * @udp_tnl_push_ports: Push the list of UDP tunnel ports to the NIC if required.
1366 * @udp_tnl_has_port: Check if a port has been added as UDP tunnel
1367 * @print_additional_fwver: Dump NIC-specific additional FW version info
1368 * @sensor_event: Handle a sensor event from MCDI
1369 * @rx_recycle_ring_size: Size of the RX recycle ring
1370 * @revision: Hardware architecture revision
1371 * @txd_ptr_tbl_base: TX descriptor ring base address
1372 * @rxd_ptr_tbl_base: RX descriptor ring base address
1373 * @buf_tbl_base: Buffer table base address
1374 * @evq_ptr_tbl_base: Event queue pointer table base address
1375 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1376 * @max_dma_mask: Maximum possible DMA mask
1377 * @rx_prefix_size: Size of RX prefix before packet data
1378 * @rx_hash_offset: Offset of RX flow hash within prefix
1379 * @rx_ts_offset: Offset of timestamp within prefix
1380 * @rx_buffer_padding: Size of padding at end of RX packet
1381 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1382 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1383 * @option_descriptors: NIC supports TX option descriptors
1384 * @flash_auto_partition: firmware flash uses AUTO partition, driver does
1385 * not need to perform image parsing
1386 * @min_interrupt_mode: Lowest capability interrupt mode supported
1387 * from &enum efx_int_mode.
1388 * @timer_period_max: Maximum period of interrupt timer (in ticks)
1389 * @offload_features: net_device feature flags for protocol offload
1390 * features implemented in hardware
1391 * @mcdi_max_ver: Maximum MCDI version supported
1392 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1393 */
1394 struct efx_nic_type {
1395 bool is_vf;
1396 unsigned int (*mem_bar)(struct efx_nic *efx);
1397 unsigned int (*mem_map_size)(struct efx_nic *efx);
1398 int (*probe)(struct efx_nic *efx);
1399 void (*remove)(struct efx_nic *efx);
1400 int (*init)(struct efx_nic *efx);
1401 int (*dimension_resources)(struct efx_nic *efx);
1402 void (*fini)(struct efx_nic *efx);
1403 void (*monitor)(struct efx_nic *efx);
1404 enum reset_type (*map_reset_reason)(enum reset_type reason);
1405 int (*map_reset_flags)(u32 *flags);
1406 int (*reset)(struct efx_nic *efx, enum reset_type method);
1407 int (*probe_port)(struct efx_nic *efx);
1408 void (*remove_port)(struct efx_nic *efx);
1409 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1410 int (*fini_dmaq)(struct efx_nic *efx);
1411 void (*prepare_flr)(struct efx_nic *efx);
1412 void (*finish_flr)(struct efx_nic *efx);
1413 size_t (*describe_stats)(struct efx_nic *efx, u8 **names);
1414 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1415 struct rtnl_link_stats64 *core_stats);
1416 size_t (*update_stats_atomic)(struct efx_nic *efx, u64 *full_stats,
1417 struct rtnl_link_stats64 *core_stats);
1418 void (*start_stats)(struct efx_nic *efx);
1419 void (*pull_stats)(struct efx_nic *efx);
1420 void (*stop_stats)(struct efx_nic *efx);
1421 void (*push_irq_moderation)(struct efx_channel *channel);
1422 int (*reconfigure_port)(struct efx_nic *efx);
1423 void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1424 int (*reconfigure_mac)(struct efx_nic *efx, bool mtu_only);
1425 bool (*check_mac_fault)(struct efx_nic *efx);
1426 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1427 int (*set_wol)(struct efx_nic *efx, u32 type);
1428 void (*resume_wol)(struct efx_nic *efx);
1429 void (*get_fec_stats)(struct efx_nic *efx,
1430 struct ethtool_fec_stats *fec_stats);
1431 unsigned int (*check_caps)(const struct efx_nic *efx,
1432 u8 flag,
1433 u32 offset);
1434 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1435 int (*test_nvram)(struct efx_nic *efx);
1436 void (*mcdi_request)(struct efx_nic *efx,
1437 const efx_dword_t *hdr, size_t hdr_len,
1438 const efx_dword_t *sdu, size_t sdu_len);
1439 bool (*mcdi_poll_response)(struct efx_nic *efx);
1440 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1441 size_t pdu_offset, size_t pdu_len);
1442 int (*mcdi_poll_reboot)(struct efx_nic *efx);
1443 void (*mcdi_reboot_detected)(struct efx_nic *efx);
1444 void (*irq_enable_master)(struct efx_nic *efx);
1445 int (*irq_test_generate)(struct efx_nic *efx);
1446 void (*irq_disable_non_ev)(struct efx_nic *efx);
1447 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1448 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1449 int (*tx_probe)(struct efx_tx_queue *tx_queue);
1450 void (*tx_init)(struct efx_tx_queue *tx_queue);
1451 void (*tx_remove)(struct efx_tx_queue *tx_queue);
1452 void (*tx_write)(struct efx_tx_queue *tx_queue);
1453 netdev_tx_t (*tx_enqueue)(struct efx_tx_queue *tx_queue, struct sk_buff *skb);
1454 unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue,
1455 dma_addr_t dma_addr, unsigned int len);
1456 int (*rx_push_rss_config)(struct efx_nic *efx, bool user,
1457 const u32 *rx_indir_table, const u8 *key);
1458 int (*rx_pull_rss_config)(struct efx_nic *efx);
1459 int (*rx_push_rss_context_config)(struct efx_nic *efx,
1460 struct efx_rss_context_priv *ctx,
1461 const u32 *rx_indir_table,
1462 const u8 *key, bool delete);
1463 int (*rx_pull_rss_context_config)(struct efx_nic *efx,
1464 struct efx_rss_context *ctx);
1465 void (*rx_restore_rss_contexts)(struct efx_nic *efx);
1466 int (*rx_probe)(struct efx_rx_queue *rx_queue);
1467 void (*rx_init)(struct efx_rx_queue *rx_queue);
1468 void (*rx_remove)(struct efx_rx_queue *rx_queue);
1469 void (*rx_write)(struct efx_rx_queue *rx_queue);
1470 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1471 void (*rx_packet)(struct efx_channel *channel);
1472 bool (*rx_buf_hash_valid)(const u8 *prefix);
1473 int (*ev_probe)(struct efx_channel *channel);
1474 int (*ev_init)(struct efx_channel *channel);
1475 void (*ev_fini)(struct efx_channel *channel);
1476 void (*ev_remove)(struct efx_channel *channel);
1477 int (*ev_process)(struct efx_channel *channel, int quota);
1478 void (*ev_read_ack)(struct efx_channel *channel);
1479 void (*ev_test_generate)(struct efx_channel *channel);
1480 int (*filter_table_probe)(struct efx_nic *efx);
1481 void (*filter_table_restore)(struct efx_nic *efx);
1482 void (*filter_table_remove)(struct efx_nic *efx);
1483 void (*filter_update_rx_scatter)(struct efx_nic *efx);
1484 s32 (*filter_insert)(struct efx_nic *efx,
1485 struct efx_filter_spec *spec, bool replace);
1486 int (*filter_remove_safe)(struct efx_nic *efx,
1487 enum efx_filter_priority priority,
1488 u32 filter_id);
1489 int (*filter_get_safe)(struct efx_nic *efx,
1490 enum efx_filter_priority priority,
1491 u32 filter_id, struct efx_filter_spec *);
1492 int (*filter_clear_rx)(struct efx_nic *efx,
1493 enum efx_filter_priority priority);
1494 u32 (*filter_count_rx_used)(struct efx_nic *efx,
1495 enum efx_filter_priority priority);
1496 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1497 s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1498 enum efx_filter_priority priority,
1499 u32 *buf, u32 size);
1500 #ifdef CONFIG_RFS_ACCEL
1501 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1502 unsigned int index);
1503 #endif
1504 #ifdef CONFIG_SFC_MTD
1505 int (*mtd_probe)(struct efx_nic *efx);
1506 void (*mtd_rename)(struct efx_mtd_partition *part);
1507 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1508 size_t *retlen, u8 *buffer);
1509 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1510 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1511 size_t *retlen, const u8 *buffer);
1512 int (*mtd_sync)(struct mtd_info *mtd);
1513 #endif
1514 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1515 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1516 int (*ptp_set_ts_config)(struct efx_nic *efx,
1517 struct kernel_hwtstamp_config *init);
1518 int (*sriov_configure)(struct efx_nic *efx, int num_vfs);
1519 int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1520 int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1521 int (*get_phys_port_id)(struct efx_nic *efx,
1522 struct netdev_phys_item_id *ppid);
1523 int (*sriov_init)(struct efx_nic *efx);
1524 void (*sriov_fini)(struct efx_nic *efx);
1525 bool (*sriov_wanted)(struct efx_nic *efx);
1526 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, const u8 *mac);
1527 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1528 u8 qos);
1529 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1530 bool spoofchk);
1531 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1532 struct ifla_vf_info *ivi);
1533 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i,
1534 int link_state);
1535 int (*vswitching_probe)(struct efx_nic *efx);
1536 int (*vswitching_restore)(struct efx_nic *efx);
1537 void (*vswitching_remove)(struct efx_nic *efx);
1538 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr);
1539 int (*set_mac_address)(struct efx_nic *efx);
1540 u32 (*tso_versions)(struct efx_nic *efx);
1541 int (*udp_tnl_push_ports)(struct efx_nic *efx);
1542 bool (*udp_tnl_has_port)(struct efx_nic *efx, __be16 port);
1543 size_t (*print_additional_fwver)(struct efx_nic *efx, char *buf,
1544 size_t len);
1545 void (*sensor_event)(struct efx_nic *efx, efx_qword_t *ev);
1546 unsigned int (*rx_recycle_ring_size)(const struct efx_nic *efx);
1547
1548 int revision;
1549 unsigned int txd_ptr_tbl_base;
1550 unsigned int rxd_ptr_tbl_base;
1551 unsigned int buf_tbl_base;
1552 unsigned int evq_ptr_tbl_base;
1553 unsigned int evq_rptr_tbl_base;
1554 u64 max_dma_mask;
1555 unsigned int rx_prefix_size;
1556 unsigned int rx_hash_offset;
1557 unsigned int rx_ts_offset;
1558 unsigned int rx_buffer_padding;
1559 bool can_rx_scatter;
1560 bool always_rx_scatter;
1561 bool option_descriptors;
1562 bool flash_auto_partition;
1563 unsigned int min_interrupt_mode;
1564 unsigned int timer_period_max;
1565 netdev_features_t offload_features;
1566 int mcdi_max_ver;
1567 unsigned int max_rx_ip_filters;
1568 u32 hwtstamp_filters;
1569 unsigned int rx_hash_key_size;
1570 };
1571
1572 /**************************************************************************
1573 *
1574 * Prototypes and inline functions
1575 *
1576 *************************************************************************/
1577
1578 static inline struct efx_channel *
efx_get_channel(struct efx_nic * efx,unsigned index)1579 efx_get_channel(struct efx_nic *efx, unsigned index)
1580 {
1581 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1582 return efx->channel[index];
1583 }
1584
1585 /* Iterate over all used channels */
1586 #define efx_for_each_channel(_channel, _efx) \
1587 for (_channel = (_efx)->channel[0]; \
1588 _channel; \
1589 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1590 (_efx)->channel[_channel->channel + 1] : NULL)
1591
1592 /* Iterate over all used channels in reverse */
1593 #define efx_for_each_channel_rev(_channel, _efx) \
1594 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1595 _channel; \
1596 _channel = _channel->channel ? \
1597 (_efx)->channel[_channel->channel - 1] : NULL)
1598
1599 static inline struct efx_channel *
efx_get_tx_channel(struct efx_nic * efx,unsigned int index)1600 efx_get_tx_channel(struct efx_nic *efx, unsigned int index)
1601 {
1602 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);
1603 return efx->channel[efx->tx_channel_offset + index];
1604 }
1605
1606 static inline struct efx_channel *
efx_get_xdp_channel(struct efx_nic * efx,unsigned int index)1607 efx_get_xdp_channel(struct efx_nic *efx, unsigned int index)
1608 {
1609 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);
1610 return efx->channel[efx->xdp_channel_offset + index];
1611 }
1612
efx_channel_is_xdp_tx(struct efx_channel * channel)1613 static inline bool efx_channel_is_xdp_tx(struct efx_channel *channel)
1614 {
1615 return channel->channel - channel->efx->xdp_channel_offset <
1616 channel->efx->n_xdp_channels;
1617 }
1618
efx_channel_has_tx_queues(struct efx_channel * channel)1619 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1620 {
1621 return channel && channel->channel >= channel->efx->tx_channel_offset;
1622 }
1623
efx_channel_num_tx_queues(struct efx_channel * channel)1624 static inline unsigned int efx_channel_num_tx_queues(struct efx_channel *channel)
1625 {
1626 if (efx_channel_is_xdp_tx(channel))
1627 return channel->efx->xdp_tx_per_channel;
1628 return channel->efx->tx_queues_per_channel;
1629 }
1630
1631 static inline struct efx_tx_queue *
efx_channel_get_tx_queue(struct efx_channel * channel,unsigned int type)1632 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned int type)
1633 {
1634 EFX_WARN_ON_ONCE_PARANOID(type >= EFX_TXQ_TYPES);
1635 return channel->tx_queue_by_type[type];
1636 }
1637
1638 static inline struct efx_tx_queue *
efx_get_tx_queue(struct efx_nic * efx,unsigned int index,unsigned int type)1639 efx_get_tx_queue(struct efx_nic *efx, unsigned int index, unsigned int type)
1640 {
1641 struct efx_channel *channel = efx_get_tx_channel(efx, index);
1642
1643 return efx_channel_get_tx_queue(channel, type);
1644 }
1645
1646 /* Iterate over all TX queues belonging to a channel */
1647 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1648 if (!efx_channel_has_tx_queues(_channel)) \
1649 ; \
1650 else \
1651 for (_tx_queue = (_channel)->tx_queue; \
1652 _tx_queue < (_channel)->tx_queue + \
1653 efx_channel_num_tx_queues(_channel); \
1654 _tx_queue++)
1655
efx_channel_has_rx_queue(struct efx_channel * channel)1656 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1657 {
1658 return channel->rx_queue.core_index >= 0;
1659 }
1660
1661 static inline struct efx_rx_queue *
efx_channel_get_rx_queue(struct efx_channel * channel)1662 efx_channel_get_rx_queue(struct efx_channel *channel)
1663 {
1664 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel));
1665 return &channel->rx_queue;
1666 }
1667
1668 /* Iterate over all RX queues belonging to a channel */
1669 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1670 if (!efx_channel_has_rx_queue(_channel)) \
1671 ; \
1672 else \
1673 for (_rx_queue = &(_channel)->rx_queue; \
1674 _rx_queue; \
1675 _rx_queue = NULL)
1676
1677 static inline struct efx_channel *
efx_rx_queue_channel(struct efx_rx_queue * rx_queue)1678 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1679 {
1680 return container_of(rx_queue, struct efx_channel, rx_queue);
1681 }
1682
efx_rx_queue_index(struct efx_rx_queue * rx_queue)1683 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1684 {
1685 return efx_rx_queue_channel(rx_queue)->channel;
1686 }
1687
1688 /* Returns a pointer to the specified receive buffer in the RX
1689 * descriptor queue.
1690 */
efx_rx_buffer(struct efx_rx_queue * rx_queue,unsigned int index)1691 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1692 unsigned int index)
1693 {
1694 return &rx_queue->buffer[index];
1695 }
1696
1697 static inline struct efx_rx_buffer *
efx_rx_buf_next(struct efx_rx_queue * rx_queue,struct efx_rx_buffer * rx_buf)1698 efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
1699 {
1700 if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
1701 return efx_rx_buffer(rx_queue, 0);
1702 else
1703 return rx_buf + 1;
1704 }
1705
1706 /**
1707 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1708 *
1709 * This calculates the maximum frame length that will be used for a
1710 * given MTU. The frame length will be equal to the MTU plus a
1711 * constant amount of header space and padding. This is the quantity
1712 * that the net driver will program into the MAC as the maximum frame
1713 * length.
1714 *
1715 * The 10G MAC requires 8-byte alignment on the frame
1716 * length, so we round up to the nearest 8.
1717 *
1718 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1719 * XGMII cycle). If the frame length reaches the maximum value in the
1720 * same cycle, the XMAC can miss the IPG altogether. We work around
1721 * this by adding a further 16 bytes.
1722 */
1723 #define EFX_FRAME_PAD 16
1724 #define EFX_MAX_FRAME_LEN(mtu) \
1725 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1726
efx_xmit_with_hwtstamp(struct sk_buff * skb)1727 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1728 {
1729 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1730 }
efx_xmit_hwtstamp_pending(struct sk_buff * skb)1731 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1732 {
1733 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1734 }
1735
1736 /* Get the max fill level of the TX queues on this channel */
1737 static inline unsigned int
efx_channel_tx_fill_level(struct efx_channel * channel)1738 efx_channel_tx_fill_level(struct efx_channel *channel)
1739 {
1740 struct efx_tx_queue *tx_queue;
1741 unsigned int fill_level = 0;
1742
1743 efx_for_each_channel_tx_queue(tx_queue, channel)
1744 fill_level = max(fill_level,
1745 tx_queue->insert_count - tx_queue->read_count);
1746
1747 return fill_level;
1748 }
1749
1750 /* Conservative approximation of efx_channel_tx_fill_level using cached value */
1751 static inline unsigned int
efx_channel_tx_old_fill_level(struct efx_channel * channel)1752 efx_channel_tx_old_fill_level(struct efx_channel *channel)
1753 {
1754 struct efx_tx_queue *tx_queue;
1755 unsigned int fill_level = 0;
1756
1757 efx_for_each_channel_tx_queue(tx_queue, channel)
1758 fill_level = max(fill_level,
1759 tx_queue->insert_count - tx_queue->old_read_count);
1760
1761 return fill_level;
1762 }
1763
1764 /* Get all supported features.
1765 * If a feature is not fixed, it is present in hw_features.
1766 * If a feature is fixed, it does not present in hw_features, but
1767 * always in features.
1768 */
efx_supported_features(const struct efx_nic * efx)1769 static inline netdev_features_t efx_supported_features(const struct efx_nic *efx)
1770 {
1771 const struct net_device *net_dev = efx->net_dev;
1772
1773 return net_dev->features | net_dev->hw_features;
1774 }
1775
1776 /* Get the current TX queue insert index. */
1777 static inline unsigned int
efx_tx_queue_get_insert_index(const struct efx_tx_queue * tx_queue)1778 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
1779 {
1780 return tx_queue->insert_count & tx_queue->ptr_mask;
1781 }
1782
1783 /* Get a TX buffer. */
1784 static inline struct efx_tx_buffer *
__efx_tx_queue_get_insert_buffer(const struct efx_tx_queue * tx_queue)1785 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1786 {
1787 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1788 }
1789
1790 /* Get a TX buffer, checking it's not currently in use. */
1791 static inline struct efx_tx_buffer *
efx_tx_queue_get_insert_buffer(const struct efx_tx_queue * tx_queue)1792 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1793 {
1794 struct efx_tx_buffer *buffer =
1795 __efx_tx_queue_get_insert_buffer(tx_queue);
1796
1797 EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1798 EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1799 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);
1800
1801 return buffer;
1802 }
1803
1804 #endif /* EFX_NET_DRIVER_H */
1805