1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
3 #include "main.h"
4
5 static struct irdma_rsrc_limits rsrc_limits_table[] = {
6 [0] = {
7 .qplimit = SZ_128,
8 },
9 [1] = {
10 .qplimit = SZ_1K,
11 },
12 [2] = {
13 .qplimit = SZ_2K,
14 },
15 [3] = {
16 .qplimit = SZ_4K,
17 },
18 [4] = {
19 .qplimit = SZ_16K,
20 },
21 [5] = {
22 .qplimit = SZ_64K,
23 },
24 [6] = {
25 .qplimit = SZ_128K,
26 },
27 [7] = {
28 .qplimit = SZ_256K,
29 },
30 };
31
32 /* types of hmc objects */
33 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = {
34 IRDMA_HMC_IW_QP,
35 IRDMA_HMC_IW_CQ,
36 IRDMA_HMC_IW_SRQ,
37 IRDMA_HMC_IW_HTE,
38 IRDMA_HMC_IW_ARP,
39 IRDMA_HMC_IW_APBVT_ENTRY,
40 IRDMA_HMC_IW_MR,
41 IRDMA_HMC_IW_XF,
42 IRDMA_HMC_IW_XFFL,
43 IRDMA_HMC_IW_Q1,
44 IRDMA_HMC_IW_Q1FL,
45 IRDMA_HMC_IW_PBLE,
46 IRDMA_HMC_IW_TIMER,
47 IRDMA_HMC_IW_FSIMC,
48 IRDMA_HMC_IW_FSIAV,
49 IRDMA_HMC_IW_RRF,
50 IRDMA_HMC_IW_RRFFL,
51 IRDMA_HMC_IW_HDR,
52 IRDMA_HMC_IW_MD,
53 IRDMA_HMC_IW_OOISC,
54 IRDMA_HMC_IW_OOISCFFL,
55 };
56
57 /**
58 * irdma_iwarp_ce_handler - handle iwarp completions
59 * @iwcq: iwarp cq receiving event
60 */
irdma_iwarp_ce_handler(struct irdma_sc_cq * iwcq)61 static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq)
62 {
63 struct irdma_cq *cq = iwcq->back_cq;
64
65 if (!cq->user_mode)
66 atomic_set(&cq->armed, 0);
67 if (cq->ibcq.comp_handler)
68 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
69 }
70
71 /**
72 * irdma_puda_ce_handler - handle puda completion events
73 * @rf: RDMA PCI function
74 * @cq: puda completion q for event
75 */
irdma_puda_ce_handler(struct irdma_pci_f * rf,struct irdma_sc_cq * cq)76 static void irdma_puda_ce_handler(struct irdma_pci_f *rf,
77 struct irdma_sc_cq *cq)
78 {
79 struct irdma_sc_dev *dev = &rf->sc_dev;
80 u32 compl_error;
81 int status;
82
83 do {
84 status = irdma_puda_poll_cmpl(dev, cq, &compl_error);
85 if (status == -ENOENT)
86 break;
87 if (status) {
88 ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status);
89 break;
90 }
91 if (compl_error) {
92 ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err =0x%x\n",
93 compl_error);
94 break;
95 }
96 } while (1);
97
98 irdma_sc_ccq_arm(cq);
99 }
100
101 /**
102 * irdma_process_normal_ceqe - Handle a CEQE for a normal CQ.
103 * @rf: RDMA PCI function.
104 * @dev: iWARP device.
105 * @cq_idx: CQ ID. Must be in table bounds.
106 *
107 * Context: Atomic (CEQ lock must be held)
108 */
irdma_process_normal_ceqe(struct irdma_pci_f * rf,struct irdma_sc_dev * dev,u32 cq_idx)109 static void irdma_process_normal_ceqe(struct irdma_pci_f *rf,
110 struct irdma_sc_dev *dev, u32 cq_idx)
111 {
112 /* cq_idx bounds validated in irdma_sc_process_ceq. */
113 struct irdma_cq *icq = READ_ONCE(rf->cq_table[cq_idx]);
114 struct irdma_sc_cq *cq;
115
116 if (unlikely(!icq)) {
117 /* Should not happen since CEQ is scrubbed upon CQ delete. */
118 ibdev_warn_ratelimited(to_ibdev(dev), "Stale CEQE for CQ %u",
119 cq_idx);
120 return;
121 }
122
123 cq = &icq->sc_cq;
124
125 if (unlikely(cq->cq_type != IRDMA_CQ_TYPE_IWARP)) {
126 ibdev_warn_ratelimited(to_ibdev(dev), "Unexpected CQ type %u",
127 cq->cq_type);
128 return;
129 }
130
131 writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);
132 irdma_iwarp_ce_handler(cq);
133 }
134
135 /**
136 * irdma_process_reserved_ceqe - Handle a CEQE for a reserved CQ.
137 * @rf: RDMA PCI function.
138 * @dev: iWARP device.
139 * @cq_idx: CQ ID.
140 *
141 * Context: Atomic
142 */
irdma_process_reserved_ceqe(struct irdma_pci_f * rf,struct irdma_sc_dev * dev,u32 cq_idx)143 static void irdma_process_reserved_ceqe(struct irdma_pci_f *rf,
144 struct irdma_sc_dev *dev, u32 cq_idx)
145 {
146 struct irdma_sc_cq *cq;
147
148 if (cq_idx == IRDMA_RSVD_CQ_ID_CQP) {
149 cq = &rf->ccq.sc_cq;
150 /* CQP CQ lifetime > CEQ. */
151 writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);
152 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work);
153 } else if (cq_idx == IRDMA_RSVD_CQ_ID_ILQ ||
154 cq_idx == IRDMA_RSVD_CQ_ID_IEQ) {
155 scoped_guard(spinlock_irqsave, &dev->puda_cq_lock) {
156 cq = (cq_idx == IRDMA_RSVD_CQ_ID_ILQ) ?
157 dev->ilq_cq : dev->ieq_cq;
158 if (!cq) {
159 ibdev_warn_ratelimited(to_ibdev(dev),
160 "Stale ILQ/IEQ CEQE");
161 return;
162 }
163 writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);
164 irdma_puda_ce_handler(rf, cq);
165 }
166 }
167 }
168
169 /**
170 * irdma_process_ceq - handle ceq for completions
171 * @rf: RDMA PCI function
172 * @ceq: ceq having cq for completion
173 */
irdma_process_ceq(struct irdma_pci_f * rf,struct irdma_ceq * ceq)174 static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq)
175 {
176 struct irdma_sc_dev *dev = &rf->sc_dev;
177 struct irdma_sc_ceq *sc_ceq;
178 unsigned long flags;
179 u32 cq_idx;
180
181 sc_ceq = &ceq->sc_ceq;
182 do {
183 spin_lock_irqsave(&ceq->ce_lock, flags);
184
185 if (!irdma_sc_process_ceq(dev, sc_ceq, &cq_idx)) {
186 spin_unlock_irqrestore(&ceq->ce_lock, flags);
187 break;
188 }
189
190 /* Normal CQs must be handled while holding CEQ lock. */
191 if (likely(cq_idx > IRDMA_RSVD_CQ_ID_IEQ)) {
192 irdma_process_normal_ceqe(rf, dev, cq_idx);
193 spin_unlock_irqrestore(&ceq->ce_lock, flags);
194 continue;
195 }
196
197 spin_unlock_irqrestore(&ceq->ce_lock, flags);
198
199 irdma_process_reserved_ceqe(rf, dev, cq_idx);
200 } while (1);
201 }
202
irdma_set_flush_fields(struct irdma_sc_qp * qp,struct irdma_aeqe_info * info)203 static void irdma_set_flush_fields(struct irdma_sc_qp *qp,
204 struct irdma_aeqe_info *info)
205 {
206 struct qp_err_code qp_err;
207
208 qp->sq_flush_code = info->sq;
209 qp->rq_flush_code = info->rq;
210 if (qp->qp_uk.uk_attrs->hw_rev >= IRDMA_GEN_3) {
211 if (info->sq) {
212 qp->err_sq_idx_valid = true;
213 qp->err_sq_idx = info->wqe_idx;
214 }
215 if (info->rq) {
216 qp->err_rq_idx_valid = true;
217 qp->err_rq_idx = info->wqe_idx;
218 }
219 }
220
221 qp_err = irdma_ae_to_qp_err_code(info->ae_id);
222 qp->flush_code = qp_err.flush_code;
223 qp->event_type = qp_err.event_type;
224 }
225
226 /**
227 * irdma_complete_cqp_request - perform post-completion cleanup
228 * @cqp: device CQP
229 * @cqp_request: CQP request
230 *
231 * Mark CQP request as done, wake up waiting thread or invoke
232 * callback function and release/free CQP request.
233 */
irdma_complete_cqp_request(struct irdma_cqp * cqp,struct irdma_cqp_request * cqp_request)234 static void irdma_complete_cqp_request(struct irdma_cqp *cqp,
235 struct irdma_cqp_request *cqp_request)
236 {
237 if (cqp_request->waiting) {
238 WRITE_ONCE(cqp_request->request_done, true);
239 wake_up(&cqp_request->waitq);
240 } else if (cqp_request->callback_fcn) {
241 cqp_request->callback_fcn(cqp_request);
242 }
243 irdma_put_cqp_request(cqp, cqp_request);
244 }
245
246 /**
247 * irdma_process_ae_def_cmpl - handle IRDMA_AE_CQP_DEFERRED_COMPLETE event
248 * @rf: RDMA PCI function
249 * @info: AEQ entry info
250 */
irdma_process_ae_def_cmpl(struct irdma_pci_f * rf,struct irdma_aeqe_info * info)251 static void irdma_process_ae_def_cmpl(struct irdma_pci_f *rf,
252 struct irdma_aeqe_info *info)
253 {
254 u32 sw_def_info;
255 u64 scratch;
256
257 irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq);
258
259 irdma_sc_cqp_def_cmpl_ae_handler(&rf->sc_dev, info, true,
260 &scratch, &sw_def_info);
261 while (scratch) {
262 struct irdma_cqp_request *cqp_request =
263 (struct irdma_cqp_request *)(uintptr_t)scratch;
264
265 irdma_complete_cqp_request(&rf->cqp, cqp_request);
266 irdma_sc_cqp_def_cmpl_ae_handler(&rf->sc_dev, info, false,
267 &scratch, &sw_def_info);
268 }
269 }
270
271 /**
272 * irdma_process_aeq - handle aeq events
273 * @rf: RDMA PCI function
274 */
irdma_process_aeq(struct irdma_pci_f * rf)275 static void irdma_process_aeq(struct irdma_pci_f *rf)
276 {
277 struct irdma_sc_dev *dev = &rf->sc_dev;
278 struct irdma_aeq *aeq = &rf->aeq;
279 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq;
280 struct irdma_aeqe_info aeinfo;
281 struct irdma_aeqe_info *info = &aeinfo;
282 int ret;
283 struct irdma_qp *iwqp = NULL;
284 struct irdma_cq *iwcq = NULL;
285 struct irdma_sc_qp *qp = NULL;
286 struct irdma_qp_host_ctx_info *ctx_info = NULL;
287 struct irdma_device *iwdev = rf->iwdev;
288 struct irdma_sc_srq *srq;
289 unsigned long flags;
290
291 u32 aeqcnt = 0;
292
293 if (!sc_aeq->size)
294 return;
295
296 do {
297 memset(info, 0, sizeof(*info));
298 ret = irdma_sc_get_next_aeqe(sc_aeq, info);
299 if (ret)
300 break;
301
302 if (info->aeqe_overflow) {
303 ibdev_err(&iwdev->ibdev, "AEQ has overflowed\n");
304 rf->reset = true;
305 rf->gen_ops.request_reset(rf);
306 return;
307 }
308
309 aeqcnt++;
310 ibdev_dbg(&iwdev->ibdev,
311 "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n",
312 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state,
313 info->iwarp_state, info->ae_src);
314
315 if (info->qp) {
316 spin_lock_irqsave(&rf->qptable_lock, flags);
317 iwqp = rf->qp_table[info->qp_cq_id];
318 if (!iwqp) {
319 spin_unlock_irqrestore(&rf->qptable_lock,
320 flags);
321 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) {
322 atomic_dec(&iwdev->vsi.qp_suspend_reqs);
323 wake_up(&iwdev->suspend_wq);
324 continue;
325 }
326 ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n",
327 info->qp_cq_id);
328 continue;
329 }
330 irdma_qp_add_ref(&iwqp->ibqp);
331 spin_unlock_irqrestore(&rf->qptable_lock, flags);
332 qp = &iwqp->sc_qp;
333 spin_lock_irqsave(&iwqp->lock, flags);
334 iwqp->hw_tcp_state = info->tcp_state;
335 iwqp->hw_iwarp_state = info->iwarp_state;
336 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE)
337 iwqp->last_aeq = info->ae_id;
338 spin_unlock_irqrestore(&iwqp->lock, flags);
339 } else if (info->srq) {
340 if (info->ae_id != IRDMA_AE_SRQ_LIMIT)
341 continue;
342 } else {
343 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR &&
344 info->ae_id != IRDMA_AE_CQP_DEFERRED_COMPLETE)
345 continue;
346 }
347
348 switch (info->ae_id) {
349 struct irdma_cm_node *cm_node;
350 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED:
351 cm_node = iwqp->cm_node;
352 if (cm_node->accept_pend) {
353 atomic_dec(&cm_node->listener->pend_accepts_cnt);
354 cm_node->accept_pend = 0;
355 }
356 iwqp->rts_ae_rcvd = 1;
357 wake_up_interruptible(&iwqp->waitq);
358 break;
359 case IRDMA_AE_LLP_FIN_RECEIVED:
360 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE:
361 if (qp->term_flags)
362 break;
363 if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
364 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT;
365 if (iwqp->hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT &&
366 iwqp->ibqp_state == IB_QPS_RTS) {
367 irdma_next_iw_state(iwqp,
368 IRDMA_QP_STATE_CLOSING,
369 0, 0, 0);
370 irdma_cm_disconn(iwqp);
371 }
372 irdma_schedule_cm_timer(iwqp->cm_node,
373 (struct irdma_puda_buf *)iwqp,
374 IRDMA_TIMER_TYPE_CLOSE,
375 1, 0);
376 }
377 break;
378 case IRDMA_AE_LLP_CLOSE_COMPLETE:
379 if (qp->term_flags)
380 irdma_terminate_done(qp, 0);
381 else
382 irdma_cm_disconn(iwqp);
383 break;
384 case IRDMA_AE_BAD_CLOSE:
385 case IRDMA_AE_RESET_SENT:
386 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0,
387 0);
388 irdma_cm_disconn(iwqp);
389 break;
390 case IRDMA_AE_LLP_CONNECTION_RESET:
391 if (atomic_read(&iwqp->close_timer_started))
392 break;
393 irdma_cm_disconn(iwqp);
394 break;
395 case IRDMA_AE_QP_SUSPEND_COMPLETE:
396 if (iwqp->iwdev->vsi.tc_change_pending) {
397 if (!atomic_dec_return(&qp->vsi->qp_suspend_reqs))
398 wake_up(&iwqp->iwdev->suspend_wq);
399 }
400 if (iwqp->suspend_pending) {
401 iwqp->suspend_pending = false;
402 wake_up(&iwqp->iwdev->suspend_wq);
403 }
404 break;
405 case IRDMA_AE_TERMINATE_SENT:
406 irdma_terminate_send_fin(qp);
407 break;
408 case IRDMA_AE_LLP_TERMINATE_RECEIVED:
409 irdma_terminate_received(qp, info);
410 break;
411 case IRDMA_AE_CQ_OPERATION_ERROR:
412 ibdev_err(&iwdev->ibdev,
413 "Processing an iWARP related AE for CQ misc = 0x%04X\n",
414 info->ae_id);
415
416 spin_lock_irqsave(&rf->cqtable_lock, flags);
417 iwcq = rf->cq_table[info->qp_cq_id];
418 if (!iwcq) {
419 spin_unlock_irqrestore(&rf->cqtable_lock,
420 flags);
421 ibdev_dbg(to_ibdev(dev),
422 "cq_id %d is already freed\n", info->qp_cq_id);
423 continue;
424 }
425 irdma_cq_add_ref(&iwcq->ibcq);
426 spin_unlock_irqrestore(&rf->cqtable_lock, flags);
427
428 if (iwcq->ibcq.event_handler) {
429 struct ib_event ibevent;
430
431 ibevent.device = iwcq->ibcq.device;
432 ibevent.event = IB_EVENT_CQ_ERR;
433 ibevent.element.cq = &iwcq->ibcq;
434 iwcq->ibcq.event_handler(&ibevent,
435 iwcq->ibcq.cq_context);
436 }
437 irdma_cq_rem_ref(&iwcq->ibcq);
438 break;
439 case IRDMA_AE_SRQ_LIMIT:
440 srq = (struct irdma_sc_srq *)(uintptr_t)info->compl_ctx;
441 irdma_srq_event(srq);
442 break;
443 case IRDMA_AE_SRQ_CATASTROPHIC_ERROR:
444 break;
445 case IRDMA_AE_CQP_DEFERRED_COMPLETE:
446 /* Remove completed CQP requests from pending list
447 * and notify about those CQP ops completion.
448 */
449 irdma_process_ae_def_cmpl(rf, info);
450 break;
451 case IRDMA_AE_RESET_NOT_SENT:
452 case IRDMA_AE_LLP_DOUBT_REACHABILITY:
453 case IRDMA_AE_RESOURCE_EXHAUSTION:
454 break;
455 case IRDMA_AE_PRIV_OPERATION_DENIED:
456 case IRDMA_AE_STAG_ZERO_INVALID:
457 case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
458 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION:
459 case IRDMA_AE_DDP_UBE_INVALID_MO:
460 case IRDMA_AE_DDP_UBE_INVALID_QN:
461 case IRDMA_AE_DDP_NO_L_BIT:
462 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
463 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
464 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST:
465 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
466 case IRDMA_AE_INVALID_ARP_ENTRY:
467 case IRDMA_AE_INVALID_TCP_OPTION_RCVD:
468 case IRDMA_AE_STALE_ARP_ENTRY:
469 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
470 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
471 case IRDMA_AE_LLP_SYN_RECEIVED:
472 case IRDMA_AE_LLP_TOO_MANY_RETRIES:
473 case IRDMA_AE_LCE_QP_CATASTROPHIC:
474 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC:
475 case IRDMA_AE_LLP_TOO_MANY_RNRS:
476 case IRDMA_AE_LCE_CQ_CATASTROPHIC:
477 case IRDMA_AE_REMOTE_QP_CATASTROPHIC:
478 case IRDMA_AE_LOCAL_QP_CATASTROPHIC:
479 case IRDMA_AE_RCE_QP_CATASTROPHIC:
480 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
481 default:
482 ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_src=%d\n",
483 info->ae_id, info->qp, info->qp_cq_id, info->ae_src);
484 ctx_info = &iwqp->ctx_info;
485 if (rdma_protocol_roce(&iwqp->iwdev->ibdev, 1)) {
486 ctx_info->roce_info->err_rq_idx_valid =
487 ctx_info->srq_valid ? false : info->err_rq_idx_valid;
488 if (ctx_info->roce_info->err_rq_idx_valid) {
489 ctx_info->roce_info->err_rq_idx = info->wqe_idx;
490 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va,
491 ctx_info);
492 }
493 irdma_set_flush_fields(qp, info);
494 irdma_cm_disconn(iwqp);
495 break;
496 }
497 ctx_info->iwarp_info->err_rq_idx_valid = info->rq;
498 if (info->rq) {
499 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx;
500 ctx_info->tcp_info_valid = false;
501 ctx_info->iwarp_info_valid = true;
502 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va,
503 ctx_info);
504 }
505 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS &&
506 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) {
507 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0);
508 irdma_cm_disconn(iwqp);
509 } else {
510 irdma_terminate_connection(qp, info);
511 }
512 break;
513 }
514 if (info->qp)
515 irdma_qp_rem_ref(&iwqp->ibqp);
516 } while (1);
517
518 if (aeqcnt)
519 irdma_sc_repost_aeq_entries(dev, aeqcnt);
520 }
521
522 /**
523 * irdma_ena_intr - set up device interrupts
524 * @dev: hardware control device structure
525 * @msix_id: id of the interrupt to be enabled
526 */
irdma_ena_intr(struct irdma_sc_dev * dev,u32 msix_id)527 static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id)
528 {
529 dev->irq_ops->irdma_en_irq(dev, msix_id);
530 }
531
532 /**
533 * irdma_dpc - tasklet for aeq and ceq 0
534 * @t: tasklet_struct ptr
535 */
irdma_dpc(struct tasklet_struct * t)536 static void irdma_dpc(struct tasklet_struct *t)
537 {
538 struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet);
539
540 if (rf->msix_shared)
541 irdma_process_ceq(rf, rf->ceqlist);
542 irdma_process_aeq(rf);
543 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx);
544 }
545
546 /**
547 * irdma_ceq_dpc - dpc handler for CEQ
548 * @t: tasklet_struct ptr
549 */
irdma_ceq_dpc(struct tasklet_struct * t)550 static void irdma_ceq_dpc(struct tasklet_struct *t)
551 {
552 struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet);
553 struct irdma_pci_f *rf = iwceq->rf;
554
555 irdma_process_ceq(rf, iwceq);
556 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx);
557 }
558
559 /**
560 * irdma_save_msix_info - copy msix vector information to iwarp device
561 * @rf: RDMA PCI function
562 *
563 * Allocate iwdev msix table and copy the msix info to the table
564 * Return 0 if successful, otherwise return error
565 */
irdma_save_msix_info(struct irdma_pci_f * rf)566 static int irdma_save_msix_info(struct irdma_pci_f *rf)
567 {
568 struct irdma_qvlist_info *iw_qvlist;
569 struct irdma_qv_info *iw_qvinfo;
570 struct msix_entry *pmsix;
571 u32 ceq_idx;
572 u32 i;
573 size_t size;
574
575 if (!rf->msix_count)
576 return -EINVAL;
577
578 size = sizeof(struct irdma_msix_vector) * rf->msix_count;
579 size += struct_size(iw_qvlist, qv_info, rf->msix_count);
580 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL);
581 if (!rf->iw_msixtbl)
582 return -ENOMEM;
583
584 rf->iw_qvlist = (struct irdma_qvlist_info *)
585 (&rf->iw_msixtbl[rf->msix_count]);
586 iw_qvlist = rf->iw_qvlist;
587 iw_qvinfo = iw_qvlist->qv_info;
588 iw_qvlist->num_vectors = rf->msix_count;
589 if (rf->msix_count <= num_online_cpus())
590 rf->msix_shared = true;
591
592 pmsix = rf->msix_entries;
593 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) {
594 rf->iw_msixtbl[i].idx = pmsix->entry;
595 rf->iw_msixtbl[i].irq = pmsix->vector;
596 rf->iw_msixtbl[i].cpu_affinity = ceq_idx;
597 if (!i) {
598 iw_qvinfo->aeq_idx = 0;
599 if (rf->msix_shared)
600 iw_qvinfo->ceq_idx = ceq_idx++;
601 else
602 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX;
603 } else {
604 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX;
605 iw_qvinfo->ceq_idx = ceq_idx++;
606 }
607 iw_qvinfo->itr_idx = 3;
608 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx;
609 pmsix++;
610 }
611
612 return 0;
613 }
614
615 /**
616 * irdma_irq_handler - interrupt handler for aeq and ceq0
617 * @irq: Interrupt request number
618 * @data: RDMA PCI function
619 */
irdma_irq_handler(int irq,void * data)620 static irqreturn_t irdma_irq_handler(int irq, void *data)
621 {
622 struct irdma_pci_f *rf = data;
623
624 tasklet_schedule(&rf->dpc_tasklet);
625
626 return IRQ_HANDLED;
627 }
628
629 /**
630 * irdma_ceq_handler - interrupt handler for ceq
631 * @irq: interrupt request number
632 * @data: ceq pointer
633 */
irdma_ceq_handler(int irq,void * data)634 static irqreturn_t irdma_ceq_handler(int irq, void *data)
635 {
636 struct irdma_ceq *iwceq = data;
637
638 if (iwceq->irq != irq)
639 ibdev_err(to_ibdev(&iwceq->rf->sc_dev), "expected irq = %d received irq = %d\n",
640 iwceq->irq, irq);
641 tasklet_schedule(&iwceq->dpc_tasklet);
642
643 return IRQ_HANDLED;
644 }
645
646 /**
647 * irdma_destroy_irq - destroy device interrupts
648 * @rf: RDMA PCI function
649 * @msix_vec: msix vector to disable irq
650 * @dev_id: parameter to pass to free_irq (used during irq setup)
651 *
652 * The function is called when destroying aeq/ceq
653 */
irdma_destroy_irq(struct irdma_pci_f * rf,struct irdma_msix_vector * msix_vec,void * dev_id)654 static void irdma_destroy_irq(struct irdma_pci_f *rf,
655 struct irdma_msix_vector *msix_vec, void *dev_id)
656 {
657 struct irdma_sc_dev *dev = &rf->sc_dev;
658
659 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx);
660 irq_update_affinity_hint(msix_vec->irq, NULL);
661 free_irq(msix_vec->irq, dev_id);
662 if (rf == dev_id) {
663 tasklet_kill(&rf->dpc_tasklet);
664 } else {
665 struct irdma_ceq *iwceq = (struct irdma_ceq *)dev_id;
666
667 tasklet_kill(&iwceq->dpc_tasklet);
668 }
669 }
670
671 /**
672 * irdma_destroy_cqp - destroy control qp
673 * @rf: RDMA PCI function
674 *
675 * Issue destroy cqp request and
676 * free the resources associated with the cqp
677 */
irdma_destroy_cqp(struct irdma_pci_f * rf)678 static void irdma_destroy_cqp(struct irdma_pci_f *rf)
679 {
680 struct irdma_sc_dev *dev = &rf->sc_dev;
681 struct irdma_cqp *cqp = &rf->cqp;
682 int status = 0;
683
684 status = irdma_sc_cqp_destroy(dev->cqp);
685 if (status)
686 ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status);
687
688 irdma_cleanup_pending_cqp_op(rf);
689 dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va,
690 cqp->sq.pa);
691 cqp->sq.va = NULL;
692 kfree(cqp->oop_op_array);
693 cqp->oop_op_array = NULL;
694 kfree(cqp->scratch_array);
695 cqp->scratch_array = NULL;
696 kfree(cqp->cqp_requests);
697 cqp->cqp_requests = NULL;
698 }
699
irdma_destroy_virt_aeq(struct irdma_pci_f * rf)700 static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf)
701 {
702 struct irdma_aeq *aeq = &rf->aeq;
703 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
704 dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr;
705
706 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt);
707 irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
708 vfree(aeq->mem.va);
709 }
710
711 /**
712 * irdma_destroy_aeq - destroy aeq
713 * @rf: RDMA PCI function
714 *
715 * Issue a destroy aeq request and
716 * free the resources associated with the aeq
717 * The function is called during driver unload
718 */
irdma_destroy_aeq(struct irdma_pci_f * rf)719 static void irdma_destroy_aeq(struct irdma_pci_f *rf)
720 {
721 struct irdma_sc_dev *dev = &rf->sc_dev;
722 struct irdma_aeq *aeq = &rf->aeq;
723 int status = -EBUSY;
724
725 if (!rf->msix_shared) {
726 if (rf->sc_dev.privileged)
727 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev,
728 rf->iw_msixtbl->idx, false);
729 irdma_destroy_irq(rf, rf->iw_msixtbl, rf);
730 }
731 if (rf->reset)
732 goto exit;
733
734 aeq->sc_aeq.size = 0;
735 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY);
736 if (status)
737 ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status);
738
739 exit:
740 if (aeq->virtual_map) {
741 irdma_destroy_virt_aeq(rf);
742 } else {
743 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va,
744 aeq->mem.pa);
745 aeq->mem.va = NULL;
746 }
747 }
748
749 /**
750 * irdma_destroy_ceq - destroy ceq
751 * @rf: RDMA PCI function
752 * @iwceq: ceq to be destroyed
753 *
754 * Issue a destroy ceq request and
755 * free the resources associated with the ceq
756 */
irdma_destroy_ceq(struct irdma_pci_f * rf,struct irdma_ceq * iwceq)757 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq)
758 {
759 struct irdma_sc_dev *dev = &rf->sc_dev;
760 int status;
761
762 if (rf->reset)
763 goto exit;
764
765 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1);
766 if (status) {
767 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status);
768 goto exit;
769 }
770
771 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq);
772 if (status)
773 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n",
774 status);
775 exit:
776 dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va,
777 iwceq->mem.pa);
778 iwceq->mem.va = NULL;
779 }
780
781 /**
782 * irdma_del_ceq_0 - destroy ceq 0
783 * @rf: RDMA PCI function
784 *
785 * Disable the ceq 0 interrupt and destroy the ceq 0
786 */
irdma_del_ceq_0(struct irdma_pci_f * rf)787 static void irdma_del_ceq_0(struct irdma_pci_f *rf)
788 {
789 struct irdma_ceq *iwceq = rf->ceqlist;
790 struct irdma_msix_vector *msix_vec;
791
792 if (rf->msix_shared) {
793 msix_vec = &rf->iw_msixtbl[0];
794 if (rf->sc_dev.privileged)
795 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev,
796 msix_vec->ceq_id,
797 msix_vec->idx, false);
798 irdma_destroy_irq(rf, msix_vec, rf);
799 } else {
800 msix_vec = &rf->iw_msixtbl[1];
801 irdma_destroy_irq(rf, msix_vec, iwceq);
802 }
803
804 irdma_destroy_ceq(rf, iwceq);
805 rf->sc_dev.ceq_valid = false;
806 rf->ceqs_count = 0;
807 }
808
809 /**
810 * irdma_del_ceqs - destroy all ceq's except CEQ 0
811 * @rf: RDMA PCI function
812 *
813 * Go through all of the device ceq's, except 0, and for each
814 * ceq disable the ceq interrupt and destroy the ceq
815 */
irdma_del_ceqs(struct irdma_pci_f * rf)816 static void irdma_del_ceqs(struct irdma_pci_f *rf)
817 {
818 struct irdma_ceq *iwceq = &rf->ceqlist[1];
819 struct irdma_msix_vector *msix_vec;
820 u32 i = 0;
821
822 if (rf->msix_shared)
823 msix_vec = &rf->iw_msixtbl[1];
824 else
825 msix_vec = &rf->iw_msixtbl[2];
826
827 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) {
828 if (rf->sc_dev.privileged)
829 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev,
830 msix_vec->ceq_id,
831 msix_vec->idx, false);
832 irdma_destroy_irq(rf, msix_vec, iwceq);
833 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
834 IRDMA_OP_CEQ_DESTROY);
835 dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size,
836 iwceq->mem.va, iwceq->mem.pa);
837 iwceq->mem.va = NULL;
838 }
839 rf->ceqs_count = 1;
840 }
841
842 /**
843 * irdma_destroy_ccq - destroy control cq
844 * @rf: RDMA PCI function
845 *
846 * Issue destroy ccq request and
847 * free the resources associated with the ccq
848 */
irdma_destroy_ccq(struct irdma_pci_f * rf)849 static void irdma_destroy_ccq(struct irdma_pci_f *rf)
850 {
851 struct irdma_sc_dev *dev = &rf->sc_dev;
852 struct irdma_ccq *ccq = &rf->ccq;
853 int status = 0;
854
855 if (rf->cqp_cmpl_wq)
856 destroy_workqueue(rf->cqp_cmpl_wq);
857
858 if (!rf->reset)
859 status = irdma_sc_ccq_destroy(dev->ccq, 0, true);
860 if (status)
861 ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status);
862 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va,
863 ccq->mem_cq.pa);
864 ccq->mem_cq.va = NULL;
865 }
866
867 /**
868 * irdma_close_hmc_objects_type - delete hmc objects of a given type
869 * @dev: iwarp device
870 * @obj_type: the hmc object type to be deleted
871 * @hmc_info: host memory info struct
872 * @privileged: permission to close HMC objects
873 * @reset: true if called before reset
874 */
irdma_close_hmc_objects_type(struct irdma_sc_dev * dev,enum irdma_hmc_rsrc_type obj_type,struct irdma_hmc_info * hmc_info,bool privileged,bool reset)875 static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev,
876 enum irdma_hmc_rsrc_type obj_type,
877 struct irdma_hmc_info *hmc_info,
878 bool privileged, bool reset)
879 {
880 struct irdma_hmc_del_obj_info info = {};
881
882 info.hmc_info = hmc_info;
883 info.rsrc_type = obj_type;
884 info.count = hmc_info->hmc_obj[obj_type].cnt;
885 info.privileged = privileged;
886 if (irdma_sc_del_hmc_obj(dev, &info, reset))
887 ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n",
888 obj_type);
889 }
890
891 /**
892 * irdma_del_hmc_objects - remove all device hmc objects
893 * @dev: iwarp device
894 * @hmc_info: hmc_info to free
895 * @privileged: permission to delete HMC objects
896 * @reset: true if called before reset
897 * @vers: hardware version
898 */
irdma_del_hmc_objects(struct irdma_sc_dev * dev,struct irdma_hmc_info * hmc_info,bool privileged,bool reset,enum irdma_vers vers)899 static void irdma_del_hmc_objects(struct irdma_sc_dev *dev,
900 struct irdma_hmc_info *hmc_info, bool privileged,
901 bool reset, enum irdma_vers vers)
902 {
903 unsigned int i;
904
905 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
906 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
907 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
908 hmc_info, privileged, reset);
909 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
910 break;
911 }
912 }
913
914 /**
915 * irdma_create_hmc_obj_type - create hmc object of a given type
916 * @dev: hardware control device structure
917 * @info: information for the hmc object to create
918 */
irdma_create_hmc_obj_type(struct irdma_sc_dev * dev,struct irdma_hmc_create_obj_info * info)919 static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev,
920 struct irdma_hmc_create_obj_info *info)
921 {
922 return irdma_sc_create_hmc_obj(dev, info);
923 }
924
925 /**
926 * irdma_create_hmc_objs - create all hmc objects for the device
927 * @rf: RDMA PCI function
928 * @privileged: permission to create HMC objects
929 * @vers: HW version
930 *
931 * Create the device hmc objects and allocate hmc pages
932 * Return 0 if successful, otherwise clean up and return error
933 */
irdma_create_hmc_objs(struct irdma_pci_f * rf,bool privileged,enum irdma_vers vers)934 static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged,
935 enum irdma_vers vers)
936 {
937 struct irdma_sc_dev *dev = &rf->sc_dev;
938 struct irdma_hmc_create_obj_info info = {};
939 int i, status = 0;
940
941 info.hmc_info = dev->hmc_info;
942 info.privileged = privileged;
943 info.entry_type = rf->sd_type;
944
945 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
946 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE)
947 continue;
948 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) {
949 info.rsrc_type = iw_hmc_obj_types[i];
950 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt;
951 info.add_sd_cnt = 0;
952 status = irdma_create_hmc_obj_type(dev, &info);
953 if (status) {
954 ibdev_dbg(to_ibdev(dev),
955 "ERR: create obj type %d status = %d\n",
956 iw_hmc_obj_types[i], status);
957 break;
958 }
959 }
960 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
961 break;
962 }
963
964 if (!status)
965 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id,
966 true, true);
967
968 while (i) {
969 i--;
970 /* destroy the hmc objects of a given type */
971 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
972 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
973 dev->hmc_info, privileged,
974 false);
975 }
976
977 return status;
978 }
979
980 /**
981 * irdma_obj_aligned_mem - get aligned memory from device allocated memory
982 * @rf: RDMA PCI function
983 * @memptr: points to the memory addresses
984 * @size: size of memory needed
985 * @mask: mask for the aligned memory
986 *
987 * Get aligned memory of the requested size and
988 * update the memptr to point to the new aligned memory
989 * Return 0 if successful, otherwise return no memory error
990 */
irdma_obj_aligned_mem(struct irdma_pci_f * rf,struct irdma_dma_mem * memptr,u32 size,u32 mask)991 static int irdma_obj_aligned_mem(struct irdma_pci_f *rf,
992 struct irdma_dma_mem *memptr, u32 size,
993 u32 mask)
994 {
995 unsigned long va, newva;
996 unsigned long extra;
997
998 va = (unsigned long)rf->obj_next.va;
999 newva = va;
1000 if (mask)
1001 newva = ALIGN(va, (unsigned long)mask + 1ULL);
1002 extra = newva - va;
1003 memptr->va = (u8 *)va + extra;
1004 memptr->pa = rf->obj_next.pa + extra;
1005 memptr->size = size;
1006 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size))
1007 return -ENOMEM;
1008
1009 rf->obj_next.va = (u8 *)memptr->va + size;
1010 rf->obj_next.pa = memptr->pa + size;
1011
1012 return 0;
1013 }
1014
1015 /**
1016 * irdma_create_cqp - create control qp
1017 * @rf: RDMA PCI function
1018 *
1019 * Return 0, if the cqp and all the resources associated with it
1020 * are successfully created, otherwise return error
1021 */
irdma_create_cqp(struct irdma_pci_f * rf)1022 static int irdma_create_cqp(struct irdma_pci_f *rf)
1023 {
1024 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048;
1025 struct irdma_dma_mem mem;
1026 struct irdma_sc_dev *dev = &rf->sc_dev;
1027 struct irdma_cqp_init_info cqp_init_info = {};
1028 struct irdma_cqp *cqp = &rf->cqp;
1029 u16 maj_err, min_err;
1030 int i, status;
1031
1032 cqp->cqp_requests = kzalloc_objs(*cqp->cqp_requests, sqsize);
1033 if (!cqp->cqp_requests)
1034 return -ENOMEM;
1035
1036 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL);
1037 if (!cqp->scratch_array) {
1038 status = -ENOMEM;
1039 goto err_scratch;
1040 }
1041
1042 cqp->oop_op_array = kzalloc_objs(*cqp->oop_op_array, sqsize);
1043 if (!cqp->oop_op_array) {
1044 status = -ENOMEM;
1045 goto err_oop;
1046 }
1047 cqp_init_info.ooo_op_array = cqp->oop_op_array;
1048 dev->cqp = &cqp->sc_cqp;
1049 dev->cqp->dev = dev;
1050 cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize,
1051 IRDMA_CQP_ALIGNMENT);
1052 cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size,
1053 &cqp->sq.pa, GFP_KERNEL);
1054 if (!cqp->sq.va) {
1055 status = -ENOMEM;
1056 goto err_sq;
1057 }
1058
1059 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx),
1060 IRDMA_HOST_CTX_ALIGNMENT_M);
1061 if (status)
1062 goto err_ctx;
1063
1064 dev->cqp->host_ctx_pa = mem.pa;
1065 dev->cqp->host_ctx = mem.va;
1066 /* populate the cqp init info */
1067 cqp_init_info.dev = dev;
1068 cqp_init_info.sq_size = sqsize;
1069 cqp_init_info.sq = cqp->sq.va;
1070 cqp_init_info.sq_pa = cqp->sq.pa;
1071 cqp_init_info.host_ctx_pa = mem.pa;
1072 cqp_init_info.host_ctx = mem.va;
1073 cqp_init_info.hmc_profile = rf->rsrc_profile;
1074 cqp_init_info.scratch_array = cqp->scratch_array;
1075 cqp_init_info.protocol_used = rf->protocol_used;
1076
1077 switch (rf->rdma_ver) {
1078 case IRDMA_GEN_1:
1079 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1;
1080 break;
1081 case IRDMA_GEN_2:
1082 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2;
1083 break;
1084 case IRDMA_GEN_3:
1085 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_3;
1086 cqp_init_info.ts_override = 1;
1087 break;
1088 }
1089 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info);
1090 if (status) {
1091 ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status);
1092 goto err_ctx;
1093 }
1094
1095 spin_lock_init(&cqp->req_lock);
1096 spin_lock_init(&cqp->compl_lock);
1097
1098 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err);
1099 if (status) {
1100 ibdev_dbg(to_ibdev(dev),
1101 "ERR: cqp create failed - status %d maj_err %d min_err %d\n",
1102 status, maj_err, min_err);
1103 goto err_ctx;
1104 }
1105
1106 INIT_LIST_HEAD(&cqp->cqp_avail_reqs);
1107 INIT_LIST_HEAD(&cqp->cqp_pending_reqs);
1108
1109 /* init the waitqueue of the cqp_requests and add them to the list */
1110 for (i = 0; i < sqsize; i++) {
1111 init_waitqueue_head(&cqp->cqp_requests[i].waitq);
1112 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs);
1113 }
1114 init_waitqueue_head(&cqp->remove_wq);
1115 return 0;
1116
1117 err_ctx:
1118 dma_free_coherent(dev->hw->device, cqp->sq.size,
1119 cqp->sq.va, cqp->sq.pa);
1120 cqp->sq.va = NULL;
1121 err_sq:
1122 kfree(cqp->oop_op_array);
1123 cqp->oop_op_array = NULL;
1124 err_oop:
1125 kfree(cqp->scratch_array);
1126 cqp->scratch_array = NULL;
1127 err_scratch:
1128 kfree(cqp->cqp_requests);
1129 cqp->cqp_requests = NULL;
1130
1131 return status;
1132 }
1133
1134 /**
1135 * irdma_create_ccq - create control cq
1136 * @rf: RDMA PCI function
1137 *
1138 * Return 0, if the ccq and the resources associated with it
1139 * are successfully created, otherwise return error
1140 */
irdma_create_ccq(struct irdma_pci_f * rf)1141 static int irdma_create_ccq(struct irdma_pci_f *rf)
1142 {
1143 struct irdma_sc_dev *dev = &rf->sc_dev;
1144 struct irdma_ccq_init_info info = {};
1145 struct irdma_ccq *ccq = &rf->ccq;
1146 int ccq_size;
1147 int status;
1148
1149 dev->ccq = &ccq->sc_cq;
1150 dev->ccq->dev = dev;
1151 info.dev = dev;
1152 ccq_size = (rf->rdma_ver >= IRDMA_GEN_3) ? IW_GEN_3_CCQ_SIZE : IW_CCQ_SIZE;
1153 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area);
1154 ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * ccq_size,
1155 IRDMA_CQ0_ALIGNMENT);
1156 ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size,
1157 &ccq->mem_cq.pa, GFP_KERNEL);
1158 if (!ccq->mem_cq.va)
1159 return -ENOMEM;
1160
1161 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area,
1162 ccq->shadow_area.size,
1163 IRDMA_SHADOWAREA_M);
1164 if (status)
1165 goto exit;
1166
1167 ccq->sc_cq.back_cq = ccq;
1168 /* populate the ccq init info */
1169 info.cq_base = ccq->mem_cq.va;
1170 info.cq_pa = ccq->mem_cq.pa;
1171 info.num_elem = ccq_size;
1172 info.shadow_area = ccq->shadow_area.va;
1173 info.shadow_area_pa = ccq->shadow_area.pa;
1174 info.ceqe_mask = false;
1175 info.ceq_id_valid = true;
1176 info.shadow_read_threshold = 16;
1177 info.vsi = &rf->default_vsi;
1178 status = irdma_sc_ccq_init(dev->ccq, &info);
1179 if (!status)
1180 status = irdma_sc_ccq_create(dev->ccq, 0, true, true);
1181 exit:
1182 if (status) {
1183 dma_free_coherent(dev->hw->device, ccq->mem_cq.size,
1184 ccq->mem_cq.va, ccq->mem_cq.pa);
1185 ccq->mem_cq.va = NULL;
1186 }
1187
1188 return status;
1189 }
1190
1191 /**
1192 * irdma_alloc_set_mac - set up a mac address table entry
1193 * @iwdev: irdma device
1194 *
1195 * Allocate a mac ip entry and add it to the hw table Return 0
1196 * if successful, otherwise return error
1197 */
irdma_alloc_set_mac(struct irdma_device * iwdev)1198 static int irdma_alloc_set_mac(struct irdma_device *iwdev)
1199 {
1200 int status;
1201
1202 status = irdma_alloc_local_mac_entry(iwdev->rf,
1203 &iwdev->mac_ip_table_idx);
1204 if (!status) {
1205 status = irdma_add_local_mac_entry(iwdev->rf,
1206 (const u8 *)iwdev->netdev->dev_addr,
1207 (u8)iwdev->mac_ip_table_idx);
1208 if (status)
1209 irdma_del_local_mac_entry(iwdev->rf,
1210 (u8)iwdev->mac_ip_table_idx);
1211 }
1212 return status;
1213 }
1214
1215 /**
1216 * irdma_cfg_ceq_vector - set up the msix interrupt vector for
1217 * ceq
1218 * @rf: RDMA PCI function
1219 * @iwceq: ceq associated with the vector
1220 * @ceq_id: the id number of the iwceq
1221 * @msix_vec: interrupt vector information
1222 *
1223 * Allocate interrupt resources and enable irq handling
1224 * Return 0 if successful, otherwise return error
1225 */
irdma_cfg_ceq_vector(struct irdma_pci_f * rf,struct irdma_ceq * iwceq,u32 ceq_id,struct irdma_msix_vector * msix_vec)1226 static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1227 u32 ceq_id, struct irdma_msix_vector *msix_vec)
1228 {
1229 int status;
1230
1231 if (rf->msix_shared && !ceq_id) {
1232 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1233 "irdma-%s-AEQCEQ-0", dev_name(&rf->pcidev->dev));
1234 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1235 status = request_irq(msix_vec->irq, irdma_irq_handler, 0,
1236 msix_vec->name, rf);
1237 } else {
1238 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1239 "irdma-%s-CEQ-%d",
1240 dev_name(&rf->pcidev->dev), ceq_id);
1241 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc);
1242
1243 status = request_irq(msix_vec->irq, irdma_ceq_handler, 0,
1244 msix_vec->name, iwceq);
1245 }
1246 cpumask_clear(&msix_vec->mask);
1247 cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask);
1248 irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask);
1249 if (status) {
1250 ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n");
1251 return status;
1252 }
1253
1254 msix_vec->ceq_id = ceq_id;
1255 if (rf->sc_dev.privileged)
1256 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id,
1257 msix_vec->idx, true);
1258 else
1259 status = irdma_vchnl_req_ceq_vec_map(&rf->sc_dev, ceq_id,
1260 msix_vec->idx);
1261 return status;
1262 }
1263
1264 /**
1265 * irdma_cfg_aeq_vector - set up the msix vector for aeq
1266 * @rf: RDMA PCI function
1267 *
1268 * Allocate interrupt resources and enable irq handling
1269 * Return 0 if successful, otherwise return error
1270 */
irdma_cfg_aeq_vector(struct irdma_pci_f * rf)1271 static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf)
1272 {
1273 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl;
1274 int ret = 0;
1275
1276 if (!rf->msix_shared) {
1277 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1278 "irdma-%s-AEQ", dev_name(&rf->pcidev->dev));
1279 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1280 ret = request_irq(msix_vec->irq, irdma_irq_handler, 0,
1281 msix_vec->name, rf);
1282 }
1283 if (ret) {
1284 ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n");
1285 return ret;
1286 }
1287
1288 if (rf->sc_dev.privileged)
1289 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx,
1290 true);
1291 else
1292 ret = irdma_vchnl_req_aeq_vec_map(&rf->sc_dev, msix_vec->idx);
1293
1294 return ret;
1295 }
1296
1297 /**
1298 * irdma_create_ceq - create completion event queue
1299 * @rf: RDMA PCI function
1300 * @iwceq: pointer to the ceq resources to be created
1301 * @ceq_id: the id number of the iwceq
1302 * @vsi_idx: vsi idx
1303 *
1304 * Return 0, if the ceq and the resources associated with it
1305 * are successfully created, otherwise return error
1306 */
irdma_create_ceq(struct irdma_pci_f * rf,struct irdma_ceq * iwceq,u32 ceq_id,u16 vsi_idx)1307 static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1308 u32 ceq_id, u16 vsi_idx)
1309 {
1310 int status;
1311 struct irdma_ceq_init_info info = {};
1312 struct irdma_sc_dev *dev = &rf->sc_dev;
1313 u32 ceq_size;
1314
1315 info.ceq_id = ceq_id;
1316 iwceq->rf = rf;
1317 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt,
1318 dev->hw_attrs.max_hw_ceq_size);
1319 iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size,
1320 IRDMA_CEQ_ALIGNMENT);
1321 iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size,
1322 &iwceq->mem.pa, GFP_KERNEL);
1323 if (!iwceq->mem.va)
1324 return -ENOMEM;
1325
1326 info.ceq_id = ceq_id;
1327 info.ceqe_base = iwceq->mem.va;
1328 info.ceqe_pa = iwceq->mem.pa;
1329 info.elem_cnt = ceq_size;
1330 iwceq->sc_ceq.ceq_id = ceq_id;
1331 info.dev = dev;
1332 info.vsi_idx = vsi_idx;
1333 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info);
1334 if (!status) {
1335 if (dev->ceq_valid)
1336 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
1337 IRDMA_OP_CEQ_CREATE);
1338 else
1339 status = irdma_sc_cceq_create(&iwceq->sc_ceq, 0);
1340 }
1341
1342 if (status) {
1343 dma_free_coherent(dev->hw->device, iwceq->mem.size,
1344 iwceq->mem.va, iwceq->mem.pa);
1345 iwceq->mem.va = NULL;
1346 }
1347
1348 return status;
1349 }
1350
1351 /**
1352 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource
1353 * @rf: RDMA PCI function
1354 *
1355 * Allocate a list for all device completion event queues
1356 * Create the ceq 0 and configure it's msix interrupt vector
1357 * Return 0, if successfully set up, otherwise return error
1358 */
irdma_setup_ceq_0(struct irdma_pci_f * rf)1359 static int irdma_setup_ceq_0(struct irdma_pci_f *rf)
1360 {
1361 struct irdma_ceq *iwceq;
1362 struct irdma_msix_vector *msix_vec;
1363 u32 i;
1364 int status = 0;
1365 u32 num_ceqs;
1366
1367 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1368 rf->ceqlist = kzalloc_objs(*rf->ceqlist, num_ceqs);
1369 if (!rf->ceqlist) {
1370 status = -ENOMEM;
1371 goto exit;
1372 }
1373
1374 iwceq = &rf->ceqlist[0];
1375 status = irdma_create_ceq(rf, iwceq, 0, rf->default_vsi.vsi_idx);
1376 if (status) {
1377 ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n",
1378 status);
1379 goto exit;
1380 }
1381
1382 spin_lock_init(&iwceq->ce_lock);
1383 i = rf->msix_shared ? 0 : 1;
1384 msix_vec = &rf->iw_msixtbl[i];
1385 iwceq->irq = msix_vec->irq;
1386 iwceq->msix_idx = msix_vec->idx;
1387 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec);
1388 if (status) {
1389 irdma_destroy_ceq(rf, iwceq);
1390 goto exit;
1391 }
1392
1393 irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1394 rf->ceqs_count++;
1395
1396 exit:
1397 if (status && !rf->ceqs_count) {
1398 kfree(rf->ceqlist);
1399 rf->ceqlist = NULL;
1400 return status;
1401 }
1402 rf->sc_dev.ceq_valid = true;
1403
1404 return 0;
1405 }
1406
1407 /**
1408 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources
1409 * @rf: RDMA PCI function
1410 * @vsi_idx: vsi_idx for this CEQ
1411 *
1412 * Allocate a list for all device completion event queues
1413 * Create the ceq's and configure their msix interrupt vectors
1414 * Return 0, if ceqs are successfully set up, otherwise return error
1415 */
irdma_setup_ceqs(struct irdma_pci_f * rf,u16 vsi_idx)1416 static int irdma_setup_ceqs(struct irdma_pci_f *rf, u16 vsi_idx)
1417 {
1418 u32 i;
1419 u32 ceq_id;
1420 struct irdma_ceq *iwceq;
1421 struct irdma_msix_vector *msix_vec;
1422 int status;
1423 u32 num_ceqs;
1424
1425 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1426 i = (rf->msix_shared) ? 1 : 2;
1427 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) {
1428 iwceq = &rf->ceqlist[ceq_id];
1429 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi_idx);
1430 if (status) {
1431 ibdev_dbg(&rf->iwdev->ibdev,
1432 "ERR: create ceq status = %d\n", status);
1433 goto del_ceqs;
1434 }
1435 spin_lock_init(&iwceq->ce_lock);
1436 msix_vec = &rf->iw_msixtbl[i];
1437 iwceq->irq = msix_vec->irq;
1438 iwceq->msix_idx = msix_vec->idx;
1439 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec);
1440 if (status) {
1441 irdma_destroy_ceq(rf, iwceq);
1442 goto del_ceqs;
1443 }
1444 irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1445 rf->ceqs_count++;
1446 }
1447
1448 return 0;
1449
1450 del_ceqs:
1451 irdma_del_ceqs(rf);
1452
1453 return status;
1454 }
1455
irdma_create_virt_aeq(struct irdma_pci_f * rf,u32 size)1456 static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size)
1457 {
1458 struct irdma_aeq *aeq = &rf->aeq;
1459 dma_addr_t *pg_arr;
1460 u32 pg_cnt;
1461 int status;
1462
1463 if (rf->rdma_ver < IRDMA_GEN_2)
1464 return -EOPNOTSUPP;
1465
1466 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size;
1467 aeq->mem.va = vzalloc(aeq->mem.size);
1468
1469 if (!aeq->mem.va)
1470 return -ENOMEM;
1471
1472 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
1473 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true);
1474 if (status) {
1475 vfree(aeq->mem.va);
1476 return status;
1477 }
1478
1479 pg_arr = (dma_addr_t *)aeq->palloc.level1.addr;
1480 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt);
1481 if (status) {
1482 irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
1483 vfree(aeq->mem.va);
1484 return status;
1485 }
1486
1487 return 0;
1488 }
1489
1490 /**
1491 * irdma_create_aeq - create async event queue
1492 * @rf: RDMA PCI function
1493 *
1494 * Return 0, if the aeq and the resources associated with it
1495 * are successfully created, otherwise return error
1496 */
irdma_create_aeq(struct irdma_pci_f * rf)1497 static int irdma_create_aeq(struct irdma_pci_f *rf)
1498 {
1499 struct irdma_aeq_init_info info = {};
1500 struct irdma_sc_dev *dev = &rf->sc_dev;
1501 struct irdma_aeq *aeq = &rf->aeq;
1502 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info;
1503 u32 aeq_size;
1504 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1;
1505 int status;
1506
1507 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt +
1508 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
1509 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size);
1510 /* GEN_3 does not support virtual AEQ. Cap at max Kernel alloc size */
1511 if (rf->rdma_ver == IRDMA_GEN_3)
1512 aeq_size = min(aeq_size, (u32)((PAGE_SIZE << MAX_PAGE_ORDER) /
1513 sizeof(struct irdma_sc_aeqe)));
1514 aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size,
1515 IRDMA_AEQ_ALIGNMENT);
1516 aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size,
1517 &aeq->mem.pa,
1518 GFP_KERNEL | __GFP_NOWARN);
1519 if (aeq->mem.va)
1520 goto skip_virt_aeq;
1521 else if (rf->rdma_ver == IRDMA_GEN_3)
1522 return -ENOMEM;
1523
1524 /* physically mapped aeq failed. setup virtual aeq */
1525 status = irdma_create_virt_aeq(rf, aeq_size);
1526 if (status)
1527 return status;
1528
1529 info.virtual_map = true;
1530 aeq->virtual_map = info.virtual_map;
1531 info.pbl_chunk_size = 1;
1532 info.first_pm_pbl_idx = aeq->palloc.level1.idx;
1533
1534 skip_virt_aeq:
1535 info.aeqe_base = aeq->mem.va;
1536 info.aeq_elem_pa = aeq->mem.pa;
1537 info.elem_cnt = aeq_size;
1538 info.dev = dev;
1539 info.msix_idx = rf->iw_msixtbl->idx;
1540 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info);
1541 if (status)
1542 goto err;
1543
1544 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE);
1545 if (status)
1546 goto err;
1547
1548 return 0;
1549
1550 err:
1551 if (aeq->virtual_map) {
1552 irdma_destroy_virt_aeq(rf);
1553 } else {
1554 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va,
1555 aeq->mem.pa);
1556 aeq->mem.va = NULL;
1557 }
1558
1559 return status;
1560 }
1561
1562 /**
1563 * irdma_setup_aeq - set up the device aeq
1564 * @rf: RDMA PCI function
1565 *
1566 * Create the aeq and configure its msix interrupt vector
1567 * Return 0 if successful, otherwise return error
1568 */
irdma_setup_aeq(struct irdma_pci_f * rf)1569 static int irdma_setup_aeq(struct irdma_pci_f *rf)
1570 {
1571 struct irdma_sc_dev *dev = &rf->sc_dev;
1572 int status;
1573
1574 status = irdma_create_aeq(rf);
1575 if (status)
1576 return status;
1577
1578 status = irdma_cfg_aeq_vector(rf);
1579 if (status) {
1580 irdma_destroy_aeq(rf);
1581 return status;
1582 }
1583
1584 if (!rf->msix_shared)
1585 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx);
1586
1587 return 0;
1588 }
1589
1590 /**
1591 * irdma_initialize_ilq - create iwarp local queue for cm
1592 * @iwdev: irdma device
1593 *
1594 * Return 0 if successful, otherwise return error
1595 */
irdma_initialize_ilq(struct irdma_device * iwdev)1596 static int irdma_initialize_ilq(struct irdma_device *iwdev)
1597 {
1598 struct irdma_puda_rsrc_info info = {};
1599 int status;
1600
1601 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ;
1602 info.cq_id = IRDMA_RSVD_CQ_ID_ILQ;
1603 info.qp_id = IRDMA_RSVD_QP_ID_GSI_ILQ;
1604 info.count = 1;
1605 info.pd_id = 1;
1606 info.abi_ver = IRDMA_ABI_VER;
1607 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1608 info.rq_size = info.sq_size;
1609 info.buf_size = 1024;
1610 info.tx_buf_cnt = 2 * info.sq_size;
1611 info.receive = irdma_receive_ilq;
1612 info.xmit_complete = irdma_free_sqbuf;
1613 status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1614 if (status)
1615 ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n");
1616
1617 return status;
1618 }
1619
1620 /**
1621 * irdma_initialize_ieq - create iwarp exception queue
1622 * @iwdev: irdma device
1623 *
1624 * Return 0 if successful, otherwise return error
1625 */
irdma_initialize_ieq(struct irdma_device * iwdev)1626 static int irdma_initialize_ieq(struct irdma_device *iwdev)
1627 {
1628 struct irdma_puda_rsrc_info info = {};
1629 int status;
1630
1631 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ;
1632 info.cq_id = IRDMA_RSVD_CQ_ID_IEQ;
1633 info.qp_id = iwdev->vsi.exception_lan_q;
1634 info.count = 1;
1635 info.pd_id = 2;
1636 info.abi_ver = IRDMA_ABI_VER;
1637 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1638 info.rq_size = info.sq_size;
1639 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD;
1640 info.tx_buf_cnt = 4096;
1641 status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1642 if (status)
1643 ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n");
1644
1645 return status;
1646 }
1647
1648 /**
1649 * irdma_reinitialize_ieq - destroy and re-create ieq
1650 * @vsi: VSI structure
1651 */
irdma_reinitialize_ieq(struct irdma_sc_vsi * vsi)1652 void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi)
1653 {
1654 struct irdma_device *iwdev = vsi->back_vsi;
1655 struct irdma_pci_f *rf = iwdev->rf;
1656
1657 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false);
1658 if (irdma_initialize_ieq(iwdev)) {
1659 iwdev->rf->reset = true;
1660 rf->gen_ops.request_reset(rf);
1661 }
1662 }
1663
1664 /**
1665 * irdma_hmc_setup - create hmc objects for the device
1666 * @rf: RDMA PCI function
1667 *
1668 * Set up the device private memory space for the number and size of
1669 * the hmc objects and create the objects
1670 * Return 0 if successful, otherwise return error
1671 */
irdma_hmc_setup(struct irdma_pci_f * rf)1672 static int irdma_hmc_setup(struct irdma_pci_f *rf)
1673 {
1674 int status;
1675 u32 qpcnt;
1676
1677 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit;
1678
1679 rf->sd_type = IRDMA_SD_TYPE_DIRECT;
1680 status = irdma_cfg_fpm_val(&rf->sc_dev, qpcnt);
1681 if (status)
1682 return status;
1683
1684 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver);
1685
1686 return status;
1687 }
1688
1689 /**
1690 * irdma_del_init_mem - deallocate memory resources
1691 * @rf: RDMA PCI function
1692 */
irdma_del_init_mem(struct irdma_pci_f * rf)1693 static void irdma_del_init_mem(struct irdma_pci_f *rf)
1694 {
1695 struct irdma_sc_dev *dev = &rf->sc_dev;
1696
1697 if (!rf->sc_dev.privileged)
1698 irdma_vchnl_req_put_hmc_fcn(&rf->sc_dev);
1699 kfree(dev->hmc_info->sd_table.sd_entry);
1700 dev->hmc_info->sd_table.sd_entry = NULL;
1701 vfree(rf->mem_rsrc);
1702 rf->mem_rsrc = NULL;
1703 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va,
1704 rf->obj_mem.pa);
1705 rf->obj_mem.va = NULL;
1706 if (rf->rdma_ver != IRDMA_GEN_1) {
1707 bitmap_free(rf->allocated_ws_nodes);
1708 rf->allocated_ws_nodes = NULL;
1709 }
1710 kfree(rf->ceqlist);
1711 rf->ceqlist = NULL;
1712 kfree(rf->iw_msixtbl);
1713 rf->iw_msixtbl = NULL;
1714 kfree(rf->hmc_info_mem);
1715 rf->hmc_info_mem = NULL;
1716 }
1717
1718 /**
1719 * irdma_initialize_dev - initialize device
1720 * @rf: RDMA PCI function
1721 *
1722 * Allocate memory for the hmc objects and initialize iwdev
1723 * Return 0 if successful, otherwise clean up the resources
1724 * and return error
1725 */
irdma_initialize_dev(struct irdma_pci_f * rf)1726 static int irdma_initialize_dev(struct irdma_pci_f *rf)
1727 {
1728 int status;
1729 struct irdma_sc_dev *dev = &rf->sc_dev;
1730 struct irdma_device_init_info info = {};
1731 struct irdma_dma_mem mem;
1732 u32 size;
1733
1734 size = sizeof(struct irdma_hmc_pble_rsrc) +
1735 sizeof(struct irdma_hmc_info) +
1736 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX);
1737
1738 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL);
1739 if (!rf->hmc_info_mem)
1740 return -ENOMEM;
1741
1742 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem;
1743 dev->hmc_info = &rf->hw.hmc;
1744 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *)
1745 (rf->pble_rsrc + 1);
1746
1747 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE,
1748 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M);
1749 if (status)
1750 goto error;
1751
1752 info.fpm_query_buf_pa = mem.pa;
1753 info.fpm_query_buf = mem.va;
1754
1755 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE,
1756 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M);
1757 if (status)
1758 goto error;
1759
1760 info.fpm_commit_buf_pa = mem.pa;
1761 info.fpm_commit_buf = mem.va;
1762
1763 info.bar0 = rf->hw.hw_addr;
1764 info.hmc_fn_id = rf->pf_id;
1765 info.protocol_used = rf->protocol_used;
1766 info.hw = &rf->hw;
1767 status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info);
1768 if (status)
1769 goto error;
1770
1771 return status;
1772 error:
1773 kfree(rf->hmc_info_mem);
1774 rf->hmc_info_mem = NULL;
1775
1776 return status;
1777 }
1778
1779 /**
1780 * irdma_rt_deinit_hw - clean up the irdma device resources
1781 * @iwdev: irdma device
1782 *
1783 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the
1784 * device queues and free the pble and the hmc objects
1785 */
irdma_rt_deinit_hw(struct irdma_device * iwdev)1786 void irdma_rt_deinit_hw(struct irdma_device *iwdev)
1787 {
1788 ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state);
1789
1790 switch (iwdev->init_state) {
1791 case IP_ADDR_REGISTERED:
1792 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1793 irdma_del_local_mac_entry(iwdev->rf,
1794 (u8)iwdev->mac_ip_table_idx);
1795 fallthrough;
1796 case IEQ_CREATED:
1797 if (!iwdev->roce_mode)
1798 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ,
1799 iwdev->rf->reset);
1800 fallthrough;
1801 case ILQ_CREATED:
1802 if (!iwdev->roce_mode)
1803 irdma_puda_dele_rsrc(&iwdev->vsi,
1804 IRDMA_PUDA_RSRC_TYPE_ILQ,
1805 iwdev->rf->reset);
1806 break;
1807 default:
1808 ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state);
1809 break;
1810 }
1811
1812 irdma_cleanup_cm_core(&iwdev->cm_core);
1813 if (iwdev->vsi.pestat) {
1814 irdma_vsi_stats_free(&iwdev->vsi);
1815 kfree(iwdev->vsi.pestat);
1816 }
1817 if (iwdev->cleanup_wq)
1818 destroy_workqueue(iwdev->cleanup_wq);
1819 }
1820
irdma_setup_init_state(struct irdma_pci_f * rf)1821 static int irdma_setup_init_state(struct irdma_pci_f *rf)
1822 {
1823 int status;
1824
1825 status = irdma_save_msix_info(rf);
1826 if (status)
1827 return status;
1828
1829 rf->hw.device = &rf->pcidev->dev;
1830 rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE);
1831 rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size,
1832 &rf->obj_mem.pa, GFP_KERNEL);
1833 if (!rf->obj_mem.va) {
1834 status = -ENOMEM;
1835 goto clean_msixtbl;
1836 }
1837
1838 rf->obj_next = rf->obj_mem;
1839 status = irdma_initialize_dev(rf);
1840 if (status)
1841 goto clean_obj_mem;
1842
1843 return 0;
1844
1845 clean_obj_mem:
1846 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va,
1847 rf->obj_mem.pa);
1848 rf->obj_mem.va = NULL;
1849 clean_msixtbl:
1850 kfree(rf->iw_msixtbl);
1851 rf->iw_msixtbl = NULL;
1852 return status;
1853 }
1854
1855 /**
1856 * irdma_get_used_rsrc - determine resources used internally
1857 * @iwdev: irdma device
1858 *
1859 * Called at the end of open to get all internal allocations
1860 */
irdma_get_used_rsrc(struct irdma_device * iwdev)1861 static void irdma_get_used_rsrc(struct irdma_device *iwdev)
1862 {
1863 iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds,
1864 iwdev->rf->max_pd);
1865 iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps,
1866 iwdev->rf->max_qp);
1867 iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs,
1868 iwdev->rf->max_cq);
1869 iwdev->rf->used_srqs = find_first_zero_bit(iwdev->rf->allocated_srqs,
1870 iwdev->rf->max_srq);
1871 iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs,
1872 iwdev->rf->max_mr);
1873 }
1874
irdma_ctrl_deinit_hw(struct irdma_pci_f * rf)1875 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf)
1876 {
1877 enum init_completion_state state = rf->init_state;
1878
1879 rf->init_state = INVALID_STATE;
1880
1881 switch (state) {
1882 case AEQ_CREATED:
1883 irdma_destroy_aeq(rf);
1884 fallthrough;
1885 case PBLE_CHUNK_MEM:
1886 irdma_destroy_pble_prm(rf->pble_rsrc);
1887 fallthrough;
1888 case CEQS_CREATED:
1889 irdma_del_ceqs(rf);
1890 fallthrough;
1891 case CEQ0_CREATED:
1892 irdma_del_ceq_0(rf);
1893 fallthrough;
1894 case CCQ_CREATED:
1895 irdma_destroy_ccq(rf);
1896 fallthrough;
1897 case HW_RSRC_INITIALIZED:
1898 case HMC_OBJS_CREATED:
1899 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true,
1900 rf->reset, rf->rdma_ver);
1901 fallthrough;
1902 case CQP_CREATED:
1903 irdma_destroy_cqp(rf);
1904 fallthrough;
1905 case INITIAL_STATE:
1906 irdma_del_init_mem(rf);
1907 break;
1908 case INVALID_STATE:
1909 default:
1910 ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state);
1911 break;
1912 }
1913 }
1914
1915 /**
1916 * irdma_rt_init_hw - Initializes runtime portion of HW
1917 * @iwdev: irdma device
1918 * @l2params: qos, tc, mtu info from netdev driver
1919 *
1920 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma
1921 * device resource objects.
1922 */
irdma_rt_init_hw(struct irdma_device * iwdev,struct irdma_l2params * l2params)1923 int irdma_rt_init_hw(struct irdma_device *iwdev,
1924 struct irdma_l2params *l2params)
1925 {
1926 struct irdma_pci_f *rf = iwdev->rf;
1927 struct irdma_sc_dev *dev = &rf->sc_dev;
1928 struct irdma_vsi_init_info vsi_info = {};
1929 struct irdma_vsi_stats_info stats_info = {};
1930 int status;
1931
1932 vsi_info.dev = dev;
1933 vsi_info.back_vsi = iwdev;
1934 vsi_info.params = l2params;
1935 vsi_info.pf_data_vsi_num = iwdev->vsi_num;
1936 vsi_info.register_qset = rf->gen_ops.register_qset;
1937 vsi_info.unregister_qset = rf->gen_ops.unregister_qset;
1938 vsi_info.exception_lan_q = IRDMA_RSVD_QP_ID_IEQ;
1939 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info);
1940
1941 status = irdma_setup_cm_core(iwdev, rf->rdma_ver);
1942 if (status)
1943 return status;
1944
1945 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
1946 if (!stats_info.pestat) {
1947 irdma_cleanup_cm_core(&iwdev->cm_core);
1948 return -ENOMEM;
1949 }
1950 stats_info.fcn_id = dev->hmc_fn_id;
1951 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info);
1952 if (status) {
1953 irdma_cleanup_cm_core(&iwdev->cm_core);
1954 kfree(stats_info.pestat);
1955 return status;
1956 }
1957
1958 do {
1959 if (!iwdev->roce_mode) {
1960 status = irdma_initialize_ilq(iwdev);
1961 if (status)
1962 break;
1963 iwdev->init_state = ILQ_CREATED;
1964 status = irdma_initialize_ieq(iwdev);
1965 if (status)
1966 break;
1967 iwdev->init_state = IEQ_CREATED;
1968 }
1969 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1970 irdma_alloc_set_mac(iwdev);
1971 irdma_add_ip(iwdev);
1972 iwdev->init_state = IP_ADDR_REGISTERED;
1973
1974 /* handles asynch cleanup tasks - disconnect CM , free qp,
1975 * free cq bufs
1976 */
1977 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq",
1978 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
1979 if (!iwdev->cleanup_wq)
1980 return -ENOMEM;
1981 irdma_get_used_rsrc(iwdev);
1982 init_waitqueue_head(&iwdev->suspend_wq);
1983
1984 return 0;
1985 } while (0);
1986
1987 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n",
1988 status, iwdev->init_state);
1989 irdma_rt_deinit_hw(iwdev);
1990
1991 return status;
1992 }
1993
1994 /**
1995 * irdma_ctrl_init_hw - Initializes control portion of HW
1996 * @rf: RDMA PCI function
1997 *
1998 * Create admin queues, HMC obejcts and RF resource objects
1999 */
irdma_ctrl_init_hw(struct irdma_pci_f * rf)2000 int irdma_ctrl_init_hw(struct irdma_pci_f *rf)
2001 {
2002 struct irdma_sc_dev *dev = &rf->sc_dev;
2003 int status;
2004 do {
2005 status = irdma_setup_init_state(rf);
2006 if (status)
2007 break;
2008 rf->init_state = INITIAL_STATE;
2009
2010 status = irdma_create_cqp(rf);
2011 if (status)
2012 break;
2013 rf->init_state = CQP_CREATED;
2014
2015 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT;
2016 if (rf->rdma_ver != IRDMA_GEN_1) {
2017 status = irdma_get_rdma_features(dev);
2018 if (status)
2019 break;
2020 }
2021
2022 status = irdma_hmc_setup(rf);
2023 if (status)
2024 break;
2025 rf->init_state = HMC_OBJS_CREATED;
2026
2027 status = irdma_initialize_hw_rsrc(rf);
2028 if (status)
2029 break;
2030 rf->init_state = HW_RSRC_INITIALIZED;
2031
2032 status = irdma_create_ccq(rf);
2033 if (status)
2034 break;
2035 rf->init_state = CCQ_CREATED;
2036
2037 status = irdma_setup_ceq_0(rf);
2038 if (status)
2039 break;
2040 rf->init_state = CEQ0_CREATED;
2041 /* Handles processing of CQP completions */
2042 rf->cqp_cmpl_wq =
2043 alloc_ordered_workqueue("cqp_cmpl_wq", WQ_HIGHPRI);
2044 if (!rf->cqp_cmpl_wq) {
2045 status = -ENOMEM;
2046 break;
2047 }
2048 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker);
2049 irdma_sc_ccq_arm(dev->ccq);
2050
2051 status = irdma_setup_ceqs(rf, rf->iwdev ? rf->iwdev->vsi_num : 0);
2052 if (status)
2053 break;
2054
2055 rf->init_state = CEQS_CREATED;
2056
2057 status = irdma_hmc_init_pble(&rf->sc_dev,
2058 rf->pble_rsrc);
2059 if (status)
2060 break;
2061
2062 rf->init_state = PBLE_CHUNK_MEM;
2063
2064 status = irdma_setup_aeq(rf);
2065 if (status)
2066 break;
2067 rf->init_state = AEQ_CREATED;
2068
2069 return 0;
2070 } while (0);
2071
2072 dev_err(&rf->pcidev->dev, "IRDMA hardware initialization FAILED init_state=%d status=%d\n",
2073 rf->init_state, status);
2074 irdma_ctrl_deinit_hw(rf);
2075 return status;
2076 }
2077
2078 /**
2079 * irdma_set_hw_rsrc - set hw memory resources.
2080 * @rf: RDMA PCI function
2081 */
irdma_set_hw_rsrc(struct irdma_pci_f * rf)2082 static void irdma_set_hw_rsrc(struct irdma_pci_f *rf)
2083 {
2084 rf->allocated_qps = (void *)(rf->mem_rsrc +
2085 (sizeof(struct irdma_arp_entry) * rf->arp_table_size));
2086 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)];
2087 rf->allocated_srqs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)];
2088 rf->allocated_mrs = &rf->allocated_srqs[BITS_TO_LONGS(rf->max_srq)];
2089 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)];
2090 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)];
2091 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)];
2092 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)];
2093 rf->qp_table = (struct irdma_qp **)
2094 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]);
2095 rf->cq_table = (struct irdma_cq **)(&rf->qp_table[rf->max_qp]);
2096
2097 spin_lock_init(&rf->rsrc_lock);
2098 spin_lock_init(&rf->arp_lock);
2099 spin_lock_init(&rf->qptable_lock);
2100 spin_lock_init(&rf->cqtable_lock);
2101 spin_lock_init(&rf->qh_list_lock);
2102 }
2103
2104 /**
2105 * irdma_calc_mem_rsrc_size - calculate memory resources size.
2106 * @rf: RDMA PCI function
2107 */
irdma_calc_mem_rsrc_size(struct irdma_pci_f * rf)2108 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf)
2109 {
2110 u32 rsrc_size;
2111
2112 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size;
2113 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp);
2114 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr);
2115 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq);
2116 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_srq);
2117 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd);
2118 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size);
2119 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah);
2120 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg);
2121 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp;
2122 rsrc_size += sizeof(struct irdma_cq **) * rf->max_cq;
2123 rsrc_size += sizeof(struct irdma_srq **) * rf->max_srq;
2124
2125 return rsrc_size;
2126 }
2127
2128 /**
2129 * irdma_initialize_hw_rsrc - initialize hw resource tracking array
2130 * @rf: RDMA PCI function
2131 */
irdma_initialize_hw_rsrc(struct irdma_pci_f * rf)2132 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf)
2133 {
2134 u32 rsrc_size;
2135 u32 mrdrvbits;
2136 u32 ret;
2137
2138 if (rf->rdma_ver != IRDMA_GEN_1) {
2139 rf->allocated_ws_nodes = bitmap_zalloc(IRDMA_MAX_WS_NODES,
2140 GFP_KERNEL);
2141 if (!rf->allocated_ws_nodes)
2142 return -ENOMEM;
2143
2144 set_bit(0, rf->allocated_ws_nodes);
2145 rf->max_ws_node_id = IRDMA_MAX_WS_NODES;
2146 }
2147 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size;
2148 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt;
2149 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt;
2150 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
2151 rf->max_srq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].cnt;
2152 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds;
2153 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt;
2154 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt;
2155 rf->max_mcg = rf->max_qp;
2156
2157 rsrc_size = irdma_calc_mem_rsrc_size(rf);
2158 rf->mem_rsrc = vzalloc(rsrc_size);
2159 if (!rf->mem_rsrc) {
2160 ret = -ENOMEM;
2161 goto mem_rsrc_vzalloc_fail;
2162 }
2163
2164 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc;
2165
2166 irdma_set_hw_rsrc(rf);
2167
2168 set_bit(0, rf->allocated_mrs);
2169 set_bit(IRDMA_RSVD_QP_ID_0, rf->allocated_qps);
2170 set_bit(IRDMA_RSVD_CQ_ID_CQP, rf->allocated_cqs);
2171 set_bit(0, rf->allocated_srqs);
2172 set_bit(0, rf->allocated_pds);
2173 set_bit(0, rf->allocated_arps);
2174 set_bit(0, rf->allocated_ahs);
2175 set_bit(0, rf->allocated_mcgs);
2176 set_bit(IRDMA_RSVD_QP_ID_IEQ, rf->allocated_qps);
2177 set_bit(IRDMA_RSVD_QP_ID_GSI_ILQ, rf->allocated_qps);
2178 set_bit(IRDMA_RSVD_CQ_ID_ILQ, rf->allocated_cqs);
2179 set_bit(1, rf->allocated_pds);
2180 set_bit(IRDMA_RSVD_CQ_ID_IEQ, rf->allocated_cqs);
2181 set_bit(2, rf->allocated_pds);
2182
2183 INIT_LIST_HEAD(&rf->mc_qht_list.list);
2184 /* stag index mask has a minimum of 14 bits */
2185 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14);
2186 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
2187
2188 return 0;
2189
2190 mem_rsrc_vzalloc_fail:
2191 bitmap_free(rf->allocated_ws_nodes);
2192 rf->allocated_ws_nodes = NULL;
2193
2194 return ret;
2195 }
2196
2197 /**
2198 * irdma_cqp_ce_handler - handle cqp completions
2199 * @rf: RDMA PCI function
2200 * @cq: cq for cqp completions
2201 */
irdma_cqp_ce_handler(struct irdma_pci_f * rf,struct irdma_sc_cq * cq)2202 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq)
2203 {
2204 struct irdma_cqp_request *cqp_request;
2205 struct irdma_sc_dev *dev = &rf->sc_dev;
2206 u32 cqe_count = 0;
2207 struct irdma_ccq_cqe_info info;
2208 unsigned long flags;
2209 int ret;
2210
2211 do {
2212 memset(&info, 0, sizeof(info));
2213 spin_lock_irqsave(&rf->cqp.compl_lock, flags);
2214 ret = irdma_sc_ccq_get_cqe_info(cq, &info);
2215 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags);
2216 if (ret)
2217 break;
2218
2219 cqp_request = (struct irdma_cqp_request *)
2220 (unsigned long)info.scratch;
2221 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd,
2222 info.maj_err_code,
2223 info.min_err_code))
2224 ibdev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n",
2225 info.op_code, info.maj_err_code, info.min_err_code);
2226 if (cqp_request) {
2227 cqp_request->compl_info.maj_err_code = info.maj_err_code;
2228 cqp_request->compl_info.min_err_code = info.min_err_code;
2229 cqp_request->compl_info.op_ret_val = info.op_ret_val;
2230 cqp_request->compl_info.error = info.error;
2231
2232 /*
2233 * If this is deferred or pending completion, then mark
2234 * CQP request as pending to not block the CQ, but don't
2235 * release CQP request, as it is still on the OOO list.
2236 */
2237 if (info.pending)
2238 cqp_request->pending = true;
2239 else
2240 irdma_complete_cqp_request(&rf->cqp,
2241 cqp_request);
2242 }
2243
2244 cqe_count++;
2245 } while (1);
2246
2247 if (cqe_count) {
2248 irdma_process_bh(dev);
2249 irdma_sc_ccq_arm(cq);
2250 }
2251 }
2252
2253 /**
2254 * cqp_compl_worker - Handle cqp completions
2255 * @work: Pointer to work structure
2256 */
cqp_compl_worker(struct work_struct * work)2257 void cqp_compl_worker(struct work_struct *work)
2258 {
2259 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f,
2260 cqp_cmpl_work);
2261 struct irdma_sc_cq *cq = &rf->ccq.sc_cq;
2262
2263 irdma_cqp_ce_handler(rf, cq);
2264 }
2265
2266 /**
2267 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port
2268 * @cm_core: cm's core
2269 * @port: port to identify apbvt entry
2270 */
irdma_lookup_apbvt_entry(struct irdma_cm_core * cm_core,u16 port)2271 static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core,
2272 u16 port)
2273 {
2274 struct irdma_apbvt_entry *entry;
2275
2276 hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) {
2277 if (entry->port == port) {
2278 entry->use_cnt++;
2279 return entry;
2280 }
2281 }
2282
2283 return NULL;
2284 }
2285
2286 /**
2287 * irdma_next_iw_state - modify qp state
2288 * @iwqp: iwarp qp to modify
2289 * @state: next state for qp
2290 * @del_hash: del hash
2291 * @term: term message
2292 * @termlen: length of term message
2293 */
irdma_next_iw_state(struct irdma_qp * iwqp,u8 state,u8 del_hash,u8 term,u8 termlen)2294 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term,
2295 u8 termlen)
2296 {
2297 struct irdma_modify_qp_info info = {};
2298
2299 info.next_iwarp_state = state;
2300 info.remove_hash_idx = del_hash;
2301 info.cq_num_valid = true;
2302 info.arp_cache_idx_valid = true;
2303 info.dont_send_term = true;
2304 info.dont_send_fin = true;
2305 info.termlen = termlen;
2306
2307 if (term & IRDMAQP_TERM_SEND_TERM_ONLY)
2308 info.dont_send_term = false;
2309 if (term & IRDMAQP_TERM_SEND_FIN_ONLY)
2310 info.dont_send_fin = false;
2311 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR)
2312 info.reset_tcp_conn = true;
2313 iwqp->hw_iwarp_state = state;
2314 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0);
2315 iwqp->iwarp_state = info.next_iwarp_state;
2316 }
2317
2318 /**
2319 * irdma_del_local_mac_entry - remove a mac entry from the hw
2320 * table
2321 * @rf: RDMA PCI function
2322 * @idx: the index of the mac ip address to delete
2323 */
irdma_del_local_mac_entry(struct irdma_pci_f * rf,u16 idx)2324 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx)
2325 {
2326 struct irdma_cqp *iwcqp = &rf->cqp;
2327 struct irdma_cqp_request *cqp_request;
2328 struct cqp_cmds_info *cqp_info;
2329
2330 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2331 if (!cqp_request)
2332 return;
2333
2334 cqp_info = &cqp_request->info;
2335 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY;
2336 cqp_info->post_sq = 1;
2337 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp;
2338 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request;
2339 cqp_info->in.u.del_local_mac_entry.entry_idx = idx;
2340 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0;
2341
2342 irdma_handle_cqp_op(rf, cqp_request);
2343 irdma_put_cqp_request(iwcqp, cqp_request);
2344 }
2345
2346 /**
2347 * irdma_add_local_mac_entry - add a mac ip address entry to the
2348 * hw table
2349 * @rf: RDMA PCI function
2350 * @mac_addr: pointer to mac address
2351 * @idx: the index of the mac ip address to add
2352 */
irdma_add_local_mac_entry(struct irdma_pci_f * rf,const u8 * mac_addr,u16 idx)2353 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx)
2354 {
2355 struct irdma_local_mac_entry_info *info;
2356 struct irdma_cqp *iwcqp = &rf->cqp;
2357 struct irdma_cqp_request *cqp_request;
2358 struct cqp_cmds_info *cqp_info;
2359 int status;
2360
2361 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2362 if (!cqp_request)
2363 return -ENOMEM;
2364
2365 cqp_info = &cqp_request->info;
2366 cqp_info->post_sq = 1;
2367 info = &cqp_info->in.u.add_local_mac_entry.info;
2368 ether_addr_copy(info->mac_addr, mac_addr);
2369 info->entry_idx = idx;
2370 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2371 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY;
2372 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp;
2373 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2374
2375 status = irdma_handle_cqp_op(rf, cqp_request);
2376 irdma_put_cqp_request(iwcqp, cqp_request);
2377
2378 return status;
2379 }
2380
2381 /**
2382 * irdma_alloc_local_mac_entry - allocate a mac entry
2383 * @rf: RDMA PCI function
2384 * @mac_tbl_idx: the index of the new mac address
2385 *
2386 * Allocate a mac address entry and update the mac_tbl_idx
2387 * to hold the index of the newly created mac address
2388 * Return 0 if successful, otherwise return error
2389 */
irdma_alloc_local_mac_entry(struct irdma_pci_f * rf,u16 * mac_tbl_idx)2390 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx)
2391 {
2392 struct irdma_cqp *iwcqp = &rf->cqp;
2393 struct irdma_cqp_request *cqp_request;
2394 struct cqp_cmds_info *cqp_info;
2395 int status = 0;
2396
2397 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2398 if (!cqp_request)
2399 return -ENOMEM;
2400
2401 cqp_info = &cqp_request->info;
2402 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY;
2403 cqp_info->post_sq = 1;
2404 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp;
2405 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request;
2406 status = irdma_handle_cqp_op(rf, cqp_request);
2407 if (!status)
2408 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val;
2409
2410 irdma_put_cqp_request(iwcqp, cqp_request);
2411
2412 return status;
2413 }
2414
2415 /**
2416 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt
2417 * @iwdev: irdma device
2418 * @accel_local_port: port for apbvt
2419 * @add_port: add ordelete port
2420 */
irdma_cqp_manage_apbvt_cmd(struct irdma_device * iwdev,u16 accel_local_port,bool add_port)2421 static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev,
2422 u16 accel_local_port, bool add_port)
2423 {
2424 struct irdma_apbvt_info *info;
2425 struct irdma_cqp_request *cqp_request;
2426 struct cqp_cmds_info *cqp_info;
2427 int status;
2428
2429 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port);
2430 if (!cqp_request)
2431 return -ENOMEM;
2432
2433 cqp_info = &cqp_request->info;
2434 info = &cqp_info->in.u.manage_apbvt_entry.info;
2435 info->add = add_port;
2436 info->port = accel_local_port;
2437 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY;
2438 cqp_info->post_sq = 1;
2439 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2440 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;
2441 ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n",
2442 (!add_port) ? "DELETE" : "ADD", accel_local_port);
2443
2444 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2445 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2446
2447 return status;
2448 }
2449
2450 /**
2451 * irdma_add_apbvt - add tcp port to HW apbvt table
2452 * @iwdev: irdma device
2453 * @port: port for apbvt
2454 */
irdma_add_apbvt(struct irdma_device * iwdev,u16 port)2455 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port)
2456 {
2457 struct irdma_cm_core *cm_core = &iwdev->cm_core;
2458 struct irdma_apbvt_entry *entry;
2459 unsigned long flags;
2460
2461 spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2462 entry = irdma_lookup_apbvt_entry(cm_core, port);
2463 if (entry) {
2464 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2465 return entry;
2466 }
2467
2468 entry = kzalloc_obj(*entry, GFP_ATOMIC);
2469 if (!entry) {
2470 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2471 return NULL;
2472 }
2473
2474 entry->port = port;
2475 entry->use_cnt = 1;
2476 hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port);
2477 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2478
2479 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) {
2480 kfree(entry);
2481 return NULL;
2482 }
2483
2484 return entry;
2485 }
2486
2487 /**
2488 * irdma_del_apbvt - delete tcp port from HW apbvt table
2489 * @iwdev: irdma device
2490 * @entry: apbvt entry object
2491 */
irdma_del_apbvt(struct irdma_device * iwdev,struct irdma_apbvt_entry * entry)2492 void irdma_del_apbvt(struct irdma_device *iwdev,
2493 struct irdma_apbvt_entry *entry)
2494 {
2495 struct irdma_cm_core *cm_core = &iwdev->cm_core;
2496 unsigned long flags;
2497
2498 spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2499 if (--entry->use_cnt) {
2500 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2501 return;
2502 }
2503
2504 hash_del(&entry->hlist);
2505 /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to
2506 * protect against race where add APBVT CQP can race ahead of the delete
2507 * APBVT for same port.
2508 */
2509 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false);
2510 kfree(entry);
2511 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2512 }
2513
2514 /**
2515 * irdma_manage_arp_cache - manage hw arp cache
2516 * @rf: RDMA PCI function
2517 * @mac_addr: mac address ptr
2518 * @ip_addr: ip addr for arp cache
2519 * @ipv4: flag inicating IPv4
2520 * @action: add, delete or modify
2521 */
irdma_manage_arp_cache(struct irdma_pci_f * rf,const unsigned char * mac_addr,u32 * ip_addr,bool ipv4,u32 action)2522 void irdma_manage_arp_cache(struct irdma_pci_f *rf,
2523 const unsigned char *mac_addr,
2524 u32 *ip_addr, bool ipv4, u32 action)
2525 {
2526 struct irdma_add_arp_cache_entry_info *info;
2527 struct irdma_cqp_request *cqp_request;
2528 struct cqp_cmds_info *cqp_info;
2529 int arp_index;
2530
2531 arp_index = irdma_arp_table(rf, ip_addr, ipv4, mac_addr, action);
2532 if (arp_index == -1)
2533 return;
2534
2535 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
2536 if (!cqp_request)
2537 return;
2538
2539 cqp_info = &cqp_request->info;
2540 if (action == IRDMA_ARP_ADD) {
2541 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY;
2542 info = &cqp_info->in.u.add_arp_cache_entry.info;
2543 info->arp_index = (u16)arp_index;
2544 info->permanent = true;
2545 ether_addr_copy(info->mac_addr, mac_addr);
2546 cqp_info->in.u.add_arp_cache_entry.scratch =
2547 (uintptr_t)cqp_request;
2548 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2549 } else {
2550 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY;
2551 cqp_info->in.u.del_arp_cache_entry.scratch =
2552 (uintptr_t)cqp_request;
2553 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2554 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index;
2555 }
2556
2557 cqp_info->post_sq = 1;
2558 irdma_handle_cqp_op(rf, cqp_request);
2559 irdma_put_cqp_request(&rf->cqp, cqp_request);
2560 }
2561
2562 /**
2563 * irdma_send_syn_cqp_callback - do syn/ack after qhash
2564 * @cqp_request: qhash cqp completion
2565 */
irdma_send_syn_cqp_callback(struct irdma_cqp_request * cqp_request)2566 static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request)
2567 {
2568 struct irdma_cm_node *cm_node = cqp_request->param;
2569
2570 irdma_send_syn(cm_node, 1);
2571 irdma_rem_ref_cm_node(cm_node);
2572 }
2573
2574 /**
2575 * irdma_manage_qhash - add or modify qhash
2576 * @iwdev: irdma device
2577 * @cminfo: cm info for qhash
2578 * @etype: type (syn or quad)
2579 * @mtype: type of qhash
2580 * @cmnode: cmnode associated with connection
2581 * @wait: wait for completion
2582 */
irdma_manage_qhash(struct irdma_device * iwdev,struct irdma_cm_info * cminfo,enum irdma_quad_entry_type etype,enum irdma_quad_hash_manage_type mtype,void * cmnode,bool wait)2583 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
2584 enum irdma_quad_entry_type etype,
2585 enum irdma_quad_hash_manage_type mtype, void *cmnode,
2586 bool wait)
2587 {
2588 struct irdma_qhash_table_info *info;
2589 struct irdma_cqp *iwcqp = &iwdev->rf->cqp;
2590 struct irdma_cqp_request *cqp_request;
2591 struct cqp_cmds_info *cqp_info;
2592 struct irdma_cm_node *cm_node = cmnode;
2593 int status;
2594
2595 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
2596 if (!cqp_request)
2597 return -ENOMEM;
2598
2599 cqp_info = &cqp_request->info;
2600 info = &cqp_info->in.u.manage_qhash_table_entry.info;
2601 info->vsi = &iwdev->vsi;
2602 info->manage = mtype;
2603 info->entry_type = etype;
2604 if (cminfo->vlan_id < VLAN_N_VID) {
2605 info->vlan_valid = true;
2606 info->vlan_id = cminfo->vlan_id;
2607 } else {
2608 info->vlan_valid = false;
2609 }
2610 info->ipv4_valid = cminfo->ipv4;
2611 info->user_pri = cminfo->user_pri;
2612 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr);
2613 info->qp_num = cminfo->qh_qpid;
2614 info->dest_port = cminfo->loc_port;
2615 info->dest_ip[0] = cminfo->loc_addr[0];
2616 info->dest_ip[1] = cminfo->loc_addr[1];
2617 info->dest_ip[2] = cminfo->loc_addr[2];
2618 info->dest_ip[3] = cminfo->loc_addr[3];
2619 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED ||
2620 etype == IRDMA_QHASH_TYPE_UDP_UNICAST ||
2621 etype == IRDMA_QHASH_TYPE_UDP_MCAST ||
2622 etype == IRDMA_QHASH_TYPE_ROCE_MCAST ||
2623 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) {
2624 info->src_port = cminfo->rem_port;
2625 info->src_ip[0] = cminfo->rem_addr[0];
2626 info->src_ip[1] = cminfo->rem_addr[1];
2627 info->src_ip[2] = cminfo->rem_addr[2];
2628 info->src_ip[3] = cminfo->rem_addr[3];
2629 }
2630 if (cmnode) {
2631 cqp_request->callback_fcn = irdma_send_syn_cqp_callback;
2632 cqp_request->param = cmnode;
2633 if (!wait)
2634 refcount_inc(&cm_node->refcnt);
2635 }
2636 if (info->ipv4_valid)
2637 ibdev_dbg(&iwdev->ibdev,
2638 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n",
2639 (!mtype) ? "DELETE" : "ADD",
2640 __builtin_return_address(0), info->dest_port,
2641 info->src_port, info->dest_ip, info->src_ip,
2642 info->mac_addr, cminfo->vlan_id,
2643 cmnode ? cmnode : NULL);
2644 else
2645 ibdev_dbg(&iwdev->ibdev,
2646 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n",
2647 (!mtype) ? "DELETE" : "ADD",
2648 __builtin_return_address(0), info->dest_port,
2649 info->src_port, info->dest_ip, info->src_ip,
2650 info->mac_addr, cminfo->vlan_id,
2651 cmnode ? cmnode : NULL);
2652
2653 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2654 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;
2655 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY;
2656 cqp_info->post_sq = 1;
2657 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2658 if (status && cm_node && !wait)
2659 irdma_rem_ref_cm_node(cm_node);
2660
2661 irdma_put_cqp_request(iwcqp, cqp_request);
2662
2663 return status;
2664 }
2665
2666 /**
2667 * irdma_hw_flush_wqes_callback - Check return code after flush
2668 * @cqp_request: qhash cqp completion
2669 */
irdma_hw_flush_wqes_callback(struct irdma_cqp_request * cqp_request)2670 static void irdma_hw_flush_wqes_callback(struct irdma_cqp_request *cqp_request)
2671 {
2672 struct irdma_qp_flush_info *hw_info;
2673 struct irdma_sc_qp *qp;
2674 struct irdma_qp *iwqp;
2675 struct cqp_cmds_info *cqp_info;
2676
2677 cqp_info = &cqp_request->info;
2678 hw_info = &cqp_info->in.u.qp_flush_wqes.info;
2679 qp = cqp_info->in.u.qp_flush_wqes.qp;
2680 iwqp = qp->qp_uk.back_qp;
2681
2682 if (cqp_request->compl_info.maj_err_code)
2683 return;
2684
2685 if (hw_info->rq &&
2686 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2687 cqp_request->compl_info.min_err_code == 0)) {
2688 /* RQ WQE flush was requested but did not happen */
2689 qp->qp_uk.rq_flush_complete = true;
2690 }
2691 if (hw_info->sq &&
2692 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED ||
2693 cqp_request->compl_info.min_err_code == 0)) {
2694 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2695 ibdev_err(&iwqp->iwdev->ibdev, "Flush QP[%d] failed, SQ has more work",
2696 qp->qp_uk.qp_id);
2697 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC);
2698 }
2699 qp->qp_uk.sq_flush_complete = true;
2700 }
2701 }
2702
2703 /**
2704 * irdma_hw_flush_wqes - flush qp's wqe
2705 * @rf: RDMA PCI function
2706 * @qp: hardware control qp
2707 * @info: info for flush
2708 * @wait: flag wait for completion
2709 */
irdma_hw_flush_wqes(struct irdma_pci_f * rf,struct irdma_sc_qp * qp,struct irdma_qp_flush_info * info,bool wait)2710 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2711 struct irdma_qp_flush_info *info, bool wait)
2712 {
2713 int status;
2714 struct irdma_qp_flush_info *hw_info;
2715 struct irdma_cqp_request *cqp_request;
2716 struct cqp_cmds_info *cqp_info;
2717 struct irdma_qp *iwqp = qp->qp_uk.back_qp;
2718
2719 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2720 if (!cqp_request)
2721 return -ENOMEM;
2722
2723 cqp_info = &cqp_request->info;
2724 if (!wait)
2725 cqp_request->callback_fcn = irdma_hw_flush_wqes_callback;
2726 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info;
2727 memcpy(hw_info, info, sizeof(*hw_info));
2728 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES;
2729 cqp_info->post_sq = 1;
2730 cqp_info->in.u.qp_flush_wqes.qp = qp;
2731 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
2732 status = irdma_handle_cqp_op(rf, cqp_request);
2733 if (status) {
2734 qp->qp_uk.sq_flush_complete = true;
2735 qp->qp_uk.rq_flush_complete = true;
2736 irdma_put_cqp_request(&rf->cqp, cqp_request);
2737 return status;
2738 }
2739
2740 if (!wait || cqp_request->compl_info.maj_err_code)
2741 goto put_cqp;
2742
2743 if (info->rq) {
2744 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2745 cqp_request->compl_info.min_err_code == 0) {
2746 /* RQ WQE flush was requested but did not happen */
2747 qp->qp_uk.rq_flush_complete = true;
2748 }
2749 }
2750 if (info->sq) {
2751 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED ||
2752 cqp_request->compl_info.min_err_code == 0) {
2753 /*
2754 * Handling case where WQE is posted to empty SQ when
2755 * flush has not completed
2756 */
2757 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2758 struct irdma_cqp_request *new_req;
2759
2760 if (!qp->qp_uk.sq_flush_complete)
2761 goto put_cqp;
2762 qp->qp_uk.sq_flush_complete = false;
2763 qp->flush_sq = false;
2764
2765 info->rq = false;
2766 info->sq = true;
2767 new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
2768 if (!new_req) {
2769 status = -ENOMEM;
2770 goto put_cqp;
2771 }
2772 cqp_info = &new_req->info;
2773 hw_info = &new_req->info.in.u.qp_flush_wqes.info;
2774 memcpy(hw_info, info, sizeof(*hw_info));
2775 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES;
2776 cqp_info->post_sq = 1;
2777 cqp_info->in.u.qp_flush_wqes.qp = qp;
2778 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req;
2779
2780 status = irdma_handle_cqp_op(rf, new_req);
2781 if (new_req->compl_info.maj_err_code ||
2782 new_req->compl_info.min_err_code != IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2783 status) {
2784 ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d",
2785 iwqp->ibqp.qp_num);
2786 qp->qp_uk.sq_flush_complete = false;
2787 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC);
2788 }
2789 irdma_put_cqp_request(&rf->cqp, new_req);
2790 } else {
2791 /* SQ WQE flush was requested but did not happen */
2792 qp->qp_uk.sq_flush_complete = true;
2793 }
2794 } else {
2795 if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring))
2796 qp->qp_uk.sq_flush_complete = true;
2797 }
2798 }
2799
2800 ibdev_dbg(&rf->iwdev->ibdev,
2801 "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n",
2802 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state,
2803 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state,
2804 cqp_request->compl_info.maj_err_code,
2805 cqp_request->compl_info.min_err_code);
2806 put_cqp:
2807 irdma_put_cqp_request(&rf->cqp, cqp_request);
2808
2809 return status;
2810 }
2811
2812 /**
2813 * irdma_gen_ae - generate AE
2814 * @rf: RDMA PCI function
2815 * @qp: qp associated with AE
2816 * @info: info for ae
2817 * @wait: wait for completion
2818 */
irdma_gen_ae(struct irdma_pci_f * rf,struct irdma_sc_qp * qp,struct irdma_gen_ae_info * info,bool wait)2819 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2820 struct irdma_gen_ae_info *info, bool wait)
2821 {
2822 struct irdma_gen_ae_info *ae_info;
2823 struct irdma_cqp_request *cqp_request;
2824 struct cqp_cmds_info *cqp_info;
2825
2826 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2827 if (!cqp_request)
2828 return;
2829
2830 cqp_info = &cqp_request->info;
2831 ae_info = &cqp_request->info.in.u.gen_ae.info;
2832 memcpy(ae_info, info, sizeof(*ae_info));
2833 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE;
2834 cqp_info->post_sq = 1;
2835 cqp_info->in.u.gen_ae.qp = qp;
2836 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request;
2837
2838 irdma_handle_cqp_op(rf, cqp_request);
2839 irdma_put_cqp_request(&rf->cqp, cqp_request);
2840 }
2841
irdma_flush_wqes(struct irdma_qp * iwqp,u32 flush_mask)2842 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask)
2843 {
2844 struct irdma_qp_flush_info info = {};
2845 struct irdma_pci_f *rf = iwqp->iwdev->rf;
2846 u8 flush_code = iwqp->sc_qp.flush_code;
2847
2848 if ((!(flush_mask & IRDMA_FLUSH_SQ) &&
2849 !(flush_mask & IRDMA_FLUSH_RQ)) ||
2850 ((flush_mask & IRDMA_REFLUSH) && rf->rdma_ver >= IRDMA_GEN_3))
2851 return;
2852
2853 /* Set flush info fields*/
2854 info.sq = flush_mask & IRDMA_FLUSH_SQ;
2855 info.rq = flush_mask & IRDMA_FLUSH_RQ;
2856
2857 /* Generate userflush errors in CQE */
2858 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2859 info.sq_minor_code = FLUSH_GENERAL_ERR;
2860 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2861 info.rq_minor_code = FLUSH_GENERAL_ERR;
2862 info.userflushcode = true;
2863 info.err_sq_idx_valid = iwqp->sc_qp.err_sq_idx_valid;
2864 info.err_sq_idx = iwqp->sc_qp.err_sq_idx;
2865 info.err_rq_idx_valid = iwqp->sc_qp.err_rq_idx_valid;
2866 info.err_rq_idx = iwqp->sc_qp.err_rq_idx;
2867
2868 if (flush_mask & IRDMA_REFLUSH) {
2869 if (info.sq)
2870 iwqp->sc_qp.flush_sq = false;
2871 if (info.rq)
2872 iwqp->sc_qp.flush_rq = false;
2873 } else {
2874 if (flush_code) {
2875 if (info.sq && iwqp->sc_qp.sq_flush_code)
2876 info.sq_minor_code = flush_code;
2877 if (info.rq && iwqp->sc_qp.rq_flush_code)
2878 info.rq_minor_code = flush_code;
2879 }
2880 if (!iwqp->user_mode)
2881 queue_delayed_work(iwqp->iwdev->cleanup_wq,
2882 &iwqp->dwork_flush,
2883 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
2884 }
2885
2886 /* Issue flush */
2887 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info,
2888 flush_mask & IRDMA_FLUSH_WAIT);
2889 iwqp->flush_issued = true;
2890 }
2891