1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IOMMU API for MTK architected m4u v1 implementations
4 *
5 * Copyright (c) 2015-2016 MediaTek Inc.
6 * Author: Honghui Zhang <honghui.zhang@mediatek.com>
7 *
8 * Based on driver/iommu/mtk_iommu.c
9 */
10 #include <linux/bug.h>
11 #include <linux/clk.h>
12 #include <linux/component.h>
13 #include <linux/device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iommu.h>
19 #include <linux/iopoll.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28 #include <linux/string_choices.h>
29 #include <asm/barrier.h>
30 #include <asm/dma-iommu.h>
31 #include <dt-bindings/memory/mtk-memory-port.h>
32 #include <dt-bindings/memory/mt2701-larb-port.h>
33 #include <soc/mediatek/smi.h>
34
35 #define REG_MMU_PT_BASE_ADDR 0x000
36
37 #define F_ALL_INVLD 0x2
38 #define F_MMU_INV_RANGE 0x1
39 #define F_INVLD_EN0 BIT(0)
40 #define F_INVLD_EN1 BIT(1)
41
42 #define F_MMU_FAULT_VA_MSK 0xfffff000
43 #define MTK_PROTECT_PA_ALIGN 128
44
45 #define REG_MMU_CTRL_REG 0x210
46 #define F_MMU_CTRL_COHERENT_EN BIT(8)
47 #define REG_MMU_IVRP_PADDR 0x214
48 #define REG_MMU_INT_CONTROL 0x220
49 #define F_INT_TRANSLATION_FAULT BIT(0)
50 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
51 #define F_INT_INVALID_PA_FAULT BIT(2)
52 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
53 #define F_INT_TABLE_WALK_FAULT BIT(4)
54 #define F_INT_TLB_MISS_FAULT BIT(5)
55 #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6)
56 #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7)
57
58 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
59 #define F_INT_CLR_BIT BIT(12)
60
61 #define REG_MMU_FAULT_ST 0x224
62 #define REG_MMU_FAULT_VA 0x228
63 #define REG_MMU_INVLD_PA 0x22C
64 #define REG_MMU_INT_ID 0x388
65 #define REG_MMU_INVALIDATE 0x5c0
66 #define REG_MMU_INVLD_START_A 0x5c4
67 #define REG_MMU_INVLD_END_A 0x5c8
68
69 #define REG_MMU_INV_SEL 0x5d8
70 #define REG_MMU_STANDARD_AXI_MODE 0x5e8
71
72 #define REG_MMU_DCM 0x5f0
73 #define F_MMU_DCM_ON BIT(1)
74 #define REG_MMU_CPE_DONE 0x60c
75 #define F_DESC_VALID 0x2
76 #define F_DESC_NONSEC BIT(3)
77 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
78 #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF)
79 /* MTK generation one iommu HW only support 4K size mapping */
80 #define MT2701_IOMMU_PAGE_SHIFT 12
81 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT)
82 #define MT2701_LARB_NR_MAX 3
83
84 /*
85 * MTK m4u support 4GB iova address space, and only support 4K page
86 * mapping. So the pagetable size should be exactly as 4M.
87 */
88 #define M2701_IOMMU_PGT_SIZE SZ_4M
89
90 struct mtk_iommu_v1_suspend_reg {
91 u32 standard_axi_mode;
92 u32 dcm_dis;
93 u32 ctrl_reg;
94 u32 int_control0;
95 };
96
97 struct mtk_iommu_v1_data {
98 void __iomem *base;
99 int irq;
100 struct device *dev;
101 struct clk *bclk;
102 phys_addr_t protect_base; /* protect memory base */
103 struct mtk_iommu_v1_domain *m4u_dom;
104
105 struct iommu_device iommu;
106 struct dma_iommu_mapping *mapping;
107 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
108
109 struct mtk_iommu_v1_suspend_reg reg;
110 };
111
112 struct mtk_iommu_v1_domain {
113 spinlock_t pgtlock; /* lock for page table */
114 struct iommu_domain domain;
115 u32 *pgt_va;
116 dma_addr_t pgt_pa;
117 struct mtk_iommu_v1_data *data;
118 };
119
mtk_iommu_v1_bind(struct device * dev)120 static int mtk_iommu_v1_bind(struct device *dev)
121 {
122 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
123
124 return component_bind_all(dev, &data->larb_imu);
125 }
126
mtk_iommu_v1_unbind(struct device * dev)127 static void mtk_iommu_v1_unbind(struct device *dev)
128 {
129 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
130
131 component_unbind_all(dev, &data->larb_imu);
132 }
133
to_mtk_domain(struct iommu_domain * dom)134 static struct mtk_iommu_v1_domain *to_mtk_domain(struct iommu_domain *dom)
135 {
136 return container_of(dom, struct mtk_iommu_v1_domain, domain);
137 }
138
139 static const int mt2701_m4u_in_larb[] = {
140 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
141 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
142 };
143
mt2701_m4u_to_larb(int id)144 static inline int mt2701_m4u_to_larb(int id)
145 {
146 int i;
147
148 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
149 if ((id) >= mt2701_m4u_in_larb[i])
150 return i;
151
152 return 0;
153 }
154
mt2701_m4u_to_port(int id)155 static inline int mt2701_m4u_to_port(int id)
156 {
157 int larb = mt2701_m4u_to_larb(id);
158
159 return id - mt2701_m4u_in_larb[larb];
160 }
161
mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data * data)162 static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data)
163 {
164 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
165 data->base + REG_MMU_INV_SEL);
166 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
167 wmb(); /* Make sure the tlb flush all done */
168 }
169
mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data * data,unsigned long iova,size_t size)170 static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data,
171 unsigned long iova, size_t size)
172 {
173 int ret;
174 u32 tmp;
175
176 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
177 data->base + REG_MMU_INV_SEL);
178 writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
179 data->base + REG_MMU_INVLD_START_A);
180 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
181 data->base + REG_MMU_INVLD_END_A);
182 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
183
184 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
185 tmp, tmp != 0, 10, 100000);
186 if (ret) {
187 dev_warn(data->dev,
188 "Partial TLB flush timed out, falling back to full flush\n");
189 mtk_iommu_v1_tlb_flush_all(data);
190 }
191 /* Clear the CPE status */
192 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
193 }
194
mtk_iommu_v1_isr(int irq,void * dev_id)195 static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id)
196 {
197 struct mtk_iommu_v1_data *data = dev_id;
198 struct mtk_iommu_v1_domain *dom = data->m4u_dom;
199 u32 int_state, regval, fault_iova, fault_pa;
200 unsigned int fault_larb, fault_port;
201
202 /* Read error information from registers */
203 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
204 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
205
206 fault_iova &= F_MMU_FAULT_VA_MSK;
207 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
208 regval = readl_relaxed(data->base + REG_MMU_INT_ID);
209 fault_larb = MT2701_M4U_TF_LARB(regval);
210 fault_port = MT2701_M4U_TF_PORT(regval);
211
212 /*
213 * MTK v1 iommu HW could not determine whether the fault is read or
214 * write fault, report as read fault.
215 */
216 if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
217 IOMMU_FAULT_READ))
218 dev_err_ratelimited(data->dev,
219 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
220 int_state, fault_iova, fault_pa,
221 fault_larb, fault_port);
222
223 /* Interrupt clear */
224 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
225 regval |= F_INT_CLR_BIT;
226 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
227
228 mtk_iommu_v1_tlb_flush_all(data);
229
230 return IRQ_HANDLED;
231 }
232
mtk_iommu_v1_config(struct mtk_iommu_v1_data * data,struct device * dev,bool enable)233 static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data,
234 struct device *dev, bool enable)
235 {
236 struct mtk_smi_larb_iommu *larb_mmu;
237 unsigned int larbid, portid;
238 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
239 int i;
240
241 for (i = 0; i < fwspec->num_ids; ++i) {
242 larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
243 portid = mt2701_m4u_to_port(fwspec->ids[i]);
244 larb_mmu = &data->larb_imu[larbid];
245
246 dev_dbg(dev, "%s iommu port: %d\n",
247 str_enable_disable(enable), portid);
248
249 if (enable)
250 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
251 else
252 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
253 }
254 }
255
mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data * data)256 static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data)
257 {
258 struct mtk_iommu_v1_domain *dom = data->m4u_dom;
259
260 spin_lock_init(&dom->pgtlock);
261
262 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
263 &dom->pgt_pa, GFP_KERNEL);
264 if (!dom->pgt_va)
265 return -ENOMEM;
266
267 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
268
269 dom->data = data;
270
271 return 0;
272 }
273
mtk_iommu_v1_domain_alloc_paging(struct device * dev)274 static struct iommu_domain *mtk_iommu_v1_domain_alloc_paging(struct device *dev)
275 {
276 struct mtk_iommu_v1_domain *dom;
277
278 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
279 if (!dom)
280 return NULL;
281
282 return &dom->domain;
283 }
284
mtk_iommu_v1_domain_free(struct iommu_domain * domain)285 static void mtk_iommu_v1_domain_free(struct iommu_domain *domain)
286 {
287 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
288 struct mtk_iommu_v1_data *data = dom->data;
289
290 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
291 dom->pgt_va, dom->pgt_pa);
292 kfree(to_mtk_domain(domain));
293 }
294
mtk_iommu_v1_attach_device(struct iommu_domain * domain,struct device * dev)295 static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device *dev)
296 {
297 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
298 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
299 struct dma_iommu_mapping *mtk_mapping;
300 int ret;
301
302 /* Only allow the domain created internally. */
303 mtk_mapping = data->mapping;
304 if (mtk_mapping->domain != domain)
305 return 0;
306
307 if (!data->m4u_dom) {
308 data->m4u_dom = dom;
309 ret = mtk_iommu_v1_domain_finalise(data);
310 if (ret) {
311 data->m4u_dom = NULL;
312 return ret;
313 }
314 }
315
316 mtk_iommu_v1_config(data, dev, true);
317 return 0;
318 }
319
mtk_iommu_v1_identity_attach(struct iommu_domain * identity_domain,struct device * dev)320 static int mtk_iommu_v1_identity_attach(struct iommu_domain *identity_domain,
321 struct device *dev)
322 {
323 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
324
325 mtk_iommu_v1_config(data, dev, false);
326 return 0;
327 }
328
329 static struct iommu_domain_ops mtk_iommu_v1_identity_ops = {
330 .attach_dev = mtk_iommu_v1_identity_attach,
331 };
332
333 static struct iommu_domain mtk_iommu_v1_identity_domain = {
334 .type = IOMMU_DOMAIN_IDENTITY,
335 .ops = &mtk_iommu_v1_identity_ops,
336 };
337
mtk_iommu_v1_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int prot,gfp_t gfp,size_t * mapped)338 static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova,
339 phys_addr_t paddr, size_t pgsize, size_t pgcount,
340 int prot, gfp_t gfp, size_t *mapped)
341 {
342 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
343 unsigned long flags;
344 unsigned int i;
345 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
346 u32 pabase = (u32)paddr;
347
348 spin_lock_irqsave(&dom->pgtlock, flags);
349 for (i = 0; i < pgcount; i++) {
350 if (pgt_base_iova[i])
351 break;
352 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
353 pabase += MT2701_IOMMU_PAGE_SIZE;
354 }
355
356 spin_unlock_irqrestore(&dom->pgtlock, flags);
357
358 *mapped = i * MT2701_IOMMU_PAGE_SIZE;
359 mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped);
360
361 return i == pgcount ? 0 : -EEXIST;
362 }
363
mtk_iommu_v1_unmap(struct iommu_domain * domain,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * gather)364 static size_t mtk_iommu_v1_unmap(struct iommu_domain *domain, unsigned long iova,
365 size_t pgsize, size_t pgcount,
366 struct iommu_iotlb_gather *gather)
367 {
368 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
369 unsigned long flags;
370 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
371 size_t size = pgcount * MT2701_IOMMU_PAGE_SIZE;
372
373 spin_lock_irqsave(&dom->pgtlock, flags);
374 memset(pgt_base_iova, 0, pgcount * sizeof(u32));
375 spin_unlock_irqrestore(&dom->pgtlock, flags);
376
377 mtk_iommu_v1_tlb_flush_range(dom->data, iova, size);
378
379 return size;
380 }
381
mtk_iommu_v1_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)382 static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
383 {
384 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain);
385 unsigned long flags;
386 phys_addr_t pa;
387
388 spin_lock_irqsave(&dom->pgtlock, flags);
389 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
390 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
391 spin_unlock_irqrestore(&dom->pgtlock, flags);
392
393 return pa;
394 }
395
396 static const struct iommu_ops mtk_iommu_v1_ops;
397
398 /*
399 * MTK generation one iommu HW only support one iommu domain, and all the client
400 * sharing the same iova address space.
401 */
mtk_iommu_v1_create_mapping(struct device * dev,const struct of_phandle_args * args)402 static int mtk_iommu_v1_create_mapping(struct device *dev,
403 const struct of_phandle_args *args)
404 {
405 struct mtk_iommu_v1_data *data;
406 struct platform_device *m4updev;
407 struct dma_iommu_mapping *mtk_mapping;
408 int ret;
409
410 if (args->args_count != 1) {
411 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
412 args->args_count);
413 return -EINVAL;
414 }
415
416 ret = iommu_fwspec_init(dev, of_fwnode_handle(args->np));
417 if (ret)
418 return ret;
419
420 if (!dev_iommu_priv_get(dev)) {
421 /* Get the m4u device */
422 m4updev = of_find_device_by_node(args->np);
423 if (WARN_ON(!m4updev))
424 return -EINVAL;
425
426 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
427 }
428
429 ret = iommu_fwspec_add_ids(dev, args->args, 1);
430 if (ret)
431 return ret;
432
433 data = dev_iommu_priv_get(dev);
434 mtk_mapping = data->mapping;
435 if (!mtk_mapping) {
436 /* MTK iommu support 4GB iova address space. */
437 mtk_mapping = arm_iommu_create_mapping(dev, 0, 1ULL << 32);
438 if (IS_ERR(mtk_mapping))
439 return PTR_ERR(mtk_mapping);
440
441 data->mapping = mtk_mapping;
442 }
443
444 return 0;
445 }
446
mtk_iommu_v1_probe_device(struct device * dev)447 static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev)
448 {
449 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
450 struct of_phandle_args iommu_spec;
451 struct mtk_iommu_v1_data *data;
452 int err, idx = 0, larbid, larbidx;
453 struct device_link *link;
454 struct device *larbdev;
455
456 /*
457 * In the deferred case, free the existed fwspec.
458 * Always initialize the fwspec internally.
459 */
460 if (fwspec) {
461 iommu_fwspec_free(dev);
462 fwspec = dev_iommu_fwspec_get(dev);
463 }
464
465 while (!of_parse_phandle_with_args(dev->of_node, "iommus",
466 "#iommu-cells",
467 idx, &iommu_spec)) {
468
469 err = mtk_iommu_v1_create_mapping(dev, &iommu_spec);
470 of_node_put(iommu_spec.np);
471 if (err)
472 return ERR_PTR(err);
473
474 /* dev->iommu_fwspec might have changed */
475 fwspec = dev_iommu_fwspec_get(dev);
476 idx++;
477 }
478
479 data = dev_iommu_priv_get(dev);
480
481 /* Link the consumer device with the smi-larb device(supplier) */
482 larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
483 if (larbid >= MT2701_LARB_NR_MAX)
484 return ERR_PTR(-EINVAL);
485
486 for (idx = 1; idx < fwspec->num_ids; idx++) {
487 larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]);
488 if (larbid != larbidx) {
489 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
490 larbid, larbidx);
491 return ERR_PTR(-EINVAL);
492 }
493 }
494
495 larbdev = data->larb_imu[larbid].dev;
496 if (!larbdev)
497 return ERR_PTR(-EINVAL);
498
499 link = device_link_add(dev, larbdev,
500 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
501 if (!link)
502 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
503
504 return &data->iommu;
505 }
506
mtk_iommu_v1_probe_finalize(struct device * dev)507 static void mtk_iommu_v1_probe_finalize(struct device *dev)
508 {
509 struct dma_iommu_mapping *mtk_mapping;
510 struct mtk_iommu_v1_data *data;
511 int err;
512
513 data = dev_iommu_priv_get(dev);
514 mtk_mapping = data->mapping;
515
516 err = arm_iommu_attach_device(dev, mtk_mapping);
517 if (err)
518 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
519 }
520
mtk_iommu_v1_release_device(struct device * dev)521 static void mtk_iommu_v1_release_device(struct device *dev)
522 {
523 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
524 struct mtk_iommu_v1_data *data;
525 struct device *larbdev;
526 unsigned int larbid;
527
528 data = dev_iommu_priv_get(dev);
529 larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
530 larbdev = data->larb_imu[larbid].dev;
531 device_link_remove(dev, larbdev);
532 }
533
mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data * data)534 static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data)
535 {
536 u32 regval;
537 int ret;
538
539 ret = clk_prepare_enable(data->bclk);
540 if (ret) {
541 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
542 return ret;
543 }
544
545 regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
546 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
547
548 regval = F_INT_TRANSLATION_FAULT |
549 F_INT_MAIN_MULTI_HIT_FAULT |
550 F_INT_INVALID_PA_FAULT |
551 F_INT_ENTRY_REPLACEMENT_FAULT |
552 F_INT_TABLE_WALK_FAULT |
553 F_INT_TLB_MISS_FAULT |
554 F_INT_PFH_DMA_FIFO_OVERFLOW |
555 F_INT_MISS_DMA_FIFO_OVERFLOW;
556 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
557
558 /* protect memory,hw will write here while translation fault */
559 writel_relaxed(data->protect_base,
560 data->base + REG_MMU_IVRP_PADDR);
561
562 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
563
564 if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0,
565 dev_name(data->dev), (void *)data)) {
566 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
567 clk_disable_unprepare(data->bclk);
568 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
569 return -ENODEV;
570 }
571
572 return 0;
573 }
574
575 static const struct iommu_ops mtk_iommu_v1_ops = {
576 .identity_domain = &mtk_iommu_v1_identity_domain,
577 .domain_alloc_paging = mtk_iommu_v1_domain_alloc_paging,
578 .probe_device = mtk_iommu_v1_probe_device,
579 .probe_finalize = mtk_iommu_v1_probe_finalize,
580 .release_device = mtk_iommu_v1_release_device,
581 .device_group = generic_device_group,
582 .pgsize_bitmap = MT2701_IOMMU_PAGE_SIZE,
583 .owner = THIS_MODULE,
584 .default_domain_ops = &(const struct iommu_domain_ops) {
585 .attach_dev = mtk_iommu_v1_attach_device,
586 .map_pages = mtk_iommu_v1_map,
587 .unmap_pages = mtk_iommu_v1_unmap,
588 .iova_to_phys = mtk_iommu_v1_iova_to_phys,
589 .free = mtk_iommu_v1_domain_free,
590 }
591 };
592
593 static const struct of_device_id mtk_iommu_v1_of_ids[] = {
594 { .compatible = "mediatek,mt2701-m4u", },
595 {}
596 };
597 MODULE_DEVICE_TABLE(of, mtk_iommu_v1_of_ids);
598
599 static const struct component_master_ops mtk_iommu_v1_com_ops = {
600 .bind = mtk_iommu_v1_bind,
601 .unbind = mtk_iommu_v1_unbind,
602 };
603
mtk_iommu_v1_probe(struct platform_device * pdev)604 static int mtk_iommu_v1_probe(struct platform_device *pdev)
605 {
606 struct device *dev = &pdev->dev;
607 struct mtk_iommu_v1_data *data;
608 struct resource *res;
609 struct component_match *match = NULL;
610 void *protect;
611 int larb_nr, ret, i;
612
613 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
614 if (!data)
615 return -ENOMEM;
616
617 data->dev = dev;
618
619 /* Protect memory. HW will access here while translation fault.*/
620 protect = devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN,
621 GFP_KERNEL | GFP_DMA);
622 if (!protect)
623 return -ENOMEM;
624 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
625
626 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
627 data->base = devm_ioremap_resource(dev, res);
628 if (IS_ERR(data->base))
629 return PTR_ERR(data->base);
630
631 data->irq = platform_get_irq(pdev, 0);
632 if (data->irq < 0)
633 return data->irq;
634
635 data->bclk = devm_clk_get(dev, "bclk");
636 if (IS_ERR(data->bclk))
637 return PTR_ERR(data->bclk);
638
639 larb_nr = of_count_phandle_with_args(dev->of_node,
640 "mediatek,larbs", NULL);
641 if (larb_nr < 0)
642 return larb_nr;
643
644 for (i = 0; i < larb_nr; i++) {
645 struct device_node *larbnode;
646 struct platform_device *plarbdev;
647
648 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
649 if (!larbnode)
650 return -EINVAL;
651
652 if (!of_device_is_available(larbnode)) {
653 of_node_put(larbnode);
654 continue;
655 }
656
657 plarbdev = of_find_device_by_node(larbnode);
658 if (!plarbdev) {
659 of_node_put(larbnode);
660 return -ENODEV;
661 }
662 if (!plarbdev->dev.driver) {
663 of_node_put(larbnode);
664 return -EPROBE_DEFER;
665 }
666 data->larb_imu[i].dev = &plarbdev->dev;
667
668 component_match_add_release(dev, &match, component_release_of,
669 component_compare_of, larbnode);
670 }
671
672 platform_set_drvdata(pdev, data);
673
674 ret = mtk_iommu_v1_hw_init(data);
675 if (ret)
676 return ret;
677
678 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
679 dev_name(&pdev->dev));
680 if (ret)
681 goto out_clk_unprepare;
682
683 ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev);
684 if (ret)
685 goto out_sysfs_remove;
686
687 ret = component_master_add_with_match(dev, &mtk_iommu_v1_com_ops, match);
688 if (ret)
689 goto out_dev_unreg;
690 return ret;
691
692 out_dev_unreg:
693 iommu_device_unregister(&data->iommu);
694 out_sysfs_remove:
695 iommu_device_sysfs_remove(&data->iommu);
696 out_clk_unprepare:
697 clk_disable_unprepare(data->bclk);
698 return ret;
699 }
700
mtk_iommu_v1_remove(struct platform_device * pdev)701 static void mtk_iommu_v1_remove(struct platform_device *pdev)
702 {
703 struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev);
704
705 iommu_device_sysfs_remove(&data->iommu);
706 iommu_device_unregister(&data->iommu);
707
708 clk_disable_unprepare(data->bclk);
709 devm_free_irq(&pdev->dev, data->irq, data);
710 component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops);
711 }
712
mtk_iommu_v1_suspend(struct device * dev)713 static int __maybe_unused mtk_iommu_v1_suspend(struct device *dev)
714 {
715 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
716 struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
717 void __iomem *base = data->base;
718
719 reg->standard_axi_mode = readl_relaxed(base +
720 REG_MMU_STANDARD_AXI_MODE);
721 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
722 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
723 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
724 return 0;
725 }
726
mtk_iommu_v1_resume(struct device * dev)727 static int __maybe_unused mtk_iommu_v1_resume(struct device *dev)
728 {
729 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
730 struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
731 void __iomem *base = data->base;
732
733 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
734 writel_relaxed(reg->standard_axi_mode,
735 base + REG_MMU_STANDARD_AXI_MODE);
736 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
737 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
738 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
739 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
740 return 0;
741 }
742
743 static const struct dev_pm_ops mtk_iommu_v1_pm_ops = {
744 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_v1_suspend, mtk_iommu_v1_resume)
745 };
746
747 static struct platform_driver mtk_iommu_v1_driver = {
748 .probe = mtk_iommu_v1_probe,
749 .remove = mtk_iommu_v1_remove,
750 .driver = {
751 .name = "mtk-iommu-v1",
752 .of_match_table = mtk_iommu_v1_of_ids,
753 .pm = &mtk_iommu_v1_pm_ops,
754 }
755 };
756 module_platform_driver(mtk_iommu_v1_driver);
757
758 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations");
759 MODULE_LICENSE("GPL v2");
760