1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2016 Nexenta Systems, Inc.
24 * Copyright (c) 2017 by Delphix. All rights reserved.
25 * Copyright 2020 Joyent, Inc.
26 * Copyright 2020 RackTop Systems, Inc.
27 * Copyright 2020 Oxide Computer Company
28 */
29 /*
30 * Copyright (c) 2010, Intel Corporation.
31 * All rights reserved.
32 */
33
34 /*
35 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
36 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
37 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
38 * PSMI 1.5 extensions are supported in Solaris Nevada.
39 * PSMI 1.6 extensions are supported in Solaris Nevada.
40 * PSMI 1.7 extensions are supported in Solaris Nevada.
41 */
42 #define PSMI_1_7
43
44 #include <sys/processor.h>
45 #include <sys/time.h>
46 #include <sys/psm.h>
47 #include <sys/smp_impldefs.h>
48 #include <sys/cram.h>
49 #include <sys/acpi/acpi.h>
50 #include <sys/acpica.h>
51 #include <sys/psm_common.h>
52 #include <sys/apic.h>
53 #include <sys/apic_timer.h>
54 #include <sys/pit.h>
55 #include <sys/ddi.h>
56 #include <sys/sunddi.h>
57 #include <sys/ddi_impldefs.h>
58 #include <sys/pci.h>
59 #include <sys/promif.h>
60 #include <sys/x86_archext.h>
61 #include <sys/cpc_impl.h>
62 #include <sys/uadmin.h>
63 #include <sys/panic.h>
64 #include <sys/debug.h>
65 #include <sys/archsystm.h>
66 #include <sys/trap.h>
67 #include <sys/machsystm.h>
68 #include <sys/cpuvar.h>
69 #include <sys/rm_platter.h>
70 #include <sys/privregs.h>
71 #include <sys/cyclic.h>
72 #include <sys/note.h>
73 #include <sys/pci_intr_lib.h>
74 #include <sys/sunndi.h>
75 #include <sys/prom_debug.h>
76 #if !defined(__xpv)
77 #include <sys/hpet.h>
78 #include <sys/clock.h>
79 #endif
80
81 /*
82 * Local Function Prototypes
83 */
84 static int apic_handle_defconf(void);
85 static int apic_parse_mpct(caddr_t mpct, int bypass);
86 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
87 static int apic_checksum(caddr_t bptr, int len);
88 static int apic_find_bus_type(char *bus);
89 static int apic_find_bus(int busid);
90 static struct apic_io_intr *apic_find_io_intr(int irqno);
91 static int apic_find_free_irq(int start, int end);
92 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
93 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
94 static void apic_free_apic_cpus(void);
95 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
96 static int apic_acpi_enter_apicmode(void);
97
98 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
99 int child_ipin, struct apic_io_intr **intrp);
100 int apic_find_bus_id(int bustype);
101 int apic_find_intin(uchar_t ioapic, uchar_t intin);
102 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
103
104 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
105
106 /* ACPI SCI interrupt configuration; -1 if SCI not used */
107 int apic_sci_vect = -1;
108 iflag_t apic_sci_flags;
109
110 #if !defined(__xpv)
111 /* ACPI HPET interrupt configuration; -1 if HPET not used */
112 int apic_hpet_vect = -1;
113 iflag_t apic_hpet_flags;
114 #endif
115
116 /*
117 * psm name pointer
118 */
119 char *psm_name;
120
121 /* ACPI support routines */
122 static int acpi_probe(char *);
123 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
124 int *pci_irqp, iflag_t *intr_flagp);
125
126 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
127 int ipin, int *pci_irqp, iflag_t *intr_flagp);
128 uchar_t acpi_find_ioapic(int irq);
129 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
130
131 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */
132 int apic_max_reps_clear_pending = 1000;
133
134 int apic_intr_policy = INTR_ROUND_ROBIN;
135
136 int apic_next_bind_cpu = 1; /* For round robin assignment */
137 /* start with cpu 1 */
138
139 /*
140 * If enabled, the distribution works as follows:
141 * On every interrupt entry, the current ipl for the CPU is set in cpu_info
142 * and the irq corresponding to the ipl is also set in the aci_current array.
143 * interrupt exit and setspl (due to soft interrupts) will cause the current
144 * ipl to be be changed. This is cache friendly as these frequently used
145 * paths write into a per cpu structure.
146 *
147 * Sampling is done by checking the structures for all CPUs and incrementing
148 * the busy field of the irq (if any) executing on each CPU and the busy field
149 * of the corresponding CPU.
150 * In periodic mode this is done on every clock interrupt.
151 * In one-shot mode, this is done thru a cyclic with an interval of
152 * apic_redistribute_sample_interval (default 10 milli sec).
153 *
154 * Every apic_sample_factor_redistribution times we sample, we do computations
155 * to decide which interrupt needs to be migrated (see comments
156 * before apic_intr_redistribute().
157 */
158
159 /*
160 * Following 3 variables start as % and can be patched or set using an
161 * API to be defined in future. They will be scaled to
162 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
163 * mode), or 101 in one-shot mode to stagger it away from one sec processing
164 */
165
166 int apic_int_busy_mark = 60;
167 int apic_int_free_mark = 20;
168 int apic_diff_for_redistribution = 10;
169
170 /* sampling interval for interrupt redistribution for dynamic migration */
171 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
172
173 /*
174 * number of times we sample before deciding to redistribute interrupts
175 * for dynamic migration
176 */
177 int apic_sample_factor_redistribution = 101;
178
179 int apic_redist_cpu_skip = 0;
180 int apic_num_imbalance = 0;
181 int apic_num_rebind = 0;
182
183 /*
184 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
185 * allocation of CPU ids is disabled.
186 */
187 int apic_max_nproc = -1;
188 int apic_nproc = 0;
189 size_t apic_cpus_size = 0;
190 int apic_defconf = 0;
191 int apic_irq_translate = 0;
192 int apic_spec_rev = 0;
193 int apic_imcrp = 0;
194
195 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */
196 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
197
198 /*
199 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
200 * will be assigned (via _SRS). If it is not set, use the current
201 * irq setting (via _CRS), but only if that irq is in the set of possible
202 * irqs (returned by _PRS) for the device.
203 */
204 int apic_unconditional_srs = 1;
205
206 /*
207 * For interrupt link devices, if apic_prefer_crs is set when we are
208 * assigning an IRQ resource to a device, prefer the current IRQ setting
209 * over other possible irq settings under same conditions.
210 */
211
212 int apic_prefer_crs = 1;
213
214 uchar_t apic_io_id[MAX_IO_APIC];
215 volatile uint32_t *apicioadr[MAX_IO_APIC];
216 uchar_t apic_io_ver[MAX_IO_APIC];
217 uchar_t apic_io_vectbase[MAX_IO_APIC];
218 uchar_t apic_io_vectend[MAX_IO_APIC];
219 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
220 uint32_t apic_physaddr[MAX_IO_APIC];
221
222 boolean_t ioapic_mask_workaround[MAX_IO_APIC];
223
224 /*
225 * First available slot to be used as IRQ index into the apic_irq_table
226 * for those interrupts (like MSI/X) that don't have a physical IRQ.
227 */
228 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ;
229
230 /*
231 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
232 * and bound elements of cpus_info and the temp_cpu element of irq_struct
233 */
234 lock_t apic_ioapic_lock;
235
236 int apic_io_max = 0; /* no. of i/o apics enabled */
237
238 struct apic_io_intr *apic_io_intrp = NULL;
239 static struct apic_bus *apic_busp;
240
241 uchar_t apic_resv_vector[MAXIPL+1];
242
243 char apic_level_intr[APIC_MAX_VECTOR+1];
244
245 uint32_t eisa_level_intr_mask = 0;
246 /* At least MSB will be set if EISA bus */
247
248 int apic_pci_bus_total = 0;
249 uchar_t apic_single_pci_busid = 0;
250
251 /*
252 * airq_mutex protects additions to the apic_irq_table - the first
253 * pointer and any airq_nexts off of that one. It also protects
254 * apic_max_device_irq & apic_min_device_irq. It also guarantees
255 * that share_id is unique as new ids are generated only when new
256 * irq_t structs are linked in. Once linked in the structs are never
257 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
258 * or allocated. Note that there is a slight gap between allocating in
259 * apic_introp_xlate and programming in addspl.
260 */
261 kmutex_t airq_mutex;
262 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
263 int apic_max_device_irq = 0;
264 int apic_min_device_irq = APIC_MAX_VECTOR;
265
266 typedef struct prs_irq_list_ent {
267 int list_prio;
268 int32_t irq;
269 iflag_t intrflags;
270 acpi_prs_private_t prsprv;
271 struct prs_irq_list_ent *next;
272 } prs_irq_list_t;
273
274
275 /*
276 * ACPI variables
277 */
278 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
279 int apic_enable_acpi = 0;
280
281 /* ACPI Multiple APIC Description Table ptr */
282 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
283
284 /* ACPI Interrupt Source Override Structure ptr */
285 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
286 int acpi_iso_cnt = 0;
287
288 /* ACPI Non-maskable Interrupt Sources ptr */
289 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
290 static int acpi_nmi_scnt = 0;
291 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
292 static int acpi_nmi_ccnt = 0;
293
294 static boolean_t acpi_found_smp_config = B_FALSE;
295
296 /*
297 * The following added to identify a software poweroff method if available.
298 */
299
300 static struct {
301 int poweroff_method;
302 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */
303 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */
304 } apic_mps_ids[] = {
305 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */
306 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */
307 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */
308 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */
309 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */
310 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */
311 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */
312 };
313
314 int apic_poweroff_method = APIC_POWEROFF_NONE;
315
316 /*
317 * Auto-configuration routines
318 */
319
320 /*
321 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
322 * May work with 1.1 - but not guaranteed.
323 * According to the MP Spec, the MP floating pointer structure
324 * will be searched in the order described below:
325 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
326 * 2. Within the last kilobyte of system base memory
327 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
328 * Once we find the right signature with proper checksum, we call
329 * either handle_defconf or parse_mpct to get all info necessary for
330 * subsequent operations.
331 */
332 int
apic_probe_common(char * modname)333 apic_probe_common(char *modname)
334 {
335 uint32_t mpct_addr, ebda_start = 0, base_mem_end;
336 caddr_t biosdatap;
337 caddr_t mpct = NULL;
338 caddr_t fptr = NULL;
339 int i, mpct_size = 0, mapsize, retval = PSM_FAILURE;
340 ushort_t ebda_seg, base_mem_size;
341 struct apic_mpfps_hdr *fpsp;
342 struct apic_mp_cnf_hdr *hdrp;
343 int bypass_cpu_and_ioapics_in_mptables;
344 int acpi_user_options;
345
346 PRM_POINT("apic_probe_common()");
347
348 if (apic_forceload < 0)
349 return (retval);
350
351 /*
352 * Remember who we are
353 */
354 psm_name = modname;
355
356 /* Allow override for MADT-only mode */
357 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
358 "acpi-user-options", 0);
359 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
360
361 /* Allow apic_use_acpi to override MADT-only mode */
362 if (!apic_use_acpi)
363 apic_use_acpi_madt_only = 0;
364
365 PRM_POINT("acpi_probe()");
366 retval = acpi_probe(modname);
367 PRM_DEBUG(retval);
368
369 /* in UEFI system, there is no BIOS data */
370 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 0, "efi-systab")) {
371 PRM_POINT("UEFI system!");
372 goto apic_ret;
373 }
374
375 /*
376 * mapin the bios data area 40:0
377 * 40:13h - two-byte location reports the base memory size
378 * 40:0Eh - two-byte location for the exact starting address of
379 * the EBDA segment for EISA
380 */
381 PRM_POINT("psm_map_phys()");
382 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
383 PRM_DEBUG(biosdatap);
384 if (!biosdatap)
385 goto apic_ret;
386 fpsp = (struct apic_mpfps_hdr *)NULL;
387 mapsize = MPFPS_RAM_WIN_LEN;
388 /*LINTED: pointer cast may result in improper alignment */
389 ebda_seg = *((ushort_t *)(biosdatap+0xe));
390 PRM_DEBUG(ebda_seg);
391 /* check the 1k of EBDA */
392 if (ebda_seg) {
393 ebda_start = ((uint32_t)ebda_seg) << 4;
394 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
395 PRM_DEBUG(fptr);
396 if (fptr) {
397 if (!(fpsp =
398 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
399 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
400 }
401 }
402 /* If not in EBDA, check the last k of system base memory */
403 PRM_DEBUG(fpsp);
404 if (!fpsp) {
405 /*LINTED: pointer cast may result in improper alignment */
406 base_mem_size = *((ushort_t *)(biosdatap + 0x13));
407
408 if (base_mem_size > 512)
409 base_mem_end = 639 * 1024;
410 else
411 base_mem_end = 511 * 1024;
412 /* if ebda == last k of base mem, skip to check BIOS ROM */
413 if (base_mem_end != ebda_start) {
414
415 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
416 PROT_READ);
417 PRM_DEBUG(fptr);
418
419 if (fptr) {
420 if (!(fpsp = apic_find_fps_sig(fptr,
421 MPFPS_RAM_WIN_LEN)))
422 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
423 }
424 }
425 }
426 PRM_POINT("psm_unmap_phys()");
427 psm_unmap_phys(biosdatap, 0x20);
428
429 /* If still cannot find it, check the BIOS ROM space */
430 PRM_DEBUG(fpsp);
431 if (!fpsp) {
432 mapsize = MPFPS_ROM_WIN_LEN;
433 fptr = psm_map_phys(MPFPS_ROM_WIN_START,
434 MPFPS_ROM_WIN_LEN, PROT_READ);
435 PRM_DEBUG(fptr);
436 if (fptr) {
437 if (!(fpsp =
438 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
439 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
440 goto apic_ret;
441 }
442 }
443 }
444
445 PRM_DEBUG(fptr);
446 PRM_DEBUG(fpsp);
447 PRM_POINT("apic_checksum()");
448 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
449 PRM_POINT("psm_unmap_phys()");
450 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
451 goto apic_ret;
452 }
453
454 apic_spec_rev = fpsp->mpfps_spec_rev;
455 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
456 PRM_POINT("psm_unmap_phys()");
457 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
458 goto apic_ret;
459 }
460
461 /* check IMCR is present or not */
462 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
463
464 /* check default configuration (dual CPUs) */
465 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
466 PRM_POINT("psm_unmap_phys()");
467 psm_unmap_phys(fptr, mapsize);
468 PRM_POINT("apic_handle_defconf()");
469 if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
470 return (retval);
471
472 goto apic_ret;
473 }
474
475 /* MP Configuration Table */
476 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
477 PRM_DEBUG(mpct_addr);
478
479 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
480
481 /*
482 * Map in enough memory for the MP Configuration Table Header.
483 * Use this table to read the total length of the BIOS data and
484 * map in all the info
485 */
486 /*LINTED: pointer cast may result in improper alignment */
487 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
488 sizeof (struct apic_mp_cnf_hdr), PROT_READ);
489 if (!hdrp)
490 goto apic_ret;
491
492 /* check mp configuration table signature PCMP */
493 if (hdrp->mpcnf_sig != 0x504d4350) {
494 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
495 goto apic_ret;
496 }
497 mpct_size = (int)hdrp->mpcnf_tbl_length;
498
499 PRM_POINT("apic_set_pwroff_method_from_mpcnfhdr()");
500 apic_set_pwroff_method_from_mpcnfhdr(hdrp);
501
502 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
503
504 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
505 /* This is an ACPI machine No need for further checks */
506 goto apic_ret;
507 }
508
509 /*
510 * Map in the entries for this machine, ie. Processor
511 * Entry Tables, Bus Entry Tables, etc.
512 * They are in fixed order following one another
513 */
514 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
515 if (!mpct)
516 goto apic_ret;
517
518 if (apic_checksum(mpct, mpct_size) != 0)
519 goto apic_fail1;
520
521 /*LINTED: pointer cast may result in improper alignment */
522 hdrp = (struct apic_mp_cnf_hdr *)mpct;
523 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
524 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
525 PRM_DEBUG(hdrp);
526 PRM_DEBUG(apicadr);
527 if (!apicadr)
528 goto apic_fail1;
529
530 /* Parse all information in the tables */
531 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
532 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
533 PSM_SUCCESS) {
534 retval = PSM_SUCCESS;
535 goto apic_ret;
536 }
537
538 apic_fail1:
539 PRM_POINT("apic_fail1:");
540 psm_unmap_phys(mpct, mpct_size);
541 mpct = NULL;
542
543 apic_ret:
544 PRM_POINT("apic_ret:");
545 if (retval == PSM_SUCCESS) {
546 extern int apic_ioapic_method_probe();
547
548 PRM_POINT("apic_ioapic_method_probe()");
549 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS) {
550 PRM_POINT("SUCCESS");
551 return (PSM_SUCCESS);
552 }
553 }
554
555 for (i = 0; i < apic_io_max; i++)
556 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
557 if (apic_cpus) {
558 kmem_free(apic_cpus, apic_cpus_size);
559 apic_cpus = NULL;
560 }
561 if (apicadr) {
562 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
563 apicadr = NULL;
564 }
565 if (mpct)
566 psm_unmap_phys(mpct, mpct_size);
567
568 PRM_DEBUG(retval);
569 return (retval);
570 }
571
572 static void
apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr * hdrp)573 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
574 {
575 int i;
576
577 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
578 i++) {
579 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
580 strlen(apic_mps_ids[i].oem_id)) == 0) &&
581 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
582 strlen(apic_mps_ids[i].prod_id)) == 0)) {
583
584 apic_poweroff_method = apic_mps_ids[i].poweroff_method;
585 break;
586 }
587 }
588
589 if (apic_debug_mps_id != 0) {
590 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
591 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
592 psm_name,
593 hdrp->mpcnf_oem_str[0],
594 hdrp->mpcnf_oem_str[1],
595 hdrp->mpcnf_oem_str[2],
596 hdrp->mpcnf_oem_str[3],
597 hdrp->mpcnf_oem_str[4],
598 hdrp->mpcnf_oem_str[5],
599 hdrp->mpcnf_oem_str[6],
600 hdrp->mpcnf_oem_str[7],
601 hdrp->mpcnf_prod_str[0],
602 hdrp->mpcnf_prod_str[1],
603 hdrp->mpcnf_prod_str[2],
604 hdrp->mpcnf_prod_str[3],
605 hdrp->mpcnf_prod_str[4],
606 hdrp->mpcnf_prod_str[5],
607 hdrp->mpcnf_prod_str[6],
608 hdrp->mpcnf_prod_str[7],
609 hdrp->mpcnf_prod_str[8],
610 hdrp->mpcnf_prod_str[9],
611 hdrp->mpcnf_prod_str[10],
612 hdrp->mpcnf_prod_str[11]);
613 }
614 }
615
616 static void
apic_free_apic_cpus(void)617 apic_free_apic_cpus(void)
618 {
619 if (apic_cpus != NULL) {
620 kmem_free(apic_cpus, apic_cpus_size);
621 apic_cpus = NULL;
622 apic_cpus_size = 0;
623 }
624 }
625
626 static uint32_t
acpi_get_apic_lid(void)627 acpi_get_apic_lid(void)
628 {
629 uint32_t id;
630
631 id = apic_reg_ops->apic_read(APIC_LID_REG);
632 if (apic_mode != LOCAL_X2APIC)
633 id >>= APIC_ID_BIT_OFFSET;
634
635 return (id);
636 }
637
638 static int
acpi_probe(char * modname)639 acpi_probe(char *modname)
640 {
641 int i, intmax;
642 uint32_t id, ver;
643 int acpi_verboseflags = 0;
644 int madt_seen, madt_size;
645 ACPI_SUBTABLE_HEADER *ap;
646 ACPI_MADT_LOCAL_APIC *mpa;
647 ACPI_MADT_LOCAL_X2APIC *mpx2a;
648 ACPI_MADT_IO_APIC *mia;
649 ACPI_MADT_IO_SAPIC *misa;
650 ACPI_MADT_INTERRUPT_OVERRIDE *mio;
651 ACPI_MADT_NMI_SOURCE *mns;
652 ACPI_MADT_INTERRUPT_SOURCE *mis;
653 ACPI_MADT_LOCAL_APIC_NMI *mlan;
654 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan;
655 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao;
656 int sci;
657 iflag_t sci_flags;
658 volatile uint32_t *ioapic;
659 int ioapic_ix;
660 uint32_t *local_ids;
661 uint32_t *proc_ids;
662 uchar_t hid;
663 int warned = 0;
664
665 if (!apic_use_acpi)
666 return (PSM_FAILURE);
667
668 PRM_POINT("AcpiGetTable(MADT)");
669 if (AcpiGetTable(ACPI_SIG_MADT, 1,
670 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) {
671 cmn_err(CE_WARN, "!acpi_probe: No MADT found!");
672 return (PSM_FAILURE);
673 }
674
675 PRM_DEBUG((uint32_t)acpi_mapic_dtp->Address);
676 PRM_POINT("mapin_apic()");
677 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
678 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
679 if (!apicadr)
680 return (PSM_FAILURE);
681
682 if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
683 KM_NOSLEEP)) == NULL) {
684 return (PSM_FAILURE);
685 }
686
687 if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
688 KM_NOSLEEP)) == NULL) {
689 kmem_free(local_ids, NCPU * sizeof (uint32_t));
690 return (PSM_FAILURE);
691 }
692
693 PRM_POINT("acpi_get_apic_lid()");
694 local_ids[0] = acpi_get_apic_lid();
695 PRM_DEBUG(local_ids[0]);
696
697 apic_nproc = 1;
698 apic_io_max = 0;
699
700 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
701 madt_size = acpi_mapic_dtp->Header.Length;
702 madt_seen = sizeof (*acpi_mapic_dtp);
703
704 PRM_DEBUG(madt_size);
705 while (madt_seen < madt_size) {
706 switch (ap->Type) {
707 case ACPI_MADT_TYPE_LOCAL_APIC:
708 mpa = (ACPI_MADT_LOCAL_APIC *) ap;
709 if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
710 if (mpa->Id == 255) {
711 cmn_err(CE_WARN, "!%s: encountered "
712 "invalid entry in MADT: CPU %d "
713 "has Local APIC Id equal to 255",
714 psm_name, mpa->ProcessorId);
715 }
716 if (mpa->Id == local_ids[0]) {
717 proc_ids[0] = mpa->ProcessorId;
718 } else if (apic_nproc < NCPU && use_mp &&
719 apic_nproc < boot_ncpus) {
720 local_ids[apic_nproc] = mpa->Id;
721 proc_ids[apic_nproc] = mpa->ProcessorId;
722 apic_nproc++;
723 } else if (apic_nproc == NCPU && !warned) {
724 cmn_err(CE_WARN, "%s: CPU limit "
725 "exceeded; will use %d CPUs.",
726 psm_name, NCPU);
727 warned = 1;
728 }
729 }
730 break;
731
732 case ACPI_MADT_TYPE_IO_APIC:
733 mia = (ACPI_MADT_IO_APIC *) ap;
734 if (apic_io_max < MAX_IO_APIC) {
735 ioapic_ix = apic_io_max;
736 apic_io_id[apic_io_max] = mia->Id;
737 apic_io_vectbase[apic_io_max] =
738 mia->GlobalIrqBase;
739 apic_physaddr[apic_io_max] =
740 (uint32_t)mia->Address;
741 ioapic = apicioadr[apic_io_max] =
742 mapin_ioapic((uint32_t)mia->Address,
743 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
744 if (!ioapic)
745 goto cleanup;
746 ioapic_mask_workaround[apic_io_max] =
747 apic_is_ioapic_AMD_813x(mia->Address);
748 apic_io_max++;
749 }
750 break;
751
752 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
753 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
754 if (acpi_isop == NULL)
755 acpi_isop = mio;
756 acpi_iso_cnt++;
757 break;
758
759 case ACPI_MADT_TYPE_NMI_SOURCE:
760 /* UNIMPLEMENTED */
761 mns = (ACPI_MADT_NMI_SOURCE *) ap;
762 if (acpi_nmi_sp == NULL)
763 acpi_nmi_sp = mns;
764 acpi_nmi_scnt++;
765
766 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x",
767 mns->GlobalIrq, mns->IntiFlags);
768 break;
769
770 case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
771 /* UNIMPLEMENTED */
772 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
773 if (acpi_nmi_cp == NULL)
774 acpi_nmi_cp = mlan;
775 acpi_nmi_ccnt++;
776
777 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d",
778 mlan->ProcessorId, mlan->IntiFlags,
779 mlan->Lint);
780 break;
781
782 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
783 /* UNIMPLEMENTED */
784 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
785 cmn_err(CE_NOTE, "!apic: address override: %lx",
786 (long)mao->Address);
787 break;
788
789 case ACPI_MADT_TYPE_IO_SAPIC:
790 /* UNIMPLEMENTED */
791 misa = (ACPI_MADT_IO_SAPIC *) ap;
792
793 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx",
794 misa->Id, misa->GlobalIrqBase,
795 (long)misa->Address);
796 break;
797
798 case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
799 /* UNIMPLEMENTED */
800 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
801
802 cmn_err(CE_NOTE,
803 "!apic: irq source: %d %d %d 0x%x %d %d",
804 mis->Id, mis->Eid, mis->GlobalIrq,
805 mis->IntiFlags, mis->Type,
806 mis->IoSapicVector);
807 break;
808
809 case ACPI_MADT_TYPE_LOCAL_X2APIC:
810 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
811
812 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
813 if (mpx2a->LocalApicId == local_ids[0]) {
814 proc_ids[0] = mpx2a->Uid;
815 } else if (apic_nproc < NCPU && use_mp &&
816 apic_nproc < boot_ncpus) {
817 local_ids[apic_nproc] =
818 mpx2a->LocalApicId;
819 proc_ids[apic_nproc] = mpx2a->Uid;
820 apic_nproc++;
821 } else if (apic_nproc == NCPU && !warned) {
822 cmn_err(CE_WARN, "%s: CPU limit "
823 "exceeded; will use %d CPUs.",
824 psm_name, NCPU);
825 warned = 1;
826 }
827 }
828
829 break;
830
831 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
832 /* UNIMPLEMENTED */
833 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
834 if (mx2alan->Uid >> 8)
835 acpi_nmi_ccnt++;
836
837 #ifdef DEBUG
838 cmn_err(CE_NOTE,
839 "!apic: local x2apic nmi: %d 0x%x %d",
840 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
841 #endif
842
843 break;
844
845 case ACPI_MADT_TYPE_RESERVED:
846 default:
847 break;
848 }
849
850 /* advance to next entry */
851 madt_seen += ap->Length;
852 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
853 }
854
855 PRM_DEBUG(apic_nproc);
856 PRM_DEBUG(apic_io_max);
857
858 /* We found multiple enabled cpus via MADT */
859 if ((apic_nproc > 1) && (apic_io_max > 0)) {
860 acpi_found_smp_config = B_TRUE;
861 cmn_err(CE_NOTE,
862 "!apic: Using ACPI (MADT) for SMP configuration");
863 }
864
865 /*
866 * allocate enough space for possible hot-adding of CPUs.
867 * max_ncpus may be less than apic_nproc if it's set by user.
868 */
869 if (plat_dr_support_cpu()) {
870 apic_max_nproc = max_ncpus;
871 }
872 PRM_DEBUG(apic_max_nproc);
873 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
874 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
875 goto cleanup;
876
877 /*
878 * ACPI doesn't provide the local apic ver, get it directly from the
879 * local apic
880 */
881 PRM_POINT("apic_read(APIC_VERS_REG)");
882 ver = apic_reg_ops->apic_read(APIC_VERS_REG);
883 PRM_DEBUG(ver);
884 PRM_DEBUG(apic_nproc);
885 PRM_DEBUG(boot_ncpus);
886 for (i = 0; i < apic_nproc; i++) {
887 apic_cpus[i].aci_local_id = local_ids[i];
888 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
889 apic_cpus[i].aci_processor_id = proc_ids[i];
890 /* Only build mapping info for CPUs present at boot. */
891 if (i < boot_ncpus) {
892 (void) acpica_map_cpu(i, proc_ids[i]);
893 }
894 }
895 PRM_POINT("acpica_map_cpu loop complete");
896
897 /*
898 * To support CPU dynamic reconfiguration, the apic CPU info structure
899 * for each possible CPU will be pre-allocated at boot time.
900 * The state for each apic CPU info structure will be assigned according
901 * to the following rules:
902 * Rule 1:
903 * Slot index range: [0, min(apic_nproc, boot_ncpus))
904 * State flags: 0
905 * Note: cpu exists and will be configured/enabled at boot time
906 * Rule 2:
907 * Slot index range: [boot_ncpus, apic_nproc)
908 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
909 * Note: cpu exists but won't be configured/enabled at boot time
910 * Rule 3:
911 * Slot index range: [apic_nproc, boot_ncpus)
912 * State flags: APIC_CPU_FREE
913 * Note: cpu doesn't exist at boot time
914 * Rule 4:
915 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
916 * State flags: APIC_CPU_FREE
917 * Note: cpu doesn't exist at boot time
918 */
919 CPUSET_ZERO(apic_cpumask);
920 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
921 CPUSET_ADD(apic_cpumask, i);
922 apic_cpus[i].aci_status = 0;
923 }
924 for (i = boot_ncpus; i < apic_nproc; i++) {
925 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
926 }
927 for (i = apic_nproc; i < boot_ncpus; i++) {
928 apic_cpus[i].aci_status = APIC_CPU_FREE;
929 }
930 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
931 apic_cpus[i].aci_status = APIC_CPU_FREE;
932 }
933
934 PRM_POINT("ioapic reads");
935 for (i = 0; i < apic_io_max; i++) {
936 ioapic_ix = i;
937 PRM_DEBUG(ioapic_ix);
938
939 /*
940 * need to check Sitka on the following acpi problem
941 * On the Sitka, the ioapic's apic_id field isn't reporting
942 * the actual io apic id. We have reported this problem
943 * to Intel. Until they fix the problem, we will get the
944 * actual id directly from the ioapic.
945 */
946 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
947 PRM_DEBUG(id);
948 hid = (uchar_t)(id >> 24);
949 PRM_DEBUG(hid);
950
951 if (hid != apic_io_id[i]) {
952 if (apic_io_id[i] == 0)
953 apic_io_id[i] = hid;
954 else { /* set ioapic id to whatever reported by ACPI */
955 id = ((uint32_t)apic_io_id[i]) << 24;
956 PRM_POINT("ioapic_write(ID)");
957 ioapic_write(ioapic_ix, APIC_ID_CMD, id);
958 }
959 }
960 PRM_POINT("ioapic_read(VERS)");
961 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
962 apic_io_ver[i] = (uchar_t)(ver & 0xff);
963 intmax = (ver >> 16) & 0xff;
964 apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
965 if (apic_first_avail_irq <= apic_io_vectend[i])
966 apic_first_avail_irq = apic_io_vectend[i] + 1;
967 }
968
969
970 /*
971 * Process SCI configuration here
972 * An error may be returned here if
973 * acpi-user-options specifies legacy mode
974 * (no SCI, no ACPI mode)
975 */
976 PRM_POINT("acpica_get_sci()");
977 if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
978 sci = -1;
979
980 /*
981 * Now call acpi_init() to generate namespaces
982 * If this fails, we don't attempt to use ACPI
983 * even if we were able to get a MADT above
984 */
985 PRM_POINT("acpica_init()");
986 if (acpica_init() != AE_OK) {
987 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!");
988 goto cleanup;
989 }
990
991 /*
992 * Call acpica_build_processor_map() now that we have
993 * ACPI namesspace access
994 */
995 PRM_POINT("acpica_build_processor_map()");
996 (void) acpica_build_processor_map();
997
998 /*
999 * Squirrel away the SCI and flags for later on
1000 * in apic_picinit() when we're ready
1001 */
1002 apic_sci_vect = sci;
1003 apic_sci_flags = sci_flags;
1004
1005 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
1006 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
1007
1008 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
1009 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
1010
1011 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
1012 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
1013
1014 PRM_POINT("acpi_psm_init()");
1015 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
1016 goto cleanup;
1017
1018 /* Enable ACPI APIC interrupt routing */
1019 PRM_POINT("apic_acpi_enter_apicmode()");
1020 if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
1021 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode");
1022 PRM_POINT("build_reserved_irqlist()");
1023 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
1024 apic_enable_acpi = 1;
1025 if (apic_sci_vect > 0) {
1026 PRM_POINT("acpica_set_core_feature()");
1027 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
1028 }
1029 if (apic_use_acpi_madt_only) {
1030 cmn_err(CE_CONT,
1031 "?Using ACPI for CPU/IOAPIC information ONLY\n");
1032 }
1033
1034 #if !defined(__xpv)
1035 /*
1036 * Probe ACPI for HPET information here which is used later in
1037 * apic_picinit(). Note that we do not need to use the HPET at
1038 * all on most modern systems, but if there is an actionable
1039 * failure message it will be logged by the routine itself.
1040 */
1041 PRM_POINT("hpet_acpi_init()");
1042 (void) hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags,
1043 apic_timer_stop_count, apic_timer_restart);
1044 #endif
1045
1046 kmem_free(local_ids, NCPU * sizeof (uint32_t));
1047 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1048 PRM_POINT("SUCCESS");
1049 return (PSM_SUCCESS);
1050 }
1051 /* if setting APIC mode failed above, we fall through to cleanup */
1052
1053 cleanup:
1054 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s",
1055 acpi_found_smp_config ? "found" : "not found");
1056 apic_free_apic_cpus();
1057 if (apicadr != NULL) {
1058 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1059 apicadr = NULL;
1060 }
1061 apic_max_nproc = -1;
1062 apic_nproc = 0;
1063 for (i = 0; i < apic_io_max; i++) {
1064 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
1065 apicioadr[i] = NULL;
1066 }
1067 apic_io_max = 0;
1068 acpi_isop = NULL;
1069 acpi_iso_cnt = 0;
1070 acpi_nmi_sp = NULL;
1071 acpi_nmi_scnt = 0;
1072 acpi_nmi_cp = NULL;
1073 acpi_nmi_ccnt = 0;
1074 acpi_found_smp_config = B_FALSE;
1075 kmem_free(local_ids, NCPU * sizeof (uint32_t));
1076 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1077 return (PSM_FAILURE);
1078 }
1079
1080 /*
1081 * Handle default configuration. Fill in reqd global variables & tables
1082 * Fill all details as MP table does not give any more info
1083 */
1084 static int
apic_handle_defconf(void)1085 apic_handle_defconf(void)
1086 {
1087 /* Failed to probe ACPI MADT tables, disable CPU DR. */
1088 apic_max_nproc = -1;
1089 apic_free_apic_cpus();
1090 plat_dr_disable_cpu();
1091
1092 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1093 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1094 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1095 APIC_LOCAL_MEMLEN, PROT_READ);
1096 apic_cpus_size = 2 * sizeof (*apic_cpus);
1097 apic_cpus = (apic_cpus_info_t *)
1098 kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1099 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1100 goto apic_handle_defconf_fail;
1101 CPUSET_ONLY(apic_cpumask, 0);
1102 CPUSET_ADD(apic_cpumask, 1);
1103 apic_nproc = 2;
1104 apic_cpus[0].aci_local_id = acpi_get_apic_lid();
1105 /*
1106 * According to the PC+MP spec 1.1, the local ids
1107 * for the default configuration has to be 0 or 1
1108 */
1109 if (apic_cpus[0].aci_local_id == 1)
1110 apic_cpus[1].aci_local_id = 0;
1111 else if (apic_cpus[0].aci_local_id == 0)
1112 apic_cpus[1].aci_local_id = 1;
1113 else
1114 goto apic_handle_defconf_fail;
1115
1116 apic_io_id[0] = 2;
1117 apic_io_max = 1;
1118 if (apic_defconf >= 5) {
1119 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1120 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1121 apic_io_ver[0] = APIC_INTEGRATED_VERS;
1122 } else {
1123 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */
1124 apic_cpus[1].aci_local_ver = 0;
1125 apic_io_ver[0] = 0;
1126 }
1127 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1128 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1129 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1130 return (PSM_SUCCESS);
1131
1132 apic_handle_defconf_fail:
1133 if (apicadr)
1134 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1135 if (apicioadr[0])
1136 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1137 return (PSM_FAILURE);
1138 }
1139
1140 /* Parse the entries in MP configuration table and collect info that we need */
1141 static int
apic_parse_mpct(caddr_t mpct,int bypass_cpus_and_ioapics)1142 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1143 {
1144 struct apic_procent *procp;
1145 struct apic_bus *busp;
1146 struct apic_io_entry *ioapicp;
1147 struct apic_io_intr *intrp;
1148 int ioapic_ix;
1149 uint32_t lid, id;
1150 uchar_t hid;
1151 int warned = 0;
1152
1153 /*LINTED: pointer cast may result in improper alignment */
1154 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1155
1156 /* No need to count cpu entries if we won't use them */
1157 if (!bypass_cpus_and_ioapics) {
1158
1159 /* Find max # of CPUS and allocate structure accordingly */
1160 apic_nproc = 0;
1161 CPUSET_ZERO(apic_cpumask);
1162 while (procp->proc_entry == APIC_CPU_ENTRY) {
1163 if (procp->proc_cpuflags & CPUFLAGS_EN) {
1164 if (apic_nproc < NCPU && use_mp &&
1165 apic_nproc < boot_ncpus) {
1166 CPUSET_ADD(apic_cpumask, apic_nproc);
1167 apic_nproc++;
1168 } else if (apic_nproc == NCPU && !warned) {
1169 cmn_err(CE_WARN, "%s: CPU limit "
1170 "exceeded; will use %d CPUs.",
1171 psm_name, NCPU);
1172 warned = 1;
1173 }
1174
1175 }
1176 procp++;
1177 }
1178 apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1179 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1180 kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1181 return (PSM_FAILURE);
1182 }
1183
1184 /*LINTED: pointer cast may result in improper alignment */
1185 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1186
1187 /*
1188 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1189 * if we're bypassing this information, it has already been filled
1190 * in by acpi_probe(), so don't overwrite it.
1191 */
1192 if (!bypass_cpus_and_ioapics)
1193 apic_nproc = 1;
1194
1195 while (procp->proc_entry == APIC_CPU_ENTRY) {
1196 /* check whether the cpu exists or not */
1197 if (!bypass_cpus_and_ioapics &&
1198 procp->proc_cpuflags & CPUFLAGS_EN) {
1199 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1200 lid = acpi_get_apic_lid();
1201 apic_cpus[0].aci_local_id = procp->proc_apicid;
1202 if (apic_cpus[0].aci_local_id != lid) {
1203 return (PSM_FAILURE);
1204 }
1205 apic_cpus[0].aci_local_ver =
1206 procp->proc_version;
1207 } else if (apic_nproc < NCPU && use_mp &&
1208 apic_nproc < boot_ncpus) {
1209 apic_cpus[apic_nproc].aci_local_id =
1210 procp->proc_apicid;
1211
1212 apic_cpus[apic_nproc].aci_local_ver =
1213 procp->proc_version;
1214 apic_nproc++;
1215
1216 }
1217 }
1218 procp++;
1219 }
1220
1221 /*
1222 * Save start of bus entries for later use.
1223 * Get EISA level cntrl if EISA bus is present.
1224 * Also get the CPI bus id for single CPI bus case
1225 */
1226 apic_busp = busp = (struct apic_bus *)procp;
1227 while (busp->bus_entry == APIC_BUS_ENTRY) {
1228 lid = apic_find_bus_type((char *)&busp->bus_str1);
1229 if (lid == BUS_EISA) {
1230 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1231 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1232 } else if (lid == BUS_PCI) {
1233 /*
1234 * apic_single_pci_busid will be used only if
1235 * apic_pic_bus_total is equal to 1
1236 */
1237 apic_pci_bus_total++;
1238 apic_single_pci_busid = busp->bus_id;
1239 }
1240 busp++;
1241 }
1242
1243 ioapicp = (struct apic_io_entry *)busp;
1244
1245 if (!bypass_cpus_and_ioapics)
1246 apic_io_max = 0;
1247 do {
1248 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1249 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1250 apic_io_id[apic_io_max] = ioapicp->io_apicid;
1251 apic_io_ver[apic_io_max] = ioapicp->io_version;
1252 apicioadr[apic_io_max] =
1253 (void *)mapin_ioapic(
1254 (uint32_t)ioapicp->io_apic_addr,
1255 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1256
1257 if (!apicioadr[apic_io_max])
1258 return (PSM_FAILURE);
1259
1260 ioapic_mask_workaround[apic_io_max] =
1261 apic_is_ioapic_AMD_813x(
1262 ioapicp->io_apic_addr);
1263
1264 ioapic_ix = apic_io_max;
1265 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1266 hid = (uchar_t)(id >> 24);
1267
1268 if (hid != apic_io_id[apic_io_max]) {
1269 if (apic_io_id[apic_io_max] == 0)
1270 apic_io_id[apic_io_max] = hid;
1271 else {
1272 /*
1273 * set ioapic id to whatever
1274 * reported by MPS
1275 *
1276 * may not need to set index
1277 * again ???
1278 * take it out and try
1279 */
1280
1281 id = ((uint32_t)
1282 apic_io_id[apic_io_max]) <<
1283 24;
1284
1285 ioapic_write(ioapic_ix,
1286 APIC_ID_CMD, id);
1287 }
1288 }
1289 apic_io_max++;
1290 }
1291 }
1292 ioapicp++;
1293 } while (ioapicp->io_entry == APIC_IO_ENTRY);
1294
1295 apic_io_intrp = (struct apic_io_intr *)ioapicp;
1296
1297 intrp = apic_io_intrp;
1298 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1299 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1300 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1301 apic_irq_translate = 1;
1302 break;
1303 }
1304 intrp++;
1305 }
1306
1307 return (PSM_SUCCESS);
1308 }
1309
1310 boolean_t
apic_cpu_in_range(int cpu)1311 apic_cpu_in_range(int cpu)
1312 {
1313 cpu &= ~IRQ_USER_BOUND;
1314 /* Check whether cpu id is in valid range. */
1315 if (cpu < 0 || cpu >= apic_nproc) {
1316 return (B_FALSE);
1317 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1318 /*
1319 * Check whether cpuid is in valid range if CPU DR is enabled.
1320 */
1321 return (B_FALSE);
1322 } else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1323 return (B_FALSE);
1324 }
1325
1326 return (B_TRUE);
1327 }
1328
1329 processorid_t
apic_get_next_bind_cpu(void)1330 apic_get_next_bind_cpu(void)
1331 {
1332 int i, count;
1333 processorid_t cpuid = 0;
1334
1335 for (count = 0; count < apic_nproc; count++) {
1336 if (apic_next_bind_cpu >= apic_nproc) {
1337 apic_next_bind_cpu = 0;
1338 }
1339 i = apic_next_bind_cpu++;
1340 if (apic_cpu_in_range(i)) {
1341 cpuid = i;
1342 break;
1343 }
1344 }
1345
1346 return (cpuid);
1347 }
1348
1349 uint16_t
apic_get_apic_version()1350 apic_get_apic_version()
1351 {
1352 int i;
1353 uchar_t min_io_apic_ver = 0;
1354 static uint16_t version; /* Cache as value is constant */
1355 static boolean_t found = B_FALSE; /* Accomodate zero version */
1356
1357 if (found == B_FALSE) {
1358 found = B_TRUE;
1359
1360 /*
1361 * Don't assume all IO APICs in the system are the same.
1362 *
1363 * Set to the minimum version.
1364 */
1365 for (i = 0; i < apic_io_max; i++) {
1366 if ((apic_io_ver[i] != 0) &&
1367 ((min_io_apic_ver == 0) ||
1368 (min_io_apic_ver >= apic_io_ver[i])))
1369 min_io_apic_ver = apic_io_ver[i];
1370 }
1371
1372 /* Assume all local APICs are of the same version. */
1373 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1374 }
1375 return (version);
1376 }
1377
1378 static struct apic_mpfps_hdr *
apic_find_fps_sig(caddr_t cptr,int len)1379 apic_find_fps_sig(caddr_t cptr, int len)
1380 {
1381 int i;
1382
1383 /* Look for the pattern "_MP_" */
1384 for (i = 0; i < len; i += 16) {
1385 if ((*(cptr+i) == '_') &&
1386 (*(cptr+i+1) == 'M') &&
1387 (*(cptr+i+2) == 'P') &&
1388 (*(cptr+i+3) == '_'))
1389 /*LINTED: pointer cast may result in improper alignment */
1390 return ((struct apic_mpfps_hdr *)(cptr + i));
1391 }
1392 return (NULL);
1393 }
1394
1395 static int
apic_checksum(caddr_t bptr,int len)1396 apic_checksum(caddr_t bptr, int len)
1397 {
1398 int i;
1399 uchar_t cksum;
1400
1401 cksum = 0;
1402 for (i = 0; i < len; i++)
1403 cksum += *bptr++;
1404 return ((int)cksum);
1405 }
1406
1407 /*
1408 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1409 * needs special handling. We may need to chase up the device tree,
1410 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1411 * to find the IPIN at the root bus that relates to the IPIN on the
1412 * subsidiary bus (for ACPI or MP). We may, however, have an entry
1413 * in the MP table or the ACPI namespace for this device itself.
1414 * We handle both cases in the search below.
1415 */
1416 /* this is the non-acpi version */
1417 int
apic_handle_pci_pci_bridge(dev_info_t * idip,int child_devno,int child_ipin,struct apic_io_intr ** intrp)1418 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1419 struct apic_io_intr **intrp)
1420 {
1421 dev_info_t *dipp, *dip;
1422 int pci_irq;
1423 ddi_acc_handle_t cfg_handle;
1424 int bridge_devno, bridge_bus;
1425 int ipin;
1426
1427 dip = idip;
1428
1429 /*CONSTCOND*/
1430 while (1) {
1431 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1432 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1433 return (-1);
1434 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1435 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1436 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1437 pci_config_teardown(&cfg_handle);
1438 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1439 NULL) != 0)
1440 return (-1);
1441 /*
1442 * This is the rotating scheme documented in the
1443 * PCI-to-PCI spec. If the PCI-to-PCI bridge is
1444 * behind another PCI-to-PCI bridge, then it needs
1445 * to keep ascending until an interrupt entry is
1446 * found or the root is reached.
1447 */
1448 ipin = (child_devno + child_ipin) % PCI_INTD;
1449 if (bridge_bus == 0 && apic_pci_bus_total == 1)
1450 bridge_bus = (int)apic_single_pci_busid;
1451 pci_irq = ((bridge_devno & 0x1f) << 2) |
1452 (ipin & 0x3);
1453 if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1454 bridge_bus)) != NULL) {
1455 return (pci_irq);
1456 }
1457 dip = dipp;
1458 child_devno = bridge_devno;
1459 child_ipin = ipin;
1460 } else {
1461 pci_config_teardown(&cfg_handle);
1462 return (-1);
1463 }
1464 }
1465 /*LINTED: function will not fall off the bottom */
1466 }
1467
1468 uchar_t
acpi_find_ioapic(int irq)1469 acpi_find_ioapic(int irq)
1470 {
1471 int i;
1472
1473 for (i = 0; i < apic_io_max; i++) {
1474 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1475 return ((uchar_t)i);
1476 }
1477 return (0xFF); /* shouldn't happen */
1478 }
1479
1480 /*
1481 * See if two irqs are compatible for sharing a vector.
1482 * Currently we only support sharing of PCI devices.
1483 */
1484 static int
acpi_intr_compatible(iflag_t iflag1,iflag_t iflag2)1485 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1486 {
1487 uint_t level1, po1;
1488 uint_t level2, po2;
1489
1490 /* Assume active high by default */
1491 po1 = 0;
1492 po2 = 0;
1493
1494 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1495 return (0);
1496
1497 if (iflag1.intr_el == INTR_EL_CONFORM)
1498 level1 = AV_LEVEL;
1499 else
1500 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1501
1502 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1503 (iflag1.intr_po == INTR_PO_CONFORM)))
1504 po1 = AV_ACTIVE_LOW;
1505
1506 if (iflag2.intr_el == INTR_EL_CONFORM)
1507 level2 = AV_LEVEL;
1508 else
1509 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1510
1511 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1512 (iflag2.intr_po == INTR_PO_CONFORM)))
1513 po2 = AV_ACTIVE_LOW;
1514
1515 if ((level1 == level2) && (po1 == po2))
1516 return (1);
1517
1518 return (0);
1519 }
1520
1521 struct apic_io_intr *
apic_find_io_intr_w_busid(int irqno,int busid)1522 apic_find_io_intr_w_busid(int irqno, int busid)
1523 {
1524 struct apic_io_intr *intrp;
1525
1526 /*
1527 * It can have more than 1 entry with same source bus IRQ,
1528 * but unique with the source bus id
1529 */
1530 intrp = apic_io_intrp;
1531 if (intrp != NULL) {
1532 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1533 if (intrp->intr_irq == irqno &&
1534 intrp->intr_busid == busid &&
1535 intrp->intr_type == IO_INTR_INT)
1536 return (intrp);
1537 intrp++;
1538 }
1539 }
1540 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1541 "busid %x:%x\n", irqno, busid));
1542 return ((struct apic_io_intr *)NULL);
1543 }
1544
1545
1546 struct mps_bus_info {
1547 char *bus_name;
1548 int bus_id;
1549 } bus_info_array[] = {
1550 "ISA ", BUS_ISA,
1551 "PCI ", BUS_PCI,
1552 "EISA ", BUS_EISA,
1553 "XPRESS", BUS_XPRESS,
1554 "PCMCIA", BUS_PCMCIA,
1555 "VL ", BUS_VL,
1556 "CBUS ", BUS_CBUS,
1557 "CBUSII", BUS_CBUSII,
1558 "FUTURE", BUS_FUTURE,
1559 "INTERN", BUS_INTERN,
1560 "MBI ", BUS_MBI,
1561 "MBII ", BUS_MBII,
1562 "MPI ", BUS_MPI,
1563 "MPSA ", BUS_MPSA,
1564 "NUBUS ", BUS_NUBUS,
1565 "TC ", BUS_TC,
1566 "VME ", BUS_VME,
1567 "PCI-E ", BUS_PCIE
1568 };
1569
1570 static int
apic_find_bus_type(char * bus)1571 apic_find_bus_type(char *bus)
1572 {
1573 int i = 0;
1574
1575 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1576 if (strncmp(bus, bus_info_array[i].bus_name,
1577 strlen(bus_info_array[i].bus_name)) == 0)
1578 return (bus_info_array[i].bus_id);
1579 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1580 return (0);
1581 }
1582
1583 static int
apic_find_bus(int busid)1584 apic_find_bus(int busid)
1585 {
1586 struct apic_bus *busp;
1587
1588 busp = apic_busp;
1589 while (busp->bus_entry == APIC_BUS_ENTRY) {
1590 if (busp->bus_id == busid)
1591 return (apic_find_bus_type((char *)&busp->bus_str1));
1592 busp++;
1593 }
1594 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1595 return (0);
1596 }
1597
1598 int
apic_find_bus_id(int bustype)1599 apic_find_bus_id(int bustype)
1600 {
1601 struct apic_bus *busp;
1602
1603 busp = apic_busp;
1604 while (busp->bus_entry == APIC_BUS_ENTRY) {
1605 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1606 return (busp->bus_id);
1607 busp++;
1608 }
1609 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1610 bustype));
1611 return (-1);
1612 }
1613
1614 /*
1615 * Check if a particular irq need to be reserved for any io_intr
1616 */
1617 static struct apic_io_intr *
apic_find_io_intr(int irqno)1618 apic_find_io_intr(int irqno)
1619 {
1620 struct apic_io_intr *intrp;
1621
1622 intrp = apic_io_intrp;
1623 if (intrp != NULL) {
1624 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1625 if (intrp->intr_irq == irqno &&
1626 intrp->intr_type == IO_INTR_INT)
1627 return (intrp);
1628 intrp++;
1629 }
1630 }
1631 return ((struct apic_io_intr *)NULL);
1632 }
1633
1634 /*
1635 * Check if the given ioapicindex intin combination has already been assigned
1636 * an irq. If so return irqno. Else -1
1637 */
1638 int
apic_find_intin(uchar_t ioapic,uchar_t intin)1639 apic_find_intin(uchar_t ioapic, uchar_t intin)
1640 {
1641 apic_irq_t *irqptr;
1642 int i;
1643
1644 /* find ioapic and intin in the apic_irq_table[] and return the index */
1645 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1646 irqptr = apic_irq_table[i];
1647 while (irqptr) {
1648 if ((irqptr->airq_mps_intr_index >= 0) &&
1649 (irqptr->airq_intin_no == intin) &&
1650 (irqptr->airq_ioapicindex == ioapic)) {
1651 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1652 "entry for ioapic:intin %x:%x "
1653 "shared interrupts ?", ioapic, intin));
1654 return (i);
1655 }
1656 irqptr = irqptr->airq_next;
1657 }
1658 }
1659 return (-1);
1660 }
1661
1662 int
apic_allocate_irq(int irq)1663 apic_allocate_irq(int irq)
1664 {
1665 int freeirq, i;
1666
1667 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) {
1668 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1669 (irq - 1))) == -1) {
1670 /*
1671 * if BIOS really defines every single irq in the mps
1672 * table, then don't worry about conflicting with
1673 * them, just use any free slot in apic_irq_table
1674 */
1675 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1676 if ((apic_irq_table[i] == NULL) ||
1677 apic_irq_table[i]->airq_mps_intr_index ==
1678 FREE_INDEX) {
1679 freeirq = i;
1680 break;
1681 }
1682 }
1683
1684 if (freeirq == -1) {
1685 /* This shouldn't happen, but just in case */
1686 cmn_err(CE_WARN, "%s: NO available IRQ",
1687 psm_name);
1688 return (-1);
1689 }
1690 }
1691 }
1692
1693 if (apic_irq_table[freeirq] == NULL) {
1694 apic_irq_table[freeirq] =
1695 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1696 if (apic_irq_table[freeirq] == NULL) {
1697 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1698 psm_name);
1699 return (-1);
1700 }
1701 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1702 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1703 }
1704 return (freeirq);
1705 }
1706
1707 static int
apic_find_free_irq(int start,int end)1708 apic_find_free_irq(int start, int end)
1709 {
1710 int i;
1711
1712 for (i = start; i <= end; i++)
1713 /* Check if any I/O entry needs this IRQ */
1714 if (apic_find_io_intr(i) == NULL) {
1715 /* Then see if it is free */
1716 if ((apic_irq_table[i] == NULL) ||
1717 (apic_irq_table[i]->airq_mps_intr_index ==
1718 FREE_INDEX)) {
1719 return (i);
1720 }
1721 }
1722 return (-1);
1723 }
1724
1725 /*
1726 * compute the polarity, trigger mode and vector for programming into
1727 * the I/O apic and record in airq_rdt_entry.
1728 */
1729 void
apic_record_rdt_entry(apic_irq_t * irqptr,int irq)1730 apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1731 {
1732 int ioapicindex, bus_type, vector;
1733 short intr_index;
1734 uint_t level, po, io_po;
1735 struct apic_io_intr *iointrp;
1736
1737 intr_index = irqptr->airq_mps_intr_index;
1738 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1739 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1740 (void *)irqptr->airq_dip, irqptr->airq_vector));
1741
1742 if (intr_index == RESERVE_INDEX) {
1743 apic_error |= APIC_ERR_INVALID_INDEX;
1744 return;
1745 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1746 return;
1747 }
1748
1749 vector = irqptr->airq_vector;
1750 ioapicindex = irqptr->airq_ioapicindex;
1751 /* Assume edge triggered by default */
1752 level = 0;
1753 /* Assume active high by default */
1754 po = 0;
1755
1756 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1757 ASSERT(irq < 16);
1758 if (eisa_level_intr_mask & (1 << irq))
1759 level = AV_LEVEL;
1760 if (intr_index == FREE_INDEX && apic_defconf == 0)
1761 apic_error |= APIC_ERR_INVALID_INDEX;
1762 } else if (intr_index == ACPI_INDEX) {
1763 bus_type = irqptr->airq_iflag.bustype;
1764 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1765 if (bus_type == BUS_PCI)
1766 level = AV_LEVEL;
1767 } else
1768 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1769 AV_LEVEL : 0;
1770 if (level &&
1771 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1772 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1773 bus_type == BUS_PCI)))
1774 po = AV_ACTIVE_LOW;
1775 } else {
1776 iointrp = apic_io_intrp + intr_index;
1777 bus_type = apic_find_bus(iointrp->intr_busid);
1778 if (iointrp->intr_el == INTR_EL_CONFORM) {
1779 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1780 level = AV_LEVEL;
1781 else if (bus_type == BUS_PCI)
1782 level = AV_LEVEL;
1783 } else
1784 level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1785 AV_LEVEL : 0;
1786 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1787 (iointrp->intr_po == INTR_PO_CONFORM &&
1788 bus_type == BUS_PCI)))
1789 po = AV_ACTIVE_LOW;
1790 }
1791 if (level)
1792 apic_level_intr[irq] = 1;
1793 /*
1794 * The 82489DX External APIC cannot do active low polarity interrupts.
1795 */
1796 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1797 io_po = po;
1798 else
1799 io_po = 0;
1800
1801 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1802 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1803 "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1804 irqptr->airq_intin_no, level, io_po, vector,
1805 irqptr->airq_cpu);
1806
1807 irqptr->airq_rdt_entry = level|io_po|vector;
1808 }
1809
1810 int
apic_acpi_translate_pci_irq(dev_info_t * dip,int busid,int devid,int ipin,int * pci_irqp,iflag_t * intr_flagp)1811 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1812 int ipin, int *pci_irqp, iflag_t *intr_flagp)
1813 {
1814
1815 int status;
1816 acpi_psm_lnk_t acpipsmlnk;
1817
1818 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1819 intr_flagp)) == ACPI_PSM_SUCCESS) {
1820 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1821 "from cache for device %s, instance #%d\n", psm_name,
1822 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1823 return (status);
1824 }
1825
1826 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1827
1828 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1829 &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1830 APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1831 " acpi_translate_pci_irq failed for device %s, instance"
1832 " #%d", psm_name, ddi_get_name(dip),
1833 ddi_get_instance(dip)));
1834 return (status);
1835 }
1836
1837 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1838 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1839 intr_flagp);
1840 if (status != ACPI_PSM_SUCCESS) {
1841 status = acpi_get_current_irq_resource(&acpipsmlnk,
1842 pci_irqp, intr_flagp);
1843 }
1844 }
1845
1846 if (status == ACPI_PSM_SUCCESS) {
1847 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1848 intr_flagp, &acpipsmlnk);
1849
1850 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1851 "new irq %d for device %s, instance #%d\n", psm_name,
1852 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1853 }
1854
1855 return (status);
1856 }
1857
1858 /*
1859 * Adds an entry to the irq list passed in, and returns the new list.
1860 * Entries are added in priority order (lower numerical priorities are
1861 * placed closer to the head of the list)
1862 */
1863 static prs_irq_list_t *
acpi_insert_prs_irq_ent(prs_irq_list_t * listp,int priority,int irq,iflag_t * iflagp,acpi_prs_private_t * prsprvp)1864 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1865 iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1866 {
1867 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1868
1869 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1870
1871 newent->list_prio = priority;
1872 newent->irq = irq;
1873 newent->intrflags = *iflagp;
1874 newent->prsprv = *prsprvp;
1875 /* ->next is NULL from kmem_zalloc */
1876
1877 /*
1878 * New list -- return the new entry as the list.
1879 */
1880 if (listp == NULL)
1881 return (newent);
1882
1883 /*
1884 * Save original list pointer for return (since we're not modifying
1885 * the head)
1886 */
1887 origlistp = listp;
1888
1889 /*
1890 * Insertion sort, with entries with identical keys stored AFTER
1891 * existing entries (the less-than-or-equal test of priority does
1892 * this for us).
1893 */
1894 while (listp != NULL && listp->list_prio <= priority) {
1895 prevp = listp;
1896 listp = listp->next;
1897 }
1898
1899 newent->next = listp;
1900
1901 if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1902 return (newent);
1903 } else {
1904 prevp->next = newent;
1905 return (origlistp);
1906 }
1907 }
1908
1909 /*
1910 * Frees the list passed in, deallocating all memory and leaving *listpp
1911 * set to NULL.
1912 */
1913 static void
acpi_destroy_prs_irq_list(prs_irq_list_t ** listpp)1914 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1915 {
1916 struct prs_irq_list_ent *nextp;
1917
1918 ASSERT(listpp != NULL);
1919
1920 while (*listpp != NULL) {
1921 nextp = (*listpp)->next;
1922 kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1923 *listpp = nextp;
1924 }
1925 }
1926
1927 /*
1928 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1929 * irqs returned by the link device's _PRS method. The irqs are chosen
1930 * to minimize contention in situations where the interrupt link device
1931 * can be programmed to steer interrupts to different interrupt controller
1932 * inputs (some of which may already be in use). The list is sorted in order
1933 * of irqs to use, with the highest priority given to interrupt controller
1934 * inputs that are not shared. When an interrupt controller input
1935 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1936 * returned list in the order that minimizes sharing (thereby ensuring lowest
1937 * possible latency from interrupt trigger time to ISR execution time).
1938 */
1939 static prs_irq_list_t *
apic_choose_irqs_from_prs(acpi_irqlist_t * irqlistent,dev_info_t * dip,int crs_irq)1940 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1941 int crs_irq)
1942 {
1943 int32_t irq;
1944 int i;
1945 prs_irq_list_t *prsirqlistp = NULL;
1946 iflag_t iflags;
1947
1948 while (irqlistent != NULL) {
1949 irqlistent->intr_flags.bustype = BUS_PCI;
1950
1951 for (i = 0; i < irqlistent->num_irqs; i++) {
1952
1953 irq = irqlistent->irqs[i];
1954
1955 if (irq <= 0) {
1956 /* invalid irq number */
1957 continue;
1958 }
1959
1960 if ((irq < 16) && (apic_reserved_irqlist[irq]))
1961 continue;
1962
1963 if ((apic_irq_table[irq] == NULL) ||
1964 (apic_irq_table[irq]->airq_dip == dip)) {
1965
1966 prsirqlistp = acpi_insert_prs_irq_ent(
1967 prsirqlistp, 0 /* Highest priority */, irq,
1968 &irqlistent->intr_flags,
1969 &irqlistent->acpi_prs_prv);
1970
1971 /*
1972 * If we do not prefer the current irq from _CRS
1973 * or if we do and this irq is the same as the
1974 * current irq from _CRS, this is the one
1975 * to pick.
1976 */
1977 if (!(apic_prefer_crs) || (irq == crs_irq)) {
1978 return (prsirqlistp);
1979 }
1980 continue;
1981 }
1982
1983 /*
1984 * Edge-triggered interrupts cannot be shared
1985 */
1986 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1987 continue;
1988
1989 /*
1990 * To work around BIOSes that contain incorrect
1991 * interrupt polarity information in interrupt
1992 * descriptors returned by _PRS, we assume that
1993 * the polarity of the other device sharing this
1994 * interrupt controller input is compatible.
1995 * If it's not, the caller will catch it when
1996 * the caller invokes the link device's _CRS method
1997 * (after invoking its _SRS method).
1998 */
1999 iflags = irqlistent->intr_flags;
2000 iflags.intr_po =
2001 apic_irq_table[irq]->airq_iflag.intr_po;
2002
2003 if (!acpi_intr_compatible(iflags,
2004 apic_irq_table[irq]->airq_iflag)) {
2005 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
2006 "not compatible [%x:%x:%x !~ %x:%x:%x]",
2007 psm_name, irq,
2008 iflags.intr_po,
2009 iflags.intr_el,
2010 iflags.bustype,
2011 apic_irq_table[irq]->airq_iflag.intr_po,
2012 apic_irq_table[irq]->airq_iflag.intr_el,
2013 apic_irq_table[irq]->airq_iflag.bustype));
2014 continue;
2015 }
2016
2017 /*
2018 * If we prefer the irq from _CRS, no need
2019 * to search any further (and make sure
2020 * to add this irq with the highest priority
2021 * so it's tried first).
2022 */
2023 if (crs_irq == irq && apic_prefer_crs) {
2024
2025 return (acpi_insert_prs_irq_ent(
2026 prsirqlistp,
2027 0 /* Highest priority */,
2028 irq, &iflags,
2029 &irqlistent->acpi_prs_prv));
2030 }
2031
2032 /*
2033 * Priority is equal to the share count (lower
2034 * share count is higher priority). Note that
2035 * the intr flags passed in here are the ones we
2036 * changed above -- if incorrect, it will be
2037 * caught by the caller's _CRS flags comparison.
2038 */
2039 prsirqlistp = acpi_insert_prs_irq_ent(
2040 prsirqlistp,
2041 apic_irq_table[irq]->airq_share, irq,
2042 &iflags, &irqlistent->acpi_prs_prv);
2043 }
2044
2045 /* Go to the next irqlist entry */
2046 irqlistent = irqlistent->next;
2047 }
2048
2049 return (prsirqlistp);
2050 }
2051
2052 /*
2053 * Configures the irq for the interrupt link device identified by
2054 * acpipsmlnkp.
2055 *
2056 * Gets the current and the list of possible irq settings for the
2057 * device. If apic_unconditional_srs is not set, and the current
2058 * resource setting is in the list of possible irq settings,
2059 * current irq resource setting is passed to the caller.
2060 *
2061 * Otherwise, picks an irq number from the list of possible irq
2062 * settings, and sets the irq of the device to this value.
2063 * If prefer_crs is set, among a set of irq numbers in the list that have
2064 * the least number of devices sharing the interrupt, we pick current irq
2065 * resource setting if it is a member of this set.
2066 *
2067 * Passes the irq number in the value pointed to by pci_irqp, and
2068 * polarity and sensitivity in the structure pointed to by dipintrflagp
2069 * to the caller.
2070 *
2071 * Note that if setting the irq resource failed, but successfuly obtained
2072 * the current irq resource settings, passes the current irq resources
2073 * and considers it a success.
2074 *
2075 * Returns:
2076 * ACPI_PSM_SUCCESS on success.
2077 *
2078 * ACPI_PSM_FAILURE if an error occured during the configuration or
2079 * if a suitable irq was not found for this device, or if setting the
2080 * irq resource and obtaining the current resource fails.
2081 *
2082 */
2083 static int
apic_acpi_irq_configure(acpi_psm_lnk_t * acpipsmlnkp,dev_info_t * dip,int * pci_irqp,iflag_t * dipintr_flagp)2084 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2085 int *pci_irqp, iflag_t *dipintr_flagp)
2086 {
2087 int32_t irq;
2088 int cur_irq = -1;
2089 acpi_irqlist_t *irqlistp;
2090 prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2091 boolean_t found_irq = B_FALSE;
2092
2093 dipintr_flagp->bustype = BUS_PCI;
2094
2095 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2096 == ACPI_PSM_FAILURE) {
2097 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2098 "or assign IRQ for device %s, instance #%d: The system was "
2099 "unable to get the list of potential IRQs from ACPI.",
2100 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2101
2102 return (ACPI_PSM_FAILURE);
2103 }
2104
2105 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2106 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2107 (cur_irq > 0)) {
2108 /*
2109 * If an IRQ is set in CRS and that IRQ exists in the set
2110 * returned from _PRS, return that IRQ, otherwise print
2111 * a warning
2112 */
2113
2114 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2115 == ACPI_PSM_SUCCESS) {
2116
2117 ASSERT(pci_irqp != NULL);
2118 *pci_irqp = cur_irq;
2119 acpi_free_irqlist(irqlistp);
2120 return (ACPI_PSM_SUCCESS);
2121 }
2122
2123 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2124 "current irq %d for device %s, instance #%d in ACPI's "
2125 "list of possible irqs for this device. Picking one from "
2126 " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2127 ddi_get_instance(dip)));
2128 }
2129
2130 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2131 cur_irq)) == NULL) {
2132
2133 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2134 "suitable irq from the list of possible irqs for device "
2135 "%s, instance #%d in ACPI's list of possible irqs",
2136 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2137
2138 acpi_free_irqlist(irqlistp);
2139 return (ACPI_PSM_FAILURE);
2140 }
2141
2142 acpi_free_irqlist(irqlistp);
2143
2144 for (prs_irq_entp = prs_irq_listp;
2145 prs_irq_entp != NULL && found_irq == B_FALSE;
2146 prs_irq_entp = prs_irq_entp->next) {
2147
2148 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2149 irq = prs_irq_entp->irq;
2150
2151 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2152 "device %s instance #%d\n", psm_name, irq,
2153 ddi_get_name(dip), ddi_get_instance(dip)));
2154
2155 if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2156 == ACPI_PSM_SUCCESS) {
2157 /*
2158 * setting irq was successful, check to make sure CRS
2159 * reflects that. If CRS does not agree with what we
2160 * set, return the irq that was set.
2161 */
2162
2163 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2164 dipintr_flagp) == ACPI_PSM_SUCCESS) {
2165
2166 if (cur_irq != irq)
2167 APIC_VERBOSE_IRQ((CE_WARN,
2168 "!%s: IRQ resource set "
2169 "(irqno %d) for device %s "
2170 "instance #%d, differs from "
2171 "current setting irqno %d",
2172 psm_name, irq, ddi_get_name(dip),
2173 ddi_get_instance(dip), cur_irq));
2174 } else {
2175 /*
2176 * On at least one system, there was a bug in
2177 * a DSDT method called by _STA, causing _STA to
2178 * indicate that the link device was disabled
2179 * (when, in fact, it was enabled). Since _SRS
2180 * succeeded, assume that _CRS is lying and use
2181 * the iflags from this _PRS interrupt choice.
2182 * If we're wrong about the flags, the polarity
2183 * will be incorrect and we may get an interrupt
2184 * storm, but there's not much else we can do
2185 * at this point.
2186 */
2187 *dipintr_flagp = prs_irq_entp->intrflags;
2188 }
2189
2190 /*
2191 * Return the irq that was set, and not what _CRS
2192 * reports, since _CRS has been seen to return
2193 * different IRQs than what was passed to _SRS on some
2194 * systems (and just not return successfully on others).
2195 */
2196 cur_irq = irq;
2197 found_irq = B_TRUE;
2198 } else {
2199 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2200 "irq %d failed for device %s instance #%d",
2201 psm_name, irq, ddi_get_name(dip),
2202 ddi_get_instance(dip)));
2203
2204 if (cur_irq == -1) {
2205 acpi_destroy_prs_irq_list(&prs_irq_listp);
2206 return (ACPI_PSM_FAILURE);
2207 }
2208 }
2209 }
2210
2211 acpi_destroy_prs_irq_list(&prs_irq_listp);
2212
2213 if (!found_irq)
2214 return (ACPI_PSM_FAILURE);
2215
2216 ASSERT(pci_irqp != NULL);
2217 *pci_irqp = cur_irq;
2218 return (ACPI_PSM_SUCCESS);
2219 }
2220
2221 void
ioapic_disable_redirection()2222 ioapic_disable_redirection()
2223 {
2224 int ioapic_ix;
2225 int intin_max;
2226 int intin_ix;
2227
2228 /* Disable the I/O APIC redirection entries */
2229 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2230
2231 /* Bits 23-16 define the maximum redirection entries */
2232 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2233 & 0xff;
2234
2235 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2236 /*
2237 * The assumption here is that this is safe, even for
2238 * systems with IOAPICs that suffer from the hardware
2239 * erratum because all devices have been quiesced before
2240 * this function is called from apic_shutdown()
2241 * (or equivalent). If that assumption turns out to be
2242 * false, this mask operation can induce the same
2243 * erratum result we're trying to avoid.
2244 */
2245 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2246 AV_MASK);
2247 }
2248 }
2249 }
2250
2251 /*
2252 * Looks for an IOAPIC with the specified physical address in the /ioapics
2253 * node in the device tree (created by the PCI enumerator).
2254 */
2255 static boolean_t
apic_is_ioapic_AMD_813x(uint32_t physaddr)2256 apic_is_ioapic_AMD_813x(uint32_t physaddr)
2257 {
2258 /*
2259 * Look in /ioapics, for the ioapic with
2260 * the physical address given
2261 */
2262 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2263 dev_info_t *ioapic_child;
2264 boolean_t rv = B_FALSE;
2265 int vid, did;
2266 uint64_t ioapic_paddr;
2267 boolean_t done = B_FALSE;
2268
2269 if (ioapicsnode == NULL)
2270 return (B_FALSE);
2271
2272 /* Load first child: */
2273 ioapic_child = ddi_get_child(ioapicsnode);
2274 while (!done && ioapic_child != 0) { /* Iterate over children */
2275
2276 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2277 ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2278 != 0 && physaddr == ioapic_paddr) {
2279
2280 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2281 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2282
2283 if (vid == VENID_AMD) {
2284
2285 did = ddi_prop_get_int(DDI_DEV_T_ANY,
2286 ioapic_child, DDI_PROP_DONTPASS,
2287 IOAPICS_PROP_DEVID, 0);
2288
2289 if (did == DEVID_8131_IOAPIC ||
2290 did == DEVID_8132_IOAPIC) {
2291 rv = B_TRUE;
2292 done = B_TRUE;
2293 }
2294 }
2295 }
2296
2297 if (!done)
2298 ioapic_child = ddi_get_next_sibling(ioapic_child);
2299 }
2300
2301 /* The ioapics node was held by ddi_find_devinfo, so release it */
2302 ndi_rele_devi(ioapicsnode);
2303 return (rv);
2304 }
2305
2306 struct apic_state {
2307 int32_t as_task_reg;
2308 int32_t as_dest_reg;
2309 int32_t as_format_reg;
2310 int32_t as_local_timer;
2311 int32_t as_pcint_vect;
2312 int32_t as_int_vect0;
2313 int32_t as_int_vect1;
2314 int32_t as_err_vect;
2315 int32_t as_init_count;
2316 int32_t as_divide_reg;
2317 int32_t as_spur_int_reg;
2318 uint32_t as_ioapic_ids[MAX_IO_APIC];
2319 };
2320
2321
2322 static int
apic_acpi_enter_apicmode(void)2323 apic_acpi_enter_apicmode(void)
2324 {
2325 ACPI_OBJECT_LIST arglist;
2326 ACPI_OBJECT arg;
2327 ACPI_STATUS status;
2328
2329 /* Setup parameter object */
2330 arglist.Count = 1;
2331 arglist.Pointer = &arg;
2332 arg.Type = ACPI_TYPE_INTEGER;
2333 arg.Integer.Value = ACPI_APIC_MODE;
2334
2335 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2336 /*
2337 * Per ACPI spec - section 5.8.1 _PIC Method
2338 * calling the \_PIC control method is optional for the OS
2339 * and might not be found. It's ok to not fail in such cases.
2340 * This is the case on linux KVM and qemu (status AE_NOT_FOUND)
2341 */
2342 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
2343 cmn_err(CE_NOTE,
2344 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x",
2345 ACPI_FAILURE(status));
2346 return (PSM_FAILURE);
2347 } else {
2348 return (PSM_SUCCESS);
2349 }
2350 }
2351
2352
2353 static void
apic_save_state(struct apic_state * sp)2354 apic_save_state(struct apic_state *sp)
2355 {
2356 int i, cpuid;
2357 ulong_t iflag;
2358
2359 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2360 /*
2361 * First the local APIC.
2362 */
2363 sp->as_task_reg = apic_reg_ops->apic_get_pri();
2364 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG);
2365 if (apic_mode == LOCAL_APIC)
2366 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2367 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2368 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2369 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2370 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2371 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2372 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2373 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2374 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2375
2376 /*
2377 * If on the boot processor then save the IOAPICs' IDs
2378 */
2379 if ((cpuid = psm_get_cpu_id()) == 0) {
2380
2381 iflag = intr_clear();
2382 lock_set(&apic_ioapic_lock);
2383
2384 for (i = 0; i < apic_io_max; i++)
2385 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2386
2387 lock_clear(&apic_ioapic_lock);
2388 intr_restore(iflag);
2389 }
2390
2391 /* apic_state() is currently invoked only in Suspend/Resume */
2392 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2393 }
2394
2395 static void
apic_restore_state(struct apic_state * sp)2396 apic_restore_state(struct apic_state *sp)
2397 {
2398 int i;
2399 ulong_t iflag;
2400
2401 /*
2402 * First the local APIC.
2403 */
2404 apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2405 if (apic_mode == LOCAL_APIC) {
2406 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2407 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2408 }
2409 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2410 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2411 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2412 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2413 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2414 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2415 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2416 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2417
2418 /*
2419 * the following only needs to be done once, so we do it on the
2420 * boot processor, since we know that we only have one of those
2421 */
2422 if (psm_get_cpu_id() == 0) {
2423
2424 iflag = intr_clear();
2425 lock_set(&apic_ioapic_lock);
2426
2427 /* Restore IOAPICs' APIC IDs */
2428 for (i = 0; i < apic_io_max; i++) {
2429 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2430 }
2431
2432 lock_clear(&apic_ioapic_lock);
2433 intr_restore(iflag);
2434
2435 /*
2436 * Reenter APIC mode before restoring LNK devices
2437 */
2438 (void) apic_acpi_enter_apicmode();
2439
2440 /*
2441 * restore acpi link device mappings
2442 */
2443 acpi_restore_link_devices();
2444 }
2445 }
2446
2447 /*
2448 * Returns 0 on success
2449 */
2450 int
apic_state(psm_state_request_t * rp)2451 apic_state(psm_state_request_t *rp)
2452 {
2453 PMD(PMD_SX, ("apic_state "))
2454 switch (rp->psr_cmd) {
2455 case PSM_STATE_ALLOC:
2456 rp->req.psm_state_req.psr_state =
2457 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2458 if (rp->req.psm_state_req.psr_state == NULL)
2459 return (ENOMEM);
2460 rp->req.psm_state_req.psr_state_size =
2461 sizeof (struct apic_state);
2462 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2463 rp->req.psm_state_req.psr_state,
2464 rp->req.psm_state_req.psr_state_size))
2465 return (0);
2466
2467 case PSM_STATE_FREE:
2468 kmem_free(rp->req.psm_state_req.psr_state,
2469 rp->req.psm_state_req.psr_state_size);
2470 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2471 rp->req.psm_state_req.psr_state,
2472 rp->req.psm_state_req.psr_state_size))
2473 return (0);
2474
2475 case PSM_STATE_SAVE:
2476 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2477 rp->req.psm_state_req.psr_state,
2478 rp->req.psm_state_req.psr_state_size))
2479 apic_save_state(rp->req.psm_state_req.psr_state);
2480 return (0);
2481
2482 case PSM_STATE_RESTORE:
2483 apic_restore_state(rp->req.psm_state_req.psr_state);
2484 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2485 rp->req.psm_state_req.psr_state,
2486 rp->req.psm_state_req.psr_state_size))
2487 return (0);
2488
2489 default:
2490 return (EINVAL);
2491 }
2492 }
2493