1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 /* 37 * Copyright 2023 Oxide Computer Company 38 */ 39 40 #ifndef _QEDE_H 41 #define _QEDE_H 42 43 #include <sys/stream.h> 44 45 #include <sys/ddi.h> 46 #include <sys/ddifm.h> 47 #include <sys/dditypes.h> 48 #include <sys/sunddi.h> 49 #include <sys/fm/io/ddi.h> 50 #include <sys/mac_provider.h> 51 #include <sys/mac_ether.h> 52 #include <sys/kobj.h> 53 #include <sys/mac.h> 54 #include <sys/mac_ether.h> 55 #include <sys/dlpi.h> 56 #include <sys/pattr.h> 57 #include <sys/gld.h> 58 #include <inet/ip.h> 59 #include <inet/tcp.h> 60 #include <netinet/udp.h> 61 #include <sys/ethernet.h> 62 #include <sys/pci.h> 63 #include <sys/netlb.h> 64 #include <sys/strsun.h> 65 #include <sys/strsubr.h> 66 #include <sys/policy.h> 67 68 #include "qede_version.h" 69 #include "bcm_osal.h" 70 #include "qede_fp.h" 71 72 #if 1 73 #include "ecore.h" 74 #include "ecore_status.h" 75 #include "ecore_utils.h" 76 #include "ecore_chain.h" 77 #include "ecore_hsi_common.h" 78 #include "ecore_hsi_eth.h" 79 #include "ecore_proto_if.h" 80 #include "ecore_iov_api.h" 81 #include "ecore_int_api.h" 82 #include "ecore_dev_api.h" 83 #include "ecore_l2_api.h" 84 #include "ecore_hw.h" 85 #include "nvm_cfg.h" 86 #include "ecore_mcp.h" 87 #include "ecore_dbg_fw_funcs.h" 88 #include <sys/pcie.h> 89 #include <sys/time.h> 90 #else 91 #include <ecore.h> 92 #include <ecore_status.h> 93 #include <ecore_utils.h> 94 #include <ecore_hsi_common.h> 95 #include <ecore_hsi_eth.h> 96 #include <ecore_proto_if.h> 97 #include <ecore_chain.h> 98 #include <ecore_iov_api.h> 99 #include <ecore_int_api.h> 100 #include <ecore_dev_api.h> 101 #include <ecore_ll2_api.h> 102 #include <ecore_l2_api.h> 103 #include <ecore_mcp.h> 104 #endif 105 106 107 108 #ifndef STRINGIFY 109 #define XSTRINGIFY(x) #x 110 #define STRINGIFY(x) XSTRINGIFY(x) 111 #endif 112 #define QEDE_STR_SIZE 32 113 /* Product Identification Banner */ 114 #define QEDE_PRODUCT_INFO\ 115 "QLogic FastLinQ QL45xxx " STRINGIFY(MAJVERSION) \ 116 "." STRINGIFY(MINVERSION) "." STRINGIFY(REVVERSION) 117 118 /* 119 * Debug Infrastructure 120 */ 121 #define DEBUG_NONE 0x0 122 #define DEBUG_ATTACH 0x1 123 124 #ifndef DEBUG_LEVEL 125 #define DEBUG_LEVEL DEBUG_NONE 126 #endif 127 128 #define qede_dbg(MASK, ptr, fmt, ...) \ 129 do { \ 130 if (DEBUG_LEVEL & (MASK)) { \ 131 qede_print("!%s(%d) STRINGIFY(MASK):" fmt, __func__, \ 132 (ptr)->instance, \ 133 ##__VA_ARGS__);\ 134 } \ 135 } while (0); 136 137 #define qede_info(ptr, fmt, ...) \ 138 do { \ 139 qede_print("!%s(%d):" fmt, __func__, (ptr)->instance, \ 140 ##__VA_ARGS__); \ 141 } while (0); 142 143 #define qede_warn(ptr, fmt, ...) \ 144 do { \ 145 qede_print_err("!%s(%d):" fmt, __func__, (ptr)->instance, \ 146 ##__VA_ARGS__); \ 147 } while (0); 148 149 #ifdef __sparc 150 #define QEDE_PAGE_ALIGNMENT 0x0000000000002000ull 151 #define QEDE_PAGE_SIZE 0x0000000000002000ull 152 #else 153 #define QEDE_PAGE_ALIGNMENT 0x0000000000001000ull 154 #define QEDE_PAGE_SIZE 0x0000000000001000ull 155 #endif 156 157 #define LE_TO_HOST_64 LE_64 158 #define HOST_TO_LE_64 LE_64 159 #define HOST_TO_LE_32 LE_32 160 #define LE_TO_HOST_32 LE_32 161 #define HOST_TO_LE_16 LE_16 162 #define LE_TO_HOST_16 LE_16 163 164 165 166 #define QEDE_LSO_MAXLEN 65535 167 168 #define BUF_2K_SIZE 2048 169 #define BUF_2K_ALIGNMENT BUF_2K_SIZE 170 171 #define MIN_TX_RING_COUNT 1 172 #define MAX_TX_RING_COUNT 1 173 #define DEFAULT_TX_RING_COUNT 1 174 #define MAX_TC_COUNT 1 175 #define DEFAULT_TRFK_CLASS_COUNT 1 176 177 #define MIN_TX_RING_SIZE 1024 178 #define DEFAULT_TX_RING_SIZE 8192 179 180 #define DEFAULT_TX_COPY_THRESHOLD 256 181 #define DEFAULT_TX_RECYCLE_THRESHOLD 128 182 183 #define TX_RING_MASK (tx_ring->tx_ring_size - 1) 184 185 #define IP_ALIGNMENT_BYTES 2 186 #define QEDE_MAX_ETHER_HDR 18 187 188 #define MIN_FASTPATH_COUNT 1 189 #define MAX_FASTPATH_COUNT 6 190 #define DEFAULT_FASTPATH_COUNT 4 191 192 #define MIN_RX_RING_SIZE 1024 193 #define DEFAULT_RX_RING_SIZE 8192 194 #define MAX_RX_RING_SIZE DEFAULT_RX_RING_SIZE 195 196 #define MIN_RX_BUF_SIZE 2048 197 #define MAX_RX_BUF_SIZE 2048 198 #define DEFAULT_RX_BUF_SIZE 2048 199 200 #define DEFAULT_RX_COPY_THRESHOLD 128 201 #define RX_RING_MASK (rx_ring->rx_buf_count - 1) 202 #define MIN_RX_BUF_COUNT MIN_RX_RING_SIZE 203 #define MAX_RX_BUF_COUNT MAX_RX_RING_SIZE 204 #define DEFAULT_RX_BUF_COUNT DEFAULT_RX_RING_SIZE 205 #define RX_LOW_BUFFER_THRESHOLD 128 206 207 #define USER_OPTION_CKSUM_NONE 0x0 208 #define USER_OPTION_CKSUM_L3 0x1 209 #define USER_OPTION_CKSUM_L3_L4 0x2 210 #define DEFAULT_CKSUM_OFFLOAD USER_OPTION_CKSUM_L3_L4 211 212 #define QEDE_OFFLOAD_NONE 0x00000000 213 #define QEDE_OFFLOAD_TX_IP_CKSUM 0x00000001 214 #define QEDE_OFFLOAD_RX_IP_CKSUM 0x00000002 215 #define QEDE_OFFLOAD_TX_TCP_CKSUM 0x00000004 216 #define QEDE_OFFLOAD_RX_TCP_CKSUM 0x00000008 217 #define QEDE_OFFLOAD_TX_UDP_CKSUM 0x00000010 218 #define QEDE_OFFLOAD_RX_UDP_CKSUM 0x00000020 219 220 #define DEFAULT_JUMBO_MTU 9000 221 #define MIN_MTU ETHERMTU 222 #define MAX_MTU DEFAULT_JUMBO_MTU 223 #define DEFAULT_MTU ETHERMTU 224 225 #define DEFAULT_ECORE_DEBUG_LEVEL ECORE_LEVEL_VERBOSE 226 227 228 #define DEFAULT_ECORE_DEBUG_MODULE ECORE_MSG_DRV 229 230 #define VLAN_TAGSZ 0x4 231 232 #define MAX_TC 1 233 234 #define DUPLEX_HALF 0 235 #define DUPLEX_FULL 1 236 237 #define ETH_ALLEN 6 238 239 #define MAC_STRING "%2x:%2x:%2x:%2x:%2x:%2x" 240 #define MACTOSTR(a) a[0], a[1], a[2], a[3], a[4], a[5] 241 242 #define MAX_MC_SOFT_LIMIT 1024 243 244 #define qede_delay(_msecs_) delay(drv_usectohz(_msecs_ * 1000)) 245 246 #define QEDE_CMD 73 247 248 249 typedef struct _KstatRingMap 250 { 251 uint32_t idx; /* ring index */ 252 void * qede; /* reference back to qede_t */ 253 } KstatRingMap; 254 255 #define IS_ETH_MULTICAST(eth_addr) \ 256 (((unsigned char *) (eth_addr))[0] & ((unsigned char) 0x01)) 257 258 #define IS_ETH_ADDRESS_EQUAL(eth_addr1, eth_addr2) \ 259 ((((unsigned char *) (eth_addr1))[0] == \ 260 ((unsigned char *) (eth_addr2))[0]) && \ 261 (((unsigned char *) (eth_addr1))[1] == \ 262 ((unsigned char *) (eth_addr2))[1]) && \ 263 (((unsigned char *) (eth_addr1))[2] == \ 264 ((unsigned char *) (eth_addr2))[2]) && \ 265 (((unsigned char *) (eth_addr1))[3] == \ 266 ((unsigned char *) (eth_addr2))[3]) && \ 267 (((unsigned char *) (eth_addr1))[4] == \ 268 ((unsigned char *) (eth_addr2))[4]) && \ 269 (((unsigned char *) (eth_addr1))[5] == \ 270 ((unsigned char *) (eth_addr2))[5])) 271 272 #define COPY_ETH_ADDRESS(src, dst) \ 273 ((unsigned char *) (dst))[0] = ((unsigned char *) (src))[0]; \ 274 ((unsigned char *) (dst))[1] = ((unsigned char *) (src))[1]; \ 275 ((unsigned char *) (dst))[2] = ((unsigned char *) (src))[2]; \ 276 ((unsigned char *) (dst))[3] = ((unsigned char *) (src))[3]; \ 277 ((unsigned char *) (dst))[4] = ((unsigned char *) (src))[4]; \ 278 ((unsigned char *) (dst))[5] = ((unsigned char *) (src))[5]; 279 280 281 union db_prod { 282 struct eth_db_data data; 283 uint32_t raw; 284 }; 285 286 struct qede; 287 struct qede_fastpath; 288 struct qede_rx_ring; 289 struct qede_tx_pktinfo_s; 290 291 typedef struct qede_tx_ring { 292 struct qede_fastpath *fp; 293 struct qede *qede; 294 uint32_t tx_queue_index; 295 uint16_t *hw_cons_ptr; 296 297 /* pointer to driver ring control */ 298 struct ecore_chain tx_bd_ring; 299 u16 sw_tx_cons; 300 u16 sw_tx_prod; 301 u16 bd_ring_size; 302 303 /* From ecore_sp_tx_queue_start() */ 304 void __iomem *doorbell_addr; 305 ddi_acc_handle_t doorbell_handle; 306 307 /* Saved copy of doorbell data for this tx queue */ 308 union db_prod tx_db; 309 310 uint32_t fp_idx; 311 kmutex_t tx_lock; 312 int tx_buf_size; 313 uint32_t tx_ring_size; 314 bool queue_started; 315 mac_ring_handle_t mac_ring_handle; 316 317 /* pre-allocated bcopy packets */ 318 qede_tx_bcopy_list_t bcopy_list; 319 /* pre-allocated dma handles */ 320 qede_dma_handles_list_t dmah_list; 321 /* List of recycle entires for tx packets */ 322 qede_tx_recycle_list_t *tx_recycle_list; 323 324 #ifdef DBLK_DMA_PREMAP 325 pm_handle_t pm_handle; 326 #endif 327 /* dma_handle for tx bd ring */ 328 ddi_dma_handle_t tx_bd_dmah; 329 ddi_dma_handle_t tx_pbl_dmah; 330 331 bool tx_q_sleeping; 332 333 uint64_t tx_pkt_count; 334 uint64_t tx_byte_count; 335 uint64_t tx_pkt_dropped; 336 uint64_t tx_copy_count; 337 uint64_t tx_bind_count; 338 uint64_t tx_bind_fail; 339 uint64_t tx_premap_count; 340 uint64_t tx_premap_fail; 341 uint64_t tx_pullup_count; 342 uint64_t tx_too_many_cookies; 343 uint64_t tx_lso_pkt_count; 344 uint64_t tx_ring_pause; 345 uint64_t tx_too_many_mblks; 346 uint64_t tx_mapped_pkts; 347 uint64_t tx_jumbo_pkt_count; 348 struct ecore_queue_cid *p_cid; 349 } qede_tx_ring_t; 350 351 352 typedef struct qede_vector_info { 353 /* 354 * Pointer to a fastpath structure, 355 * or to a hwfnc. 356 */ 357 void *fp; 358 struct qede *qede; 359 uint32_t vect_index; 360 bool handler_added; 361 /* set and cleared by ISR, checked by stop path 362 * when waiting for quiesce 363 */ 364 bool in_isr; 365 } qede_vector_info_t; 366 367 368 typedef struct qede_fastpath { 369 qede_vector_info_t *vect_info; 370 371 /* Status block associated with this fp */ 372 ddi_dma_handle_t sb_dma_handle; 373 ddi_acc_handle_t sb_acc_handle; 374 struct status_block *sb_virt; 375 uint64_t sb_phys; 376 377 struct ecore_sb_info *sb_info; 378 struct qede_rx_ring *rx_ring; 379 qede_tx_ring_t *tx_ring[MAX_TC]; 380 struct qede *qede; 381 382 uint32_t fp_index; 383 uint32_t fp_hw_eng_index; 384 uint32_t vport_id; /* */ 385 uint32_t stats_id; /* vport id to hold stats */ 386 uint32_t rx_queue_index; 387 uint32_t rss_id; 388 kmutex_t fp_lock; 389 uint32_t disabled_by_poll; 390 } qede_fastpath_t; 391 392 enum qede_agg_state { 393 QEDE_AGG_STATE_NONE = 0, 394 QEDE_AGG_STATE_START = 1, 395 QEDE_AGG_STATE_ERROR = 2 396 }; 397 398 #define QEDE_MAX_BD_PER_AGG 16 399 struct qede_rx_buffer_s; 400 typedef struct qede_lro_info { 401 uint16_t pars_flags; 402 uint16_t pad; 403 uint16_t vlan_tag; 404 uint16_t bd_count; 405 uint32_t rss_hash; 406 uint32_t header_len; 407 uint32_t free_buffer_count; 408 struct qede_rx_buffer_s *rx_buffer[QEDE_MAX_BD_PER_AGG]; 409 enum qede_agg_state agg_state; 410 } qede_lro_info_t; 411 412 typedef struct qede_dma_info_s { 413 ddi_acc_handle_t acc_handle; 414 ddi_dma_handle_t dma_handle; 415 u32 ncookies; 416 u32 offset; 417 u64 phys_addr; 418 void *virt_addr; 419 u32 pad; 420 } qede_dma_info_t; 421 422 enum rx_buf_state { 423 RX_BUF_STATE_FREE, 424 RX_BUF_STATE_WITH_FW, 425 RX_BUF_STATE_WITH_OS, 426 RX_BUF_STATE_WITH_DRV, 427 }; 428 429 struct qede_rx_buf_area; 430 431 typedef struct qede_rx_buffer_s { 432 qede_dma_info_t dma_info; 433 mblk_t *mp; 434 u32 index; 435 struct qede_rx_ring *rx_ring; 436 437 /* Recycle function */ 438 frtn_t recycle; 439 u32 ref_cnt; 440 enum rx_buf_state buf_state; 441 struct qede_rx_buf_area *rx_buf_area; 442 } qede_rx_buffer_t; 443 444 typedef struct qede_rx_buf_list_s { 445 kmutex_t lock; 446 u16 head, tail; 447 u32 num_entries; 448 qede_rx_buffer_t *buf_list[DEFAULT_RX_RING_SIZE]; 449 } qede_rx_buf_list_t; 450 451 typedef struct qede_rx_buf_area { 452 //kmutex_t rx_buf_area_lock; 453 qede_rx_buffer_t rx_buf_pool[DEFAULT_RX_RING_SIZE]; 454 455 qede_rx_buf_list_t active_buf_list; 456 qede_rx_buf_list_t passive_buf_list; 457 458 u32 bufs_per_page; 459 struct qede_rx_ring *rx_ring; 460 u32 inactive; 461 u32 buf_upstream; 462 } qede_rx_buf_area_t; 463 464 typedef struct qede_rx_ring { 465 uint32_t rx_buf_count; 466 uint32_t rx_buf_size; 467 /* 468 * Pointer to an array of producer indicies. 469 * Returned in call to ecore_sp_eth_rx_queue_start() 470 * during qede_start(). Driver uses address 471 * to update producer indicies for 472 * CQE and RX buffer chains. 473 */ 474 void __iomem *hw_rxq_prod_addr; 475 476 /* Pointer to hw cqe consumer index. 477 * Taken from sb_virt->pi_array after 478 * rx_ring has been started by calling 479 * ecore_sp_eth_rx_queue_start(). 480 * This value is little endian and requires 481 * swapping on big endian platforms. 482 * It is updated by ecore and read by 483 * the driver while processing rings. 484 */ 485 uint16_t *hw_cons_ptr; 486 487 u16 sw_rx_cons; 488 u16 sw_rx_prod; 489 u16 last_cqe_consumer; 490 491 /* 492 * Driver buffer descriptor ring defining 493 * buffers on a one-to-one releationship 494 * to ecore_chain rx_bd_ring. 495 */ 496 qede_rx_buffer_t *rx_buffers; 497 qede_rx_buf_area_t *rx_buf_area; 498 /* 499 * Descriptor rings returned from 500 * ecore_chain_alloc() 501 */ 502 struct ecore_chain rx_bd_ring; 503 struct ecore_chain rx_cqe_ring; 504 505 uint32_t rss_id; 506 bool queue_started; 507 bool mac_ring_started; 508 kmutex_t rx_lock; 509 kmutex_t rx_replen_lock; 510 mac_ring_handle_t mac_ring_handle; 511 u64 mr_gen_num; /* Mac rings generation number */ 512 uint32_t group_index; 513 qede_fastpath_t *fp; 514 struct qede *qede; 515 516 /* dma_handles for rx dma mem */ 517 ddi_dma_handle_t rx_bd_dmah; 518 ddi_dma_handle_t rx_cqe_dmah; 519 ddi_dma_handle_t rx_cqe_pbl_dmah; 520 uint32_t rx_copy_threshold; 521 uint32_t rx_low_buffer_threshold; 522 struct qede_lro_info lro_info[ETH_TPA_MAX_AGGS_NUM]; 523 uint32_t lro_active_count; 524 525 uint64_t rx_copy_cnt; 526 uint64_t rx_drop_cnt; 527 uint64_t rx_low_water_cnt; 528 uint64_t rx_poll_cnt; 529 uint64_t rx_reg_pkt_cnt; 530 uint64_t rx_jumbo_pkt_cnt; 531 uint64_t rx_lro_pkt_cnt; 532 uint64_t rx_byte_cnt; 533 uint64_t rx_pkt_cnt; 534 uint8_t intrEnableCnt; 535 uint8_t intrDisableCnt; 536 struct ecore_queue_cid *p_cid; 537 } qede_rx_ring_t; 538 539 typedef uint32_t qede_offload_t; 540 typedef struct qede_params { 541 qede_offload_t enabled_offloads; 542 boolean_t multi_promisc_fl; 543 boolean_t promisc_fl; 544 uint32_t link_state; 545 u32 loopback_mode; 546 } qede_params_t; 547 548 typedef struct qede_intr_context { 549 /* bit field indicating enable/disable state of vector */ 550 volatile uint32_t intr_state; 551 qede_vector_info_t *intr_vect_info; 552 int intr_vect_info_array_size; /* based on hw max vectors */ 553 ddi_intr_handle_t *intr_hdl_array; /* handle array from ddi_intr_alloc() */ 554 int intr_hdl_array_size; /* based on hw max vectors */ 555 int intr_types_available; /* from ddi_intr_get_supported_types */ 556 int intr_type_forced; /* from qede.conf */ 557 int intr_type_in_use; /* interrupt type currently used */ 558 int intr_vect_supported; /* from ddi_intr_get_nintrs */ 559 int intr_vect_available; /* from ddi_intr_get_navail */ 560 int intr_vect_to_request; /* intr count requested */ 561 int intr_vect_allocated; /* intr count taken */ 562 uint32_t intr_pri; 563 int intr_cap; 564 uint32_t intr_fp_vector_count; 565 enum ecore_int_mode intr_mode; 566 } qede_intr_context_t; 567 568 #define QEDE_LINK_PAUSE_AUTONEG_ENABLE (1 << 0) 569 #define QEDE_LINK_PAUSE_RX_ENABLE (1 << 1) 570 #define QEDE_LINK_PAUSE_TX_ENABLE (1 << 2) 571 572 typedef struct qede_props { 573 uint32_t link_speed; 574 boolean_t link_duplex; 575 boolean_t tx_pause; 576 boolean_t rx_pause; 577 time_t uptime; 578 } qede_props_t; 579 580 typedef struct qede_link_props { 581 uint8_t port_type; 582 boolean_t autoneg; 583 boolean_t asym_pause; 584 boolean_t pause; 585 boolean_t param_100000fdx; 586 boolean_t param_50000fdx; 587 boolean_t param_40000fdx; 588 boolean_t param_25000fdx; 589 boolean_t param_10000fdx; 590 boolean_t param_1000fdx; 591 boolean_t param_1000hdx; 592 } qede_link_props_t; 593 594 typedef struct qede_link_cfg { 595 boolean_t link_up; 596 uint32_t speed; 597 uint8_t duplex; 598 boolean_t autoneg; 599 uint32_t pause_cfg; 600 qede_link_props_t supp_capab; 601 qede_link_props_t adv_capab; 602 qede_link_props_t rem_capab; 603 uint32_t media; 604 uint32_t txr_data; 605 } qede_link_cfg_t; 606 607 enum qede_filter_type { 608 QEDE_FILTER_UCAST, 609 QEDE_FILTER_MCAST, 610 QEDE_FILTER_RX_MODE, 611 QEDE_MAX_FILTER_TYPES, 612 613 }; 614 615 enum qede_filter_rx_mode_type { 616 QEDE_FILTER_RX_MODE_REGULAR, 617 QEDE_FILTER_RX_MODE_MULTI_PROMISC, 618 QEDE_FILTER_RX_MODE_PROMISC, 619 }; 620 621 622 623 struct qede_mcast_filter_params { 624 enum qede_filter_rx_mode_type acc_flg; 625 struct ecore_filter_mcast mcast; 626 }; 627 628 #define QEDE_MAX_UCST_CNT 8 629 typedef struct qede_mac_addr { 630 struct ether_addr mac_addr; 631 boolean_t set; 632 } qede_mac_addr_t; 633 634 635 636 enum qede_state { 637 QEDE_STATE_UNKNOWN, 638 QEDE_STATE_ATTACHED, 639 QEDE_STATE_STARTING, /* Transitioning State */ 640 QEDE_STATE_STARTED, 641 QEDE_STATE_STOPPING, /* Transitioning State */ 642 QEDE_STATE_STOPPED, 643 QEDE_STATE_SUSPENDING, /* Transitioning State */ 644 QEDE_STATE_SUSPENDED, 645 QEDE_STATE_RESUMING, /* Transitioning State */ 646 QEDE_STATE_FAILED, 647 }; 648 649 enum qede_attach_resources { 650 QEDE_STRUCT_ALLOC = (1 << 0), 651 QEDE_FM = (1 << 1), 652 QEDE_PCI = (1 << 2), 653 QEDE_ECORE_HW_PREP = (1 << 3), 654 QEDE_SET_PARAMS = (1 << 4), 655 QEDE_CALLBACK = (1 << 5), 656 QEDE_IO_STRUCT_ALLOC = (1 << 6), 657 QEDE_INIT_LOCKS = (1 << 7), 658 QEDE_INTR_ALLOC = (1 << 8), 659 QEDE_INTR_CONFIG = (1 << 9), 660 QEDE_EDEV_CONFIG = (1 << 10), 661 QEDE_KSTAT_INIT = (1 << 11), 662 QEDE_GLD_INIT = (1 << 12), 663 QEDE_SP_INTR_ENBL = (1 << 13), 664 QEDE_ECORE_HW_INIT = (1 << 14), 665 /* 666 = (1 << 15), 667 = (1 << 16), 668 = (1 << 17), 669 = (1 << 18), 670 = (1 << 19), 671 = (1 << 20), 672 */ 673 }; 674 675 enum qede_vport_state { 676 QEDE_VPORT_UNKNOWN, 677 QEDE_VPORT_STARTED, 678 QEDE_VPORT_ON, 679 QEDE_VPORT_OFF, 680 QEDE_VPORT_STOPPED 681 }; 682 683 #define QEDE_MAX_GROUPS 1 684 typedef struct qede_mac_group { 685 int group_index; 686 mac_group_handle_t group_handle; 687 struct qede *qede; 688 } qede_mac_group_t; 689 690 typedef struct qede_link_input_params { 691 struct ecore_mcp_link_params default_link_params; 692 u32 loopback_mode; 693 }qede_link_input_params_t; 694 695 typedef struct qede { 696 struct ecore_dev edev; /* keep this at the beginning of the structure */ 697 dev_info_t *dip; 698 int instance; 699 enum qede_state qede_state; 700 #define MAX_QEDE_NAME_LEN 8 701 char name[MAX_QEDE_NAME_LEN]; 702 703 /* PCI access handle */ 704 ddi_acc_handle_t pci_cfg_handle; 705 706 /* BAR 0 - registers */ 707 ddi_acc_handle_t regs_handle; 708 off_t regview_size; 709 caddr_t regview; 710 uint64_t pci_bar0_base; 711 712 /* BAR 2 - doorbell */ 713 ddi_acc_handle_t doorbell_handle; 714 off_t doorbell_size; 715 caddr_t doorbell; 716 uint64_t pci_bar2_base; 717 718 /* Vport params */ 719 struct ecore_sp_vport_update_params vport_params[MAX_HWFNS_PER_DEVICE]; 720 struct ecore_rss_params rss_params[MAX_HWFNS_PER_DEVICE]; 721 enum qede_vport_state vport_state[MAX_HWFNS_PER_DEVICE]; 722 723 /* mac Layer related vars */ 724 mac_handle_t mac_handle; 725 qede_mac_group_t rx_groups[QEDE_MAX_GROUPS]; 726 qede_mac_group_t tx_groups[QEDE_MAX_GROUPS]; 727 728 u8 *sp_dpc; 729 /* 730 * pre-mapped buffer cache handle for TX 731 * used for getting sglist for mbkls 732 * that were already mapped in mac layer 733 */ 734 #ifdef DBLK_DMA_PREMAP 735 pm_handle_t pm_handle; 736 #endif 737 738 /* current operating paramters */ 739 uint32_t mtu; 740 uint32_t num_fp; 741 uint32_t mc_cnt; 742 743 uint32_t tx_ring_size; 744 uint32_t tx_buf_size; 745 uint16_t tx_recycle_threshold; 746 u16 pad; // remove later 747 748 int checksum; 749 qede_offload_t enabled_offloads; 750 uint32_t rx_ring_size; 751 uint32_t rx_buf_count; 752 uint32_t rx_buf_size; 753 uint32_t rx_copy_threshold; 754 uint32_t rx_low_buffer_threshold; 755 boolean_t lso_enable; 756 boolean_t lro_enable; 757 boolean_t jumbo_enable; 758 boolean_t log_enable; 759 uint32_t ecore_debug_level; 760 uint32_t ecore_debug_module; 761 boolean_t intr_coalesce; 762 uint32_t intr_rx_coal_usec; 763 uint32_t intr_tx_coal_usec; 764 765 /* From ecore_hw_init */ 766 uint32_t num_hwfns; 767 unsigned char ether_addr[ETHERADDRL]; 768 uint32_t num_tc; 769 770 qede_mac_addr_t ucst_mac[QEDE_MAX_UCST_CNT]; 771 uint32_t ucst_total; 772 uint32_t ucst_avail; 773 qede_mac_addr_t suspnd_mac_list[QEDE_MAX_UCST_CNT]; 774 775 776 /* software data structures for tx/rx */ 777 qede_intr_context_t intr_ctx; 778 qede_fastpath_t fp_array[MAX_FASTPATH_COUNT]; 779 struct ecore_sb_info sb_array[MAX_FASTPATH_COUNT]; 780 qede_rx_ring_t rx_array[MAX_FASTPATH_COUNT]; 781 qede_tx_ring_t tx_array[MAX_TC_COUNT][MAX_FASTPATH_COUNT]; 782 783 uint16_t tx_bcopy_threshold; 784 uint16_t pad1; /* remove later */ 785 786 /* status_block phys mem */ 787 bool sb_phy_mem_alloc; 788 789 kmutex_t drv_lock; 790 kmutex_t watch_lock; 791 uint32_t callback_flags; 792 enum qede_attach_resources attach_resources; 793 794 /* 795 * qede osal mem management queues 796 */ 797 qede_phys_mem_list_t phys_mem_list; 798 qede_mem_list_t mem_list; 799 800 qede_props_t props; 801 qede_link_cfg_t hwinit; 802 qede_link_cfg_t curcfg; 803 qede_params_t params; 804 volatile uint32_t plumbed; 805 qede_mcast_list_t mclist; 806 807 uint32_t mfw_ver; 808 809 char devName[QEDE_STR_SIZE]; 810 char version[QEDE_STR_SIZE]; 811 char versionFW[QEDE_STR_SIZE]; 812 char versionMFW[QEDE_STR_SIZE]; 813 char chip_name[QEDE_STR_SIZE]; 814 char chipID[QEDE_STR_SIZE]; 815 char intrAlloc[QEDE_STR_SIZE]; 816 char bus_dev_func[QEDE_STR_SIZE]; 817 char vendor_device[QEDE_STR_SIZE]; 818 819 uint64_t txTotalPkts; 820 uint64_t txTotalBytes; 821 uint64_t txTotalDiscards; 822 uint64_t rxTotalPkts; 823 uint64_t rxTotalBytes; 824 uint64_t rxTotalDiscards; 825 826 uint64_t intrFired; 827 kmutex_t kstat_lock; 828 kmutex_t gld_lock; 829 uint64_t intrSbCnt[MAX_FASTPATH_COUNT + 1]; 830 uint64_t intrSbNoChangeCnt[MAX_FASTPATH_COUNT + 1]; 831 uint64_t intrSbPollCnt[MAX_FASTPATH_COUNT + 1]; 832 uint64_t intrSbPollNoChangeCnt[MAX_FASTPATH_COUNT + 1]; 833 834 kstat_t *kstats; 835 kstat_t *kstats_link; 836 kstat_t *kstats_intr; 837 kstat_t *kstats_vport; 838 kstat_t *kstats_rxq[MAX_FASTPATH_COUNT]; 839 KstatRingMap kstats_rxq_map[MAX_FASTPATH_COUNT]; 840 kstat_t *kstats_txq[MAX_FASTPATH_COUNT]; 841 KstatRingMap kstats_txq_map[MAX_FASTPATH_COUNT]; 842 struct ecore_eth_stats save_stats; 843 844 mblk_t *stored_mp; 845 int mp_index; 846 qede_link_input_params_t link_input_params; /*(test) */ 847 uint32_t loop_back_mode; /*(test) */ 848 bool lb_linkup; /*(test) */ 849 uint32_t forced_speed_10G; 850 uint8_t pci_func; 851 void *nvm_buf; 852 void *nvm_buf_start; 853 uint32_t nvm_buf_size; 854 uint32_t copy_len; 855 uint8_t *reserved_buf; 856 int fm_cap; 857 uint64_t allocbFailures; 858 volatile uint32_t detach_unsafe; 859 860 } qede_t; 861 862 /* 863 * ioctl commands 864 */ 865 866 typedef enum { 867 QEDE_DRV_INFO = 2, 868 QEDE_RD_PCICFG, 869 QEDE_WR_PCICFG, 870 QEDE_RW_REG, 871 QEDE_RW_NVRAM, 872 QEDE_FUNC_INFO, 873 QEDE_MAC_ADDR 874 } qede_ioctl_cmd_t; 875 876 877 878 /* 879 * ioctl message structure for FW update utility 880 */ 881 882 /* regiser read/write commands */ 883 #define QEDE_REG_READ 0 884 #define QEDE_REG_WRITE 1 885 886 /* nvram read/write commands */ 887 #define QEDE_NVRAM_CMD_READ 0 888 #define QEDE_NVRAM_CMD_WRITE 1 889 #define QEDE_NVRAM_CMD_PUT_FILE_DATA 2 890 #define QEDE_NVRAM_CMD_SET_SECURE_MODE 3 891 #define QEDE_NVRAM_CMD_DEL_FILE 4 892 #define QEDE_NVRAM_CMD_PUT_FILE_BEGIN 5 893 #define QEDE_NVRAM_CMD_GET_NVRAM_RESP 6 894 895 typedef struct { 896 uint32_t cmd; 897 uint32_t unused1; 898 uint64_t off; 899 uint32_t size; 900 uint32_t rv; 901 char uabc[2048]; 902 uint64_t address; 903 void *ptr; 904 } qede_ioctl_data_t; 905 906 typedef struct { 907 uint32_t cmd; 908 uint32_t unused1; 909 uint64_t off; 910 uint32_t size; 911 uint32_t buf_size; 912 char uabc[2048]; 913 uint64_t cmd2; 914 #define START_NVM_WRITE 1 915 #define ACCUMULATE_NVM_BUF 2 916 #define STOP_NVM_WRITE 3 917 #define READ_BUF 4 918 void *ptr; 919 }qede_nvram_data_t; 920 921 typedef struct { 922 char drv_name[MAX_QEDE_NAME_LEN]; 923 char drv_version[QEDE_STR_SIZE]; 924 char mfw_version[QEDE_STR_SIZE]; 925 char stormfw_version[QEDE_STR_SIZE]; 926 uint32_t eeprom_dump_len; /* in bytes */ 927 uint32_t reg_dump_len; /* in bytes */ 928 char bus_info[QEDE_STR_SIZE]; 929 } qede_driver_info_t; 930 931 typedef struct { 932 uint32_t supported; /* Features this interface supports */ 933 uint32_t advertising; /* Features this interface advertises */ 934 uint32_t speed; /* The forced speed, 10Mb, 100Mb, gigabit */ 935 uint32_t duplex; /* Duplex, half or full */ 936 uint32_t port; /* Which connector port */ 937 uint32_t phy_address; /* port number*/ 938 uint32_t autoneg; /* Enable or disable autonegotiation */ 939 } qede_func_info_t; 940 941 942 typedef struct { 943 bool link_up; 944 u32 supported_caps; /* In SUPPORTED defs */ 945 u32 advertised_caps; /* In ADVERTISED defs */ 946 u32 lp_caps; /* In ADVERTISED defs */ 947 u32 speed; /* In Mb/s */ 948 u8 duplex; /* In DUPLEX defs */ 949 u8 port; /* In PORT defs */ 950 bool autoneg; 951 } qede_link_output_t; 952 953 #define PORT_FIBRE (1) 954 #define SUPPORTED_FIBRE (1 << 15) 955 #define SUPPORTED_Autoneg (1 << 16) 956 #define SUPPORTED_Pause (1 << 17) 957 #define SUPPORTED_Asym_Pause (1 << 18) 958 #define SUPPORTED_1000baseT_Half (1 << 19) 959 #define SUPPORTED_1000baseT_Full (1 << 20) 960 #define SUPPORTED_10000baseKR_Full (1 << 21) 961 #define SUPPORTED_20000baseKR2_Full (1 << 22) 962 #define SUPPORTED_40000baseKR4_Full (1 << 23) 963 #define SUPPORTED_40000baseCR4_Full (1 << 24) 964 #define SUPPORTED_40000baseSR4_Full (1 << 25) 965 #define SUPPORTED_40000baseLR4_Full (1 << 26) 966 967 968 969 typedef struct { 970 uint32_t cmd; 971 #define QEDE_PCICFG_READ 0x01 972 #define QEDE_PCICFG_WRITE 0x02 973 uint32_t reg; 974 uint32_t val; 975 uint32_t width; 976 } qede_pcicfg_rdw_t; 977 /* 978 * (Internal) return values from ioctl subroutines 979 * 980 */ 981 enum ioc_reply { 982 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 983 IOC_DONE, /* OK, reply sent */ 984 IOC_ACK, /* OK, just send ACK */ 985 IOC_REPLY, /* OK, just send reply */ 986 IOC_RESTART_ACK, /* OK, restart & ACK */ 987 IOC_RESTART_REPLY /* OK, restart & reply */ 988 }; 989 990 /* 991 * Loop Back Modes 992 */ 993 enum { 994 QEDE_LOOP_NONE, 995 QEDE_LOOP_INTERNAL, 996 QEDE_LOOP_EXTERNAL, 997 }; 998 999 /* Loopback test return values */ 1000 enum { 1001 QEDE_LB_TEST_OK, 1002 QEDE_LB_SEND_WAIT_QUEUE_ERR, 1003 QEDE_LB_NORCV_ERR, 1004 QEDE_LB_NOMEM_ERR, 1005 QEDE_LB_TX_QUEUE_ERR, 1006 QEDE_LB_SHORT_DATA_ERR, 1007 QEDE_LB_SEQUENCE_ERR, 1008 QEDE_LB_DATA_ERR, 1009 QEDE_LB_ERRCNT, 1010 QEDE_LB_NOT_SUPPORTED, 1011 QEDE_LB_TEST_CHECK_CABLE, 1012 QEDE_LB_TEST_IN_PROGRESS 1013 }; 1014 1015 extern qede_link_props_t qede_def_link_props; 1016 /* Functions exported by qede_cfg.c */ 1017 void qede_cfg_reset(qede_t *qede); 1018 void qede_cfg_init(qede_t *qede); 1019 1020 /* Functions exported by qede_gld.c */ 1021 boolean_t qede_gld_init(qede_t *qede); 1022 int qede_multicast(qede_t * qede, boolean_t flag, const uint8_t *ptr_mcaddr); 1023 int qede_set_filter_rx_mode(qede_t *qede, enum qede_filter_rx_mode_type type); 1024 int qede_set_rx_mac_mcast(qede_t *qede, enum ecore_filter_opcode opcode, 1025 uint8_t *mac, int mc_cnt); 1026 int qede_ucst_find(qede_t *qede, const uint8_t *mac_addr); 1027 int qede_clear_filters(qede_t *qede); 1028 /* Functions exported by qede_main.c */ 1029 int 1030 qede_stop(qede_t *); 1031 int 1032 qede_start(qede_t *); 1033 1034 #define QEDE_DOORBELL_WR qede_bar2_write32_tx_doorbell 1035 void 1036 qede_bar2_write32_tx_doorbell(qede_tx_ring_t *tx_ring, u32 val); 1037 void 1038 qede_enable_hw_intr(qede_fastpath_t *); 1039 void 1040 qede_disable_hw_intr(qede_fastpath_t *); 1041 1042 /* Functions exported by qede_dbg.c */ 1043 extern void 1044 qede_stacktrace(qede_t *); 1045 extern void 1046 qede_print_vport_params(qede_t *, 1047 struct ecore_sp_vport_update_params *); 1048 void 1049 qede_dump_single_mblk(qede_t *qede, mblk_t *mp); 1050 void 1051 qede_dump_mblk_chain_bnext_ptr(qede_t *qede, mblk_t *mp); 1052 void 1053 qede_dump_mblk_chain_bcont_ptr(qede_t *qede, mblk_t *mp); 1054 void 1055 qede_dump_bytes(char *, int); 1056 void qede_dump_reg_cqe(struct eth_fast_path_rx_reg_cqe *cqe); 1057 void qede_dump_start_lro_cqe(struct eth_fast_path_rx_tpa_start_cqe *); 1058 void qede_dump_cont_lro_cqe(struct eth_fast_path_rx_tpa_cont_cqe *); 1059 void qede_dump_end_lro_cqe(struct eth_fast_path_rx_tpa_end_cqe *); 1060 void qede_dump_mblk_chain_bcont_ptr(qede_t *, mblk_t *); 1061 1062 /* Functions exported by qede_fp.c */ 1063 mblk_t *qede_fp_poll(void *arg, int poll_bytes, int poll_pkts); 1064 int qede_fp_stat(mac_ring_driver_t rh, uint_t stat, u64 *val); 1065 mblk_t * 1066 qede_process_fastpath(qede_fastpath_t *fp, 1067 int nbytes, int npkts, int *work_done); 1068 void 1069 qede_desc_dma_mem_sync(ddi_dma_handle_t *dma_handle, 1070 uint_t start, uint_t count, uint_t range, 1071 uint_t unit_size, uint_t direction); 1072 1073 /* Functions exported by qede_osal.c */ 1074 u32 qede_osal_cleanup(qede_t *qede); 1075 int 1076 qede_osal_find_dma_handle_for_block(qede_t *qede, void *addr, 1077 ddi_dma_handle_t *dma_handle); 1078 1079 /* Functions exported by qede_main.c */ 1080 int 1081 qede_get_mag_elem(qede_rx_ring_t *, qede_rx_buffer_t *); 1082 void 1083 qede_update_rx_q_producer(qede_rx_ring_t *rx_ring); 1084 void qede_get_link_info(struct ecore_hwfn *hwfn,struct qede_link_cfg *lnkcfg); 1085 int 1086 qede_put_to_passive_list(qede_rx_ring_t *rx_ring, qede_rx_buffer_t *rx_buffer); 1087 qede_rx_buffer_t * 1088 qede_get_from_active_list(qede_rx_ring_t *, uint32_t *); 1089 void 1090 qede_replenish_rx_buffers(qede_rx_ring_t *); 1091 void 1092 qede_recycle_copied_rx_buffer(qede_rx_buffer_t *rx_buffer); 1093 boolean_t qede_kstat_init(qede_t *qede); 1094 void qede_kstat_fini(qede_t *qede); 1095 1096 /* Functions exported by qede_main.c */ 1097 void qede_update_media_info(struct ecore_dev *, qede_link_cfg_t *); 1098 mac_ether_media_t qede_link_to_media(qede_link_cfg_t *, uint32_t); 1099 #endif /* _QEDE_H */ 1100