xref: /illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_int.c (revision 14b24e2b79293068c8e016a69ef1d872fb5e2fd5)
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1,  (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1,  (the "License").
26 
27 * You may not use this file except in compliance with the License.
28 
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31 
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35 
36 #include "bcm_osal.h"
37 #include "ecore.h"
38 #include "ecore_spq.h"
39 #include "reg_addr.h"
40 #include "ecore_gtt_reg_addr.h"
41 #include "ecore_init_ops.h"
42 #include "ecore_rt_defs.h"
43 #include "ecore_int.h"
44 #include "reg_addr.h"
45 #include "ecore_hw.h"
46 #include "ecore_sriov.h"
47 #include "ecore_vf.h"
48 #include "ecore_hw_defs.h"
49 #include "ecore_hsi_common.h"
50 #include "ecore_mcp.h"
51 #include "ecore_dbg_fw_funcs.h"
52 
53 #ifdef DIAG
54 /* This is nasty, but diag is using the drv_dbg_fw_funcs.c [non-ecore flavor],
55  * and so the functions are lacking ecore prefix.
56  * If there would be other clients needing this [or if the content that isn't
57  * really optional there would increase], we'll need to re-think this.
58  */
59 enum dbg_status dbg_read_attn(struct ecore_hwfn *dev,
60 							  struct ecore_ptt *ptt,
61 							  enum block_id block,
62 							  enum dbg_attn_type attn_type,
63 							  bool clear_status,
64 							  struct dbg_attn_block_result *results);
65 
66 enum dbg_status dbg_parse_attn(struct ecore_hwfn *dev,
67 							   struct dbg_attn_block_result *results);
68 
69 const char* dbg_get_status_str(enum dbg_status status);
70 
71 #define ecore_dbg_read_attn(hwfn, ptt, id, type, clear, results) \
72 	dbg_read_attn(hwfn, ptt, id, type, clear, results)
73 #define ecore_dbg_parse_attn(hwfn, results) \
74 	dbg_parse_attn(hwfn, results)
75 #define ecore_dbg_get_status_str(status) \
76 	dbg_get_status_str(status)
77 #endif
78 
79 struct ecore_pi_info {
80 	ecore_int_comp_cb_t comp_cb;
81 	void *cookie; /* Will be sent to the completion callback function */
82 };
83 
84 struct ecore_sb_sp_info {
85 	struct ecore_sb_info sb_info;
86 	/* per protocol index data */
87 	struct ecore_pi_info pi_info_arr[PIS_PER_SB];
88 };
89 
90 enum ecore_attention_type {
91 	ECORE_ATTN_TYPE_ATTN,
92 	ECORE_ATTN_TYPE_PARITY,
93 };
94 
95 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
96 	ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
97 
98 struct aeu_invert_reg_bit {
99 	char bit_name[30];
100 
101 #define ATTENTION_PARITY		(1 << 0)
102 
103 #define ATTENTION_LENGTH_MASK		(0x00000ff0)
104 #define ATTENTION_LENGTH_SHIFT		(4)
105 #define ATTENTION_LENGTH(flags)		(((flags) & ATTENTION_LENGTH_MASK) >> \
106 					 ATTENTION_LENGTH_SHIFT)
107 #define ATTENTION_SINGLE		(1 << ATTENTION_LENGTH_SHIFT)
108 #define ATTENTION_PAR			(ATTENTION_SINGLE | ATTENTION_PARITY)
109 #define ATTENTION_PAR_INT		((2 << ATTENTION_LENGTH_SHIFT) | \
110 					 ATTENTION_PARITY)
111 
112 /* Multiple bits start with this offset */
113 #define ATTENTION_OFFSET_MASK		(0x000ff000)
114 #define ATTENTION_OFFSET_SHIFT		(12)
115 
116 #define ATTENTION_BB_MASK		(0x00700000)
117 #define ATTENTION_BB_SHIFT		(20)
118 #define ATTENTION_BB(value)		(value << ATTENTION_BB_SHIFT)
119 #define ATTENTION_BB_DIFFERENT		(1 << 23)
120 
121 #define	ATTENTION_CLEAR_ENABLE		(1 << 28)
122 	unsigned int flags;
123 
124 	/* Callback to call if attention will be triggered */
125 	enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
126 
127 	enum block_id block_index;
128 };
129 
130 struct aeu_invert_reg {
131 	struct aeu_invert_reg_bit bits[32];
132 };
133 
134 #define MAX_ATTN_GRPS		(8)
135 #define NUM_ATTN_REGS		(9)
136 
ecore_mcp_attn_cb(struct ecore_hwfn * p_hwfn)137 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
138 {
139 	u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
140 
141 	DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
142 		tmp);
143 	ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
144 		 0xffffffff);
145 
146 	return ECORE_SUCCESS;
147 }
148 
149 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK		(0x3c000)
150 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT	(14)
151 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK		(0x03fc0)
152 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT	(6)
153 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK	(0x00020)
154 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT	(5)
155 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK	(0x0001e)
156 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT	(1)
157 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK	(0x1)
158 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT	(0)
159 #define ECORE_PSWHST_ATTENTION_VF_DISABLED		(0x1)
160 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS		(0x1)
161 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK 	(0x1)
162 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT	(0)
163 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK	(0x1e)
164 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT	(1)
165 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK	(0x20)
166 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT	(5)
167 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK	(0x3fc0)
168 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT	(6)
169 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK	(0x3c000)
170 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT	(14)
171 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK	(0x3fc0000)
172 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT	(18)
ecore_pswhst_attn_cb(struct ecore_hwfn * p_hwfn)173 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
174 {
175 	u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, PSWHST_REG_VF_DISABLED_ERROR_VALID);
176 
177 	/* Disabled VF access */
178 	if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
179 		u32 addr, data;
180 
181 		addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
182 				PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
183 		data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
184 				PSWHST_REG_VF_DISABLED_ERROR_DATA);
185 		DP_INFO(p_hwfn->p_dev, "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x] Write [0x%02x] Addr [0x%08x]\n",
186 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK) >>
187 			     ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
188 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK) >>
189 			     ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
190 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
191 			     ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
192 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
193 			     ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
194 			(u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
195 			     ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
196 			addr);
197 	}
198 
199 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
200 		       PSWHST_REG_INCORRECT_ACCESS_VALID);
201 	if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
202 		u32 addr, data, length;
203 
204 		addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
205 				PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
206 		data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
207 				PSWHST_REG_INCORRECT_ACCESS_DATA);
208 		length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
209 				  PSWHST_REG_INCORRECT_ACCESS_LENGTH);
210 
211 		DP_INFO(p_hwfn->p_dev, "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n",
212 			addr, length,
213 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
214 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
215 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
216 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
217 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
218 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
219 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
220 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
221 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
222 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
223 			(u8)((data & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
224 			     ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
225 			data);
226 	}
227 
228 	/* TODO - We know 'some' of these are legal due to virtualization,
229 	 * but is it true for all of them?
230 	 */
231 	return ECORE_SUCCESS;
232 }
233 
234 #define ECORE_GRC_ATTENTION_VALID_BIT		(1 << 0)
235 #define ECORE_GRC_ATTENTION_ADDRESS_MASK	(0x7fffff << 0)
236 #define ECORE_GRC_ATTENTION_RDWR_BIT		(1 << 23)
237 #define ECORE_GRC_ATTENTION_MASTER_MASK		(0xf << 24)
238 #define ECORE_GRC_ATTENTION_MASTER_SHIFT	(24)
239 #define ECORE_GRC_ATTENTION_PF_MASK		(0xf)
240 #define ECORE_GRC_ATTENTION_VF_MASK		(0xff << 4)
241 #define ECORE_GRC_ATTENTION_VF_SHIFT		(4)
242 #define ECORE_GRC_ATTENTION_PRIV_MASK		(0x3 << 14)
243 #define ECORE_GRC_ATTENTION_PRIV_SHIFT		(14)
244 #define ECORE_GRC_ATTENTION_PRIV_VF		(0)
grc_timeout_attn_master_to_str(u8 master)245 static const char* grc_timeout_attn_master_to_str(u8 master)
246 {
247 	switch(master) {
248 	case 1: return "PXP";
249 	case 2: return "MCP";
250 	case 3: return "MSDM";
251 	case 4: return "PSDM";
252 	case 5: return "YSDM";
253 	case 6: return "USDM";
254 	case 7: return "TSDM";
255 	case 8: return "XSDM";
256 	case 9: return "DBU";
257 	case 10: return "DMAE";
258 	default:
259 		return "Unkown";
260 	}
261 }
262 
ecore_grc_attn_cb(struct ecore_hwfn * p_hwfn)263 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
264 {
265 	u32 tmp, tmp2;
266 
267 	/* We've already cleared the timeout interrupt register, so we learn
268 	 * of interrupts via the validity register
269 	 */
270 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
271 		       GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
272 	if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT))
273 		goto out;
274 
275 	/* Read the GRC timeout information */
276 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
277 		       GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
278 	tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
279 			GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
280 
281 	DP_INFO(p_hwfn->p_dev,
282 		"GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
283 		tmp2, tmp,
284 		(tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
285 		(tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
286 		grc_timeout_attn_master_to_str((tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >>
287 					       ECORE_GRC_ATTENTION_MASTER_SHIFT),
288 		(tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
289 		(((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
290 		  ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
291 		 ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
292 		(tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
293 		ECORE_GRC_ATTENTION_VF_SHIFT);
294 
295 out:
296 	/* Regardles of anything else, clean the validity bit */
297 	ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
298 		 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
299 	return ECORE_SUCCESS;
300 }
301 
302 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
303 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
304 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
305 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
306 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
307 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
308 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
309 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
310 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME	(1 << 22)
311 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
312 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
313 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
314 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
ecore_pglub_rbc_attn_cb(struct ecore_hwfn * p_hwfn)315 static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
316 {
317 	u32 tmp;
318 
319 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
320 		       PGLUE_B_REG_TX_ERR_WR_DETAILS2);
321 	if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
322 		u32 addr_lo, addr_hi, details;
323 
324 		addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
325 				   PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
326 		addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
327 				   PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
328 		details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
329 				   PGLUE_B_REG_TX_ERR_WR_DETAILS);
330 
331 		DP_INFO(p_hwfn, "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
332 			addr_hi, addr_lo, details,
333 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
334 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
335 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
336 			tmp,
337 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0),
338 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0),
339 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0));
340 	}
341 
342 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
343 		       PGLUE_B_REG_TX_ERR_RD_DETAILS2);
344 	if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
345 		u32 addr_lo, addr_hi, details;
346 
347 		addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
348 				   PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
349 		addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
350 				   PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
351 		details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
352 				   PGLUE_B_REG_TX_ERR_RD_DETAILS);
353 
354 		DP_INFO(p_hwfn, "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
355 			addr_hi, addr_lo, details,
356 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
357 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >> ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
358 			(u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
359 			tmp,
360 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0),
361 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0),
362 			(u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0));
363 	}
364 
365 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
366 		       PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
367 	if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
368 		DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp);
369 
370 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
371 		       PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
372 	if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
373 		u32 addr_hi, addr_lo;
374 
375 		addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
376 				   PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
377 		addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
378 				   PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
379 
380 		DP_INFO(p_hwfn, "ICPL eror - %08x [Address %08x:%08x]\n",
381 			tmp, addr_hi, addr_lo);
382 	}
383 
384 	tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
385 		       PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
386 	if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
387 		u32 addr_hi, addr_lo, details;
388 
389 		addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
390 				   PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
391 		addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
392 				   PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
393 		details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
394 				   PGLUE_B_REG_VF_ILT_ERR_DETAILS);
395 
396 		DP_INFO(p_hwfn, "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
397 			details, tmp, addr_hi, addr_lo);
398 	}
399 
400 	/* Clear the indications */
401 	ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
402 		 PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
403 
404 	return ECORE_SUCCESS;
405 }
406 
ecore_fw_assertion(struct ecore_hwfn * p_hwfn)407 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
408 {
409 	DP_NOTICE(p_hwfn, false, "FW assertion!\n");
410 
411 	ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
412 
413 	return ECORE_INVAL;
414 }
415 
416 static enum _ecore_status_t
ecore_general_attention_35(struct ecore_hwfn * p_hwfn)417 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
418 {
419 	DP_INFO(p_hwfn, "General attention 35!\n");
420 
421 	return ECORE_SUCCESS;
422 }
423 
424 #define ECORE_DORQ_ATTENTION_REASON_MASK (0xfffff)
425 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
426 #define ECORE_DORQ_ATTENTION_SIZE_MASK	 (0x7f0000)
427 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT	 (16)
428 
ecore_dorq_attn_cb(struct ecore_hwfn * p_hwfn)429 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
430 {
431 	u32 reason;
432 
433 	reason = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
434 		 ECORE_DORQ_ATTENTION_REASON_MASK;
435 	if (reason) {
436 		u32 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
437 				       DORQ_REG_DB_DROP_DETAILS);
438 
439 		DP_INFO(p_hwfn->p_dev,
440 			"DORQ db_drop: adress 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n",
441 			 ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
442 				  DORQ_REG_DB_DROP_DETAILS_ADDRESS),
443 			(u16)(details & ECORE_DORQ_ATTENTION_OPAQUE_MASK),
444 			((details & ECORE_DORQ_ATTENTION_SIZE_MASK) >>
445 			 ECORE_DORQ_ATTENTION_SIZE_SHIFT) * 4, reason);
446 	}
447 
448 	return ECORE_INVAL;
449 }
450 
ecore_tm_attn_cb(struct ecore_hwfn * p_hwfn)451 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
452 {
453 #ifndef ASIC_ONLY
454 	if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
455 		u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
456 				   TM_REG_INT_STS_1);
457 
458 		if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
459 			    TM_REG_INT_STS_1_PEND_CONN_SCAN))
460 			return ECORE_INVAL;
461 
462 		if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
463 			   TM_REG_INT_STS_1_PEND_CONN_SCAN))
464 			DP_INFO(p_hwfn, "TM attention on emulation - most likely results of clock-ratios\n");
465 		val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
466 		val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
467 		       TM_REG_INT_MASK_1_PEND_TASK_SCAN;
468 		ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
469 
470 		return ECORE_SUCCESS;
471 	}
472 #endif
473 
474 	return ECORE_INVAL;
475 }
476 
477 /* Instead of major changes to the data-structure, we have a some 'special'
478  * identifiers for sources that changed meaning between adapters.
479  */
480 enum aeu_invert_reg_special_type {
481 	AEU_INVERT_REG_SPECIAL_CNIG_0,
482 	AEU_INVERT_REG_SPECIAL_CNIG_1,
483 	AEU_INVERT_REG_SPECIAL_CNIG_2,
484 	AEU_INVERT_REG_SPECIAL_CNIG_3,
485 	AEU_INVERT_REG_SPECIAL_MAX,
486 };
487 
488 static struct aeu_invert_reg_bit
489 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
490 	{"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
491 	{"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
492 	{"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
493 	{"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
494 };
495 
496 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
497 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] =
498 {
499 	{
500 		{	/* After Invert 1 */
501 			{"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
502 		}
503 	},
504 
505 	{
506 		{	/* After Invert 2 */
507 			{"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
508 			{"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
509 			{"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglub_rbc_attn_cb, BLOCK_PGLUE_B},
510 			{"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
511 			{"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
512 			{"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
513 			{"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
514 			{"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
515 			{"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, BLOCK_PGLCS},
516 		}
517 	},
518 
519 	{
520 		{	/* After Invert 3 */
521 			{"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
522 		}
523 	},
524 
525 	{
526 		{	/* After Invert 4 */
527 			{"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE, ecore_fw_assertion, MAX_BLOCK_ID},
528 			{"General Attention %d", (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT), OSAL_NULL, MAX_BLOCK_ID},
529 			{"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE, ecore_general_attention_35, MAX_BLOCK_ID},
530 			{"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
531 				       ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0) , OSAL_NULL, BLOCK_NWS},
532 			{"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
533 					  ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), OSAL_NULL, BLOCK_NWS},
534 			{"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
535 				       ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), OSAL_NULL, BLOCK_NWM},
536 			{"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
537 					  ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), OSAL_NULL, BLOCK_NWM},
538 			{"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
539 			{"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
540 			{"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
541 			{"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
542 			{"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
543 			{"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
544 			{"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID },
545 			{"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
546 			{"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
547 			{"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
548 			{"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
549 			{"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
550 		}
551 	},
552 
553 	{
554 		{	/* After Invert 5 */
555 			{"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
556 			{"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
557 			{"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
558 			{"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
559 			{"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
560 			{"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
561 			{"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
562 			{"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
563 			{"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
564 			{"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
565 			{"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
566 			{"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
567 			{"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
568 			{"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
569 			{"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
570 			{"TSEM", ATTENTION_PAR_INT,  OSAL_NULL, BLOCK_TSEM},
571 		}
572 	},
573 
574 	{
575 		{	/* After Invert 6 */
576 			{"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
577 			{"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
578 			{"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
579 			{"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
580 			{"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
581 			{"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
582 			{"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
583 			{"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
584 			{"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
585 			{"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
586 			{"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
587 			{"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
588 			{"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
589 			{"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
590 			{"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
591 			{"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
592 		}
593 	},
594 
595 	{
596 		{	/* After Invert 7 */
597 			{"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
598 			{"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
599 			{"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
600 			{"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
601 			{"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
602 			{"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
603 			{"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
604 			{"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
605 			{"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
606 			{"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
607 			{"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
608 			{"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
609 			{"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
610 			{"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
611 			{"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
612 			{"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
613 			{"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
614 		}
615 	},
616 
617 	{
618 		{	/* After Invert 8 */
619 			{"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
620 			{"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
621 			{"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
622 			{"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
623 			{"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
624 			{"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
625 			{"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
626 			{"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
627 			{"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
628 			{"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
629 			{"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
630 			{"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
631 			{"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
632 			{"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
633 			{"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
634 			{"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
635 			{"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
636 			{"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
637 			{"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
638 			{"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
639 			{"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID },
640 		}
641 	},
642 
643 	{
644 		{	/* After Invert 9 */
645 			{"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
646 			{"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
647 			{"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
648 			{"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
649 			{"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL, MAX_BLOCK_ID },
650 		}
651 	},
652 
653 };
654 
655 static struct aeu_invert_reg_bit *
ecore_int_aeu_translate(struct ecore_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_bit)656 ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
657 			struct aeu_invert_reg_bit *p_bit)
658 {
659 	if (!ECORE_IS_BB(p_hwfn->p_dev))
660 		return p_bit;
661 
662 	if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
663 		return p_bit;
664 
665 	return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
666 				  ATTENTION_BB_SHIFT];
667 }
668 
ecore_int_is_parity_flag(struct ecore_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_bit)669 static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
670 				     struct aeu_invert_reg_bit *p_bit)
671 {
672 	return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
673 		  ATTENTION_PARITY);
674 }
675 
676 #define ATTN_STATE_BITS		(0xfff)
677 #define ATTN_BITS_MASKABLE	(0x3ff)
678 struct ecore_sb_attn_info {
679 	/* Virtual & Physical address of the SB */
680 	struct atten_status_block	*sb_attn;
681 	dma_addr_t			sb_phys;
682 
683 	/* Last seen running index */
684 	u16				index;
685 
686 	/* A mask of the AEU bits resulting in a parity error */
687 	u32				parity_mask[NUM_ATTN_REGS];
688 
689 	/* A pointer to the attention description structure */
690 	struct aeu_invert_reg		*p_aeu_desc;
691 
692 	/* Previously asserted attentions, which are still unasserted */
693 	u16				known_attn;
694 
695 	/* Cleanup address for the link's general hw attention */
696 	u32				mfw_attn_addr;
697 };
698 
ecore_attn_update_idx(struct ecore_hwfn * p_hwfn,struct ecore_sb_attn_info * p_sb_desc)699 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
700 				 struct ecore_sb_attn_info *p_sb_desc)
701 {
702 	u16 rc = 0, index;
703 
704 	OSAL_MMIOWB(p_hwfn->p_dev);
705 
706 	index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
707 	if (p_sb_desc->index != index) {
708 		p_sb_desc->index = index;
709 		rc = ECORE_SB_ATT_IDX;
710 	}
711 
712 	OSAL_MMIOWB(p_hwfn->p_dev);
713 
714 	return rc;
715 }
716 
717 /**
718  * @brief ecore_int_assertion - handles asserted attention bits
719  *
720  * @param p_hwfn
721  * @param asserted_bits newly asserted bits
722  * @return enum _ecore_status_t
723  */
ecore_int_assertion(struct ecore_hwfn * p_hwfn,u16 asserted_bits)724 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
725 						u16 asserted_bits)
726 {
727 	struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
728 	u32 igu_mask;
729 
730 	/* Mask the source of the attention in the IGU */
731 	igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
732 			    IGU_REG_ATTENTION_ENABLE);
733 	DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
734 		   igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
735 	igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
736 	ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
737 
738 	DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
739 		   "inner known ATTN state: 0x%04x --> 0x%04x\n",
740 		   sb_attn_sw->known_attn,
741 		   sb_attn_sw->known_attn | asserted_bits);
742 	sb_attn_sw->known_attn |= asserted_bits;
743 
744 	/* Handle MCP events */
745 	if (asserted_bits & 0x100) {
746 		ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
747 		/* Clean the MCP attention */
748 		ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
749 			 sb_attn_sw->mfw_attn_addr, 0);
750 	}
751 
752 	/* FIXME - this will change once we'll have GOOD gtt definitions */
753 	DIRECT_REG_WR(p_hwfn,
754 		      (u8 OSAL_IOMEM*)p_hwfn->regview +
755 		      GTT_BAR0_MAP_REG_IGU_CMD +
756 		      ((IGU_CMD_ATTN_BIT_SET_UPPER -
757 			IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
758 
759 	DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
760 		   asserted_bits);
761 
762 	return ECORE_SUCCESS;
763 }
764 
ecore_int_attn_print(struct ecore_hwfn * p_hwfn,enum block_id id,enum dbg_attn_type type,bool b_clear)765 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
766 				 enum block_id id, enum dbg_attn_type type,
767 				 bool b_clear)
768 {
769 	struct dbg_attn_block_result attn_results;
770 	enum dbg_status status;
771 
772 	OSAL_MEMSET(&attn_results, 0, sizeof(attn_results));
773 
774 	status = ecore_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type,
775 				     b_clear, &attn_results);
776 #ifdef ATTN_DESC
777 	if (status != DBG_STATUS_OK)
778 		DP_NOTICE(p_hwfn, true,
779 			  "Failed to parse attention information [status: %s]\n",
780 			  ecore_dbg_get_status_str(status));
781 	else
782 		ecore_dbg_parse_attn(p_hwfn, &attn_results);
783 #else
784 	if (status != DBG_STATUS_OK)
785 		DP_NOTICE(p_hwfn, true,
786 			  "Failed to parse attention information [status: %d]\n",
787 			  status);
788 	else
789 		ecore_dbg_print_attn(p_hwfn, &attn_results);
790 #endif
791 }
792 
793 /**
794  * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
795  * cause of the attention
796  *
797  * @param p_hwfn
798  * @param p_aeu - descriptor of an AEU bit which caused the attention
799  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
800  *  this bit to this group.
801  * @param bit_index - index of this bit in the aeu_en_reg
802  *
803  * @return enum _ecore_status_t
804  */
805 static enum _ecore_status_t
ecore_int_deassertion_aeu_bit(struct ecore_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_aeu,u32 aeu_en_reg,const char * p_bit_name,u32 bitmask)806 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
807 			      struct aeu_invert_reg_bit *p_aeu,
808 			      u32 aeu_en_reg,
809 			      const char *p_bit_name,
810 			      u32 bitmask)
811 {
812 	enum _ecore_status_t rc = ECORE_INVAL;
813 	bool b_fatal = false;
814 
815 	DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
816 		p_bit_name, bitmask);
817 
818 	/* Call callback before clearing the interrupt status */
819 	if (p_aeu->cb) {
820 		DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
821 			p_bit_name);
822 		rc = p_aeu->cb(p_hwfn);
823 	}
824 
825 	if (rc != ECORE_SUCCESS)
826 		b_fatal = true;
827 
828 	/* Print HW block interrupt registers */
829 	if (p_aeu->block_index != MAX_BLOCK_ID)
830 		ecore_int_attn_print(p_hwfn, p_aeu->block_index,
831 				     ATTN_TYPE_INTERRUPT, !b_fatal);
832 
833 	/* Reach assertion if attention is fatal */
834 	if (b_fatal) {
835 		DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
836 			  p_bit_name);
837 
838 		ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
839 	}
840 
841 	/* Prevent this Attention from being asserted in the future */
842 	if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
843 	    p_hwfn->p_dev->attn_clr_en) {
844 		u32 val;
845 		u32 mask = ~bitmask;
846 		val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
847 		ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
848 		DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
849 			p_bit_name);
850 	}
851 
852 	return rc;
853 }
854 
855 /**
856  * @brief ecore_int_deassertion_parity - handle a single parity AEU source
857  *
858  * @param p_hwfn
859  * @param p_aeu - descriptor of an AEU bit which caused the parity
860  * @param aeu_en_reg - address of the AEU enable register
861  * @param bit_index
862  */
ecore_int_deassertion_parity(struct ecore_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_aeu,u32 aeu_en_reg,u8 bit_index)863 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
864 					 struct aeu_invert_reg_bit *p_aeu,
865 					 u32 aeu_en_reg, u8 bit_index)
866 {
867 	u32 block_id = p_aeu->block_index, mask, val;
868 
869 	DP_NOTICE(p_hwfn->p_dev, false,
870 		  "%s parity attention is set [address 0x%08x, bit %d]\n",
871 		  p_aeu->bit_name, aeu_en_reg, bit_index);
872 
873 	if (block_id == MAX_BLOCK_ID)
874 		return;
875 
876 	ecore_int_attn_print(p_hwfn, block_id,
877 			     ATTN_TYPE_PARITY, false);
878 
879 	/* In A0, there's a single parity bit for several blocks */
880 	if (block_id == BLOCK_BTB) {
881 		ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
882 				     ATTN_TYPE_PARITY, false);
883 		ecore_int_attn_print(p_hwfn, BLOCK_MCP,
884 				     ATTN_TYPE_PARITY, false);
885 	}
886 
887 	/* Prevent this parity error from being re-asserted */
888 	mask = ~(0x1 << bit_index);
889 	val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
890 	ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
891 	DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
892 		p_aeu->bit_name);
893 }
894 
895 /**
896  * @brief - handles deassertion of previously asserted attentions.
897  *
898  * @param p_hwfn
899  * @param deasserted_bits - newly deasserted bits
900  * @return enum _ecore_status_t
901  *
902  */
ecore_int_deassertion(struct ecore_hwfn * p_hwfn,u16 deasserted_bits)903 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
904 						  u16 deasserted_bits)
905 {
906 	struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
907 	u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
908 	u8 i, j, k, bit_idx;
909 	enum _ecore_status_t rc = ECORE_SUCCESS;
910 
911 	/* Read the attention registers in the AEU */
912 	for (i = 0; i < NUM_ATTN_REGS; i++) {
913 		aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
914 					  MISC_REG_AEU_AFTER_INVERT_1_IGU +
915 					  i * 0x4);
916 		DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
917 			   "Deasserted bits [%d]: %08x\n",
918 			   i, aeu_inv_arr[i]);
919 	}
920 
921 	/* Handle parity attentions first */
922 	for (i = 0; i < NUM_ATTN_REGS; i++)
923 	{
924 		struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
925 		u32 parities;
926 
927 		aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
928 		en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
929 		parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
930 
931 		/* Skip register in which no parity bit is currently set */
932 		if (!parities)
933 			continue;
934 
935 		for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
936 			struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
937 
938 			if (ecore_int_is_parity_flag(p_hwfn, p_bit) &&
939 			    !!(parities & (1 << bit_idx)))
940 				ecore_int_deassertion_parity(p_hwfn, p_bit,
941 							     aeu_en, bit_idx);
942 
943 			bit_idx += ATTENTION_LENGTH(p_bit->flags);
944 		}
945 	}
946 
947 	/* Find non-parity cause for attention and act */
948 	for (k = 0; k < MAX_ATTN_GRPS; k++) {
949 		struct aeu_invert_reg_bit *p_aeu;
950 
951 		/* Handle only groups whose attention is currently deasserted */
952 		if (!(deasserted_bits & (1 << k)))
953 			continue;
954 
955 		for (i = 0; i < NUM_ATTN_REGS; i++) {
956 			u32 bits;
957 
958 			aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
959 				 i * sizeof(u32) +
960 				 k * sizeof(u32) * NUM_ATTN_REGS;
961 			en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
962 			bits = aeu_inv_arr[i] & en;
963 
964 			/* Skip if no bit from this group is currently set */
965 			if (!bits)
966 				continue;
967 
968 			/* Find all set bits from current register which belong
969 			 * to current group, making them responsible for the
970 			 * previous assertion.
971 			 */
972 			for (j = 0, bit_idx = 0; bit_idx < 32; j++)
973 			{
974 				long unsigned int bitmask;
975 				u8 bit, bit_len;
976 
977 				/* Need to account bits with changed meaning */
978 				p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
979 				p_aeu = ecore_int_aeu_translate(p_hwfn, p_aeu);
980 
981 				bit = bit_idx;
982 				bit_len = ATTENTION_LENGTH(p_aeu->flags);
983 				if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) {
984 					/* Skip Parity */
985 					bit++;
986 					bit_len--;
987 				}
988 
989 				/* Find the bits relating to HW-block, then
990 				 * shift so they'll become LSB.
991 				 */
992 				bitmask = bits & (((1 << bit_len) - 1) << bit);
993 				bitmask >>= bit;
994 
995 				if (bitmask) {
996 					u32 flags = p_aeu->flags;
997 					char bit_name[30];
998 					u8 num;
999 
1000 					num = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
1001 								bit_len);
1002 
1003 					/* Some bits represent more than a
1004 					 * a single interrupt. Correctly print
1005 					 * their name.
1006 					 */
1007 					if (ATTENTION_LENGTH(flags) > 2 ||
1008 					    ((flags & ATTENTION_PAR_INT) &&
1009 					    ATTENTION_LENGTH(flags) > 1))
1010 						OSAL_SNPRINTF(bit_name, 30,
1011 							      p_aeu->bit_name,
1012 							      num);
1013 					else
1014 						OSAL_STRNCPY(bit_name,
1015 							     p_aeu->bit_name,
1016 							     30);
1017 
1018 					/* We now need to pass bitmask in its
1019 					 * correct position.
1020 					 */
1021 					bitmask <<= bit;
1022 
1023 					/* Handle source of the attention */
1024 					ecore_int_deassertion_aeu_bit(p_hwfn,
1025 								      p_aeu,
1026 								      aeu_en,
1027 								      bit_name,
1028 								      bitmask);
1029 				}
1030 
1031 				bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1032 			}
1033 		}
1034 	}
1035 
1036 	/* Clear IGU indication for the deasserted bits */
1037 	/* FIXME - this will change once we'll have GOOD gtt definitions */
1038 	DIRECT_REG_WR(p_hwfn,
1039 		      (u8 OSAL_IOMEM*)p_hwfn->regview +
1040 				      GTT_BAR0_MAP_REG_IGU_CMD +
1041 				      ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1042 					IGU_CMD_INT_ACK_BASE) << 3),
1043 		      ~((u32)deasserted_bits));
1044 
1045 	/* Unmask deasserted attentions in IGU */
1046 	aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1047 			    IGU_REG_ATTENTION_ENABLE);
1048 	aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1049 	ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1050 
1051 	/* Clear deassertion from inner state */
1052 	sb_attn_sw->known_attn &= ~deasserted_bits;
1053 
1054 	return rc;
1055 }
1056 
ecore_int_attentions(struct ecore_hwfn * p_hwfn)1057 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
1058 {
1059 	struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1060 	struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1061 	u16 index = 0, asserted_bits, deasserted_bits;
1062 	u32 attn_bits = 0, attn_acks = 0;
1063 	enum _ecore_status_t rc = ECORE_SUCCESS;
1064 
1065 	/* Read current attention bits/acks - safeguard against attentions
1066 	 * by guaranting work on a synchronized timeframe
1067 	 */
1068 	do {
1069 		index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1070 		attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1071 		attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1072 	} while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1073 	p_sb_attn->sb_index = index;
1074 
1075 	/* Attention / Deassertion are meaningful (and in correct state)
1076 	 * only when they differ and consistent with known state - deassertion
1077 	 * when previous attention & current ack, and assertion when current
1078 	 * attention with no previous attention
1079 	 */
1080 	asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1081 			~p_sb_attn_sw->known_attn;
1082 	deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1083 			  p_sb_attn_sw->known_attn;
1084 
1085 	if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1086 		DP_INFO(p_hwfn,
1087 			"Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1088 			index, attn_bits, attn_acks, asserted_bits,
1089 			deasserted_bits, p_sb_attn_sw->known_attn);
1090 	else if (asserted_bits == 0x100)
1091 		DP_INFO(p_hwfn,
1092 			"MFW indication via attention\n");
1093 	else
1094 		DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1095 			   "MFW indication [deassertion]\n");
1096 
1097 	if (asserted_bits) {
1098 		rc = ecore_int_assertion(p_hwfn, asserted_bits);
1099 		if (rc)
1100 			return rc;
1101 	}
1102 
1103 	if (deasserted_bits)
1104 		rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1105 
1106 	return rc;
1107 }
1108 
ecore_sb_ack_attn(struct ecore_hwfn * p_hwfn,void OSAL_IOMEM * igu_addr,u32 ack_cons)1109 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1110 			      void OSAL_IOMEM *igu_addr, u32 ack_cons)
1111 {
1112 	struct igu_prod_cons_update igu_ack = { 0 };
1113 
1114 	igu_ack.sb_id_and_flags =
1115 		((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1116 		 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1117 		 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1118 		 (IGU_SEG_ACCESS_ATTN <<
1119 		  IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1120 
1121 	DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1122 
1123 	/* Both segments (interrupts & acks) are written to same place address;
1124 	 * Need to guarantee all commands will be received (in-order) by HW.
1125 	 */
1126 	OSAL_MMIOWB(p_hwfn->p_dev);
1127 	OSAL_BARRIER(p_hwfn->p_dev);
1128 }
1129 
ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)1130 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1131 {
1132 	struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1133 	struct ecore_pi_info *pi_info = OSAL_NULL;
1134 	struct ecore_sb_attn_info *sb_attn;
1135 	struct ecore_sb_info *sb_info;
1136 	int arr_size;
1137 	u16 rc = 0;
1138 
1139 	if (!p_hwfn)
1140 		return;
1141 
1142 	if (!p_hwfn->p_sp_sb) {
1143 		DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1144 		return;
1145 	}
1146 
1147 	sb_info = &p_hwfn->p_sp_sb->sb_info;
1148 	arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1149 	if (!sb_info) {
1150 		DP_ERR(p_hwfn->p_dev, "Status block is NULL - cannot ack interrupts\n");
1151 		return;
1152 	}
1153 
1154 	if (!p_hwfn->p_sb_attn) {
1155 		DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1156 		return;
1157 	}
1158 	sb_attn =  p_hwfn->p_sb_attn;
1159 
1160 	DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1161 		   p_hwfn, p_hwfn->my_id);
1162 
1163 	/* Disable ack for def status block. Required both for msix +
1164 	 * inta in non-mask mode, in inta does no harm.
1165 	 */
1166 	ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1167 
1168 	/* Gather Interrupts/Attentions information */
1169 	if (!sb_info->sb_virt) {
1170 		DP_ERR(p_hwfn->p_dev, "Interrupt Status block is NULL - cannot check for new interrupts!\n");
1171 	} else {
1172 		u32 tmp_index = sb_info->sb_ack;
1173 		rc = ecore_sb_update_sb_idx(sb_info);
1174 		DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1175 			   "Interrupt indices: 0x%08x --> 0x%08x\n",
1176 			   tmp_index, sb_info->sb_ack);
1177 	}
1178 
1179 	if (!sb_attn || !sb_attn->sb_attn) {
1180 		DP_ERR(p_hwfn->p_dev, "Attentions Status block is NULL - cannot check for new attentions!\n");
1181 	} else {
1182 		u16 tmp_index = sb_attn->index;
1183 
1184 		rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1185 		DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1186 			   "Attention indices: 0x%08x --> 0x%08x\n",
1187 			   tmp_index, sb_attn->index);
1188 	}
1189 
1190 	/* Check if we expect interrupts at this time. if not just ack them */
1191 	if (!(rc & ECORE_SB_EVENT_MASK)) {
1192 		ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1193 		return;
1194 	}
1195 
1196 	/* Check the validity of the DPC ptt. If not ack interrupts and fail */
1197 	if (!p_hwfn->p_dpc_ptt) {
1198 		DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1199 		ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1200 		return;
1201 	}
1202 
1203 	if (rc & ECORE_SB_ATT_IDX)
1204 		ecore_int_attentions(p_hwfn);
1205 
1206 	if (rc & ECORE_SB_IDX) {
1207 		int pi;
1208 
1209 		/* Since we only looked at the SB index, it's possible more
1210 		 * than a single protocol-index on the SB incremented.
1211 		 * Iterate over all configured protocol indices and check
1212 		 * whether something happened for each.
1213 		 */
1214 		for (pi = 0; pi < arr_size; pi++) {
1215 			pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1216 			if (pi_info->comp_cb != OSAL_NULL)
1217 				pi_info->comp_cb(p_hwfn, pi_info->cookie);
1218 		}
1219 	}
1220 
1221 	if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1222 		/* This should be done before the interrupts are enabled,
1223 		 * since otherwise a new attention will be generated.
1224 		 */
1225 		ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1226 	}
1227 
1228 	ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1229 }
1230 
ecore_int_sb_attn_free(struct ecore_hwfn * p_hwfn)1231 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1232 {
1233 	struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1234 
1235 	if (!p_sb)
1236 		return;
1237 
1238 	if (p_sb->sb_attn) {
1239 		OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1240 				       p_sb->sb_phys,
1241 				       SB_ATTN_ALIGNED_SIZE(p_hwfn));
1242 	}
1243 
1244 	OSAL_FREE(p_hwfn->p_dev, p_sb);
1245 	p_hwfn->p_sb_attn = OSAL_NULL;
1246 }
1247 
ecore_int_sb_attn_setup(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)1248 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1249 				    struct ecore_ptt *p_ptt)
1250 {
1251 	struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1252 
1253 	OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1254 
1255 	sb_info->index = 0;
1256 	sb_info->known_attn = 0;
1257 
1258 	/* Configure Attention Status Block in IGU */
1259 	ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1260 		 DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1261 	ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1262 		 DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1263 }
1264 
ecore_int_sb_attn_init(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,void * sb_virt_addr,dma_addr_t sb_phy_addr)1265 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1266 				   struct ecore_ptt *p_ptt,
1267 				   void *sb_virt_addr,
1268 				   dma_addr_t sb_phy_addr)
1269 {
1270 	struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1271 	int i, j, k;
1272 
1273 	sb_info->sb_attn = sb_virt_addr;
1274 	sb_info->sb_phys = sb_phy_addr;
1275 
1276 	/* Set the pointer to the AEU descriptors */
1277 	sb_info->p_aeu_desc = aeu_descs;
1278 
1279 	/* Calculate Parity Masks */
1280 	OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1281 	for (i = 0; i < NUM_ATTN_REGS; i++) {
1282 		/* j is array index, k is bit index */
1283 		for (j = 0, k = 0; k < 32; j++) {
1284 			struct aeu_invert_reg_bit *p_aeu;
1285 
1286 			p_aeu = &aeu_descs[i].bits[j];
1287 			if (ecore_int_is_parity_flag(p_hwfn, p_aeu))
1288 				sb_info->parity_mask[i] |= 1 << k;
1289 
1290 			k += ATTENTION_LENGTH(p_aeu->flags);
1291 		}
1292 		DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1293 			   "Attn Mask [Reg %d]: 0x%08x\n",
1294 			   i, sb_info->parity_mask[i]);
1295 	}
1296 
1297 	/* Set the address of cleanup for the mcp attention */
1298 	sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1299 				 MISC_REG_AEU_GENERAL_ATTN_0;
1300 
1301 	ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1302 }
1303 
ecore_int_sb_attn_alloc(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)1304 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1305 						    struct ecore_ptt *p_ptt)
1306 {
1307 	struct ecore_dev *p_dev = p_hwfn->p_dev;
1308 	struct ecore_sb_attn_info *p_sb;
1309 	dma_addr_t p_phys = 0;
1310 	void *p_virt;
1311 
1312 	/* SB struct */
1313 	p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1314 	if (!p_sb) {
1315 		DP_NOTICE(p_dev, true, "Failed to allocate `struct ecore_sb_attn_info'\n");
1316 		return ECORE_NOMEM;
1317 	}
1318 
1319 	/* SB ring  */
1320 	p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1321 					 SB_ATTN_ALIGNED_SIZE(p_hwfn));
1322 	if (!p_virt) {
1323 		DP_NOTICE(p_dev, true, "Failed to allocate status block (attentions)\n");
1324 		OSAL_FREE(p_dev, p_sb);
1325 		return ECORE_NOMEM;
1326 	}
1327 
1328 	/* Attention setup */
1329 	p_hwfn->p_sb_attn = p_sb;
1330 	ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1331 
1332 	return ECORE_SUCCESS;
1333 }
1334 
1335 /* coalescing timeout = timeset << (timer_res + 1) */
1336 #define ECORE_CAU_DEF_RX_USECS 24
1337 #define ECORE_CAU_DEF_TX_USECS 48
1338 
ecore_init_cau_sb_entry(struct ecore_hwfn * p_hwfn,struct cau_sb_entry * p_sb_entry,u8 pf_id,u16 vf_number,u8 vf_valid)1339 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1340 			     struct cau_sb_entry *p_sb_entry,
1341 			     u8 pf_id, u16 vf_number, u8 vf_valid)
1342 {
1343 	struct ecore_dev *p_dev = p_hwfn->p_dev;
1344 	u32 cau_state;
1345 	u8 timer_res;
1346 
1347 	OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1348 
1349 	SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1350 	SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1351 	SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1352 	SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1353 	SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1354 
1355 	cau_state = CAU_HC_DISABLE_STATE;
1356 
1357 	if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1358 		cau_state = CAU_HC_ENABLE_STATE;
1359 		if (!p_dev->rx_coalesce_usecs)
1360 			p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1361 		if (!p_dev->tx_coalesce_usecs)
1362 			p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1363 	}
1364 
1365 	/* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1366 	if (p_dev->rx_coalesce_usecs <= 0x7F)
1367 		timer_res = 0;
1368 	else if (p_dev->rx_coalesce_usecs <= 0xFF)
1369 		timer_res = 1;
1370 	else
1371 		timer_res = 2;
1372 	SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1373 
1374 	if (p_dev->tx_coalesce_usecs <= 0x7F)
1375 		timer_res = 0;
1376 	else if (p_dev->tx_coalesce_usecs <= 0xFF)
1377 		timer_res = 1;
1378 	else
1379 		timer_res = 2;
1380 	SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1381 
1382 	SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1383 	SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1384 }
1385 
_ecore_int_cau_conf_pi(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 igu_sb_id,u32 pi_index,enum ecore_coalescing_fsm coalescing_fsm,u8 timeset)1386 static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1387 				   struct ecore_ptt *p_ptt,
1388 				   u16 igu_sb_id, u32 pi_index,
1389 				   enum ecore_coalescing_fsm coalescing_fsm,
1390 				   u8 timeset)
1391 {
1392 	struct cau_pi_entry pi_entry;
1393 	u32 sb_offset, pi_offset;
1394 
1395 	if (IS_VF(p_hwfn->p_dev))
1396 		return;/* @@@TBD MichalK- VF CAU... */
1397 
1398 	sb_offset = igu_sb_id * PIS_PER_SB;
1399 	OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1400 
1401 	SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1402 	if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1403 		SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1404 	else
1405 		SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1406 
1407 	pi_offset = sb_offset + pi_index;
1408 	if (p_hwfn->hw_init_done) {
1409 		ecore_wr(p_hwfn, p_ptt,
1410 			 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1411 			 *((u32 *)&(pi_entry)));
1412 	} else {
1413 		STORE_RT_REG(p_hwfn,
1414 			     CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1415 			     *((u32 *)&(pi_entry)));
1416 	}
1417 }
1418 
ecore_int_cau_conf_pi(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct ecore_sb_info * p_sb,u32 pi_index,enum ecore_coalescing_fsm coalescing_fsm,u8 timeset)1419 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1420 			   struct ecore_ptt *p_ptt,
1421 			   struct ecore_sb_info *p_sb, u32 pi_index,
1422 			   enum ecore_coalescing_fsm coalescing_fsm,
1423 			   u8 timeset)
1424 {
1425 	_ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id,
1426 			       pi_index, coalescing_fsm, timeset);
1427 }
1428 
ecore_int_cau_conf_sb(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,dma_addr_t sb_phys,u16 igu_sb_id,u16 vf_number,u8 vf_valid)1429 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1430 			   struct ecore_ptt *p_ptt,
1431 			   dma_addr_t sb_phys, u16 igu_sb_id,
1432 			   u16 vf_number, u8 vf_valid)
1433 {
1434 	struct cau_sb_entry sb_entry;
1435 
1436 	ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1437 				vf_number, vf_valid);
1438 
1439 	if (p_hwfn->hw_init_done) {
1440 		/* Wide-bus, initialize via DMAE */
1441 		u64 phys_addr = (u64)sb_phys;
1442 
1443 		ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&phys_addr,
1444 				    CAU_REG_SB_ADDR_MEMORY +
1445 				    igu_sb_id * sizeof(u64), 2, 0);
1446 		ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&sb_entry,
1447 				    CAU_REG_SB_VAR_MEMORY +
1448 				    igu_sb_id * sizeof(u64), 2, 0);
1449 	} else {
1450 		/* Initialize Status Block Address */
1451 		STORE_RT_REG_AGG(p_hwfn,
1452 				 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET+igu_sb_id*2,
1453 				 sb_phys);
1454 
1455 		STORE_RT_REG_AGG(p_hwfn,
1456 				 CAU_REG_SB_VAR_MEMORY_RT_OFFSET+igu_sb_id*2,
1457 				 sb_entry);
1458 	}
1459 
1460 	/* Configure pi coalescing if set */
1461 	if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1462 		/* eth will open queues for all tcs, so configure all of them
1463 		 * properly, rather than just the active ones
1464 		 */
1465 		u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1466 
1467 		u8 timeset, timer_res;
1468 		u8 i;
1469 
1470 		/* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1471 		if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1472 			timer_res = 0;
1473 		else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1474 			timer_res = 1;
1475 		else
1476 			timer_res = 2;
1477 		timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1478 		_ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1479 				       ECORE_COAL_RX_STATE_MACHINE,
1480 				       timeset);
1481 
1482 		if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1483 			timer_res = 0;
1484 		else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1485 			timer_res = 1;
1486 		else
1487 			timer_res = 2;
1488 		timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1489 		for (i = 0; i < num_tc; i++) {
1490 			_ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1491 					       igu_sb_id, TX_PI(i),
1492 					       ECORE_COAL_TX_STATE_MACHINE,
1493 					       timeset);
1494 		}
1495 	}
1496 }
1497 
ecore_int_sb_setup(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct ecore_sb_info * sb_info)1498 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1499 			       struct ecore_ptt *p_ptt,
1500 			       struct ecore_sb_info *sb_info)
1501 {
1502 	/* zero status block and ack counter */
1503 	sb_info->sb_ack = 0;
1504 	OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1505 
1506 	if (IS_PF(p_hwfn->p_dev))
1507 		ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1508 				      sb_info->igu_sb_id, 0, 0);
1509 }
1510 
1511 struct ecore_igu_block *
ecore_get_igu_free_sb(struct ecore_hwfn * p_hwfn,bool b_is_pf)1512 ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf)
1513 {
1514 	struct ecore_igu_block *p_block;
1515 	u16 igu_id;
1516 
1517 	for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1518 	     igu_id++) {
1519 		p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1520 
1521 		if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1522 		    !(p_block->status & ECORE_IGU_STATUS_FREE))
1523 			continue;
1524 
1525 		if (!!(p_block->status & ECORE_IGU_STATUS_PF) ==
1526 		    b_is_pf)
1527 			return p_block;
1528 	}
1529 
1530 	return OSAL_NULL;
1531 }
1532 
ecore_get_pf_igu_sb_id(struct ecore_hwfn * p_hwfn,u16 vector_id)1533 static u16 ecore_get_pf_igu_sb_id(struct ecore_hwfn *p_hwfn,
1534 				  u16 vector_id)
1535 {
1536 	struct ecore_igu_block *p_block;
1537 	u16 igu_id;
1538 
1539 	for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1540 	     igu_id++) {
1541 		p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1542 
1543 		if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1544 		    !p_block->is_pf ||
1545 		    p_block->vector_number != vector_id)
1546 			continue;
1547 
1548 		return igu_id;
1549 	}
1550 
1551 	return ECORE_SB_INVALID_IDX;
1552 }
1553 
ecore_get_igu_sb_id(struct ecore_hwfn * p_hwfn,u16 sb_id)1554 u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1555 {
1556 	u16 igu_sb_id;
1557 
1558 	/* Assuming continuous set of IGU SBs dedicated for given PF */
1559 	if (sb_id == ECORE_SP_SB_ID)
1560 		igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1561 	else if (IS_PF(p_hwfn->p_dev))
1562 		igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1563 	else
1564 		igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1565 
1566 	if (igu_sb_id == ECORE_SB_INVALID_IDX)
1567 		DP_NOTICE(p_hwfn, true,
1568 			  "Slowpath SB vector %04x doesn't exist\n",
1569 			  sb_id);
1570 	else if (sb_id == ECORE_SP_SB_ID)
1571 		DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1572 			   "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1573 	else
1574 		DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1575 			   "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1576 
1577 	return igu_sb_id;
1578 }
1579 
ecore_int_sb_init(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct ecore_sb_info * sb_info,void * sb_virt_addr,dma_addr_t sb_phy_addr,u16 sb_id)1580 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1581 				       struct ecore_ptt *p_ptt,
1582 				       struct ecore_sb_info *sb_info,
1583 				       void *sb_virt_addr,
1584 				       dma_addr_t sb_phy_addr,
1585 				       u16 sb_id)
1586 {
1587 	sb_info->sb_virt = sb_virt_addr;
1588 	sb_info->sb_phys = sb_phy_addr;
1589 
1590 	sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1591 
1592 	if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX)
1593 		return ECORE_INVAL;
1594 
1595 	/* Let the igu info reference the client's SB info */
1596 	if (sb_id != ECORE_SP_SB_ID) {
1597 		if (IS_PF(p_hwfn->p_dev)) {
1598 			struct ecore_igu_info *p_info;
1599 			struct ecore_igu_block *p_block;
1600 
1601 			p_info = p_hwfn->hw_info.p_igu_info;
1602 			p_block = &p_info->entry[sb_info->igu_sb_id];
1603 
1604 			p_block->sb_info = sb_info;
1605 			p_block->status &= ~ECORE_IGU_STATUS_FREE;
1606 			p_info->usage.free_cnt--;
1607 		} else {
1608 			ecore_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1609 		}
1610 	}
1611 
1612 #ifdef ECORE_CONFIG_DIRECT_HWFN
1613 	sb_info->p_hwfn = p_hwfn;
1614 #endif
1615 	sb_info->p_dev = p_hwfn->p_dev;
1616 
1617 	/* The igu address will hold the absolute address that needs to be
1618 	 * written to for a specific status block
1619 	 */
1620 	if (IS_PF(p_hwfn->p_dev)) {
1621 		sb_info->igu_addr = (u8 OSAL_IOMEM*)p_hwfn->regview +
1622 				    GTT_BAR0_MAP_REG_IGU_CMD +
1623 				    (sb_info->igu_sb_id << 3);
1624 
1625 	} else {
1626 		sb_info->igu_addr =
1627 			(u8 OSAL_IOMEM*)p_hwfn->regview +
1628 			PXP_VF_BAR0_START_IGU +
1629 			((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1630 	}
1631 
1632 	sb_info->flags |= ECORE_SB_INFO_INIT;
1633 
1634 	ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1635 
1636 	return ECORE_SUCCESS;
1637 }
1638 
ecore_int_sb_release(struct ecore_hwfn * p_hwfn,struct ecore_sb_info * sb_info,u16 sb_id)1639 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1640 					  struct ecore_sb_info *sb_info,
1641 					  u16 sb_id)
1642 {
1643 	struct ecore_igu_info *p_info;
1644 	struct ecore_igu_block *p_block;
1645 
1646 	if (sb_info == OSAL_NULL)
1647 		return ECORE_SUCCESS;
1648 
1649 	/* zero status block and ack counter */
1650 	sb_info->sb_ack = 0;
1651 	OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1652 
1653 	if (IS_VF(p_hwfn->p_dev)) {
1654 		ecore_vf_set_sb_info(p_hwfn, sb_id, OSAL_NULL);
1655 		return ECORE_SUCCESS;
1656 	}
1657 
1658 	p_info = p_hwfn->hw_info.p_igu_info;
1659 	p_block = &p_info->entry[sb_info->igu_sb_id];
1660 
1661 	/* Vector 0 is reserved to Default SB */
1662 	if (p_block->vector_number == 0) {
1663 		DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1664 		return ECORE_INVAL;
1665 	}
1666 
1667 	/* Lose reference to client's SB info, and fix counters */
1668 	p_block->sb_info = OSAL_NULL;
1669 	p_block->status |= ECORE_IGU_STATUS_FREE;
1670 	p_info->usage.free_cnt++;
1671 
1672 	return ECORE_SUCCESS;
1673 }
1674 
ecore_int_sp_sb_free(struct ecore_hwfn * p_hwfn)1675 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1676 {
1677 	struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1678 
1679 	if (!p_sb)
1680 		return;
1681 
1682 	if (p_sb->sb_info.sb_virt) {
1683 		OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1684 				       p_sb->sb_info.sb_virt,
1685 				       p_sb->sb_info.sb_phys,
1686 				       SB_ALIGNED_SIZE(p_hwfn));
1687 	}
1688 
1689 	OSAL_FREE(p_hwfn->p_dev, p_sb);
1690 	p_hwfn->p_sp_sb = OSAL_NULL;
1691 }
1692 
ecore_int_sp_sb_alloc(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)1693 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1694 						  struct ecore_ptt *p_ptt)
1695 {
1696 	struct ecore_sb_sp_info *p_sb;
1697 	dma_addr_t p_phys = 0;
1698 	void *p_virt;
1699 
1700 	/* SB struct */
1701 	p_sb = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_sb));
1702 	if (!p_sb) {
1703 		DP_NOTICE(p_hwfn, true, "Failed to allocate `struct ecore_sb_info'\n");
1704 		return ECORE_NOMEM;
1705 	}
1706 
1707 	/* SB ring  */
1708 	p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1709 					 &p_phys,
1710 					 SB_ALIGNED_SIZE(p_hwfn));
1711 	if (!p_virt) {
1712 		DP_NOTICE(p_hwfn, true, "Failed to allocate status block\n");
1713 		OSAL_FREE(p_hwfn->p_dev, p_sb);
1714 		return ECORE_NOMEM;
1715 	}
1716 
1717 
1718 	/* Status Block setup */
1719 	p_hwfn->p_sp_sb = p_sb;
1720 	ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1721 			  p_virt, p_phys, ECORE_SP_SB_ID);
1722 
1723 	OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1724 
1725 	return ECORE_SUCCESS;
1726 }
1727 
ecore_int_register_cb(struct ecore_hwfn * p_hwfn,ecore_int_comp_cb_t comp_cb,void * cookie,u8 * sb_idx,__le16 ** p_fw_cons)1728 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1729 					   ecore_int_comp_cb_t comp_cb,
1730 					   void *cookie,
1731 					   u8 *sb_idx,
1732 					   __le16 **p_fw_cons)
1733 {
1734 	struct ecore_sb_sp_info *p_sp_sb  = p_hwfn->p_sp_sb;
1735 	enum _ecore_status_t rc = ECORE_NOMEM;
1736 	u8 pi;
1737 
1738 	/* Look for a free index */
1739 	for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1740 		if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1741 			continue;
1742 
1743 		p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1744 		p_sp_sb->pi_info_arr[pi].cookie = cookie;
1745 		*sb_idx = pi;
1746 		*p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1747 		rc = ECORE_SUCCESS;
1748 		break;
1749 	}
1750 
1751 	return rc;
1752 }
1753 
ecore_int_unregister_cb(struct ecore_hwfn * p_hwfn,u8 pi)1754 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn,
1755 					     u8 pi)
1756 {
1757 	struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1758 
1759 	if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1760 		return ECORE_NOMEM;
1761 
1762 	p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1763 	p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1764 
1765 	return ECORE_SUCCESS;
1766 }
1767 
ecore_int_get_sp_sb_id(struct ecore_hwfn * p_hwfn)1768 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1769 {
1770 	return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1771 }
1772 
ecore_int_igu_enable_int(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,enum ecore_int_mode int_mode)1773 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1774 			      struct ecore_ptt	*p_ptt,
1775 			      enum ecore_int_mode int_mode)
1776 {
1777 	u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1778 
1779 #ifndef ASIC_ONLY
1780 	if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1781 		DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1782 		igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1783 	}
1784 #endif
1785 
1786 	p_hwfn->p_dev->int_mode = int_mode;
1787 	switch (p_hwfn->p_dev->int_mode) {
1788 	case ECORE_INT_MODE_INTA:
1789 		igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1790 		igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1791 		break;
1792 
1793 	case ECORE_INT_MODE_MSI:
1794 		igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1795 		igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1796 		break;
1797 
1798 	case ECORE_INT_MODE_MSIX:
1799 		igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1800 		break;
1801 	case ECORE_INT_MODE_POLL:
1802 		break;
1803 	}
1804 
1805 	ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1806 }
1807 
ecore_int_igu_enable_attn(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)1808 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1809 				      struct ecore_ptt *p_ptt)
1810 {
1811 #ifndef ASIC_ONLY
1812 	if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1813 		DP_INFO(p_hwfn, "FPGA - Don't enable Attentions in IGU and MISC\n");
1814 		return;
1815 	}
1816 #endif
1817 
1818 	/* Configure AEU signal change to produce attentions */
1819 	ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1820 	ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1821 	ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1822 	ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1823 
1824 	/* Flush the writes to IGU */
1825 	OSAL_MMIOWB(p_hwfn->p_dev);
1826 
1827 	/* Unmask AEU signals toward IGU */
1828 	ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1829 }
1830 
1831 enum _ecore_status_t
ecore_int_igu_enable(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,enum ecore_int_mode int_mode)1832 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1833 			  enum ecore_int_mode int_mode)
1834 {
1835 	enum _ecore_status_t rc = ECORE_SUCCESS;
1836 	u32 tmp;
1837 
1838 	/* @@@tmp - Starting with MFW 8.2.1.0 we've started hitting AVS stop
1839 	 * attentions. Since we're waiting for BRCM answer regarding this
1840 	 * attention, in the meanwhile we simply mask it.
1841 	 */
1842 	tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
1843 	tmp &= ~0x800;
1844 	ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
1845 
1846 	ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1847 
1848 	if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1849 		rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1850 		if (rc != ECORE_SUCCESS) {
1851 			DP_NOTICE(p_hwfn, true, "Slowpath IRQ request failed\n");
1852 			return ECORE_NORESOURCES;
1853 		}
1854 		p_hwfn->b_int_requested = true;
1855 	}
1856 
1857 	/* Enable interrupt Generation */
1858 	ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1859 
1860 	p_hwfn->b_int_enabled = 1;
1861 
1862 	return rc;
1863 }
1864 
ecore_int_igu_disable_int(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)1865 void ecore_int_igu_disable_int(struct ecore_hwfn	*p_hwfn,
1866 			       struct ecore_ptt		*p_ptt)
1867 {
1868 	p_hwfn->b_int_enabled = 0;
1869 
1870 	if (IS_VF(p_hwfn->p_dev))
1871 		return;
1872 
1873 	ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1874 }
1875 
1876 #define IGU_CLEANUP_SLEEP_LENGTH		(1000)
ecore_int_igu_cleanup_sb(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 igu_sb_id,bool cleanup_set,u16 opaque_fid)1877 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1878 				     struct ecore_ptt *p_ptt,
1879 				     u16 igu_sb_id,
1880 				     bool cleanup_set,
1881 				     u16 opaque_fid)
1882 {
1883 	u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1884 	u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1885 	u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1886 	u8  type = 0; /* FIXME MichalS type??? */
1887 
1888 	OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1889 			   IGU_REG_CLEANUP_STATUS_0) != 0x200);
1890 
1891 	/* USE Control Command Register to perform cleanup. There is an
1892 	 * option to do this using IGU bar, but then it can't be used for VFs.
1893 	 */
1894 
1895 	/* Set the data field */
1896 	SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1897 	SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
1898 	SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1899 
1900 	/* Set the control register */
1901 	SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1902 	SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1903 	SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1904 
1905 	ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1906 
1907 	OSAL_BARRIER(p_hwfn->p_dev);
1908 
1909 	ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1910 
1911 	/* Flush the write to IGU */
1912 	OSAL_MMIOWB(p_hwfn->p_dev);
1913 
1914 	/* calculate where to read the status bit from */
1915 	sb_bit = 1 << (igu_sb_id % 32);
1916 	sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
1917 
1918 	sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
1919 
1920 	/* Now wait for the command to complete */
1921 	while (--sleep_cnt) {
1922 		val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
1923 		if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1924 			break;
1925 		OSAL_MSLEEP(5);
1926 	}
1927 
1928 	if (!sleep_cnt)
1929 		DP_NOTICE(p_hwfn, true,
1930 			  "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1931 			  val, igu_sb_id);
1932 }
1933 
ecore_int_igu_init_pure_rt_single(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 igu_sb_id,u16 opaque,bool b_set)1934 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
1935 				       struct ecore_ptt *p_ptt,
1936 				       u16 igu_sb_id, u16 opaque, bool b_set)
1937 {
1938 	struct ecore_igu_block *p_block;
1939 	int pi, i;
1940 
1941 	p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
1942 	DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1943 		   "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
1944 		   igu_sb_id, p_block->function_id, p_block->is_pf,
1945 		   p_block->vector_number);
1946 
1947 	/* Set */
1948 	if (b_set)
1949 		ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
1950 
1951 	/* Clear */
1952 	ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
1953 
1954 	/* Wait for the IGU SB to cleanup */
1955 	for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
1956 		u32 val;
1957 
1958 		val = ecore_rd(p_hwfn, p_ptt,
1959 			       IGU_REG_WRITE_DONE_PENDING +
1960 			       ((igu_sb_id / 32) * 4));
1961 		if (val & (1 << (igu_sb_id % 32)))
1962 			OSAL_UDELAY(10);
1963 		else
1964 			break;
1965 	}
1966 	if (i == IGU_CLEANUP_SLEEP_LENGTH)
1967 		DP_NOTICE(p_hwfn, true,
1968 			  "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
1969 			  igu_sb_id);
1970 
1971 	/* Clear the CAU for the SB */
1972 	for (pi = 0; pi < 12; pi++)
1973 		ecore_wr(p_hwfn, p_ptt,
1974 			 CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
1975 }
1976 
ecore_int_igu_init_pure_rt(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,bool b_set,bool b_slowpath)1977 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
1978 				 struct ecore_ptt *p_ptt,
1979 				 bool b_set,
1980 				 bool b_slowpath)
1981 {
1982 	struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
1983 	struct ecore_igu_block *p_block;
1984 	u16 igu_sb_id = 0;
1985 	u32 val = 0;
1986 
1987 	/* @@@TBD MichalK temporary... should be moved to init-tool... */
1988 	val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
1989 	val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
1990 	val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
1991 	ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
1992 	/* end temporary */
1993 
1994 	for (igu_sb_id = 0;
1995 	     igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1996 	     igu_sb_id++) {
1997 		p_block = &p_info->entry[igu_sb_id];
1998 
1999 		if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2000 		    !p_block->is_pf ||
2001 		    (p_block->status & ECORE_IGU_STATUS_DSB))
2002 			continue;
2003 
2004 		ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2005 						  p_hwfn->hw_info.opaque_fid,
2006 						  b_set);
2007 	}
2008 
2009 	if (b_slowpath)
2010 		ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2011 						  p_info->igu_dsb_id,
2012 						  p_hwfn->hw_info.opaque_fid,
2013 						  b_set);
2014 }
2015 
ecore_int_igu_reset_cam(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)2016 int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn,
2017 			    struct ecore_ptt *p_ptt)
2018 {
2019 	struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2020 	struct ecore_igu_block *p_block;
2021 	int pf_sbs, vf_sbs;
2022 	u16 igu_sb_id;
2023 	u32 val, rval;
2024 
2025 	if (!RESC_NUM(p_hwfn, ECORE_SB)) {
2026 		/* We're using an old MFW - have to prevent any switching
2027 		 * of SBs between PF and VFs as later driver wouldn't be
2028 		 * able to tell which belongs to which.
2029 		 */
2030 		p_info->b_allow_pf_vf_change = false;
2031 	} else {
2032 		/* Use the numbers the MFW have provided -
2033 		 * don't forget MFW accounts for the default SB as well.
2034 		 */
2035 		p_info->b_allow_pf_vf_change = true;
2036 
2037 		if (p_info->usage.cnt != RESC_NUM(p_hwfn, ECORE_SB) - 1) {
2038 			DP_INFO(p_hwfn,
2039 				"MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2040 				RESC_NUM(p_hwfn, ECORE_SB) - 1,
2041 				p_info->usage.cnt);
2042 			p_info->usage.cnt = RESC_NUM(p_hwfn, ECORE_SB) - 1;
2043 		}
2044 
2045 		/* TODO - how do we learn about VF SBs from MFW? */
2046 		if (IS_PF_SRIOV(p_hwfn)) {
2047 			u16 vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
2048 
2049 			if (vfs != p_info->usage.iov_cnt)
2050 				DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2051 					   "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2052 					   p_info->usage.iov_cnt, vfs);
2053 
2054 			/* At this point we know how many SBs we have totally
2055 			 * in IGU + number of PF SBs. So we can validate that
2056 			 * we'd have sufficient for VF.
2057 			 */
2058 			if (vfs > p_info->usage.free_cnt +
2059 				  p_info->usage.free_cnt_iov -
2060 				  p_info->usage.cnt) {
2061 				DP_NOTICE(p_hwfn, true,
2062 					  "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2063 					  p_info->usage.free_cnt +
2064 					  p_info->usage.free_cnt_iov,
2065 					  p_info->usage.cnt, vfs);
2066 				return ECORE_INVAL;
2067 			}
2068 
2069 			/* Currently cap the number of VFs SBs by the
2070 			 * number of VFs.
2071 			 */
2072 			p_info->usage.iov_cnt = vfs;
2073 		}
2074 	}
2075 
2076 	/* Mark all SBs as free, now in the right PF/VFs division */
2077 	p_info->usage.free_cnt = p_info->usage.cnt;
2078 	p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2079 	p_info->usage.orig = p_info->usage.cnt;
2080 	p_info->usage.iov_orig = p_info->usage.iov_cnt;
2081 
2082 	/* We now proceed to re-configure the IGU cam to reflect the initial
2083 	 * configuration. We can start with the Default SB.
2084 	 */
2085 	pf_sbs = p_info->usage.cnt;
2086 	vf_sbs = p_info->usage.iov_cnt;
2087 
2088 	for (igu_sb_id = p_info->igu_dsb_id;
2089 	     igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2090 	     igu_sb_id++) {
2091 		p_block = &p_info->entry[igu_sb_id];
2092 		val = 0;
2093 
2094 		if (!(p_block->status & ECORE_IGU_STATUS_VALID))
2095 			continue;
2096 
2097 		if (p_block->status & ECORE_IGU_STATUS_DSB) {
2098 			p_block->function_id = p_hwfn->rel_pf_id;
2099 			p_block->is_pf = 1;
2100 			p_block->vector_number = 0;
2101 			p_block->status = ECORE_IGU_STATUS_VALID |
2102 					  ECORE_IGU_STATUS_PF |
2103 					  ECORE_IGU_STATUS_DSB;
2104 		} else if (pf_sbs) {
2105 			pf_sbs--;
2106 			p_block->function_id = p_hwfn->rel_pf_id;
2107 			p_block->is_pf = 1;
2108 			p_block->vector_number = p_info->usage.cnt - pf_sbs;
2109 			p_block->status = ECORE_IGU_STATUS_VALID |
2110 					  ECORE_IGU_STATUS_PF |
2111 					  ECORE_IGU_STATUS_FREE;
2112 		} else if (vf_sbs) {
2113 			p_block->function_id =
2114 				p_hwfn->p_dev->p_iov_info->first_vf_in_pf +
2115 				p_info->usage.iov_cnt - vf_sbs;
2116 			p_block->is_pf = 0;
2117 			p_block->vector_number = 0;
2118 			p_block->status = ECORE_IGU_STATUS_VALID |
2119 					  ECORE_IGU_STATUS_FREE;
2120 			vf_sbs--;
2121 		} else {
2122 			p_block->function_id = 0;
2123 			p_block->is_pf = 0;
2124 			p_block->vector_number = 0;
2125 		}
2126 
2127 		SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2128 			  p_block->function_id);
2129 		SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2130 		SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2131 			  p_block->vector_number);
2132 
2133 		/* VF entries would be enabled when VF is initializaed */
2134 		SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2135 
2136 		rval = ecore_rd(p_hwfn, p_ptt,
2137 				IGU_REG_MAPPING_MEMORY +
2138 				sizeof(u32) * igu_sb_id);
2139 
2140 		if (rval != val) {
2141 			ecore_wr(p_hwfn, p_ptt,
2142 				 IGU_REG_MAPPING_MEMORY +
2143 				 sizeof(u32) * igu_sb_id,
2144 				 val);
2145 
2146 			DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2147 				   "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2148 				   igu_sb_id, p_block->function_id,
2149 				   p_block->is_pf, p_block->vector_number,
2150 				   rval, val);
2151 		}
2152 	}
2153 
2154 	return 0;
2155 }
2156 
ecore_int_igu_reset_cam_default(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)2157 int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn,
2158 				    struct ecore_ptt *p_ptt)
2159 {
2160 	struct ecore_sb_cnt_info *p_cnt = &p_hwfn->hw_info.p_igu_info->usage;
2161 
2162 	/* Return all the usage indications to default prior to the reset;
2163 	 * The reset expects the !orig to reflect the initial status of the
2164 	 * SBs, and would re-calculate the originals based on those.
2165 	 */
2166 	p_cnt->cnt = p_cnt->orig;
2167 	p_cnt->free_cnt = p_cnt->orig;
2168 	p_cnt->iov_cnt = p_cnt->iov_orig;
2169 	p_cnt->free_cnt_iov = p_cnt->iov_orig;
2170 	p_cnt->orig = 0;
2171 	p_cnt->iov_orig = 0;
2172 
2173 	/* TODO - we probably need to re-configure the CAU as well... */
2174 	return ecore_int_igu_reset_cam(p_hwfn, p_ptt);
2175 }
2176 
ecore_int_igu_read_cam_block(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 igu_sb_id)2177 static void ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
2178 					 struct ecore_ptt *p_ptt,
2179 					 u16 igu_sb_id)
2180 {
2181 	u32 val = ecore_rd(p_hwfn, p_ptt,
2182 			   IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2183 	struct ecore_igu_block *p_block;
2184 
2185 	p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2186 
2187 	/* Fill the block information */
2188 	p_block->function_id = GET_FIELD(val,
2189 					 IGU_MAPPING_LINE_FUNCTION_NUMBER);
2190 	p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2191 	p_block->vector_number = GET_FIELD(val,
2192 					   IGU_MAPPING_LINE_VECTOR_NUMBER);
2193 	p_block->igu_sb_id = igu_sb_id;
2194 }
2195 
ecore_int_igu_read_cam(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)2196 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
2197 					    struct ecore_ptt *p_ptt)
2198 {
2199 	struct ecore_igu_info *p_igu_info;
2200 	struct ecore_igu_block *p_block;
2201 	u32 min_vf = 0, max_vf = 0;
2202 	u16 igu_sb_id;
2203 
2204 	p_hwfn->hw_info.p_igu_info = OSAL_ZALLOC(p_hwfn->p_dev,
2205 						 GFP_KERNEL,
2206 						 sizeof(*p_igu_info));
2207 	if (!p_hwfn->hw_info.p_igu_info)
2208 		return ECORE_NOMEM;
2209 	p_igu_info = p_hwfn->hw_info.p_igu_info;
2210 
2211 	/* Distinguish between existent and onn-existent default SB */
2212 	p_igu_info->igu_dsb_id = ECORE_SB_INVALID_IDX;
2213 
2214 	/* Find the range of VF ids whose SB belong to this PF */
2215 	if (p_hwfn->p_dev->p_iov_info) {
2216 		struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
2217 
2218 		min_vf = p_iov->first_vf_in_pf;
2219 		max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2220 	}
2221 
2222 	for (igu_sb_id = 0;
2223 	     igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2224 	     igu_sb_id++) {
2225 		/* Read current entry; Notice it might not belong to this PF */
2226 		ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2227 		p_block = &p_igu_info->entry[igu_sb_id];
2228 
2229 		if ((p_block->is_pf) &&
2230 		    (p_block->function_id == p_hwfn->rel_pf_id)) {
2231 			p_block->status = ECORE_IGU_STATUS_PF |
2232 					  ECORE_IGU_STATUS_VALID |
2233 					  ECORE_IGU_STATUS_FREE;
2234 
2235 			if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2236 				p_igu_info->usage.cnt++;
2237 		} else if (!(p_block->is_pf) &&
2238 			   (p_block->function_id >= min_vf) &&
2239 			   (p_block->function_id < max_vf)) {
2240 			/* Available for VFs of this PF */
2241 			p_block->status = ECORE_IGU_STATUS_VALID |
2242 					  ECORE_IGU_STATUS_FREE;
2243 
2244 			if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2245 				p_igu_info->usage.iov_cnt++;
2246 		}
2247 
2248 		/* Mark the First entry belonging to the PF or its VFs
2249 		 * as the default SB [we'll reset IGU prior to first usage].
2250 		 */
2251 		if ((p_block->status & ECORE_IGU_STATUS_VALID) &&
2252 		    (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX)) {
2253 			p_igu_info->igu_dsb_id = igu_sb_id;
2254 			p_block->status |= ECORE_IGU_STATUS_DSB;
2255 		}
2256 
2257 		/* While this isn't suitable for all clients, limit number
2258 		 * of prints by having each PF print only its entries with the
2259 		 * exception of PF0 which would print everything.
2260 		 */
2261 		if ((p_block->status & ECORE_IGU_STATUS_VALID) ||
2262 		    (p_hwfn->abs_pf_id == 0))
2263 			DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2264 				   "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2265 				   igu_sb_id, p_block->function_id,
2266 				   p_block->is_pf, p_block->vector_number);
2267 	}
2268 
2269 	if (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX) {
2270 		DP_NOTICE(p_hwfn, true,
2271 			  "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2272 			  p_igu_info->igu_dsb_id);
2273 		return ECORE_INVAL;
2274 	}
2275 
2276 	/* All non default SB are considered free at this point */
2277 	p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2278 	p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2279 
2280 	DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2281 		   "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2282 		   p_igu_info->igu_dsb_id, p_igu_info->usage.cnt,
2283 		   p_igu_info->usage.iov_cnt);
2284 
2285 	return ECORE_SUCCESS;
2286 }
2287 
2288 enum _ecore_status_t
ecore_int_igu_relocate_sb(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 sb_id,bool b_to_vf)2289 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2290 			  u16 sb_id, bool b_to_vf)
2291 {
2292 	struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2293 	struct ecore_igu_block *p_block = OSAL_NULL;
2294 	u16 igu_sb_id = 0, vf_num = 0;
2295 	u32 val = 0;
2296 
2297 	if (IS_VF(p_hwfn->p_dev) || !IS_PF_SRIOV(p_hwfn))
2298 		return ECORE_INVAL;
2299 
2300 	if (sb_id == ECORE_SP_SB_ID)
2301 		return ECORE_INVAL;
2302 
2303 	if (!p_info->b_allow_pf_vf_change) {
2304 		DP_INFO(p_hwfn, "Can't relocate SBs as MFW is too old.\n");
2305 		return ECORE_INVAL;
2306 	}
2307 
2308 	/* If we're moving a SB from PF to VF, the client had to specify
2309 	 * which vector it wants to move.
2310 	 */
2311 	if (b_to_vf) {
2312 		igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
2313 		if (igu_sb_id == ECORE_SB_INVALID_IDX)
2314 			return ECORE_INVAL;
2315 	}
2316 
2317 	/* If we're moving a SB from VF to PF, need to validate there isn't
2318 	 * already a line configured for that vector.
2319 	 */
2320 	if (!b_to_vf) {
2321 		if (ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1) !=
2322 		    ECORE_SB_INVALID_IDX)
2323 			return ECORE_INVAL;
2324 	}
2325 
2326 	/* We need to validate that the SB can actually be relocated.
2327 	 * This would also handle the previous case where we've explicitly
2328 	 * stated which IGU SB needs to move.
2329 	 */
2330 	for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2331 	     igu_sb_id++) {
2332 		p_block = &p_info->entry[igu_sb_id];
2333 
2334 		if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2335 		    !(p_block->status & ECORE_IGU_STATUS_FREE) ||
2336 		    (!!(p_block->status & ECORE_IGU_STATUS_PF) != b_to_vf)) {
2337 			if (b_to_vf)
2338 				return ECORE_INVAL;
2339 			else
2340 				continue;
2341 		}
2342 
2343 		break;
2344 	}
2345 
2346 	if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) {
2347 		DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
2348 			   "Failed to find a free SB to move\n");
2349 		return ECORE_INVAL;
2350 	}
2351 
2352 	/* At this point, p_block points to the SB we want to relocate */
2353 	if (b_to_vf) {
2354 		p_block->status &= ~ECORE_IGU_STATUS_PF;
2355 
2356 		/* It doesn't matter which VF number we choose, since we're
2357 		 * going to disable the line; But let's keep it in range.
2358 		 */
2359 		vf_num = (u16)p_hwfn->p_dev->p_iov_info->first_vf_in_pf;
2360 
2361 		p_block->function_id = (u8)vf_num;
2362 		p_block->is_pf = 0;
2363 		p_block->vector_number = 0;
2364 
2365 		p_info->usage.cnt--;
2366 		p_info->usage.free_cnt--;
2367 		p_info->usage.iov_cnt++;
2368 		p_info->usage.free_cnt_iov++;
2369 
2370 		/* TODO - if SBs aren't really the limiting factor,
2371 		 * then it might not be accurate [in the since that
2372 		 * we might not need decrement the feature].
2373 		 */
2374 		p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]--;
2375 		p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]++;
2376 	} else {
2377 		p_block->status |= ECORE_IGU_STATUS_PF;
2378 		p_block->function_id = p_hwfn->rel_pf_id;
2379 		p_block->is_pf = 1;
2380 		p_block->vector_number = sb_id + 1;
2381 
2382 		p_info->usage.cnt++;
2383 		p_info->usage.free_cnt++;
2384 		p_info->usage.iov_cnt--;
2385 		p_info->usage.free_cnt_iov--;
2386 
2387 		p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]++;
2388 		p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]--;
2389 	}
2390 
2391 	/* Update the IGU and CAU with the new configuration */
2392 	SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2393 		  p_block->function_id);
2394 	SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2395 	SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2396 	SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2397 		  p_block->vector_number);
2398 
2399 	ecore_wr(p_hwfn, p_ptt,
2400 		 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id,
2401 		 val);
2402 
2403 	ecore_int_cau_conf_sb(p_hwfn, p_ptt, 0,
2404 			      igu_sb_id, vf_num,
2405 			      p_block->is_pf ? 0 : 1);
2406 
2407 	DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2408 		   "Relocation: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2409 		   igu_sb_id, p_block->function_id,
2410 		   p_block->is_pf, p_block->vector_number);
2411 
2412 	return ECORE_SUCCESS;
2413 }
2414 
2415 /**
2416  * @brief Initialize igu runtime registers
2417  *
2418  * @param p_hwfn
2419  */
ecore_int_igu_init_rt(struct ecore_hwfn * p_hwfn)2420 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2421 {
2422 	u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2423 
2424 	STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2425 }
2426 
2427 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2428 			  IGU_CMD_INT_ACK_BASE)
2429 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2430 			  IGU_CMD_INT_ACK_BASE)
ecore_int_igu_read_sisr_reg(struct ecore_hwfn * p_hwfn)2431 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2432 {
2433 	u32 intr_status_hi = 0, intr_status_lo = 0;
2434 	u64 intr_status = 0;
2435 
2436 	intr_status_lo = REG_RD(p_hwfn,
2437 				GTT_BAR0_MAP_REG_IGU_CMD +
2438 				LSB_IGU_CMD_ADDR * 8);
2439 	intr_status_hi = REG_RD(p_hwfn,
2440 				GTT_BAR0_MAP_REG_IGU_CMD +
2441 				MSB_IGU_CMD_ADDR * 8);
2442 	intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2443 
2444 	return intr_status;
2445 }
2446 
ecore_int_sp_dpc_setup(struct ecore_hwfn * p_hwfn)2447 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2448 {
2449 	OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2450 	p_hwfn->b_sp_dpc_enabled = true;
2451 }
2452 
ecore_int_sp_dpc_alloc(struct ecore_hwfn * p_hwfn)2453 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2454 {
2455 	p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2456 	if (!p_hwfn->sp_dpc)
2457 		return ECORE_NOMEM;
2458 
2459 	return ECORE_SUCCESS;
2460 }
2461 
ecore_int_sp_dpc_free(struct ecore_hwfn * p_hwfn)2462 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2463 {
2464 	OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2465 	p_hwfn->sp_dpc = OSAL_NULL;
2466 }
2467 
ecore_int_alloc(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)2468 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2469 				     struct ecore_ptt *p_ptt)
2470 {
2471 	enum _ecore_status_t rc = ECORE_SUCCESS;
2472 
2473 	rc = ecore_int_sp_dpc_alloc(p_hwfn);
2474 	if (rc != ECORE_SUCCESS) {
2475 		DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2476 		return rc;
2477 	}
2478 
2479 	rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2480 	if (rc != ECORE_SUCCESS) {
2481 		DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2482 		return rc;
2483 	}
2484 
2485 	rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2486 	if (rc != ECORE_SUCCESS)
2487 		DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2488 
2489 	return rc;
2490 }
2491 
ecore_int_free(struct ecore_hwfn * p_hwfn)2492 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2493 {
2494 	ecore_int_sp_sb_free(p_hwfn);
2495 	ecore_int_sb_attn_free(p_hwfn);
2496 	ecore_int_sp_dpc_free(p_hwfn);
2497 }
2498 
ecore_int_setup(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)2499 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2500 {
2501 	if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2502 		return;
2503 
2504 	ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2505 	ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2506 	ecore_int_sp_dpc_setup(p_hwfn);
2507 }
2508 
ecore_int_get_num_sbs(struct ecore_hwfn * p_hwfn,struct ecore_sb_cnt_info * p_sb_cnt_info)2509 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2510 			   struct ecore_sb_cnt_info *p_sb_cnt_info)
2511 {
2512 	struct ecore_igu_info *p_igu_info = p_hwfn->hw_info.p_igu_info;
2513 
2514 	if (!p_igu_info || !p_sb_cnt_info)
2515 		return;
2516 
2517 	OSAL_MEMCPY(p_sb_cnt_info, &p_igu_info->usage,
2518 		    sizeof(*p_sb_cnt_info));
2519 }
2520 
ecore_int_disable_post_isr_release(struct ecore_dev * p_dev)2521 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2522 {
2523 	int i;
2524 
2525 	for_each_hwfn(p_dev, i)
2526 		p_dev->hwfns[i].b_int_requested = false;
2527 }
2528 
ecore_int_attn_clr_enable(struct ecore_dev * p_dev,bool clr_enable)2529 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2530 {
2531 	p_dev->attn_clr_en = clr_enable;
2532 }
2533 
ecore_int_set_timer_res(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 timer_res,u16 sb_id,bool tx)2534 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2535 					     struct ecore_ptt *p_ptt,
2536 					     u8 timer_res, u16 sb_id, bool tx)
2537 {
2538 	struct cau_sb_entry sb_entry;
2539 	enum _ecore_status_t rc;
2540 
2541 	if (!p_hwfn->hw_init_done) {
2542 		DP_ERR(p_hwfn, "hardware not initialized yet\n");
2543 		return ECORE_INVAL;
2544 	}
2545 
2546 	rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2547 				 sb_id * sizeof(u64),
2548 				 (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2549 	if (rc != ECORE_SUCCESS) {
2550 		DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2551 		return rc;
2552 	}
2553 
2554 	if (tx)
2555 		SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2556 	else
2557 		SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2558 
2559 	rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2560 				 (u64)(osal_uintptr_t)&sb_entry,
2561 				 CAU_REG_SB_VAR_MEMORY +
2562 				 sb_id * sizeof(u64), 2, 0);
2563 	if (rc != ECORE_SUCCESS) {
2564 		DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2565 		return rc;
2566 	}
2567 
2568 	return rc;
2569 }
2570 
ecore_int_get_sb_dbg(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct ecore_sb_info * p_sb,struct ecore_sb_info_dbg * p_info)2571 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
2572 					  struct ecore_ptt *p_ptt,
2573 					  struct ecore_sb_info *p_sb,
2574 					  struct ecore_sb_info_dbg *p_info)
2575 {
2576 	u16 sbid = p_sb->igu_sb_id;
2577 	int i;
2578 
2579 	if (IS_VF(p_hwfn->p_dev))
2580 		return ECORE_INVAL;
2581 
2582 	if (sbid > NUM_OF_SBS(p_hwfn->p_dev))
2583 		return ECORE_INVAL;
2584 
2585 	p_info->igu_prod = ecore_rd(p_hwfn, p_ptt,
2586 				    IGU_REG_PRODUCER_MEMORY + sbid * 4);
2587 	p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
2588 				    IGU_REG_CONSUMER_MEM + sbid * 4);
2589 
2590 	for (i = 0; i < PIS_PER_SB; i++)
2591 		p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
2592 					      CAU_REG_PI_MEMORY +
2593 					      sbid * 4 * PIS_PER_SB +  i * 4);
2594 
2595 	return ECORE_SUCCESS;
2596 }
2597