xref: /titanic_41/usr/src/uts/common/io/cxgbe/t4nex/adapter.h (revision 6774dc07ebd5a9d69956f033d5ac5a68803bd66b)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source. A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * This file is part of the Chelsio T4 support code.
14  *
15  * Copyright (C) 2011-2013 Chelsio Communications.  All rights reserved.
16  *
17  * This program is distributed in the hope that it will be useful, but WITHOUT
18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
20  * release for licensing terms and conditions.
21  */
22 
23 #ifndef __CXGBE_ADAPTER_H
24 #define	__CXGBE_ADAPTER_H
25 
26 #include <sys/ddi.h>
27 #include <sys/mac_provider.h>
28 #include <sys/ethernet.h>
29 #include <sys/queue.h>
30 
31 #include "offload.h"
32 #include "firmware/t4fw_interface.h"
33 
34 struct adapter;
35 typedef struct adapter adapter_t;
36 
37 enum {
38 	FW_IQ_QSIZE = 256,
39 	FW_IQ_ESIZE = 64,	/* At least 64 mandated by the firmware spec */
40 
41 	RX_IQ_QSIZE = 1024,
42 	RX_IQ_ESIZE = 64,	/* At least 64 so CPL_RX_PKT will fit */
43 
44 	EQ_ESIZE = 64,		/* All egres queues use this entry size */
45 
46 	RX_FL_ESIZE = 64,	/* 8 64bit addresses */
47 
48 	FL_BUF_SIZES = 4,
49 
50 	CTRL_EQ_QSIZE = 128,
51 
52 	TX_EQ_QSIZE = 1024,
53 	TX_SGL_SEGS = 36,
54 	TX_WR_FLITS = SGE_MAX_WR_LEN / 8
55 };
56 
57 enum {
58 	/* adapter flags */
59 	FULL_INIT_DONE	= (1 << 0),
60 	FW_OK		= (1 << 1),
61 	INTR_FWD	= (1 << 2),
62 	INTR_ALLOCATED	= (1 << 3),
63 	MASTER_PF	= (1 << 4),
64 
65 	CXGBE_BUSY	= (1 << 9),
66 
67 	/* port flags */
68 	DOOMED		= (1 << 0),
69 	PORT_INIT_DONE	= (1 << 1),
70 };
71 
72 enum {
73 	/* Features */
74 	CXGBE_HW_LSO	= (1 << 0),
75 	CXGBE_HW_CSUM	= (1 << 1),
76 };
77 
78 #define	IS_DOOMED(pi)	(pi->flags & DOOMED)
79 #define	SET_DOOMED(pi)	do { pi->flags |= DOOMED; } while (0)
80 #define	IS_BUSY(sc)	(sc->flags & CXGBE_BUSY)
81 #define	SET_BUSY(sc)	do { sc->flags |= CXGBE_BUSY; } while (0)
82 #define	CLR_BUSY(sc)	do { sc->flags &= ~CXGBE_BUSY; } while (0)
83 
84 struct port_info {
85 	PORT_INFO_HDR;
86 
87 	kmutex_t lock;
88 	struct adapter *adapter;
89 
90 #ifndef TCP_OFFLOAD_DISABLE
91 	void *tdev;
92 #endif
93 
94 	unsigned int flags;
95 
96 	uint16_t viid;
97 	int16_t  xact_addr_filt; /* index of exact MAC address filter */
98 	uint16_t rss_size;	/* size of VI's RSS table slice */
99 	uint16_t ntxq;		/* # of tx queues */
100 	uint16_t first_txq;	/* index of first tx queue */
101 	uint16_t nrxq;		/* # of rx queues */
102 	uint16_t first_rxq;	/* index of first rx queue */
103 #ifndef TCP_OFFLOAD_DISABLE
104 	uint16_t nofldtxq;		/* # of offload tx queues */
105 	uint16_t first_ofld_txq;	/* index of first offload tx queue */
106 	uint16_t nofldrxq;		/* # of offload rx queues */
107 	uint16_t first_ofld_rxq;	/* index of first offload rx queue */
108 #endif
109 	uint8_t  lport;		/* associated offload logical port */
110 	int8_t   mdio_addr;
111 	uint8_t  port_type;
112 	uint8_t  mod_type;
113 	uint8_t  port_id;
114 	uint8_t  tx_chan;
115 	uint8_t instance; /* Associated adapter instance */
116 	uint8_t child_inst; /* Associated child instance */
117 	uint8_t	tmr_idx;
118 	int8_t	pktc_idx;
119 	struct link_config link_cfg;
120 	struct port_stats stats;
121 	uint32_t features;
122 	kstat_t *ksp_config;
123 	kstat_t *ksp_info;
124 };
125 
126 struct fl_sdesc {
127 	struct rxbuf *rxb;
128 };
129 
130 struct tx_desc {
131 	__be64 flit[8];
132 };
133 
134 /* DMA maps used for tx */
135 struct tx_maps {
136 	ddi_dma_handle_t *map;
137 	uint32_t map_total;	/* # of DMA maps */
138 	uint32_t map_pidx;	/* next map to be used */
139 	uint32_t map_cidx;	/* reclaimed up to this index */
140 	uint32_t map_avail;	/* # of available maps */
141 };
142 
143 struct tx_sdesc {
144 	mblk_t *m;
145 	uint32_t txb_used;	/* # of bytes of tx copy buffer used */
146 	uint16_t hdls_used;	/* # of dma handles used */
147 	uint16_t desc_used;	/* # of hardware descriptors used */
148 };
149 
150 enum {
151 	/* iq flags */
152 	IQ_ALLOCATED	= (1 << 0),	/* firmware resources allocated */
153 	IQ_INTR		= (1 << 1),	/* iq takes direct interrupt */
154 	IQ_HAS_FL	= (1 << 2),	/* iq has fl */
155 
156 	/* iq state */
157 	IQS_DISABLED	= 0,
158 	IQS_BUSY	= 1,
159 	IQS_IDLE	= 2,
160 };
161 
162 /*
163  * Ingress Queue: T4 is producer, driver is consumer.
164  */
165 struct sge_iq {
166 	unsigned int flags;
167 	ddi_dma_handle_t dhdl;
168 	ddi_acc_handle_t ahdl;
169 
170 	volatile uint_t state;
171 	__be64 *desc;		/* KVA of descriptor ring */
172 	uint64_t ba;		/* bus address of descriptor ring */
173 	const __be64 *cdesc;	/* current descriptor */
174 	struct adapter *adapter; /* associated  adapter */
175 	uint8_t  gen;		/* generation bit */
176 	uint8_t  intr_params;	/* interrupt holdoff parameters */
177 	int8_t   intr_pktc_idx;	/* packet count threshold index */
178 	uint8_t  intr_next;	/* holdoff for next interrupt */
179 	uint8_t  esize;		/* size (bytes) of each entry in the queue */
180 	uint16_t qsize;		/* size (# of entries) of the queue */
181 	uint16_t cidx;		/* consumer index */
182 	uint16_t pending;	/* # of descs processed since last doorbell */
183 	uint16_t cntxt_id;	/* SGE context id  for the iq */
184 	uint16_t abs_id;	/* absolute SGE id for the iq */
185 
186 	STAILQ_ENTRY(sge_iq) link;
187 };
188 
189 enum {
190 	EQ_CTRL		= 1,
191 	EQ_ETH		= 2,
192 #ifndef TCP_OFFLOAD_DISABLE
193 	EQ_OFLD		= 3,
194 #endif
195 
196 	/* eq flags */
197 	EQ_TYPEMASK	= 7,		/* 3 lsbits hold the type */
198 	EQ_ALLOCATED	= (1 << 3),	/* firmware resources allocated */
199 	EQ_DOOMED	= (1 << 4),	/* about to be destroyed */
200 	EQ_CRFLUSHED	= (1 << 5),	/* expecting an update from SGE */
201 	EQ_STALLED	= (1 << 6),	/* out of hw descriptors or dmamaps */
202 	EQ_MTX		= (1 << 7),	/* mutex has been initialized */
203 	EQ_STARTED	= (1 << 8),	/* started */
204 };
205 
206 /*
207  * Egress Queue: driver is producer, T4 is consumer.
208  *
209  * Note: A free list is an egress queue (driver produces the buffers and T4
210  * consumes them) but it's special enough to have its own struct (see sge_fl).
211  */
212 struct sge_eq {
213 	ddi_dma_handle_t desc_dhdl;
214 	ddi_acc_handle_t desc_ahdl;
215 	unsigned int flags;
216 	kmutex_t lock;
217 
218 	struct tx_desc *desc;	/* KVA of descriptor ring */
219 	uint64_t ba;		/* bus address of descriptor ring */
220 	struct sge_qstat *spg;	/* status page, for convenience */
221 	uint16_t cap;		/* max # of desc, for convenience */
222 	uint16_t avail;		/* available descriptors, for convenience */
223 	uint16_t qsize;		/* size (# of entries) of the queue */
224 	uint16_t cidx;		/* consumer idx (desc idx) */
225 	uint16_t pidx;		/* producer idx (desc idx) */
226 	uint16_t pending;	/* # of descriptors used since last doorbell */
227 	uint16_t iqid;		/* iq that gets egr_update for the eq */
228 	uint8_t tx_chan;	/* tx channel used by the eq */
229 	uint32_t cntxt_id;	/* SGE context id for the eq */
230 };
231 
232 enum {
233 	/* fl flags */
234 	FL_MTX		= (1 << 0),	/* mutex has been initialized */
235 	FL_STARVING	= (1 << 1),	/* on the list of starving fl's */
236 	FL_DOOMED	= (1 << 2),	/* about to be destroyed */
237 };
238 
239 #define	FL_RUNNING_LOW(fl)	(fl->cap - fl->needed <= fl->lowat)
240 #define	FL_NOT_RUNNING_LOW(fl)	(fl->cap - fl->needed >= 2 * fl->lowat)
241 
242 struct sge_fl {
243 	unsigned int flags;
244 	kmutex_t lock;
245 	ddi_dma_handle_t dhdl;
246 	ddi_acc_handle_t ahdl;
247 
248 	__be64 *desc;		/* KVA of descriptor ring, ptr to addresses */
249 	uint64_t ba;		/* bus address of descriptor ring */
250 	struct fl_sdesc *sdesc;	/* KVA of software descriptor ring */
251 	uint32_t cap;		/* max # of buffers, for convenience */
252 	uint16_t qsize;		/* size (# of entries) of the queue */
253 	uint16_t cntxt_id;	/* SGE context id for the freelist */
254 	uint32_t cidx;		/* consumer idx (buffer idx, NOT hw desc idx) */
255 	uint32_t pidx;		/* producer idx (buffer idx, NOT hw desc idx) */
256 	uint32_t needed;	/* # of buffers needed to fill up fl. */
257 	uint32_t lowat;		/* # of buffers <= this means fl needs help */
258 	uint32_t pending;	/* # of bufs allocated since last doorbell */
259 	uint32_t offset;	/* current packet within the larger buffer */
260 	uint16_t copy_threshold; /* anything this size or less is copied up */
261 
262 	uint64_t copied_up;	/* # of frames copied into mblk and handed up */
263 	uint64_t passed_up;	/* # of frames wrapped in mblk and handed up */
264 
265 	TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
266 };
267 
268 /* txq: SGE egress queue + miscellaneous items */
269 struct sge_txq {
270 	struct sge_eq eq;	/* MUST be first */
271 
272 	struct port_info *port;	/* the port this txq belongs to */
273 	struct tx_sdesc *sdesc;	/* KVA of software descriptor ring */
274 
275 	/* DMA handles used for tx */
276 	ddi_dma_handle_t *tx_dhdl;
277 	uint32_t tx_dhdl_total;	/* Total # of handles */
278 	uint32_t tx_dhdl_pidx;	/* next handle to be used */
279 	uint32_t tx_dhdl_cidx;	/* reclaimed up to this index */
280 	uint32_t tx_dhdl_avail;	/* # of available handles */
281 
282 	/* Copy buffers for tx */
283 	ddi_dma_handle_t txb_dhdl;
284 	ddi_acc_handle_t txb_ahdl;
285 	caddr_t txb_va;		/* KVA of copy buffers area */
286 	uint64_t txb_ba;	/* bus address of copy buffers area */
287 	uint32_t txb_size;	/* total size */
288 	uint32_t txb_next;	/* offset of next useable area in the buffer */
289 	uint32_t txb_avail;	/* # of bytes available */
290 	uint16_t copy_threshold; /* anything this size or less is copied up */
291 
292 	kstat_t *ksp;
293 
294 	/* stats for common events first */
295 
296 	uint64_t txcsum;	/* # of times hardware assisted with checksum */
297 	uint64_t tso_wrs;	/* # of IPv4 TSO work requests */
298 	uint64_t imm_wrs;	/* # of work requests with immediate data */
299 	uint64_t sgl_wrs;	/* # of work requests with direct SGL */
300 	uint64_t txpkt_wrs;	/* # of txpkt work requests (not coalesced) */
301 	uint64_t txpkts_wrs;	/* # of coalesced tx work requests */
302 	uint64_t txpkts_pkts;	/* # of frames in coalesced tx work requests */
303 	uint64_t txb_used;	/* # of tx copy buffers used (64 byte each) */
304 	uint64_t hdl_used;	/* # of DMA handles used */
305 
306 	/* stats for not-that-common events */
307 
308 	uint32_t txb_full;	/* txb ran out of space */
309 	uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */
310 	uint32_t dma_map_failed; /* couldn't obtain DMA mapping */
311 	uint32_t qfull;		/* out of hardware descriptors */
312 	uint32_t qflush;	/* # of SGE_EGR_UPDATE notifications for txq */
313 	uint32_t pullup_early;	/* # of pullups before starting frame's SGL */
314 	uint32_t pullup_late;	/* # of pullups while building frame's SGL */
315 	uint32_t pullup_failed;	/* # of failed pullups */
316 };
317 
318 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
319 struct sge_rxq {
320 	struct sge_iq iq;	/* MUST be first */
321 	struct sge_fl fl;
322 
323 	struct port_info *port;	/* the port this rxq belongs to */
324 	kstat_t *ksp;
325 
326 	/* stats for common events first */
327 
328 	uint64_t rxcsum;	/* # of times hardware assisted with checksum */
329 
330 	/* stats for not-that-common events */
331 
332 	uint32_t nomem;		/* mblk allocation during rx failed */
333 };
334 
335 #ifndef TCP_OFFLOAD_DISABLE
336 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
337 struct sge_ofld_rxq {
338 	struct sge_iq iq;	/* MUST be first */
339 	struct sge_fl fl;
340 };
341 
342 /*
343  * wrq: SGE egress queue that is given prebuilt work requests.  Both the control
344  * and offload tx queues are of this type.
345  */
346 struct sge_wrq {
347 	struct sge_eq eq;	/* MUST be first */
348 
349 	struct adapter *adapter;
350 
351 	/* List of WRs held up due to lack of tx descriptors */
352 	struct mblk_pair wr_list;
353 
354 	/* stats for common events first */
355 
356 	uint64_t tx_wrs;	/* # of tx work requests */
357 
358 	/* stats for not-that-common events */
359 
360 	uint32_t no_desc;	/* out of hardware descriptors */
361 };
362 #endif
363 
364 struct sge {
365 	int fl_starve_threshold;
366 
367 	int nrxq;	/* total rx queues (all ports and the rest) */
368 	int ntxq;	/* total tx queues (all ports and the rest) */
369 #ifndef TCP_OFFLOAD_DISABLE
370 	int nofldrxq;	/* total # of TOE rx queues */
371 	int nofldtxq;	/* total # of TOE tx queues */
372 #endif
373 	int niq;	/* total ingress queues */
374 	int neq;	/* total egress queues */
375 
376 	struct sge_iq fwq;	/* Firmware event queue */
377 	struct sge_wrq mgmtq;	/* Management queue (Control queue) */
378 	struct sge_txq *txq;	/* NIC tx queues */
379 	struct sge_rxq *rxq;	/* NIC rx queues */
380 #ifndef TCP_OFFLOAD_DISABLE
381 	struct sge_wrq *ctrlq;	/* Control queues */
382 	struct sge_wrq *ofld_txq;	/* TOE tx queues */
383 	struct sge_ofld_rxq *ofld_rxq;	/* TOE rx queues */
384 #endif
385 
386 	uint16_t iq_start;
387 	int eq_start;
388 	struct sge_iq **iqmap;	/* iq->cntxt_id to iq mapping */
389 	struct sge_eq **eqmap;	/* eq->cntxt_id to eq mapping */
390 
391 	/* Device access and DMA attributes for all the descriptor rings */
392 	ddi_device_acc_attr_t acc_attr_desc;
393 	ddi_dma_attr_t	dma_attr_desc;
394 
395 	/* Device access and DMA attributes for tx buffers */
396 	ddi_device_acc_attr_t acc_attr_tx;
397 	ddi_dma_attr_t	dma_attr_tx;
398 
399 	/* Device access and DMA attributes for rx buffers are in rxb_params */
400 	kmem_cache_t *rxbuf_cache;
401 	struct rxbuf_cache_params rxb_params;
402 };
403 
404 struct driver_properties {
405 	/* There is a driver.conf variable for each of these */
406 	int max_ntxq_10g;
407 	int max_nrxq_10g;
408 	int max_ntxq_1g;
409 	int max_nrxq_1g;
410 #ifndef TCP_OFFLOAD_DISABLE
411 	int max_nofldtxq_10g;
412 	int max_nofldrxq_10g;
413 	int max_nofldtxq_1g;
414 	int max_nofldrxq_1g;
415 #endif
416 	int intr_types;
417 	int tmr_idx_10g;
418 	int pktc_idx_10g;
419 	int tmr_idx_1g;
420 	int pktc_idx_1g;
421 	int qsize_txq;
422 	int qsize_rxq;
423 
424 	int timer_val[SGE_NTIMERS];
425 	int counter_val[SGE_NCOUNTERS];
426 };
427 
428 struct rss_header;
429 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
430     mblk_t *);
431 
432 struct adapter {
433 	SLIST_ENTRY(adapter) link;
434 	dev_info_t *dip;
435 	dev_t dev;
436 
437 	unsigned int pf;
438 	unsigned int mbox;
439 
440 	uint_t open;	/* character device is open */
441 
442 	/* PCI config space access handle */
443 	ddi_acc_handle_t pci_regh;
444 
445 	/* MMIO register access handle */
446 	ddi_acc_handle_t regh;
447 	caddr_t regp;
448 
449 	/* Interrupt information */
450 	int intr_type;
451 	int intr_count;
452 	int intr_cap;
453 	uint_t intr_pri;
454 	ddi_intr_handle_t *intr_handle;
455 
456 	struct driver_properties props;
457 	kstat_t *ksp;
458 
459 	struct sge sge;
460 
461 	struct port_info *port[MAX_NPORTS];
462 	uint8_t chan_map[NCHAN];
463 	uint32_t filter_mode;
464 
465 	struct l2t_data *l2t;	/* L2 table */
466 	struct tid_info tids;
467 
468 	int registered_device_map;
469 	int open_device_map;
470 	int flags;
471 
472 	unsigned int cfcsum;
473 	struct adapter_params params;
474 	struct t4_virt_res vres;
475 
476 #ifndef TCP_OFFLOAD_DISABLE
477 	struct uld_softc tom;
478 	struct tom_tunables tt;
479 #endif
480 
481 #ifndef TCP_OFFLOAD_DISABLE
482 	int offload_map;
483 #endif
484 	uint16_t linkcaps;
485 	uint16_t niccaps;
486 	uint16_t toecaps;
487 	uint16_t rdmacaps;
488 	uint16_t iscsicaps;
489 	uint16_t fcoecaps;
490 
491 	cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
492 
493 	kmutex_t lock;
494 	kcondvar_t cv;
495 
496 	/* Starving free lists */
497 	kmutex_t sfl_lock;	/* same cache-line as sc_lock? but that's ok */
498 	TAILQ_HEAD(, sge_fl) sfl;
499 	timeout_id_t sfl_timer;
500 };
501 
502 enum {
503 	NIC_H = 0,
504 	TOM_H,
505 	IW_H,
506 	ISCSI_H
507 };
508 
509 #define	ADAPTER_LOCK(sc)		mutex_enter(&(sc)->lock)
510 #define	ADAPTER_UNLOCK(sc)		mutex_exit(&(sc)->lock)
511 #define	ADAPTER_LOCK_ASSERT_OWNED(sc)	ASSERT(mutex_owned(&(sc)->lock))
512 #define	ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock))
513 
514 #define	PORT_LOCK(pi)			mutex_enter(&(pi)->lock)
515 #define	PORT_UNLOCK(pi)			mutex_exit(&(pi)->lock)
516 #define	PORT_LOCK_ASSERT_OWNED(pi)	ASSERT(mutex_owned(&(pi)->lock))
517 #define	PORT_LOCK_ASSERT_NOTOWNED(pi)	ASSERT(!mutex_owned(&(pi)->lock))
518 
519 #define	IQ_LOCK(iq)			mutex_enter(&(iq)->lock)
520 #define	IQ_UNLOCK(iq)			mutex_exit(&(iq)->lock)
521 #define	IQ_LOCK_ASSERT_OWNED(iq)	ASSERT(mutex_owned(&(iq)->lock))
522 #define	IQ_LOCK_ASSERT_NOTOWNED(iq)	ASSERT(!mutex_owned(&(iq)->lock))
523 
524 #define	FL_LOCK(fl)			mutex_enter(&(fl)->lock)
525 #define	FL_UNLOCK(fl)			mutex_exit(&(fl)->lock)
526 #define	FL_LOCK_ASSERT_OWNED(fl)	ASSERT(mutex_owned(&(fl)->lock))
527 #define	FL_LOCK_ASSERT_NOTOWNED(fl)	ASSERT(!mutex_owned(&(fl)->lock))
528 
529 #define	RXQ_LOCK(rxq)			IQ_LOCK(&(rxq)->iq)
530 #define	RXQ_UNLOCK(rxq)			IQ_UNLOCK(&(rxq)->iq)
531 #define	RXQ_LOCK_ASSERT_OWNED(rxq)	IQ_LOCK_ASSERT_OWNED(&(rxq)->iq)
532 #define	RXQ_LOCK_ASSERT_NOTOWNED(rxq)	IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq)
533 
534 #define	RXQ_FL_LOCK(rxq)		FL_LOCK(&(rxq)->fl)
535 #define	RXQ_FL_UNLOCK(rxq)		FL_UNLOCK(&(rxq)->fl)
536 #define	RXQ_FL_LOCK_ASSERT_OWNED(rxq)	FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
537 #define	RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
538 
539 #define	EQ_LOCK(eq)			mutex_enter(&(eq)->lock)
540 #define	EQ_UNLOCK(eq)			mutex_exit(&(eq)->lock)
541 #define	EQ_LOCK_ASSERT_OWNED(eq)	ASSERT(mutex_owned(&(eq)->lock))
542 #define	EQ_LOCK_ASSERT_NOTOWNED(eq)	ASSERT(!mutex_owned(&(eq)->lock))
543 
544 #define	TXQ_LOCK(txq)			EQ_LOCK(&(txq)->eq)
545 #define	TXQ_UNLOCK(txq)			EQ_UNLOCK(&(txq)->eq)
546 #define	TXQ_LOCK_ASSERT_OWNED(txq)	EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
547 #define	TXQ_LOCK_ASSERT_NOTOWNED(txq)	EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
548 
549 #define	for_each_txq(pi, iter, txq) \
550 	txq = &pi->adapter->sge.txq[pi->first_txq]; \
551 	for (iter = 0; iter < pi->ntxq; ++iter, ++txq)
552 #define	for_each_rxq(pi, iter, rxq) \
553 	rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \
554 	for (iter = 0; iter < pi->nrxq; ++iter, ++rxq)
555 #define	for_each_ofld_txq(pi, iter, ofld_txq) \
556 	ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \
557 	for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq)
558 #define	for_each_ofld_rxq(pi, iter, ofld_rxq) \
559 	ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \
560 	for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq)
561 
562 #define	NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1)
563 
564 /* One for errors, one for firmware events */
565 #define	T4_EXTRA_INTR 2
566 
567 /* adapter.c */
568 uint32_t t4_read_reg(struct adapter *sc, uint32_t reg);
569 void t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val);
570 void t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val);
571 void t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val);
572 void t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val);
573 void t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val);
574 void t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val);
575 void t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val);
576 uint64_t t4_read_reg64(struct adapter *sc, uint32_t reg);
577 void t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val);
578 struct port_info *adap2pinfo(struct adapter *sc, int idx);
579 void t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]);
580 bool is_10G_port(const struct port_info *pi);
581 struct sge_rxq *iq_to_rxq(struct sge_iq *iq);
582 int t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m);
583 
584 /* t4_nexus.c */
585 int t4_os_find_pci_capability(struct adapter *sc, int cap);
586 void t4_os_portmod_changed(const struct adapter *sc, int idx);
587 int adapter_full_init(struct adapter *sc);
588 int adapter_full_uninit(struct adapter *sc);
589 int port_full_init(struct port_info *pi);
590 int port_full_uninit(struct port_info *pi);
591 void enable_port_queues(struct port_info *pi);
592 void disable_port_queues(struct port_info *pi);
593 int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h);
594 void t4_iterate(void (*func)(int, void *), void *arg);
595 
596 /* t4_sge.c */
597 void t4_sge_init(struct adapter *sc);
598 int t4_setup_adapter_queues(struct adapter *sc);
599 int t4_teardown_adapter_queues(struct adapter *sc);
600 int t4_setup_port_queues(struct port_info *pi);
601 int t4_teardown_port_queues(struct port_info *pi);
602 uint_t t4_intr_all(caddr_t arg1, caddr_t arg2);
603 uint_t t4_intr(caddr_t arg1, caddr_t arg2);
604 uint_t t4_intr_err(caddr_t arg1, caddr_t arg2);
605 int t4_mgmt_tx(struct adapter *sc, mblk_t *m);
606 int t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0);
607 
608 mblk_t *t4_eth_tx(struct port_info *pi, struct sge_txq *txq, mblk_t *frame);
609 int t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps,  int count,
610     int flags);
611 
612 /* t4_mac.c */
613 void t4_mc_init(struct port_info *pi);
614 void t4_os_link_changed(struct adapter *sc, int idx, int link_stat);
615 void t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m);
616 
617 /* t4_ioctl.c */
618 int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode);
619 
620 struct l2t_data *t4_init_l2t(struct adapter *sc);
621 #endif /* __CXGBE_ADAPTER_H */
622