1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_ERR_IMPL_H 27 #define _SYS_PX_ERR_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Bit Error handling tables: 37 * bit Bit Number 38 * counter Counter for number of errors countered for this bit 39 * err_handler Error Handler Function 40 * erpt_handler Ereport Handler Function 41 * class_name Class Name used for sending ereports for this bit. 42 */ 43 typedef struct px_err_bit_desc { 44 uint_t bit; 45 uint_t counter; 46 int (*err_handler)(); 47 int (*erpt_handler)(); 48 char *class_name; 49 } px_err_bit_desc_t; 50 51 /* 52 * Reg Error handling tables: 53 * 54 * chip_mask mask of chip types supporting this error register 55 * 56 * *intr_mask_p bitmask for enabled interrupts 57 * *log_mask_p bitmask for logged interrupts 58 * *count_mask_p bitmask for counted interrupts 59 * 60 * *err_bit_tbl error bit table 61 * err_bit_keys number of entries in the error bit table. 62 * 63 * reg_bank register bank base 64 * 65 * last_reg last captured register 66 * log_addr interrupt log register offset 67 * enable_addr interrupt enable register offset 68 * status_addr interrupt status register offset 69 * clear_addr interrupt clear register offset 70 * 71 * *msg error messages table 72 */ 73 typedef struct px_err_reg_desc { 74 uint8_t chip_mask; 75 uint64_t *intr_mask_p; 76 uint64_t *log_mask_p; 77 uint64_t *count_mask_p; 78 px_err_bit_desc_t *err_bit_tbl; 79 uint_t err_bit_keys; 80 uint_t reg_bank; 81 uint64_t last_reg; 82 uint32_t log_addr; 83 uint32_t enable_addr; 84 uint32_t status_addr; 85 uint32_t clear_addr; 86 char *msg; 87 } px_err_reg_desc_t; 88 89 /* 90 * Macro to create the error handling forward declaration 91 * 92 * The error handlers examines error, determine the nature of the error 93 * and return error status in terms of PX_HW_RESET | PX_PANIC | ... 94 * terminology. 95 */ 96 #define PX_ERR_BIT_HANDLE_DEC(n) int px_err_ ## n ## _handle\ 97 (dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, \ 98 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 99 #define PX_ERR_BIT_HANDLE(n) px_err_ ## n ## _handle 100 101 /* 102 * Macro to create the ereport forward declaration 103 */ 104 #define PX_ERPT_SEND_DEC(n) int px_err_ ## n ## _send_ereport\ 105 (dev_info_t *rpdip, caddr_t csr_base, uint64_t ss_reg, \ 106 ddi_fm_error_t *derr, uint_t bit, char *class_name) 107 #define PX_ERPT_SEND(n) px_err_ ## n ## _send_ereport 108 109 /* 110 * Macro to test for primary vs secondary 111 */ 112 #define PX_ERR_IS_PRI(bit) (bit < 32) 113 114 /* 115 * Predefined error handling functions. 116 */ 117 void px_err_log_handle(dev_info_t *rpdip, px_err_reg_desc_t *err_reg_descr, 118 px_err_bit_desc_t *err_bit_descr, char *msg); 119 int px_err_hw_reset_handle(dev_info_t *rpdip, caddr_t csr_base, 120 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 121 px_err_bit_desc_t *err_bit_descr); 122 int px_err_panic_handle(dev_info_t *rpdip, caddr_t csr_base, 123 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 124 px_err_bit_desc_t *err_bit_descr); 125 int px_err_protected_handle(dev_info_t *rpdip, caddr_t csr_base, 126 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 127 px_err_bit_desc_t *err_bit_descr); 128 int px_err_no_panic_handle(dev_info_t *rpdip, caddr_t csr_base, 129 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 130 px_err_bit_desc_t *err_bit_descr); 131 int px_err_no_error_handle(dev_info_t *rpdip, caddr_t csr_base, 132 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 133 px_err_bit_desc_t *err_bit_descr); 134 135 /* 136 * Predefined ereport functions 137 */ 138 PX_ERPT_SEND_DEC(do_not); 139 140 141 /* 142 * JBC/UBC error handling and ereport forward declarations 143 */ 144 145 #define PX_ERR_JBC_CLASS(n) PCIEX_FIRE "." FIRE_JBC_ ## n 146 #define PX_ERR_UBC_CLASS(n) PCIEX_OBERON "." FIRE_UBC_ ## n 147 148 /* 149 * Fire JBC error Handling Forward Declarations 150 * the must-panic type errors such as PX_PANIC or 151 * post-reset-diagnosed type error such as PX_HW_RESET 152 * are not furthur diagnosed here because there is no 153 * justification to find out more as immediate error 154 * handling. FMA DE will do the post analysis. 155 */ 156 int px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 157 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 158 px_err_bit_desc_t *err_bit_descr); 159 int px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 160 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 161 px_err_bit_desc_t *err_bit_descr); 162 int px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 163 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 164 px_err_bit_desc_t *err_bit_descr); 165 int px_err_jbc_safe_acc_handle(dev_info_t *rpdip, caddr_t csr_base, 166 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 167 px_err_bit_desc_t *err_bit_descr); 168 169 /* Fire JBC error ereport Forward Declarations */ 170 PX_ERPT_SEND_DEC(jbc_fatal); 171 PX_ERPT_SEND_DEC(jbc_merge); 172 PX_ERPT_SEND_DEC(jbc_in); 173 PX_ERPT_SEND_DEC(jbc_out); 174 PX_ERPT_SEND_DEC(jbc_odcd); 175 PX_ERPT_SEND_DEC(jbc_idc); 176 PX_ERPT_SEND_DEC(jbc_csr); 177 178 /* Oberon UBC error ereport Forward Declarations */ 179 PX_ERPT_SEND_DEC(ubc_fatal); 180 181 182 /* 183 * DMC error handling and ereport forward declarations 184 */ 185 186 #define PX_ERR_DMC_CLASS(n) PCIEX_FIRE "." FIRE_DMC_ ## n 187 188 /* Fire Bit Error Handling Forward Declarations */ 189 int px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 190 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 191 px_err_bit_desc_t *err_bit_descr); 192 int px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 193 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 194 px_err_bit_desc_t *err_bit_descr); 195 int px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 196 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 197 px_err_bit_desc_t *err_bit_descr); 198 int px_err_mmu_parity_handle(dev_info_t *rpdip, caddr_t csr_base, 199 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 200 px_err_bit_desc_t *err_bit_descr); 201 202 /* Fire Ereport Handling Forward Declarations */ 203 PX_ERPT_SEND_DEC(imu_rds); 204 PX_ERPT_SEND_DEC(imu_scs); 205 PX_ERPT_SEND_DEC(imu); 206 PX_ERPT_SEND_DEC(mmu_tfar_tfsr); 207 PX_ERPT_SEND_DEC(mmu); 208 209 /* 210 * PEC error handling and ereport forward declarations 211 */ 212 213 #define PX_ERR_PEC_CLASS(n) PCIEX_FIRE "." FIRE_PEC_ ## n 214 #define PX_ERR_PEC_OB_CLASS(n) PCIEX_OBERON "." FIRE_PEC_ ## n 215 216 int px_err_wuc_ruc_handle(dev_info_t *rpdip, caddr_t csr_base, 217 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 218 px_err_bit_desc_t *err_bit_descr); 219 int px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 220 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 221 px_err_bit_desc_t *err_bit_descr); 222 int px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 223 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 224 px_err_bit_desc_t *err_bit_descr); 225 226 /* Fire Ereport Handling Forward Declarations */ 227 int px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 228 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 229 px_err_bit_desc_t *err_bit_descr); 230 int px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 231 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 232 px_err_bit_desc_t *err_bit_descr); 233 234 PX_ERPT_SEND_DEC(pec_ilu); 235 PX_ERPT_SEND_DEC(pciex_rx_ue); 236 PX_ERPT_SEND_DEC(pciex_tx_ue); 237 PX_ERPT_SEND_DEC(pciex_rx_tx_ue); 238 PX_ERPT_SEND_DEC(pciex_ue); 239 PX_ERPT_SEND_DEC(pciex_ce); 240 PX_ERPT_SEND_DEC(pciex_rx_oe); 241 PX_ERPT_SEND_DEC(pciex_rx_tx_oe); 242 PX_ERPT_SEND_DEC(pciex_oe); 243 244 #ifdef __cplusplus 245 } 246 #endif 247 248 #endif /* _SYS_PX_ERR_IMPL_H */ 249