1 #ifndef __src_common_sdk_nvidia_inc_alloc_alloc_channel_h__ 2 #define __src_common_sdk_nvidia_inc_alloc_alloc_channel_h__ 3 #include <nvrm/535.113.01/common/sdk/nvidia/inc/nvlimits.h> 4 5 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ 6 7 /* 8 * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 9 * SPDX-License-Identifier: MIT 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in 19 * all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 26 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 27 * DEALINGS IN THE SOFTWARE. 28 */ 29 30 typedef struct NV_MEMORY_DESC_PARAMS { 31 NV_DECLARE_ALIGNED(NvU64 base, 8); 32 NV_DECLARE_ALIGNED(NvU64 size, 8); 33 NvU32 addressSpace; 34 NvU32 cacheAttrib; 35 } NV_MEMORY_DESC_PARAMS; 36 37 #define NVOS04_FLAGS_CHANNEL_TYPE 1:0 38 #define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000 39 #define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE 40 #define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE 41 42 #define NVOS04_FLAGS_VPR 2:2 43 #define NVOS04_FLAGS_VPR_FALSE 0x00000000 44 #define NVOS04_FLAGS_VPR_TRUE 0x00000001 45 46 #define NVOS04_FLAGS_CC_SECURE 2:2 47 #define NVOS04_FLAGS_CC_SECURE_FALSE 0x00000000 48 #define NVOS04_FLAGS_CC_SECURE_TRUE 0x00000001 49 50 #define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3 51 #define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000 52 #define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001 53 54 #define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4 55 #define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000 56 #define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001 57 58 #define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5 59 #define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000 60 #define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001 61 62 #define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6 63 #define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000 64 #define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001 65 66 #define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7 67 #define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000 68 #define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001 69 70 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8 71 72 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11 73 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000 74 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001 75 76 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12 77 78 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21 79 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000 80 #define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001 81 82 #define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22 83 #define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000 84 #define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001 85 86 #define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23 87 #define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000 88 #define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001 89 90 #define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24 91 #define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000 92 #define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001 93 94 #define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25 95 #define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000 96 #define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001 97 98 #define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26 99 #define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000 100 #define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001 101 102 #define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27 103 #define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000 104 #define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001 105 106 #define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28 107 #define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000 108 #define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001 109 #define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002 110 111 #define NVOS04_FLAGS_MAP_CHANNEL 30:30 112 #define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000 113 #define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001 114 115 #define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31 116 #define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000 117 #define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001 118 119 #define CC_CHAN_ALLOC_IV_SIZE_DWORD 3U 120 #define CC_CHAN_ALLOC_NONCE_SIZE_DWORD 8U 121 122 typedef struct NV_CHANNEL_ALLOC_PARAMS { 123 124 NvHandle hObjectError; // error context DMA 125 NvHandle hObjectBuffer; // no longer used 126 NV_DECLARE_ALIGNED(NvU64 gpFifoOffset, 8); // offset to beginning of GP FIFO 127 NvU32 gpFifoEntries; // number of GP FIFO entries 128 129 NvU32 flags; 130 131 132 NvHandle hContextShare; // context share handle 133 NvHandle hVASpace; // VASpace for the channel 134 135 // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0 136 NvHandle hUserdMemory[NV_MAX_SUBDEVICES]; 137 138 // offset to beginning of UserD within hUserdMemory[x] 139 NV_DECLARE_ALIGNED(NvU64 userdOffset[NV_MAX_SUBDEVICES], 8); 140 141 // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated 142 NvU32 engineType; 143 // Channel identifier that is unique for the duration of a RM session 144 NvU32 cid; 145 // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods 146 NvU32 subDeviceId; 147 NvHandle hObjectEccError; // ECC error context DMA 148 149 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS instanceMem, 8); 150 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS userdMem, 8); 151 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS ramfcMem, 8); 152 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS mthdbufMem, 8); 153 154 NvHandle hPhysChannelGroup; // reserved 155 NvU32 internalFlags; // reserved 156 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS errorNotifierMem, 8); // reserved 157 NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved 158 NvU32 ProcessID; // reserved 159 NvU32 SubProcessID; // reserved 160 // IV used for CPU-side encryption / GPU-side decryption. 161 NvU32 encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved 162 // IV used for CPU-side decryption / GPU-side encryption. 163 NvU32 decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD]; // reserved 164 // Nonce used CPU-side signing / GPU-side signature verification. 165 NvU32 hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD]; // reserved 166 } NV_CHANNEL_ALLOC_PARAMS; 167 168 typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS; 169 170 #endif 171