xref: /linux/drivers/gpu/drm/i915/display/intel_cdclk.c (revision 003ec4ce424cc3421cf82ec1b6f004f9c0fcb8a3)
1 /*
2  * Copyright © 2006-2017 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include <linux/debugfs.h>
25 #include <linux/time.h>
26 
27 #include <drm/drm_fixed.h>
28 
29 #include "soc/intel_dram.h"
30 
31 #include "hsw_ips.h"
32 #include "i915_drv.h"
33 #include "i915_reg.h"
34 #include "intel_atomic.h"
35 #include "intel_atomic_plane.h"
36 #include "intel_audio.h"
37 #include "intel_bw.h"
38 #include "intel_cdclk.h"
39 #include "intel_crtc.h"
40 #include "intel_de.h"
41 #include "intel_display_types.h"
42 #include "intel_mchbar_regs.h"
43 #include "intel_pci_config.h"
44 #include "intel_pcode.h"
45 #include "intel_psr.h"
46 #include "intel_vdsc.h"
47 #include "skl_watermark.h"
48 #include "skl_watermark_regs.h"
49 #include "vlv_dsi.h"
50 #include "vlv_sideband.h"
51 
52 /**
53  * DOC: CDCLK / RAWCLK
54  *
55  * The display engine uses several different clocks to do its work. There
56  * are two main clocks involved that aren't directly related to the actual
57  * pixel clock or any symbol/bit clock of the actual output port. These
58  * are the core display clock (CDCLK) and RAWCLK.
59  *
60  * CDCLK clocks most of the display pipe logic, and thus its frequency
61  * must be high enough to support the rate at which pixels are flowing
62  * through the pipes. Downscaling must also be accounted as that increases
63  * the effective pixel rate.
64  *
65  * On several platforms the CDCLK frequency can be changed dynamically
66  * to minimize power consumption for a given display configuration.
67  * Typically changes to the CDCLK frequency require all the display pipes
68  * to be shut down while the frequency is being changed.
69  *
70  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
71  * DMC will not change the active CDCLK frequency however, so that part
72  * will still be performed by the driver directly.
73  *
74  * There are multiple components involved in the generation of the CDCLK
75  * frequency:
76  *
77  * - We have the CDCLK PLL, which generates an output clock based on a
78  *   reference clock and a ratio parameter.
79  * - The CD2X Divider, which divides the output of the PLL based on a
80  *   divisor selected from a set of pre-defined choices.
81  * - The CD2X Squasher, which further divides the output based on a
82  *   waveform represented as a sequence of bits where each zero
83  *   "squashes out" a clock cycle.
84  * - And, finally, a fixed divider that divides the output frequency by 2.
85  *
86  * As such, the resulting CDCLK frequency can be calculated with the
87  * following formula:
88  *
89  *     cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
90  *
91  * , where vco is the frequency generated by the PLL; cd2x_div
92  * represents the CD2X Divider; sq_len and sq_div are the bit length
93  * and the number of high bits for the CD2X Squasher waveform, respectively;
94  * and 2 represents the fixed divider.
95  *
96  * Note that some older platforms do not contain the CD2X Divider
97  * and/or CD2X Squasher, in which case we can ignore their respective
98  * factors in the formula above.
99  *
100  * Several methods exist to change the CDCLK frequency, which ones are
101  * supported depends on the platform:
102  *
103  * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
104  * - CD2X divider update. Single pipe can be active as the divider update
105  *   can be synchronized with the pipe's start of vblank.
106  * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
107  * - Squash waveform update. Pipes can be active.
108  * - Crawl and squash can also be done back to back. Pipes can be active.
109  *
110  * RAWCLK is a fixed frequency clock, often used by various auxiliary
111  * blocks such as AUX CH or backlight PWM. Hence the only thing we
112  * really need to know about RAWCLK is its frequency so that various
113  * dividers can be programmed correctly.
114  */
115 
116 struct intel_cdclk_funcs {
117 	void (*get_cdclk)(struct intel_display *display,
118 			  struct intel_cdclk_config *cdclk_config);
119 	void (*set_cdclk)(struct intel_display *display,
120 			  const struct intel_cdclk_config *cdclk_config,
121 			  enum pipe pipe);
122 	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
123 	u8 (*calc_voltage_level)(int cdclk);
124 };
125 
126 void intel_cdclk_get_cdclk(struct intel_display *display,
127 			   struct intel_cdclk_config *cdclk_config)
128 {
129 	display->funcs.cdclk->get_cdclk(display, cdclk_config);
130 }
131 
132 static void intel_cdclk_set_cdclk(struct intel_display *display,
133 				  const struct intel_cdclk_config *cdclk_config,
134 				  enum pipe pipe)
135 {
136 	display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
137 }
138 
139 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
140 {
141 	struct intel_display *display = to_intel_display(state);
142 
143 	return display->funcs.cdclk->modeset_calc_cdclk(state);
144 }
145 
146 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
147 					 int cdclk)
148 {
149 	return display->funcs.cdclk->calc_voltage_level(cdclk);
150 }
151 
152 static void fixed_133mhz_get_cdclk(struct intel_display *display,
153 				   struct intel_cdclk_config *cdclk_config)
154 {
155 	cdclk_config->cdclk = 133333;
156 }
157 
158 static void fixed_200mhz_get_cdclk(struct intel_display *display,
159 				   struct intel_cdclk_config *cdclk_config)
160 {
161 	cdclk_config->cdclk = 200000;
162 }
163 
164 static void fixed_266mhz_get_cdclk(struct intel_display *display,
165 				   struct intel_cdclk_config *cdclk_config)
166 {
167 	cdclk_config->cdclk = 266667;
168 }
169 
170 static void fixed_333mhz_get_cdclk(struct intel_display *display,
171 				   struct intel_cdclk_config *cdclk_config)
172 {
173 	cdclk_config->cdclk = 333333;
174 }
175 
176 static void fixed_400mhz_get_cdclk(struct intel_display *display,
177 				   struct intel_cdclk_config *cdclk_config)
178 {
179 	cdclk_config->cdclk = 400000;
180 }
181 
182 static void fixed_450mhz_get_cdclk(struct intel_display *display,
183 				   struct intel_cdclk_config *cdclk_config)
184 {
185 	cdclk_config->cdclk = 450000;
186 }
187 
188 static void i85x_get_cdclk(struct intel_display *display,
189 			   struct intel_cdclk_config *cdclk_config)
190 {
191 	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
192 	u16 hpllcc = 0;
193 
194 	/*
195 	 * 852GM/852GMV only supports 133 MHz and the HPLLCC
196 	 * encoding is different :(
197 	 * FIXME is this the right way to detect 852GM/852GMV?
198 	 */
199 	if (pdev->revision == 0x1) {
200 		cdclk_config->cdclk = 133333;
201 		return;
202 	}
203 
204 	pci_bus_read_config_word(pdev->bus,
205 				 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
206 
207 	/* Assume that the hardware is in the high speed state.  This
208 	 * should be the default.
209 	 */
210 	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
211 	case GC_CLOCK_133_200:
212 	case GC_CLOCK_133_200_2:
213 	case GC_CLOCK_100_200:
214 		cdclk_config->cdclk = 200000;
215 		break;
216 	case GC_CLOCK_166_250:
217 		cdclk_config->cdclk = 250000;
218 		break;
219 	case GC_CLOCK_100_133:
220 		cdclk_config->cdclk = 133333;
221 		break;
222 	case GC_CLOCK_133_266:
223 	case GC_CLOCK_133_266_2:
224 	case GC_CLOCK_166_266:
225 		cdclk_config->cdclk = 266667;
226 		break;
227 	}
228 }
229 
230 static void i915gm_get_cdclk(struct intel_display *display,
231 			     struct intel_cdclk_config *cdclk_config)
232 {
233 	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
234 	u16 gcfgc = 0;
235 
236 	pci_read_config_word(pdev, GCFGC, &gcfgc);
237 
238 	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
239 		cdclk_config->cdclk = 133333;
240 		return;
241 	}
242 
243 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
244 	case GC_DISPLAY_CLOCK_333_320_MHZ:
245 		cdclk_config->cdclk = 333333;
246 		break;
247 	default:
248 	case GC_DISPLAY_CLOCK_190_200_MHZ:
249 		cdclk_config->cdclk = 190000;
250 		break;
251 	}
252 }
253 
254 static void i945gm_get_cdclk(struct intel_display *display,
255 			     struct intel_cdclk_config *cdclk_config)
256 {
257 	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
258 	u16 gcfgc = 0;
259 
260 	pci_read_config_word(pdev, GCFGC, &gcfgc);
261 
262 	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
263 		cdclk_config->cdclk = 133333;
264 		return;
265 	}
266 
267 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
268 	case GC_DISPLAY_CLOCK_333_320_MHZ:
269 		cdclk_config->cdclk = 320000;
270 		break;
271 	default:
272 	case GC_DISPLAY_CLOCK_190_200_MHZ:
273 		cdclk_config->cdclk = 200000;
274 		break;
275 	}
276 }
277 
278 static unsigned int intel_hpll_vco(struct intel_display *display)
279 {
280 	static const unsigned int blb_vco[8] = {
281 		[0] = 3200000,
282 		[1] = 4000000,
283 		[2] = 5333333,
284 		[3] = 4800000,
285 		[4] = 6400000,
286 	};
287 	static const unsigned int pnv_vco[8] = {
288 		[0] = 3200000,
289 		[1] = 4000000,
290 		[2] = 5333333,
291 		[3] = 4800000,
292 		[4] = 2666667,
293 	};
294 	static const unsigned int cl_vco[8] = {
295 		[0] = 3200000,
296 		[1] = 4000000,
297 		[2] = 5333333,
298 		[3] = 6400000,
299 		[4] = 3333333,
300 		[5] = 3566667,
301 		[6] = 4266667,
302 	};
303 	static const unsigned int elk_vco[8] = {
304 		[0] = 3200000,
305 		[1] = 4000000,
306 		[2] = 5333333,
307 		[3] = 4800000,
308 	};
309 	static const unsigned int ctg_vco[8] = {
310 		[0] = 3200000,
311 		[1] = 4000000,
312 		[2] = 5333333,
313 		[3] = 6400000,
314 		[4] = 2666667,
315 		[5] = 4266667,
316 	};
317 	const unsigned int *vco_table;
318 	unsigned int vco;
319 	u8 tmp = 0;
320 
321 	/* FIXME other chipsets? */
322 	if (display->platform.gm45)
323 		vco_table = ctg_vco;
324 	else if (display->platform.g45)
325 		vco_table = elk_vco;
326 	else if (display->platform.i965gm)
327 		vco_table = cl_vco;
328 	else if (display->platform.pineview)
329 		vco_table = pnv_vco;
330 	else if (display->platform.g33)
331 		vco_table = blb_vco;
332 	else
333 		return 0;
334 
335 	tmp = intel_de_read(display, display->platform.pineview ||
336 			    display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO);
337 
338 	vco = vco_table[tmp & 0x7];
339 	if (vco == 0)
340 		drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
341 			tmp);
342 	else
343 		drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
344 
345 	return vco;
346 }
347 
348 static void g33_get_cdclk(struct intel_display *display,
349 			  struct intel_cdclk_config *cdclk_config)
350 {
351 	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
352 	static const u8 div_3200[] = { 12, 10,  8,  7, 5, 16 };
353 	static const u8 div_4000[] = { 14, 12, 10,  8, 6, 20 };
354 	static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
355 	static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
356 	const u8 *div_table;
357 	unsigned int cdclk_sel;
358 	u16 tmp = 0;
359 
360 	cdclk_config->vco = intel_hpll_vco(display);
361 
362 	pci_read_config_word(pdev, GCFGC, &tmp);
363 
364 	cdclk_sel = (tmp >> 4) & 0x7;
365 
366 	if (cdclk_sel >= ARRAY_SIZE(div_3200))
367 		goto fail;
368 
369 	switch (cdclk_config->vco) {
370 	case 3200000:
371 		div_table = div_3200;
372 		break;
373 	case 4000000:
374 		div_table = div_4000;
375 		break;
376 	case 4800000:
377 		div_table = div_4800;
378 		break;
379 	case 5333333:
380 		div_table = div_5333;
381 		break;
382 	default:
383 		goto fail;
384 	}
385 
386 	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
387 						div_table[cdclk_sel]);
388 	return;
389 
390 fail:
391 	drm_err(display->drm,
392 		"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
393 		cdclk_config->vco, tmp);
394 	cdclk_config->cdclk = 190476;
395 }
396 
397 static void pnv_get_cdclk(struct intel_display *display,
398 			  struct intel_cdclk_config *cdclk_config)
399 {
400 	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
401 	u16 gcfgc = 0;
402 
403 	pci_read_config_word(pdev, GCFGC, &gcfgc);
404 
405 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
406 	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
407 		cdclk_config->cdclk = 266667;
408 		break;
409 	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
410 		cdclk_config->cdclk = 333333;
411 		break;
412 	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
413 		cdclk_config->cdclk = 444444;
414 		break;
415 	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
416 		cdclk_config->cdclk = 200000;
417 		break;
418 	default:
419 		drm_err(display->drm,
420 			"Unknown pnv display core clock 0x%04x\n", gcfgc);
421 		fallthrough;
422 	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
423 		cdclk_config->cdclk = 133333;
424 		break;
425 	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
426 		cdclk_config->cdclk = 166667;
427 		break;
428 	}
429 }
430 
431 static void i965gm_get_cdclk(struct intel_display *display,
432 			     struct intel_cdclk_config *cdclk_config)
433 {
434 	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
435 	static const u8 div_3200[] = { 16, 10,  8 };
436 	static const u8 div_4000[] = { 20, 12, 10 };
437 	static const u8 div_5333[] = { 24, 16, 14 };
438 	const u8 *div_table;
439 	unsigned int cdclk_sel;
440 	u16 tmp = 0;
441 
442 	cdclk_config->vco = intel_hpll_vco(display);
443 
444 	pci_read_config_word(pdev, GCFGC, &tmp);
445 
446 	cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
447 
448 	if (cdclk_sel >= ARRAY_SIZE(div_3200))
449 		goto fail;
450 
451 	switch (cdclk_config->vco) {
452 	case 3200000:
453 		div_table = div_3200;
454 		break;
455 	case 4000000:
456 		div_table = div_4000;
457 		break;
458 	case 5333333:
459 		div_table = div_5333;
460 		break;
461 	default:
462 		goto fail;
463 	}
464 
465 	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
466 						div_table[cdclk_sel]);
467 	return;
468 
469 fail:
470 	drm_err(display->drm,
471 		"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
472 		cdclk_config->vco, tmp);
473 	cdclk_config->cdclk = 200000;
474 }
475 
476 static void gm45_get_cdclk(struct intel_display *display,
477 			   struct intel_cdclk_config *cdclk_config)
478 {
479 	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
480 	unsigned int cdclk_sel;
481 	u16 tmp = 0;
482 
483 	cdclk_config->vco = intel_hpll_vco(display);
484 
485 	pci_read_config_word(pdev, GCFGC, &tmp);
486 
487 	cdclk_sel = (tmp >> 12) & 0x1;
488 
489 	switch (cdclk_config->vco) {
490 	case 2666667:
491 	case 4000000:
492 	case 5333333:
493 		cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
494 		break;
495 	case 3200000:
496 		cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
497 		break;
498 	default:
499 		drm_err(display->drm,
500 			"Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
501 			cdclk_config->vco, tmp);
502 		cdclk_config->cdclk = 222222;
503 		break;
504 	}
505 }
506 
507 static void hsw_get_cdclk(struct intel_display *display,
508 			  struct intel_cdclk_config *cdclk_config)
509 {
510 	u32 lcpll = intel_de_read(display, LCPLL_CTL);
511 	u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
512 
513 	if (lcpll & LCPLL_CD_SOURCE_FCLK)
514 		cdclk_config->cdclk = 800000;
515 	else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
516 		cdclk_config->cdclk = 450000;
517 	else if (freq == LCPLL_CLK_FREQ_450)
518 		cdclk_config->cdclk = 450000;
519 	else if (display->platform.haswell_ult)
520 		cdclk_config->cdclk = 337500;
521 	else
522 		cdclk_config->cdclk = 540000;
523 }
524 
525 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)
526 {
527 	struct drm_i915_private *dev_priv = to_i915(display->drm);
528 	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
529 		333333 : 320000;
530 
531 	/*
532 	 * We seem to get an unstable or solid color picture at 200MHz.
533 	 * Not sure what's wrong. For now use 200MHz only when all pipes
534 	 * are off.
535 	 */
536 	if (display->platform.valleyview && min_cdclk > freq_320)
537 		return 400000;
538 	else if (min_cdclk > 266667)
539 		return freq_320;
540 	else if (min_cdclk > 0)
541 		return 266667;
542 	else
543 		return 200000;
544 }
545 
546 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)
547 {
548 	struct drm_i915_private *dev_priv = to_i915(display->drm);
549 
550 	if (display->platform.valleyview) {
551 		if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
552 			return 2;
553 		else if (cdclk >= 266667)
554 			return 1;
555 		else
556 			return 0;
557 	} else {
558 		/*
559 		 * Specs are full of misinformation, but testing on actual
560 		 * hardware has shown that we just need to write the desired
561 		 * CCK divider into the Punit register.
562 		 */
563 		return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
564 	}
565 }
566 
567 static void vlv_get_cdclk(struct intel_display *display,
568 			  struct intel_cdclk_config *cdclk_config)
569 {
570 	struct drm_i915_private *dev_priv = to_i915(display->drm);
571 	u32 val;
572 
573 	vlv_iosf_sb_get(dev_priv,
574 			BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
575 
576 	cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
577 	cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
578 						CCK_DISPLAY_CLOCK_CONTROL,
579 						cdclk_config->vco);
580 
581 	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
582 
583 	vlv_iosf_sb_put(dev_priv,
584 			BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
585 
586 	if (display->platform.valleyview)
587 		cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
588 			DSPFREQGUAR_SHIFT;
589 	else
590 		cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
591 			DSPFREQGUAR_SHIFT_CHV;
592 }
593 
594 static void vlv_program_pfi_credits(struct intel_display *display)
595 {
596 	struct drm_i915_private *dev_priv = to_i915(display->drm);
597 	unsigned int credits, default_credits;
598 
599 	if (display->platform.cherryview)
600 		default_credits = PFI_CREDIT(12);
601 	else
602 		default_credits = PFI_CREDIT(8);
603 
604 	if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
605 		/* CHV suggested value is 31 or 63 */
606 		if (display->platform.cherryview)
607 			credits = PFI_CREDIT_63;
608 		else
609 			credits = PFI_CREDIT(15);
610 	} else {
611 		credits = default_credits;
612 	}
613 
614 	/*
615 	 * WA - write default credits before re-programming
616 	 * FIXME: should we also set the resend bit here?
617 	 */
618 	intel_de_write(display, GCI_CONTROL,
619 		       VGA_FAST_MODE_DISABLE | default_credits);
620 
621 	intel_de_write(display, GCI_CONTROL,
622 		       VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
623 
624 	/*
625 	 * FIXME is this guaranteed to clear
626 	 * immediately or should we poll for it?
627 	 */
628 	drm_WARN_ON(display->drm,
629 		    intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
630 }
631 
632 static void vlv_set_cdclk(struct intel_display *display,
633 			  const struct intel_cdclk_config *cdclk_config,
634 			  enum pipe pipe)
635 {
636 	struct drm_i915_private *dev_priv = to_i915(display->drm);
637 	int cdclk = cdclk_config->cdclk;
638 	u32 val, cmd = cdclk_config->voltage_level;
639 	intel_wakeref_t wakeref;
640 
641 	switch (cdclk) {
642 	case 400000:
643 	case 333333:
644 	case 320000:
645 	case 266667:
646 	case 200000:
647 		break;
648 	default:
649 		MISSING_CASE(cdclk);
650 		return;
651 	}
652 
653 	/* There are cases where we can end up here with power domains
654 	 * off and a CDCLK frequency other than the minimum, like when
655 	 * issuing a modeset without actually changing any display after
656 	 * a system suspend.  So grab the display core domain, which covers
657 	 * the HW blocks needed for the following programming.
658 	 */
659 	wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
660 
661 	vlv_iosf_sb_get(dev_priv,
662 			BIT(VLV_IOSF_SB_CCK) |
663 			BIT(VLV_IOSF_SB_BUNIT) |
664 			BIT(VLV_IOSF_SB_PUNIT));
665 
666 	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
667 	val &= ~DSPFREQGUAR_MASK;
668 	val |= (cmd << DSPFREQGUAR_SHIFT);
669 	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
670 	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
671 		      DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
672 		     50)) {
673 		drm_err(display->drm,
674 			"timed out waiting for CDclk change\n");
675 	}
676 
677 	if (cdclk == 400000) {
678 		u32 divider;
679 
680 		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
681 					    cdclk) - 1;
682 
683 		/* adjust cdclk divider */
684 		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
685 		val &= ~CCK_FREQUENCY_VALUES;
686 		val |= divider;
687 		vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
688 
689 		if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
690 			      CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
691 			     50))
692 			drm_err(display->drm,
693 				"timed out waiting for CDclk change\n");
694 	}
695 
696 	/* adjust self-refresh exit latency value */
697 	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
698 	val &= ~0x7f;
699 
700 	/*
701 	 * For high bandwidth configs, we set a higher latency in the bunit
702 	 * so that the core display fetch happens in time to avoid underruns.
703 	 */
704 	if (cdclk == 400000)
705 		val |= 4500 / 250; /* 4.5 usec */
706 	else
707 		val |= 3000 / 250; /* 3.0 usec */
708 	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
709 
710 	vlv_iosf_sb_put(dev_priv,
711 			BIT(VLV_IOSF_SB_CCK) |
712 			BIT(VLV_IOSF_SB_BUNIT) |
713 			BIT(VLV_IOSF_SB_PUNIT));
714 
715 	intel_update_cdclk(display);
716 
717 	vlv_program_pfi_credits(display);
718 
719 	intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
720 }
721 
722 static void chv_set_cdclk(struct intel_display *display,
723 			  const struct intel_cdclk_config *cdclk_config,
724 			  enum pipe pipe)
725 {
726 	struct drm_i915_private *dev_priv = to_i915(display->drm);
727 	int cdclk = cdclk_config->cdclk;
728 	u32 val, cmd = cdclk_config->voltage_level;
729 	intel_wakeref_t wakeref;
730 
731 	switch (cdclk) {
732 	case 333333:
733 	case 320000:
734 	case 266667:
735 	case 200000:
736 		break;
737 	default:
738 		MISSING_CASE(cdclk);
739 		return;
740 	}
741 
742 	/* There are cases where we can end up here with power domains
743 	 * off and a CDCLK frequency other than the minimum, like when
744 	 * issuing a modeset without actually changing any display after
745 	 * a system suspend.  So grab the display core domain, which covers
746 	 * the HW blocks needed for the following programming.
747 	 */
748 	wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE);
749 
750 	vlv_punit_get(dev_priv);
751 	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
752 	val &= ~DSPFREQGUAR_MASK_CHV;
753 	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
754 	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
755 	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
756 		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
757 		     50)) {
758 		drm_err(display->drm,
759 			"timed out waiting for CDclk change\n");
760 	}
761 
762 	vlv_punit_put(dev_priv);
763 
764 	intel_update_cdclk(display);
765 
766 	vlv_program_pfi_credits(display);
767 
768 	intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
769 }
770 
771 static int bdw_calc_cdclk(int min_cdclk)
772 {
773 	if (min_cdclk > 540000)
774 		return 675000;
775 	else if (min_cdclk > 450000)
776 		return 540000;
777 	else if (min_cdclk > 337500)
778 		return 450000;
779 	else
780 		return 337500;
781 }
782 
783 static u8 bdw_calc_voltage_level(int cdclk)
784 {
785 	switch (cdclk) {
786 	default:
787 	case 337500:
788 		return 2;
789 	case 450000:
790 		return 0;
791 	case 540000:
792 		return 1;
793 	case 675000:
794 		return 3;
795 	}
796 }
797 
798 static void bdw_get_cdclk(struct intel_display *display,
799 			  struct intel_cdclk_config *cdclk_config)
800 {
801 	u32 lcpll = intel_de_read(display, LCPLL_CTL);
802 	u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
803 
804 	if (lcpll & LCPLL_CD_SOURCE_FCLK)
805 		cdclk_config->cdclk = 800000;
806 	else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
807 		cdclk_config->cdclk = 450000;
808 	else if (freq == LCPLL_CLK_FREQ_450)
809 		cdclk_config->cdclk = 450000;
810 	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
811 		cdclk_config->cdclk = 540000;
812 	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
813 		cdclk_config->cdclk = 337500;
814 	else
815 		cdclk_config->cdclk = 675000;
816 
817 	/*
818 	 * Can't read this out :( Let's assume it's
819 	 * at least what the CDCLK frequency requires.
820 	 */
821 	cdclk_config->voltage_level =
822 		bdw_calc_voltage_level(cdclk_config->cdclk);
823 }
824 
825 static u32 bdw_cdclk_freq_sel(int cdclk)
826 {
827 	switch (cdclk) {
828 	default:
829 		MISSING_CASE(cdclk);
830 		fallthrough;
831 	case 337500:
832 		return LCPLL_CLK_FREQ_337_5_BDW;
833 	case 450000:
834 		return LCPLL_CLK_FREQ_450;
835 	case 540000:
836 		return LCPLL_CLK_FREQ_54O_BDW;
837 	case 675000:
838 		return LCPLL_CLK_FREQ_675_BDW;
839 	}
840 }
841 
842 static void bdw_set_cdclk(struct intel_display *display,
843 			  const struct intel_cdclk_config *cdclk_config,
844 			  enum pipe pipe)
845 {
846 	struct drm_i915_private *dev_priv = to_i915(display->drm);
847 	int cdclk = cdclk_config->cdclk;
848 	int ret;
849 
850 	if (drm_WARN(display->drm,
851 		     (intel_de_read(display, LCPLL_CTL) &
852 		      (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
853 		       LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
854 		       LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
855 		       LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
856 		     "trying to change cdclk frequency with cdclk not enabled\n"))
857 		return;
858 
859 	ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
860 	if (ret) {
861 		drm_err(display->drm,
862 			"failed to inform pcode about cdclk change\n");
863 		return;
864 	}
865 
866 	intel_de_rmw(display, LCPLL_CTL,
867 		     0, LCPLL_CD_SOURCE_FCLK);
868 
869 	/*
870 	 * According to the spec, it should be enough to poll for this 1 us.
871 	 * However, extensive testing shows that this can take longer.
872 	 */
873 	if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
874 			LCPLL_CD_SOURCE_FCLK_DONE, 100))
875 		drm_err(display->drm, "Switching to FCLK failed\n");
876 
877 	intel_de_rmw(display, LCPLL_CTL,
878 		     LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
879 
880 	intel_de_rmw(display, LCPLL_CTL,
881 		     LCPLL_CD_SOURCE_FCLK, 0);
882 
883 	if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
884 			 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
885 		drm_err(display->drm, "Switching back to LCPLL failed\n");
886 
887 	snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
888 			cdclk_config->voltage_level);
889 
890 	intel_de_write(display, CDCLK_FREQ,
891 		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
892 
893 	intel_update_cdclk(display);
894 }
895 
896 static int skl_calc_cdclk(int min_cdclk, int vco)
897 {
898 	if (vco == 8640000) {
899 		if (min_cdclk > 540000)
900 			return 617143;
901 		else if (min_cdclk > 432000)
902 			return 540000;
903 		else if (min_cdclk > 308571)
904 			return 432000;
905 		else
906 			return 308571;
907 	} else {
908 		if (min_cdclk > 540000)
909 			return 675000;
910 		else if (min_cdclk > 450000)
911 			return 540000;
912 		else if (min_cdclk > 337500)
913 			return 450000;
914 		else
915 			return 337500;
916 	}
917 }
918 
919 static u8 skl_calc_voltage_level(int cdclk)
920 {
921 	if (cdclk > 540000)
922 		return 3;
923 	else if (cdclk > 450000)
924 		return 2;
925 	else if (cdclk > 337500)
926 		return 1;
927 	else
928 		return 0;
929 }
930 
931 static void skl_dpll0_update(struct intel_display *display,
932 			     struct intel_cdclk_config *cdclk_config)
933 {
934 	u32 val;
935 
936 	cdclk_config->ref = 24000;
937 	cdclk_config->vco = 0;
938 
939 	val = intel_de_read(display, LCPLL1_CTL);
940 	if ((val & LCPLL_PLL_ENABLE) == 0)
941 		return;
942 
943 	if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
944 		return;
945 
946 	val = intel_de_read(display, DPLL_CTRL1);
947 
948 	if (drm_WARN_ON(display->drm,
949 			(val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
950 				DPLL_CTRL1_SSC(SKL_DPLL0) |
951 				DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
952 			DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
953 		return;
954 
955 	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
956 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
957 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
958 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
959 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
960 		cdclk_config->vco = 8100000;
961 		break;
962 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
963 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
964 		cdclk_config->vco = 8640000;
965 		break;
966 	default:
967 		MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
968 		break;
969 	}
970 }
971 
972 static void skl_get_cdclk(struct intel_display *display,
973 			  struct intel_cdclk_config *cdclk_config)
974 {
975 	u32 cdctl;
976 
977 	skl_dpll0_update(display, cdclk_config);
978 
979 	cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
980 
981 	if (cdclk_config->vco == 0)
982 		goto out;
983 
984 	cdctl = intel_de_read(display, CDCLK_CTL);
985 
986 	if (cdclk_config->vco == 8640000) {
987 		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
988 		case CDCLK_FREQ_450_432:
989 			cdclk_config->cdclk = 432000;
990 			break;
991 		case CDCLK_FREQ_337_308:
992 			cdclk_config->cdclk = 308571;
993 			break;
994 		case CDCLK_FREQ_540:
995 			cdclk_config->cdclk = 540000;
996 			break;
997 		case CDCLK_FREQ_675_617:
998 			cdclk_config->cdclk = 617143;
999 			break;
1000 		default:
1001 			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1002 			break;
1003 		}
1004 	} else {
1005 		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1006 		case CDCLK_FREQ_450_432:
1007 			cdclk_config->cdclk = 450000;
1008 			break;
1009 		case CDCLK_FREQ_337_308:
1010 			cdclk_config->cdclk = 337500;
1011 			break;
1012 		case CDCLK_FREQ_540:
1013 			cdclk_config->cdclk = 540000;
1014 			break;
1015 		case CDCLK_FREQ_675_617:
1016 			cdclk_config->cdclk = 675000;
1017 			break;
1018 		default:
1019 			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1020 			break;
1021 		}
1022 	}
1023 
1024  out:
1025 	/*
1026 	 * Can't read this out :( Let's assume it's
1027 	 * at least what the CDCLK frequency requires.
1028 	 */
1029 	cdclk_config->voltage_level =
1030 		skl_calc_voltage_level(cdclk_config->cdclk);
1031 }
1032 
1033 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
1034 static int skl_cdclk_decimal(int cdclk)
1035 {
1036 	return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
1037 }
1038 
1039 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
1040 {
1041 	bool changed = display->cdclk.skl_preferred_vco_freq != vco;
1042 
1043 	display->cdclk.skl_preferred_vco_freq = vco;
1044 
1045 	if (changed)
1046 		intel_update_max_cdclk(display);
1047 }
1048 
1049 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
1050 {
1051 	drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
1052 
1053 	/*
1054 	 * We always enable DPLL0 with the lowest link rate possible, but still
1055 	 * taking into account the VCO required to operate the eDP panel at the
1056 	 * desired frequency. The usual DP link rates operate with a VCO of
1057 	 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1058 	 * The modeset code is responsible for the selection of the exact link
1059 	 * rate later on, with the constraint of choosing a frequency that
1060 	 * works with vco.
1061 	 */
1062 	if (vco == 8640000)
1063 		return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
1064 	else
1065 		return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
1066 }
1067 
1068 static void skl_dpll0_enable(struct intel_display *display, int vco)
1069 {
1070 	intel_de_rmw(display, DPLL_CTRL1,
1071 		     DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
1072 		     DPLL_CTRL1_SSC(SKL_DPLL0) |
1073 		     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
1074 		     DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
1075 		     skl_dpll0_link_rate(display, vco));
1076 	intel_de_posting_read(display, DPLL_CTRL1);
1077 
1078 	intel_de_rmw(display, LCPLL1_CTL,
1079 		     0, LCPLL_PLL_ENABLE);
1080 
1081 	if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
1082 		drm_err(display->drm, "DPLL0 not locked\n");
1083 
1084 	display->cdclk.hw.vco = vco;
1085 
1086 	/* We'll want to keep using the current vco from now on. */
1087 	skl_set_preferred_cdclk_vco(display, vco);
1088 }
1089 
1090 static void skl_dpll0_disable(struct intel_display *display)
1091 {
1092 	intel_de_rmw(display, LCPLL1_CTL,
1093 		     LCPLL_PLL_ENABLE, 0);
1094 
1095 	if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1096 		drm_err(display->drm, "Couldn't disable DPLL0\n");
1097 
1098 	display->cdclk.hw.vco = 0;
1099 }
1100 
1101 static u32 skl_cdclk_freq_sel(struct intel_display *display,
1102 			      int cdclk, int vco)
1103 {
1104 	switch (cdclk) {
1105 	default:
1106 		drm_WARN_ON(display->drm,
1107 			    cdclk != display->cdclk.hw.bypass);
1108 		drm_WARN_ON(display->drm, vco != 0);
1109 		fallthrough;
1110 	case 308571:
1111 	case 337500:
1112 		return CDCLK_FREQ_337_308;
1113 	case 450000:
1114 	case 432000:
1115 		return CDCLK_FREQ_450_432;
1116 	case 540000:
1117 		return CDCLK_FREQ_540;
1118 	case 617143:
1119 	case 675000:
1120 		return CDCLK_FREQ_675_617;
1121 	}
1122 }
1123 
1124 static void skl_set_cdclk(struct intel_display *display,
1125 			  const struct intel_cdclk_config *cdclk_config,
1126 			  enum pipe pipe)
1127 {
1128 	struct drm_i915_private *dev_priv = to_i915(display->drm);
1129 	int cdclk = cdclk_config->cdclk;
1130 	int vco = cdclk_config->vco;
1131 	u32 freq_select, cdclk_ctl;
1132 	int ret;
1133 
1134 	/*
1135 	 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1136 	 * unsupported on SKL. In theory this should never happen since only
1137 	 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1138 	 * supported on SKL either, see the above WA. WARN whenever trying to
1139 	 * use the corresponding VCO freq as that always leads to using the
1140 	 * minimum 308MHz CDCLK.
1141 	 */
1142 	drm_WARN_ON_ONCE(display->drm,
1143 			 display->platform.skylake && vco == 8640000);
1144 
1145 	ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1146 				SKL_CDCLK_PREPARE_FOR_CHANGE,
1147 				SKL_CDCLK_READY_FOR_CHANGE,
1148 				SKL_CDCLK_READY_FOR_CHANGE, 3);
1149 	if (ret) {
1150 		drm_err(display->drm,
1151 			"Failed to inform PCU about cdclk change (%d)\n", ret);
1152 		return;
1153 	}
1154 
1155 	freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
1156 
1157 	if (display->cdclk.hw.vco != 0 &&
1158 	    display->cdclk.hw.vco != vco)
1159 		skl_dpll0_disable(display);
1160 
1161 	cdclk_ctl = intel_de_read(display, CDCLK_CTL);
1162 
1163 	if (display->cdclk.hw.vco != vco) {
1164 		/* Wa Display #1183: skl,kbl,cfl */
1165 		cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1166 		cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1167 		intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1168 	}
1169 
1170 	/* Wa Display #1183: skl,kbl,cfl */
1171 	cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1172 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1173 	intel_de_posting_read(display, CDCLK_CTL);
1174 
1175 	if (display->cdclk.hw.vco != vco)
1176 		skl_dpll0_enable(display, vco);
1177 
1178 	/* Wa Display #1183: skl,kbl,cfl */
1179 	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1180 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1181 
1182 	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1183 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1184 
1185 	/* Wa Display #1183: skl,kbl,cfl */
1186 	cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1187 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
1188 	intel_de_posting_read(display, CDCLK_CTL);
1189 
1190 	/* inform PCU of the change */
1191 	snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1192 			cdclk_config->voltage_level);
1193 
1194 	intel_update_cdclk(display);
1195 }
1196 
1197 static void skl_sanitize_cdclk(struct intel_display *display)
1198 {
1199 	u32 cdctl, expected;
1200 
1201 	/*
1202 	 * check if the pre-os initialized the display
1203 	 * There is SWF18 scratchpad register defined which is set by the
1204 	 * pre-os which can be used by the OS drivers to check the status
1205 	 */
1206 	if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1207 		goto sanitize;
1208 
1209 	intel_update_cdclk(display);
1210 	intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
1211 
1212 	/* Is PLL enabled and locked ? */
1213 	if (display->cdclk.hw.vco == 0 ||
1214 	    display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
1215 		goto sanitize;
1216 
1217 	/* DPLL okay; verify the cdclock
1218 	 *
1219 	 * Noticed in some instances that the freq selection is correct but
1220 	 * decimal part is programmed wrong from BIOS where pre-os does not
1221 	 * enable display. Verify the same as well.
1222 	 */
1223 	cdctl = intel_de_read(display, CDCLK_CTL);
1224 	expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1225 		skl_cdclk_decimal(display->cdclk.hw.cdclk);
1226 	if (cdctl == expected)
1227 		/* All well; nothing to sanitize */
1228 		return;
1229 
1230 sanitize:
1231 	drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
1232 
1233 	/* force cdclk programming */
1234 	display->cdclk.hw.cdclk = 0;
1235 	/* force full PLL disable + enable */
1236 	display->cdclk.hw.vco = ~0;
1237 }
1238 
1239 static void skl_cdclk_init_hw(struct intel_display *display)
1240 {
1241 	struct intel_cdclk_config cdclk_config;
1242 
1243 	skl_sanitize_cdclk(display);
1244 
1245 	if (display->cdclk.hw.cdclk != 0 &&
1246 	    display->cdclk.hw.vco != 0) {
1247 		/*
1248 		 * Use the current vco as our initial
1249 		 * guess as to what the preferred vco is.
1250 		 */
1251 		if (display->cdclk.skl_preferred_vco_freq == 0)
1252 			skl_set_preferred_cdclk_vco(display,
1253 						    display->cdclk.hw.vco);
1254 		return;
1255 	}
1256 
1257 	cdclk_config = display->cdclk.hw;
1258 
1259 	cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
1260 	if (cdclk_config.vco == 0)
1261 		cdclk_config.vco = 8100000;
1262 	cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1263 	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1264 
1265 	skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
1266 }
1267 
1268 static void skl_cdclk_uninit_hw(struct intel_display *display)
1269 {
1270 	struct intel_cdclk_config cdclk_config = display->cdclk.hw;
1271 
1272 	cdclk_config.cdclk = cdclk_config.bypass;
1273 	cdclk_config.vco = 0;
1274 	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1275 
1276 	skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
1277 }
1278 
1279 struct intel_cdclk_vals {
1280 	u32 cdclk;
1281 	u16 refclk;
1282 	u16 waveform;
1283 	u8 ratio;
1284 };
1285 
1286 static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1287 	{ .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1288 	{ .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1289 	{ .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1290 	{ .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1291 	{ .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1292 	{}
1293 };
1294 
1295 static const struct intel_cdclk_vals glk_cdclk_table[] = {
1296 	{ .refclk = 19200, .cdclk =  79200, .ratio = 33 },
1297 	{ .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1298 	{ .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1299 	{}
1300 };
1301 
1302 static const struct intel_cdclk_vals icl_cdclk_table[] = {
1303 	{ .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1304 	{ .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1305 	{ .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1306 	{ .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1307 	{ .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1308 	{ .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1309 
1310 	{ .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1311 	{ .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1312 	{ .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1313 	{ .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1314 	{ .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1315 	{ .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1316 
1317 	{ .refclk = 38400, .cdclk = 172800, .ratio =  9 },
1318 	{ .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1319 	{ .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1320 	{ .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1321 	{ .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1322 	{ .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1323 	{}
1324 };
1325 
1326 static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1327 	{ .refclk = 19200, .cdclk = 172800, .ratio =  36 },
1328 	{ .refclk = 19200, .cdclk = 192000, .ratio =  40 },
1329 	{ .refclk = 19200, .cdclk = 307200, .ratio =  64 },
1330 	{ .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1331 	{ .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1332 	{ .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1333 
1334 	{ .refclk = 24000, .cdclk = 180000, .ratio =  30 },
1335 	{ .refclk = 24000, .cdclk = 192000, .ratio =  32 },
1336 	{ .refclk = 24000, .cdclk = 312000, .ratio =  52 },
1337 	{ .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1338 	{ .refclk = 24000, .cdclk = 552000, .ratio =  92 },
1339 	{ .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1340 
1341 	{ .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1342 	{ .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1343 	{ .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1344 	{ .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1345 	{ .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1346 	{ .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1347 	{}
1348 };
1349 
1350 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1351 	{ .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1352 	{ .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1353 	{ .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1354 
1355 	{ .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1356 	{ .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1357 	{ .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1358 
1359 	{ .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1360 	{ .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1361 	{ .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1362 	{}
1363 };
1364 
1365 static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1366 	{ .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1367 	{ .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1368 	{ .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1369 	{ .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1370 	{ .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1371 
1372 	{ .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1373 	{ .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1374 	{ .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1375 	{ .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1376 	{ .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1377 
1378 	{ .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1379 	{ .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1380 	{ .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1381 	{ .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1382 	{ .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1383 	{}
1384 };
1385 
1386 static const struct intel_cdclk_vals rplu_cdclk_table[] = {
1387 	{ .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1388 	{ .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1389 	{ .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1390 	{ .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1391 	{ .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1392 	{ .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1393 
1394 	{ .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1395 	{ .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1396 	{ .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1397 	{ .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1398 	{ .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1399 	{ .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1400 
1401 	{ .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1402 	{ .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1403 	{ .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1404 	{ .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1405 	{ .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1406 	{ .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1407 	{}
1408 };
1409 
1410 static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1411 	{ .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1412 	{ .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1413 	{ .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1414 	{ .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1415 	{ .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1416 	{ .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1417 	{ .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1418 	{ .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1419 	{ .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1420 	{ .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1421 	{ .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1422 	{ .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1423 	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1424 	{}
1425 };
1426 
1427 static const struct intel_cdclk_vals mtl_cdclk_table[] = {
1428 	{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1429 	{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1430 	{ .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1431 	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1432 	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1433 	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1434 	{}
1435 };
1436 
1437 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = {
1438 	{ .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1439 	{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1440 	{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1441 	{ .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1442 	{ .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1443 	{ .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1444 	{ .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1445 	{ .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1446 	{ .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1447 	{ .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1448 	{ .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1449 	{ .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1450 	{ .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1451 	{ .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1452 	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1453 	{ .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1454 	{ .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1455 	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1456 	{ .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1457 	{ .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1458 	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1459 	{}
1460 };
1461 
1462 /*
1463  * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
1464  */
1465 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = {
1466 	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1467 	{}
1468 };
1469 
1470 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
1471 	{ .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1472 	{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1473 	{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1474 	{ .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1475 	{ .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1476 	{ .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1477 	{ .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1478 	{ .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1479 	{ .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1480 	{ .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },
1481 	{ .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
1482 	{ .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
1483 	{ .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
1484 	{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1485 	{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1486 	{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1487 	{ .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1488 	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1489 	{ .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1490 	{ .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1491 	{ .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1492 	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1493 	{ .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1494 	{ .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1495 	{ .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1496 	{ .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1497 	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1498 	{ .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1499 	{ .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1500 	{}
1501 };
1502 
1503 static const int cdclk_squash_len = 16;
1504 
1505 static int cdclk_squash_divider(u16 waveform)
1506 {
1507 	return hweight16(waveform ?: 0xffff);
1508 }
1509 
1510 static int cdclk_divider(int cdclk, int vco, u16 waveform)
1511 {
1512 	/* 2 * cd2x divider */
1513 	return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1514 				 cdclk * cdclk_squash_len);
1515 }
1516 
1517 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)
1518 {
1519 	const struct intel_cdclk_vals *table = display->cdclk.table;
1520 	int i;
1521 
1522 	for (i = 0; table[i].refclk; i++)
1523 		if (table[i].refclk == display->cdclk.hw.ref &&
1524 		    table[i].cdclk >= min_cdclk)
1525 			return table[i].cdclk;
1526 
1527 	drm_WARN(display->drm, 1,
1528 		 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1529 		 min_cdclk, display->cdclk.hw.ref);
1530 	return 0;
1531 }
1532 
1533 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)
1534 {
1535 	const struct intel_cdclk_vals *table = display->cdclk.table;
1536 	int i;
1537 
1538 	if (cdclk == display->cdclk.hw.bypass)
1539 		return 0;
1540 
1541 	for (i = 0; table[i].refclk; i++)
1542 		if (table[i].refclk == display->cdclk.hw.ref &&
1543 		    table[i].cdclk == cdclk)
1544 			return display->cdclk.hw.ref * table[i].ratio;
1545 
1546 	drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1547 		 cdclk, display->cdclk.hw.ref);
1548 	return 0;
1549 }
1550 
1551 static u8 bxt_calc_voltage_level(int cdclk)
1552 {
1553 	return DIV_ROUND_UP(cdclk, 25000);
1554 }
1555 
1556 static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
1557 			     const int voltage_level_max_cdclk[])
1558 {
1559 	int voltage_level;
1560 
1561 	for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
1562 		if (cdclk <= voltage_level_max_cdclk[voltage_level])
1563 			return voltage_level;
1564 	}
1565 
1566 	MISSING_CASE(cdclk);
1567 	return num_voltage_levels - 1;
1568 }
1569 
1570 static u8 icl_calc_voltage_level(int cdclk)
1571 {
1572 	static const int icl_voltage_level_max_cdclk[] = {
1573 		[0] = 312000,
1574 		[1] = 556800,
1575 		[2] = 652800,
1576 	};
1577 
1578 	return calc_voltage_level(cdclk,
1579 				  ARRAY_SIZE(icl_voltage_level_max_cdclk),
1580 				  icl_voltage_level_max_cdclk);
1581 }
1582 
1583 static u8 ehl_calc_voltage_level(int cdclk)
1584 {
1585 	static const int ehl_voltage_level_max_cdclk[] = {
1586 		[0] = 180000,
1587 		[1] = 312000,
1588 		[2] = 326400,
1589 		/*
1590 		 * Bspec lists the limit as 556.8 MHz, but some JSL
1591 		 * development boards (at least) boot with 652.8 MHz
1592 		 */
1593 		[3] = 652800,
1594 	};
1595 
1596 	return calc_voltage_level(cdclk,
1597 				  ARRAY_SIZE(ehl_voltage_level_max_cdclk),
1598 				  ehl_voltage_level_max_cdclk);
1599 }
1600 
1601 static u8 tgl_calc_voltage_level(int cdclk)
1602 {
1603 	static const int tgl_voltage_level_max_cdclk[] = {
1604 		[0] = 312000,
1605 		[1] = 326400,
1606 		[2] = 556800,
1607 		[3] = 652800,
1608 	};
1609 
1610 	return calc_voltage_level(cdclk,
1611 				  ARRAY_SIZE(tgl_voltage_level_max_cdclk),
1612 				  tgl_voltage_level_max_cdclk);
1613 }
1614 
1615 static u8 rplu_calc_voltage_level(int cdclk)
1616 {
1617 	static const int rplu_voltage_level_max_cdclk[] = {
1618 		[0] = 312000,
1619 		[1] = 480000,
1620 		[2] = 556800,
1621 		[3] = 652800,
1622 	};
1623 
1624 	return calc_voltage_level(cdclk,
1625 				  ARRAY_SIZE(rplu_voltage_level_max_cdclk),
1626 				  rplu_voltage_level_max_cdclk);
1627 }
1628 
1629 static u8 xe3lpd_calc_voltage_level(int cdclk)
1630 {
1631 	/*
1632 	 * Starting with xe3lpd power controller does not need the voltage
1633 	 * index when doing the modeset update. This function is best left
1634 	 * defined but returning 0 to the mask.
1635 	 */
1636 	return 0;
1637 }
1638 
1639 static void icl_readout_refclk(struct intel_display *display,
1640 			       struct intel_cdclk_config *cdclk_config)
1641 {
1642 	u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1643 
1644 	switch (dssm) {
1645 	default:
1646 		MISSING_CASE(dssm);
1647 		fallthrough;
1648 	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1649 		cdclk_config->ref = 24000;
1650 		break;
1651 	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1652 		cdclk_config->ref = 19200;
1653 		break;
1654 	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1655 		cdclk_config->ref = 38400;
1656 		break;
1657 	}
1658 }
1659 
1660 static void bxt_de_pll_readout(struct intel_display *display,
1661 			       struct intel_cdclk_config *cdclk_config)
1662 {
1663 	u32 val, ratio;
1664 
1665 	if (display->platform.dg2)
1666 		cdclk_config->ref = 38400;
1667 	else if (DISPLAY_VER(display) >= 11)
1668 		icl_readout_refclk(display, cdclk_config);
1669 	else
1670 		cdclk_config->ref = 19200;
1671 
1672 	val = intel_de_read(display, BXT_DE_PLL_ENABLE);
1673 	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1674 	    (val & BXT_DE_PLL_LOCK) == 0) {
1675 		/*
1676 		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1677 		 * setting it to zero is a way to signal that.
1678 		 */
1679 		cdclk_config->vco = 0;
1680 		return;
1681 	}
1682 
1683 	/*
1684 	 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1685 	 * gen9lp had it in a separate PLL control register.
1686 	 */
1687 	if (DISPLAY_VER(display) >= 11)
1688 		ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1689 	else
1690 		ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1691 
1692 	cdclk_config->vco = ratio * cdclk_config->ref;
1693 }
1694 
1695 static void bxt_get_cdclk(struct intel_display *display,
1696 			  struct intel_cdclk_config *cdclk_config)
1697 {
1698 	u32 squash_ctl = 0;
1699 	u32 divider;
1700 	int div;
1701 
1702 	bxt_de_pll_readout(display, cdclk_config);
1703 
1704 	if (DISPLAY_VER(display) >= 12)
1705 		cdclk_config->bypass = cdclk_config->ref / 2;
1706 	else if (DISPLAY_VER(display) >= 11)
1707 		cdclk_config->bypass = 50000;
1708 	else
1709 		cdclk_config->bypass = cdclk_config->ref;
1710 
1711 	if (cdclk_config->vco == 0) {
1712 		cdclk_config->cdclk = cdclk_config->bypass;
1713 		goto out;
1714 	}
1715 
1716 	divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1717 
1718 	switch (divider) {
1719 	case BXT_CDCLK_CD2X_DIV_SEL_1:
1720 		div = 2;
1721 		break;
1722 	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1723 		div = 3;
1724 		break;
1725 	case BXT_CDCLK_CD2X_DIV_SEL_2:
1726 		div = 4;
1727 		break;
1728 	case BXT_CDCLK_CD2X_DIV_SEL_4:
1729 		div = 8;
1730 		break;
1731 	default:
1732 		MISSING_CASE(divider);
1733 		return;
1734 	}
1735 
1736 	if (HAS_CDCLK_SQUASH(display))
1737 		squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
1738 
1739 	if (squash_ctl & CDCLK_SQUASH_ENABLE) {
1740 		u16 waveform;
1741 		int size;
1742 
1743 		size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;
1744 		waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1745 
1746 		cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1747 							cdclk_config->vco, size * div);
1748 	} else {
1749 		cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1750 	}
1751 
1752  out:
1753 	if (DISPLAY_VER(display) >= 20)
1754 		cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
1755 	/*
1756 	 * Can't read this out :( Let's assume it's
1757 	 * at least what the CDCLK frequency requires.
1758 	 */
1759 	cdclk_config->voltage_level =
1760 		intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk);
1761 }
1762 
1763 static void bxt_de_pll_disable(struct intel_display *display)
1764 {
1765 	intel_de_write(display, BXT_DE_PLL_ENABLE, 0);
1766 
1767 	/* Timeout 200us */
1768 	if (intel_de_wait_for_clear(display,
1769 				    BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1770 		drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
1771 
1772 	display->cdclk.hw.vco = 0;
1773 }
1774 
1775 static void bxt_de_pll_enable(struct intel_display *display, int vco)
1776 {
1777 	int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1778 
1779 	intel_de_rmw(display, BXT_DE_PLL_CTL,
1780 		     BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1781 
1782 	intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1783 
1784 	/* Timeout 200us */
1785 	if (intel_de_wait_for_set(display,
1786 				  BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1787 		drm_err(display->drm, "timeout waiting for DE PLL lock\n");
1788 
1789 	display->cdclk.hw.vco = vco;
1790 }
1791 
1792 static void icl_cdclk_pll_disable(struct intel_display *display)
1793 {
1794 	intel_de_rmw(display, BXT_DE_PLL_ENABLE,
1795 		     BXT_DE_PLL_PLL_ENABLE, 0);
1796 
1797 	/* Timeout 200us */
1798 	if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1799 		drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
1800 
1801 	display->cdclk.hw.vco = 0;
1802 }
1803 
1804 static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
1805 {
1806 	int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1807 	u32 val;
1808 
1809 	val = ICL_CDCLK_PLL_RATIO(ratio);
1810 	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1811 
1812 	val |= BXT_DE_PLL_PLL_ENABLE;
1813 	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1814 
1815 	/* Timeout 200us */
1816 	if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1817 		drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
1818 
1819 	display->cdclk.hw.vco = vco;
1820 }
1821 
1822 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
1823 {
1824 	int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1825 	u32 val;
1826 
1827 	/* Write PLL ratio without disabling */
1828 	val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1829 	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1830 
1831 	/* Submit freq change request */
1832 	val |= BXT_DE_PLL_FREQ_REQ;
1833 	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1834 
1835 	/* Timeout 200us */
1836 	if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE,
1837 				  BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
1838 		drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
1839 
1840 	val &= ~BXT_DE_PLL_FREQ_REQ;
1841 	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1842 
1843 	display->cdclk.hw.vco = vco;
1844 }
1845 
1846 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
1847 {
1848 	if (DISPLAY_VER(display) >= 12) {
1849 		if (pipe == INVALID_PIPE)
1850 			return TGL_CDCLK_CD2X_PIPE_NONE;
1851 		else
1852 			return TGL_CDCLK_CD2X_PIPE(pipe);
1853 	} else if (DISPLAY_VER(display) >= 11) {
1854 		if (pipe == INVALID_PIPE)
1855 			return ICL_CDCLK_CD2X_PIPE_NONE;
1856 		else
1857 			return ICL_CDCLK_CD2X_PIPE(pipe);
1858 	} else {
1859 		if (pipe == INVALID_PIPE)
1860 			return BXT_CDCLK_CD2X_PIPE_NONE;
1861 		else
1862 			return BXT_CDCLK_CD2X_PIPE(pipe);
1863 	}
1864 }
1865 
1866 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,
1867 				  int cdclk, int vco, u16 waveform)
1868 {
1869 	/* cdclk = vco / 2 / div{1,1.5,2,4} */
1870 	switch (cdclk_divider(cdclk, vco, waveform)) {
1871 	default:
1872 		drm_WARN_ON(display->drm,
1873 			    cdclk != display->cdclk.hw.bypass);
1874 		drm_WARN_ON(display->drm, vco != 0);
1875 		fallthrough;
1876 	case 2:
1877 		return BXT_CDCLK_CD2X_DIV_SEL_1;
1878 	case 3:
1879 		return BXT_CDCLK_CD2X_DIV_SEL_1_5;
1880 	case 4:
1881 		return BXT_CDCLK_CD2X_DIV_SEL_2;
1882 	case 8:
1883 		return BXT_CDCLK_CD2X_DIV_SEL_4;
1884 	}
1885 }
1886 
1887 static u16 cdclk_squash_waveform(struct intel_display *display,
1888 				 int cdclk)
1889 {
1890 	const struct intel_cdclk_vals *table = display->cdclk.table;
1891 	int i;
1892 
1893 	if (cdclk == display->cdclk.hw.bypass)
1894 		return 0;
1895 
1896 	for (i = 0; table[i].refclk; i++)
1897 		if (table[i].refclk == display->cdclk.hw.ref &&
1898 		    table[i].cdclk == cdclk)
1899 			return table[i].waveform;
1900 
1901 	drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1902 		 cdclk, display->cdclk.hw.ref);
1903 
1904 	return 0xffff;
1905 }
1906 
1907 static void icl_cdclk_pll_update(struct intel_display *display, int vco)
1908 {
1909 	if (display->cdclk.hw.vco != 0 &&
1910 	    display->cdclk.hw.vco != vco)
1911 		icl_cdclk_pll_disable(display);
1912 
1913 	if (display->cdclk.hw.vco != vco)
1914 		icl_cdclk_pll_enable(display, vco);
1915 }
1916 
1917 static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
1918 {
1919 	if (display->cdclk.hw.vco != 0 &&
1920 	    display->cdclk.hw.vco != vco)
1921 		bxt_de_pll_disable(display);
1922 
1923 	if (display->cdclk.hw.vco != vco)
1924 		bxt_de_pll_enable(display, vco);
1925 }
1926 
1927 static void dg2_cdclk_squash_program(struct intel_display *display,
1928 				     u16 waveform)
1929 {
1930 	u32 squash_ctl = 0;
1931 
1932 	if (waveform)
1933 		squash_ctl = CDCLK_SQUASH_ENABLE |
1934 			     CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
1935 
1936 	intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl);
1937 }
1938 
1939 static bool cdclk_pll_is_unknown(unsigned int vco)
1940 {
1941 	/*
1942 	 * Ensure driver does not take the crawl path for the
1943 	 * case when the vco is set to ~0 in the
1944 	 * sanitize path.
1945 	 */
1946 	return vco == ~0;
1947 }
1948 
1949 static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
1950 {
1951 	return DISPLAY_VER(display) >= 20;
1952 }
1953 
1954 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)
1955 {
1956 	if (mdclk_source_is_cdclk_pll(display))
1957 		return MDCLK_SOURCE_SEL_CDCLK_PLL;
1958 
1959 	return MDCLK_SOURCE_SEL_CD2XCLK;
1960 }
1961 
1962 int intel_mdclk_cdclk_ratio(struct intel_display *display,
1963 			    const struct intel_cdclk_config *cdclk_config)
1964 {
1965 	if (mdclk_source_is_cdclk_pll(display))
1966 		return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
1967 
1968 	/* Otherwise, source for MDCLK is CD2XCLK. */
1969 	return 2;
1970 }
1971 
1972 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
1973 					     const struct intel_cdclk_config *cdclk_config)
1974 {
1975 	struct drm_i915_private *i915 = to_i915(display->drm);
1976 
1977 	intel_dbuf_mdclk_cdclk_ratio_update(i915,
1978 					    intel_mdclk_cdclk_ratio(display, cdclk_config),
1979 					    cdclk_config->joined_mbus);
1980 }
1981 
1982 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
1983 						    const struct intel_cdclk_config *old_cdclk_config,
1984 						    const struct intel_cdclk_config *new_cdclk_config,
1985 						    struct intel_cdclk_config *mid_cdclk_config)
1986 {
1987 	u16 old_waveform, new_waveform, mid_waveform;
1988 	int old_div, new_div, mid_div;
1989 
1990 	/* Return if PLL is in an unknown state, force a complete disable and re-enable. */
1991 	if (cdclk_pll_is_unknown(old_cdclk_config->vco))
1992 		return false;
1993 
1994 	/* Return if both Squash and Crawl are not present */
1995 	if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
1996 		return false;
1997 
1998 	old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk);
1999 	new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk);
2000 
2001 	/* Return if Squash only or Crawl only is the desired action */
2002 	if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
2003 	    old_cdclk_config->vco == new_cdclk_config->vco ||
2004 	    old_waveform == new_waveform)
2005 		return false;
2006 
2007 	old_div = cdclk_divider(old_cdclk_config->cdclk,
2008 				old_cdclk_config->vco, old_waveform);
2009 	new_div = cdclk_divider(new_cdclk_config->cdclk,
2010 				new_cdclk_config->vco, new_waveform);
2011 
2012 	/*
2013 	 * Should not happen currently. We might need more midpoint
2014 	 * transitions if we need to also change the cd2x divider.
2015 	 */
2016 	if (drm_WARN_ON(display->drm, old_div != new_div))
2017 		return false;
2018 
2019 	*mid_cdclk_config = *new_cdclk_config;
2020 
2021 	/*
2022 	 * Populate the mid_cdclk_config accordingly.
2023 	 * - If moving to a higher cdclk, the desired action is squashing.
2024 	 * The mid cdclk config should have the new (squash) waveform.
2025 	 * - If moving to a lower cdclk, the desired action is crawling.
2026 	 * The mid cdclk config should have the new vco.
2027 	 */
2028 
2029 	if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
2030 		mid_cdclk_config->vco = old_cdclk_config->vco;
2031 		mid_div = old_div;
2032 		mid_waveform = new_waveform;
2033 	} else {
2034 		mid_cdclk_config->vco = new_cdclk_config->vco;
2035 		mid_div = new_div;
2036 		mid_waveform = old_waveform;
2037 	}
2038 
2039 	mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
2040 						    mid_cdclk_config->vco,
2041 						    cdclk_squash_len * mid_div);
2042 
2043 	/* make sure the mid clock came out sane */
2044 
2045 	drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
2046 		    min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
2047 	drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
2048 		    display->cdclk.max_cdclk_freq);
2049 	drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
2050 		    mid_waveform);
2051 
2052 	return true;
2053 }
2054 
2055 static bool pll_enable_wa_needed(struct intel_display *display)
2056 {
2057 	return (DISPLAY_VERx100(display) == 2000 ||
2058 		DISPLAY_VERx100(display) == 1400 ||
2059 		display->platform.dg2) &&
2060 		display->cdclk.hw.vco > 0;
2061 }
2062 
2063 static u32 bxt_cdclk_ctl(struct intel_display *display,
2064 			 const struct intel_cdclk_config *cdclk_config,
2065 			 enum pipe pipe)
2066 {
2067 	int cdclk = cdclk_config->cdclk;
2068 	int vco = cdclk_config->vco;
2069 	u16 waveform;
2070 	u32 val;
2071 
2072 	waveform = cdclk_squash_waveform(display, cdclk);
2073 
2074 	val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
2075 		bxt_cdclk_cd2x_pipe(display, pipe);
2076 
2077 	/*
2078 	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
2079 	 * enable otherwise.
2080 	 */
2081 	if ((display->platform.geminilake || display->platform.broxton) &&
2082 	    cdclk >= 500000)
2083 		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
2084 
2085 	if (DISPLAY_VER(display) >= 20)
2086 		val |= xe2lpd_mdclk_source_sel(display);
2087 	else
2088 		val |= skl_cdclk_decimal(cdclk);
2089 
2090 	return val;
2091 }
2092 
2093 static void _bxt_set_cdclk(struct intel_display *display,
2094 			   const struct intel_cdclk_config *cdclk_config,
2095 			   enum pipe pipe)
2096 {
2097 	int cdclk = cdclk_config->cdclk;
2098 	int vco = cdclk_config->vco;
2099 
2100 	if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
2101 	    !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {
2102 		if (display->cdclk.hw.vco != vco)
2103 			adlp_cdclk_pll_crawl(display, vco);
2104 	} else if (DISPLAY_VER(display) >= 11) {
2105 		/* wa_15010685871: dg2, mtl */
2106 		if (pll_enable_wa_needed(display))
2107 			dg2_cdclk_squash_program(display, 0);
2108 
2109 		icl_cdclk_pll_update(display, vco);
2110 	} else {
2111 		bxt_cdclk_pll_update(display, vco);
2112 	}
2113 
2114 	if (HAS_CDCLK_SQUASH(display)) {
2115 		u16 waveform = cdclk_squash_waveform(display, cdclk);
2116 
2117 		dg2_cdclk_squash_program(display, waveform);
2118 	}
2119 
2120 	intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe));
2121 
2122 	if (pipe != INVALID_PIPE)
2123 		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
2124 }
2125 
2126 static void bxt_set_cdclk(struct intel_display *display,
2127 			  const struct intel_cdclk_config *cdclk_config,
2128 			  enum pipe pipe)
2129 {
2130 	struct drm_i915_private *dev_priv = to_i915(display->drm);
2131 	struct intel_cdclk_config mid_cdclk_config;
2132 	int cdclk = cdclk_config->cdclk;
2133 	int ret = 0;
2134 
2135 	/*
2136 	 * Inform power controller of upcoming frequency change.
2137 	 * Display versions 14 and beyond do not follow the PUnit
2138 	 * mailbox communication, skip
2139 	 * this step.
2140 	 */
2141 	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
2142 		; /* NOOP */
2143 	else if (DISPLAY_VER(display) >= 11)
2144 		ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2145 					SKL_CDCLK_PREPARE_FOR_CHANGE,
2146 					SKL_CDCLK_READY_FOR_CHANGE,
2147 					SKL_CDCLK_READY_FOR_CHANGE, 3);
2148 	else
2149 		/*
2150 		 * BSpec requires us to wait up to 150usec, but that leads to
2151 		 * timeouts; the 2ms used here is based on experiment.
2152 		 */
2153 		ret = snb_pcode_write_timeout(&dev_priv->uncore,
2154 					      HSW_PCODE_DE_WRITE_FREQ_REQ,
2155 					      0x80000000, 150, 2);
2156 
2157 	if (ret) {
2158 		drm_err(display->drm,
2159 			"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
2160 			ret, cdclk);
2161 		return;
2162 	}
2163 
2164 	if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
2165 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2166 
2167 	if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw,
2168 						    cdclk_config, &mid_cdclk_config)) {
2169 		_bxt_set_cdclk(display, &mid_cdclk_config, pipe);
2170 		_bxt_set_cdclk(display, cdclk_config, pipe);
2171 	} else {
2172 		_bxt_set_cdclk(display, cdclk_config, pipe);
2173 	}
2174 
2175 	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
2176 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2177 
2178 	if (DISPLAY_VER(display) >= 14)
2179 		/*
2180 		 * NOOP - No Pcode communication needed for
2181 		 * Display versions 14 and beyond
2182 		 */;
2183 	else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
2184 		ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2185 				      cdclk_config->voltage_level);
2186 	if (DISPLAY_VER(display) < 11) {
2187 		/*
2188 		 * The timeout isn't specified, the 2ms used here is based on
2189 		 * experiment.
2190 		 * FIXME: Waiting for the request completion could be delayed
2191 		 * until the next PCODE request based on BSpec.
2192 		 */
2193 		ret = snb_pcode_write_timeout(&dev_priv->uncore,
2194 					      HSW_PCODE_DE_WRITE_FREQ_REQ,
2195 					      cdclk_config->voltage_level,
2196 					      150, 2);
2197 	}
2198 	if (ret) {
2199 		drm_err(display->drm,
2200 			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
2201 			ret, cdclk);
2202 		return;
2203 	}
2204 
2205 	intel_update_cdclk(display);
2206 
2207 	if (DISPLAY_VER(display) >= 11)
2208 		/*
2209 		 * Can't read out the voltage level :(
2210 		 * Let's just assume everything is as expected.
2211 		 */
2212 		display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
2213 }
2214 
2215 static void bxt_sanitize_cdclk(struct intel_display *display)
2216 {
2217 	u32 cdctl, expected;
2218 	int cdclk, vco;
2219 
2220 	intel_update_cdclk(display);
2221 	intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
2222 
2223 	if (display->cdclk.hw.vco == 0 ||
2224 	    display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
2225 		goto sanitize;
2226 
2227 	/* Make sure this is a legal cdclk value for the platform */
2228 	cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk);
2229 	if (cdclk != display->cdclk.hw.cdclk)
2230 		goto sanitize;
2231 
2232 	/* Make sure the VCO is correct for the cdclk */
2233 	vco = bxt_calc_cdclk_pll_vco(display, cdclk);
2234 	if (vco != display->cdclk.hw.vco)
2235 		goto sanitize;
2236 
2237 	/*
2238 	 * Some BIOS versions leave an incorrect decimal frequency value and
2239 	 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
2240 	 * so sanitize this register.
2241 	 */
2242 	cdctl = intel_de_read(display, CDCLK_CTL);
2243 	expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE);
2244 
2245 	/*
2246 	 * Let's ignore the pipe field, since BIOS could have configured the
2247 	 * dividers both syncing to an active pipe, or asynchronously
2248 	 * (PIPE_NONE).
2249 	 */
2250 	cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
2251 	expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
2252 
2253 	if (cdctl == expected)
2254 		/* All well; nothing to sanitize */
2255 		return;
2256 
2257 sanitize:
2258 	drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
2259 
2260 	/* force cdclk programming */
2261 	display->cdclk.hw.cdclk = 0;
2262 
2263 	/* force full PLL disable + enable */
2264 	display->cdclk.hw.vco = ~0;
2265 }
2266 
2267 static void bxt_cdclk_init_hw(struct intel_display *display)
2268 {
2269 	struct intel_cdclk_config cdclk_config;
2270 
2271 	bxt_sanitize_cdclk(display);
2272 
2273 	if (display->cdclk.hw.cdclk != 0 &&
2274 	    display->cdclk.hw.vco != 0)
2275 		return;
2276 
2277 	cdclk_config = display->cdclk.hw;
2278 
2279 	/*
2280 	 * FIXME:
2281 	 * - The initial CDCLK needs to be read from VBT.
2282 	 *   Need to make this change after VBT has changes for BXT.
2283 	 */
2284 	cdclk_config.cdclk = bxt_calc_cdclk(display, 0);
2285 	cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);
2286 	cdclk_config.voltage_level =
2287 		intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
2288 
2289 	bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
2290 }
2291 
2292 static void bxt_cdclk_uninit_hw(struct intel_display *display)
2293 {
2294 	struct intel_cdclk_config cdclk_config = display->cdclk.hw;
2295 
2296 	cdclk_config.cdclk = cdclk_config.bypass;
2297 	cdclk_config.vco = 0;
2298 	cdclk_config.voltage_level =
2299 		intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
2300 
2301 	bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
2302 }
2303 
2304 /**
2305  * intel_cdclk_init_hw - Initialize CDCLK hardware
2306  * @display: display instance
2307  *
2308  * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2309  * sanitizing the state of the hardware if needed. This is generally done only
2310  * during the display core initialization sequence, after which the DMC will
2311  * take care of turning CDCLK off/on as needed.
2312  */
2313 void intel_cdclk_init_hw(struct intel_display *display)
2314 {
2315 	if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2316 		bxt_cdclk_init_hw(display);
2317 	else if (DISPLAY_VER(display) == 9)
2318 		skl_cdclk_init_hw(display);
2319 }
2320 
2321 /**
2322  * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2323  * @display: display instance
2324  *
2325  * Uninitialize CDCLK. This is done only during the display core
2326  * uninitialization sequence.
2327  */
2328 void intel_cdclk_uninit_hw(struct intel_display *display)
2329 {
2330 	if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2331 		bxt_cdclk_uninit_hw(display);
2332 	else if (DISPLAY_VER(display) == 9)
2333 		skl_cdclk_uninit_hw(display);
2334 }
2335 
2336 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
2337 					     const struct intel_cdclk_config *a,
2338 					     const struct intel_cdclk_config *b)
2339 {
2340 	u16 old_waveform;
2341 	u16 new_waveform;
2342 
2343 	drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
2344 
2345 	if (a->vco == 0 || b->vco == 0)
2346 		return false;
2347 
2348 	if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
2349 		return false;
2350 
2351 	old_waveform = cdclk_squash_waveform(display, a->cdclk);
2352 	new_waveform = cdclk_squash_waveform(display, b->cdclk);
2353 
2354 	return a->vco != b->vco &&
2355 	       old_waveform != new_waveform;
2356 }
2357 
2358 static bool intel_cdclk_can_crawl(struct intel_display *display,
2359 				  const struct intel_cdclk_config *a,
2360 				  const struct intel_cdclk_config *b)
2361 {
2362 	int a_div, b_div;
2363 
2364 	if (!HAS_CDCLK_CRAWL(display))
2365 		return false;
2366 
2367 	/*
2368 	 * The vco and cd2x divider will change independently
2369 	 * from each, so we disallow cd2x change when crawling.
2370 	 */
2371 	a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2372 	b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2373 
2374 	return a->vco != 0 && b->vco != 0 &&
2375 		a->vco != b->vco &&
2376 		a_div == b_div &&
2377 		a->ref == b->ref;
2378 }
2379 
2380 static bool intel_cdclk_can_squash(struct intel_display *display,
2381 				   const struct intel_cdclk_config *a,
2382 				   const struct intel_cdclk_config *b)
2383 {
2384 	/*
2385 	 * FIXME should store a bit more state in intel_cdclk_config
2386 	 * to differentiate squasher vs. cd2x divider properly. For
2387 	 * the moment all platforms with squasher use a fixed cd2x
2388 	 * divider.
2389 	 */
2390 	if (!HAS_CDCLK_SQUASH(display))
2391 		return false;
2392 
2393 	return a->cdclk != b->cdclk &&
2394 		a->vco != 0 &&
2395 		a->vco == b->vco &&
2396 		a->ref == b->ref;
2397 }
2398 
2399 /**
2400  * intel_cdclk_clock_changed - Check whether the clock changed
2401  * @a: first CDCLK configuration
2402  * @b: second CDCLK configuration
2403  *
2404  * Returns:
2405  * True if CDCLK changed in a way that requires re-programming and
2406  * False otherwise.
2407  */
2408 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
2409 			       const struct intel_cdclk_config *b)
2410 {
2411 	return a->cdclk != b->cdclk ||
2412 		a->vco != b->vco ||
2413 		a->ref != b->ref;
2414 }
2415 
2416 /**
2417  * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2418  *                               configurations requires only a cd2x divider update
2419  * @display: display instance
2420  * @a: first CDCLK configuration
2421  * @b: second CDCLK configuration
2422  *
2423  * Returns:
2424  * True if changing between the two CDCLK configurations
2425  * can be done with just a cd2x divider update, false if not.
2426  */
2427 static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
2428 					const struct intel_cdclk_config *a,
2429 					const struct intel_cdclk_config *b)
2430 {
2431 	/* Older hw doesn't have the capability */
2432 	if (DISPLAY_VER(display) < 10 && !display->platform.broxton)
2433 		return false;
2434 
2435 	/*
2436 	 * FIXME should store a bit more state in intel_cdclk_config
2437 	 * to differentiate squasher vs. cd2x divider properly. For
2438 	 * the moment all platforms with squasher use a fixed cd2x
2439 	 * divider.
2440 	 */
2441 	if (HAS_CDCLK_SQUASH(display))
2442 		return false;
2443 
2444 	return a->cdclk != b->cdclk &&
2445 		a->vco != 0 &&
2446 		a->vco == b->vco &&
2447 		a->ref == b->ref;
2448 }
2449 
2450 /**
2451  * intel_cdclk_changed - Determine if two CDCLK configurations are different
2452  * @a: first CDCLK configuration
2453  * @b: second CDCLK configuration
2454  *
2455  * Returns:
2456  * True if the CDCLK configurations don't match, false if they do.
2457  */
2458 static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
2459 				const struct intel_cdclk_config *b)
2460 {
2461 	return intel_cdclk_clock_changed(a, b) ||
2462 		a->voltage_level != b->voltage_level;
2463 }
2464 
2465 void intel_cdclk_dump_config(struct intel_display *display,
2466 			     const struct intel_cdclk_config *cdclk_config,
2467 			     const char *context)
2468 {
2469 	drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2470 		    context, cdclk_config->cdclk, cdclk_config->vco,
2471 		    cdclk_config->ref, cdclk_config->bypass,
2472 		    cdclk_config->voltage_level);
2473 }
2474 
2475 static void intel_pcode_notify(struct intel_display *display,
2476 			       u8 voltage_level,
2477 			       u8 active_pipe_count,
2478 			       u16 cdclk,
2479 			       bool cdclk_update_valid,
2480 			       bool pipe_count_update_valid)
2481 {
2482 	struct drm_i915_private *i915 = to_i915(display->drm);
2483 	int ret;
2484 	u32 update_mask = 0;
2485 
2486 	if (!display->platform.dg2)
2487 		return;
2488 
2489 	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2490 
2491 	if (cdclk_update_valid)
2492 		update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID;
2493 
2494 	if (pipe_count_update_valid)
2495 		update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2496 
2497 	ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL,
2498 				SKL_CDCLK_PREPARE_FOR_CHANGE |
2499 				update_mask,
2500 				SKL_CDCLK_READY_FOR_CHANGE,
2501 				SKL_CDCLK_READY_FOR_CHANGE, 3);
2502 	if (ret)
2503 		drm_err(display->drm,
2504 			"Failed to inform PCU about display config (err %d)\n",
2505 			ret);
2506 }
2507 
2508 static void intel_set_cdclk(struct intel_display *display,
2509 			    const struct intel_cdclk_config *cdclk_config,
2510 			    enum pipe pipe, const char *context)
2511 {
2512 	struct intel_encoder *encoder;
2513 
2514 	if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config))
2515 		return;
2516 
2517 	if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
2518 		return;
2519 
2520 	intel_cdclk_dump_config(display, cdclk_config, context);
2521 
2522 	for_each_intel_encoder_with_psr(display->drm, encoder) {
2523 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2524 
2525 		intel_psr_pause(intel_dp);
2526 	}
2527 
2528 	intel_audio_cdclk_change_pre(display);
2529 
2530 	/*
2531 	 * Lock aux/gmbus while we change cdclk in case those
2532 	 * functions use cdclk. Not all platforms/ports do,
2533 	 * but we'll lock them all for simplicity.
2534 	 */
2535 	mutex_lock(&display->gmbus.mutex);
2536 	for_each_intel_dp(display->drm, encoder) {
2537 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2538 
2539 		mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2540 				     &display->gmbus.mutex);
2541 	}
2542 
2543 	intel_cdclk_set_cdclk(display, cdclk_config, pipe);
2544 
2545 	for_each_intel_dp(display->drm, encoder) {
2546 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2547 
2548 		mutex_unlock(&intel_dp->aux.hw_mutex);
2549 	}
2550 	mutex_unlock(&display->gmbus.mutex);
2551 
2552 	for_each_intel_encoder_with_psr(display->drm, encoder) {
2553 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2554 
2555 		intel_psr_resume(intel_dp);
2556 	}
2557 
2558 	intel_audio_cdclk_change_post(display);
2559 
2560 	if (drm_WARN(display->drm,
2561 		     intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
2562 		     "cdclk state doesn't match!\n")) {
2563 		intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]");
2564 		intel_cdclk_dump_config(display, cdclk_config, "[sw state]");
2565 	}
2566 }
2567 
2568 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
2569 {
2570 	struct intel_display *display = to_intel_display(state);
2571 	const struct intel_cdclk_state *old_cdclk_state =
2572 		intel_atomic_get_old_cdclk_state(state);
2573 	const struct intel_cdclk_state *new_cdclk_state =
2574 		intel_atomic_get_new_cdclk_state(state);
2575 	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2576 	bool change_cdclk, update_pipe_count;
2577 
2578 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
2579 				 &new_cdclk_state->actual) &&
2580 				 new_cdclk_state->active_pipes ==
2581 				 old_cdclk_state->active_pipes)
2582 		return;
2583 
2584 	/* According to "Sequence Before Frequency Change", voltage level set to 0x3 */
2585 	voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX;
2586 
2587 	change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2588 	update_pipe_count = hweight8(new_cdclk_state->active_pipes) >
2589 			    hweight8(old_cdclk_state->active_pipes);
2590 
2591 	/*
2592 	 * According to "Sequence Before Frequency Change",
2593 	 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK,
2594 	 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
2595 	 * which basically means we choose the maximum of old and new CDCLK, if we know both
2596 	 */
2597 	if (change_cdclk)
2598 		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2599 
2600 	/*
2601 	 * According to "Sequence For Pipe Count Change",
2602 	 * if pipe count is increasing, set bits 25:16 to upcoming pipe count
2603 	 * (power well is enabled)
2604 	 * no action if it is decreasing, before the change
2605 	 */
2606 	if (update_pipe_count)
2607 		num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2608 
2609 	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
2610 			   change_cdclk, update_pipe_count);
2611 }
2612 
2613 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
2614 {
2615 	struct intel_display *display = to_intel_display(state);
2616 	const struct intel_cdclk_state *new_cdclk_state =
2617 		intel_atomic_get_new_cdclk_state(state);
2618 	const struct intel_cdclk_state *old_cdclk_state =
2619 		intel_atomic_get_old_cdclk_state(state);
2620 	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2621 	bool update_cdclk, update_pipe_count;
2622 
2623 	/* According to "Sequence After Frequency Change", set voltage to used level */
2624 	voltage_level = new_cdclk_state->actual.voltage_level;
2625 
2626 	update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2627 	update_pipe_count = hweight8(new_cdclk_state->active_pipes) <
2628 			    hweight8(old_cdclk_state->active_pipes);
2629 
2630 	/*
2631 	 * According to "Sequence After Frequency Change",
2632 	 * set bits 25:16 to current CDCLK
2633 	 */
2634 	if (update_cdclk)
2635 		cdclk = new_cdclk_state->actual.cdclk;
2636 
2637 	/*
2638 	 * According to "Sequence For Pipe Count Change",
2639 	 * if pipe count is decreasing, set bits 25:16 to current pipe count,
2640 	 * after the change(power well is disabled)
2641 	 * no action if it is increasing, after the change
2642 	 */
2643 	if (update_pipe_count)
2644 		num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2645 
2646 	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
2647 			   update_cdclk, update_pipe_count);
2648 }
2649 
2650 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
2651 {
2652 	const struct intel_cdclk_state *old_cdclk_state =
2653 		intel_atomic_get_old_cdclk_state(state);
2654 	const struct intel_cdclk_state *new_cdclk_state =
2655 		intel_atomic_get_new_cdclk_state(state);
2656 
2657 	return new_cdclk_state && !new_cdclk_state->disable_pipes &&
2658 		new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
2659 }
2660 
2661 /**
2662  * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2663  * @state: intel atomic state
2664  *
2665  * Program the hardware before updating the HW plane state based on the
2666  * new CDCLK state, if necessary.
2667  */
2668 void
2669 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2670 {
2671 	struct intel_display *display = to_intel_display(state);
2672 	const struct intel_cdclk_state *old_cdclk_state =
2673 		intel_atomic_get_old_cdclk_state(state);
2674 	const struct intel_cdclk_state *new_cdclk_state =
2675 		intel_atomic_get_new_cdclk_state(state);
2676 	struct intel_cdclk_config cdclk_config;
2677 	enum pipe pipe;
2678 
2679 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
2680 				 &new_cdclk_state->actual))
2681 		return;
2682 
2683 	if (display->platform.dg2)
2684 		intel_cdclk_pcode_pre_notify(state);
2685 
2686 	if (new_cdclk_state->disable_pipes) {
2687 		cdclk_config = new_cdclk_state->actual;
2688 		pipe = INVALID_PIPE;
2689 	} else {
2690 		if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
2691 			cdclk_config = new_cdclk_state->actual;
2692 			pipe = new_cdclk_state->pipe;
2693 		} else {
2694 			cdclk_config = old_cdclk_state->actual;
2695 			pipe = INVALID_PIPE;
2696 		}
2697 
2698 		cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
2699 						 old_cdclk_state->actual.voltage_level);
2700 	}
2701 
2702 	/*
2703 	 * mbus joining will be changed later by
2704 	 * intel_dbuf_mbus_{pre,post}_ddb_update()
2705 	 */
2706 	cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
2707 
2708 	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2709 
2710 	intel_set_cdclk(display, &cdclk_config, pipe,
2711 			"Pre changing CDCLK to");
2712 }
2713 
2714 /**
2715  * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2716  * @state: intel atomic state
2717  *
2718  * Program the hardware after updating the HW plane state based on the
2719  * new CDCLK state, if necessary.
2720  */
2721 void
2722 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2723 {
2724 	struct intel_display *display = to_intel_display(state);
2725 	const struct intel_cdclk_state *old_cdclk_state =
2726 		intel_atomic_get_old_cdclk_state(state);
2727 	const struct intel_cdclk_state *new_cdclk_state =
2728 		intel_atomic_get_new_cdclk_state(state);
2729 	enum pipe pipe;
2730 
2731 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
2732 				 &new_cdclk_state->actual))
2733 		return;
2734 
2735 	if (display->platform.dg2)
2736 		intel_cdclk_pcode_post_notify(state);
2737 
2738 	if (!new_cdclk_state->disable_pipes &&
2739 	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
2740 		pipe = new_cdclk_state->pipe;
2741 	else
2742 		pipe = INVALID_PIPE;
2743 
2744 	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2745 
2746 	intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
2747 			"Post changing CDCLK to");
2748 }
2749 
2750 /* pixels per CDCLK */
2751 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
2752 {
2753 	return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
2754 }
2755 
2756 /* max pixel rate as % of CDCLK (not accounting for PPC) */
2757 static int intel_cdclk_guardband(struct intel_display *display)
2758 {
2759 	if (DISPLAY_VER(display) >= 9 ||
2760 	    display->platform.broadwell || display->platform.haswell)
2761 		return 100;
2762 	else if (display->platform.cherryview)
2763 		return 95;
2764 	else
2765 		return 90;
2766 }
2767 
2768 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2769 {
2770 	struct intel_display *display = to_intel_display(crtc_state);
2771 	int ppc = intel_cdclk_ppc(display, crtc_state->double_wide);
2772 	int guardband = intel_cdclk_guardband(display);
2773 	int pixel_rate = crtc_state->pixel_rate;
2774 
2775 	return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);
2776 }
2777 
2778 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2779 {
2780 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2781 	struct intel_display *display = to_intel_display(crtc);
2782 	struct intel_plane *plane;
2783 	int min_cdclk = 0;
2784 
2785 	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
2786 		min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
2787 
2788 	return min_cdclk;
2789 }
2790 
2791 static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2792 {
2793 	int min_cdclk;
2794 
2795 	if (!crtc_state->hw.enable)
2796 		return 0;
2797 
2798 	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2799 	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
2800 	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
2801 	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));
2802 	min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state));
2803 	min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
2804 
2805 	return min_cdclk;
2806 }
2807 
2808 static int intel_compute_min_cdclk(struct intel_atomic_state *state)
2809 {
2810 	struct intel_display *display = to_intel_display(state);
2811 	struct drm_i915_private *dev_priv = to_i915(display->drm);
2812 	struct intel_cdclk_state *cdclk_state =
2813 		intel_atomic_get_new_cdclk_state(state);
2814 	const struct intel_bw_state *bw_state;
2815 	struct intel_crtc *crtc;
2816 	struct intel_crtc_state *crtc_state;
2817 	int min_cdclk, i;
2818 	enum pipe pipe;
2819 
2820 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2821 		int ret;
2822 
2823 		min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2824 		if (min_cdclk < 0)
2825 			return min_cdclk;
2826 
2827 		if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2828 			continue;
2829 
2830 		cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2831 
2832 		ret = intel_atomic_lock_global_state(&cdclk_state->base);
2833 		if (ret)
2834 			return ret;
2835 	}
2836 
2837 	bw_state = intel_atomic_get_new_bw_state(state);
2838 	if (bw_state) {
2839 		min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
2840 
2841 		if (cdclk_state->bw_min_cdclk != min_cdclk) {
2842 			int ret;
2843 
2844 			cdclk_state->bw_min_cdclk = min_cdclk;
2845 
2846 			ret = intel_atomic_lock_global_state(&cdclk_state->base);
2847 			if (ret)
2848 				return ret;
2849 		}
2850 	}
2851 
2852 	min_cdclk = max(cdclk_state->force_min_cdclk,
2853 			cdclk_state->bw_min_cdclk);
2854 	for_each_pipe(display, pipe)
2855 		min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);
2856 
2857 	/*
2858 	 * Avoid glk_force_audio_cdclk() causing excessive screen
2859 	 * blinking when multiple pipes are active by making sure
2860 	 * CDCLK frequency is always high enough for audio. With a
2861 	 * single active pipe we can always change CDCLK frequency
2862 	 * by changing the cd2x divider (see glk_cdclk_table[]) and
2863 	 * thus a full modeset won't be needed then.
2864 	 */
2865 	if (display->platform.geminilake && cdclk_state->active_pipes &&
2866 	    !is_power_of_2(cdclk_state->active_pipes))
2867 		min_cdclk = max(min_cdclk, 2 * 96000);
2868 
2869 	if (min_cdclk > display->cdclk.max_cdclk_freq) {
2870 		drm_dbg_kms(display->drm,
2871 			    "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2872 			    min_cdclk, display->cdclk.max_cdclk_freq);
2873 		return -EINVAL;
2874 	}
2875 
2876 	return min_cdclk;
2877 }
2878 
2879 /*
2880  * Account for port clock min voltage level requirements.
2881  * This only really does something on DISPLA_VER >= 11 but can be
2882  * called on earlier platforms as well.
2883  *
2884  * Note that this functions assumes that 0 is
2885  * the lowest voltage value, and higher values
2886  * correspond to increasingly higher voltages.
2887  *
2888  * Should that relationship no longer hold on
2889  * future platforms this code will need to be
2890  * adjusted.
2891  */
2892 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
2893 {
2894 	struct intel_display *display = to_intel_display(state);
2895 	struct intel_cdclk_state *cdclk_state =
2896 		intel_atomic_get_new_cdclk_state(state);
2897 	struct intel_crtc *crtc;
2898 	struct intel_crtc_state *crtc_state;
2899 	u8 min_voltage_level;
2900 	int i;
2901 	enum pipe pipe;
2902 
2903 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2904 		int ret;
2905 
2906 		if (crtc_state->hw.enable)
2907 			min_voltage_level = crtc_state->min_voltage_level;
2908 		else
2909 			min_voltage_level = 0;
2910 
2911 		if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
2912 			continue;
2913 
2914 		cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
2915 
2916 		ret = intel_atomic_lock_global_state(&cdclk_state->base);
2917 		if (ret)
2918 			return ret;
2919 	}
2920 
2921 	min_voltage_level = 0;
2922 	for_each_pipe(display, pipe)
2923 		min_voltage_level = max(min_voltage_level,
2924 					cdclk_state->min_voltage_level[pipe]);
2925 
2926 	return min_voltage_level;
2927 }
2928 
2929 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
2930 {
2931 	struct intel_display *display = to_intel_display(state);
2932 	struct intel_cdclk_state *cdclk_state =
2933 		intel_atomic_get_new_cdclk_state(state);
2934 	int min_cdclk, cdclk;
2935 
2936 	min_cdclk = intel_compute_min_cdclk(state);
2937 	if (min_cdclk < 0)
2938 		return min_cdclk;
2939 
2940 	cdclk = vlv_calc_cdclk(display, min_cdclk);
2941 
2942 	cdclk_state->logical.cdclk = cdclk;
2943 	cdclk_state->logical.voltage_level =
2944 		vlv_calc_voltage_level(display, cdclk);
2945 
2946 	if (!cdclk_state->active_pipes) {
2947 		cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk);
2948 
2949 		cdclk_state->actual.cdclk = cdclk;
2950 		cdclk_state->actual.voltage_level =
2951 			vlv_calc_voltage_level(display, cdclk);
2952 	} else {
2953 		cdclk_state->actual = cdclk_state->logical;
2954 	}
2955 
2956 	return 0;
2957 }
2958 
2959 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
2960 {
2961 	struct intel_cdclk_state *cdclk_state =
2962 		intel_atomic_get_new_cdclk_state(state);
2963 	int min_cdclk, cdclk;
2964 
2965 	min_cdclk = intel_compute_min_cdclk(state);
2966 	if (min_cdclk < 0)
2967 		return min_cdclk;
2968 
2969 	cdclk = bdw_calc_cdclk(min_cdclk);
2970 
2971 	cdclk_state->logical.cdclk = cdclk;
2972 	cdclk_state->logical.voltage_level =
2973 		bdw_calc_voltage_level(cdclk);
2974 
2975 	if (!cdclk_state->active_pipes) {
2976 		cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2977 
2978 		cdclk_state->actual.cdclk = cdclk;
2979 		cdclk_state->actual.voltage_level =
2980 			bdw_calc_voltage_level(cdclk);
2981 	} else {
2982 		cdclk_state->actual = cdclk_state->logical;
2983 	}
2984 
2985 	return 0;
2986 }
2987 
2988 static int skl_dpll0_vco(struct intel_atomic_state *state)
2989 {
2990 	struct intel_display *display = to_intel_display(state);
2991 	struct intel_cdclk_state *cdclk_state =
2992 		intel_atomic_get_new_cdclk_state(state);
2993 	struct intel_crtc *crtc;
2994 	struct intel_crtc_state *crtc_state;
2995 	int vco, i;
2996 
2997 	vco = cdclk_state->logical.vco;
2998 	if (!vco)
2999 		vco = display->cdclk.skl_preferred_vco_freq;
3000 
3001 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
3002 		if (!crtc_state->hw.enable)
3003 			continue;
3004 
3005 		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
3006 			continue;
3007 
3008 		/*
3009 		 * DPLL0 VCO may need to be adjusted to get the correct
3010 		 * clock for eDP. This will affect cdclk as well.
3011 		 */
3012 		switch (crtc_state->port_clock / 2) {
3013 		case 108000:
3014 		case 216000:
3015 			vco = 8640000;
3016 			break;
3017 		default:
3018 			vco = 8100000;
3019 			break;
3020 		}
3021 	}
3022 
3023 	return vco;
3024 }
3025 
3026 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
3027 {
3028 	struct intel_cdclk_state *cdclk_state =
3029 		intel_atomic_get_new_cdclk_state(state);
3030 	int min_cdclk, cdclk, vco;
3031 
3032 	min_cdclk = intel_compute_min_cdclk(state);
3033 	if (min_cdclk < 0)
3034 		return min_cdclk;
3035 
3036 	vco = skl_dpll0_vco(state);
3037 
3038 	cdclk = skl_calc_cdclk(min_cdclk, vco);
3039 
3040 	cdclk_state->logical.vco = vco;
3041 	cdclk_state->logical.cdclk = cdclk;
3042 	cdclk_state->logical.voltage_level =
3043 		skl_calc_voltage_level(cdclk);
3044 
3045 	if (!cdclk_state->active_pipes) {
3046 		cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
3047 
3048 		cdclk_state->actual.vco = vco;
3049 		cdclk_state->actual.cdclk = cdclk;
3050 		cdclk_state->actual.voltage_level =
3051 			skl_calc_voltage_level(cdclk);
3052 	} else {
3053 		cdclk_state->actual = cdclk_state->logical;
3054 	}
3055 
3056 	return 0;
3057 }
3058 
3059 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
3060 {
3061 	struct intel_display *display = to_intel_display(state);
3062 	struct intel_cdclk_state *cdclk_state =
3063 		intel_atomic_get_new_cdclk_state(state);
3064 	int min_cdclk, min_voltage_level, cdclk, vco;
3065 
3066 	min_cdclk = intel_compute_min_cdclk(state);
3067 	if (min_cdclk < 0)
3068 		return min_cdclk;
3069 
3070 	min_voltage_level = bxt_compute_min_voltage_level(state);
3071 	if (min_voltage_level < 0)
3072 		return min_voltage_level;
3073 
3074 	cdclk = bxt_calc_cdclk(display, min_cdclk);
3075 	vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3076 
3077 	cdclk_state->logical.vco = vco;
3078 	cdclk_state->logical.cdclk = cdclk;
3079 	cdclk_state->logical.voltage_level =
3080 		max_t(int, min_voltage_level,
3081 		      intel_cdclk_calc_voltage_level(display, cdclk));
3082 
3083 	if (!cdclk_state->active_pipes) {
3084 		cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk);
3085 		vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3086 
3087 		cdclk_state->actual.vco = vco;
3088 		cdclk_state->actual.cdclk = cdclk;
3089 		cdclk_state->actual.voltage_level =
3090 			intel_cdclk_calc_voltage_level(display, cdclk);
3091 	} else {
3092 		cdclk_state->actual = cdclk_state->logical;
3093 	}
3094 
3095 	return 0;
3096 }
3097 
3098 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
3099 {
3100 	int min_cdclk;
3101 
3102 	/*
3103 	 * We can't change the cdclk frequency, but we still want to
3104 	 * check that the required minimum frequency doesn't exceed
3105 	 * the actual cdclk frequency.
3106 	 */
3107 	min_cdclk = intel_compute_min_cdclk(state);
3108 	if (min_cdclk < 0)
3109 		return min_cdclk;
3110 
3111 	return 0;
3112 }
3113 
3114 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
3115 {
3116 	struct intel_cdclk_state *cdclk_state;
3117 
3118 	cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
3119 	if (!cdclk_state)
3120 		return NULL;
3121 
3122 	cdclk_state->pipe = INVALID_PIPE;
3123 	cdclk_state->disable_pipes = false;
3124 
3125 	return &cdclk_state->base;
3126 }
3127 
3128 static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
3129 				      struct intel_global_state *state)
3130 {
3131 	kfree(state);
3132 }
3133 
3134 static const struct intel_global_state_funcs intel_cdclk_funcs = {
3135 	.atomic_duplicate_state = intel_cdclk_duplicate_state,
3136 	.atomic_destroy_state = intel_cdclk_destroy_state,
3137 };
3138 
3139 struct intel_cdclk_state *
3140 intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
3141 {
3142 	struct intel_display *display = to_intel_display(state);
3143 	struct intel_global_state *cdclk_state;
3144 
3145 	cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj);
3146 	if (IS_ERR(cdclk_state))
3147 		return ERR_CAST(cdclk_state);
3148 
3149 	return to_intel_cdclk_state(cdclk_state);
3150 }
3151 
3152 int intel_cdclk_atomic_check(struct intel_atomic_state *state,
3153 			     bool *need_cdclk_calc)
3154 {
3155 	const struct intel_cdclk_state *old_cdclk_state;
3156 	const struct intel_cdclk_state *new_cdclk_state;
3157 	struct intel_plane_state __maybe_unused *plane_state;
3158 	struct intel_plane *plane;
3159 	int ret;
3160 	int i;
3161 
3162 	/*
3163 	 * active_planes bitmask has been updated, and potentially affected
3164 	 * planes are part of the state. We can now compute the minimum cdclk
3165 	 * for each plane.
3166 	 */
3167 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3168 		ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
3169 		if (ret)
3170 			return ret;
3171 	}
3172 
3173 	ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
3174 	if (ret)
3175 		return ret;
3176 
3177 	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3178 	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
3179 
3180 	if (new_cdclk_state &&
3181 	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
3182 		*need_cdclk_calc = true;
3183 
3184 	return 0;
3185 }
3186 
3187 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus)
3188 {
3189 	struct intel_cdclk_state *cdclk_state;
3190 
3191 	cdclk_state = intel_atomic_get_cdclk_state(state);
3192 	if (IS_ERR(cdclk_state))
3193 		return PTR_ERR(cdclk_state);
3194 
3195 	cdclk_state->actual.joined_mbus = joined_mbus;
3196 	cdclk_state->logical.joined_mbus = joined_mbus;
3197 
3198 	return intel_atomic_lock_global_state(&cdclk_state->base);
3199 }
3200 
3201 int intel_cdclk_init(struct intel_display *display)
3202 {
3203 	struct intel_cdclk_state *cdclk_state;
3204 
3205 	cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
3206 	if (!cdclk_state)
3207 		return -ENOMEM;
3208 
3209 	intel_atomic_global_obj_init(display, &display->cdclk.obj,
3210 				     &cdclk_state->base, &intel_cdclk_funcs);
3211 
3212 	return 0;
3213 }
3214 
3215 static bool intel_cdclk_need_serialize(struct intel_display *display,
3216 				       const struct intel_cdclk_state *old_cdclk_state,
3217 				       const struct intel_cdclk_state *new_cdclk_state)
3218 {
3219 	bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
3220 				      hweight8(new_cdclk_state->active_pipes);
3221 	bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
3222 						 &new_cdclk_state->actual);
3223 	/*
3224 	 * We need to poke hw for gen >= 12, because we notify PCode if
3225 	 * pipe power well count changes.
3226 	 */
3227 	return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed);
3228 }
3229 
3230 int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
3231 {
3232 	struct intel_display *display = to_intel_display(state);
3233 	const struct intel_cdclk_state *old_cdclk_state;
3234 	struct intel_cdclk_state *new_cdclk_state;
3235 	enum pipe pipe = INVALID_PIPE;
3236 	int ret;
3237 
3238 	new_cdclk_state = intel_atomic_get_cdclk_state(state);
3239 	if (IS_ERR(new_cdclk_state))
3240 		return PTR_ERR(new_cdclk_state);
3241 
3242 	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3243 
3244 	new_cdclk_state->active_pipes =
3245 		intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
3246 
3247 	ret = intel_cdclk_modeset_calc_cdclk(state);
3248 	if (ret)
3249 		return ret;
3250 
3251 	if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {
3252 		/*
3253 		 * Also serialize commits across all crtcs
3254 		 * if the actual hw needs to be poked.
3255 		 */
3256 		ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
3257 		if (ret)
3258 			return ret;
3259 	} else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
3260 		   old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
3261 		   intel_cdclk_changed(&old_cdclk_state->logical,
3262 				       &new_cdclk_state->logical)) {
3263 		ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3264 		if (ret)
3265 			return ret;
3266 	} else {
3267 		return 0;
3268 	}
3269 
3270 	if (is_power_of_2(new_cdclk_state->active_pipes) &&
3271 	    intel_cdclk_can_cd2x_update(display,
3272 					&old_cdclk_state->actual,
3273 					&new_cdclk_state->actual)) {
3274 		struct intel_crtc *crtc;
3275 		struct intel_crtc_state *crtc_state;
3276 
3277 		pipe = ilog2(new_cdclk_state->active_pipes);
3278 		crtc = intel_crtc_for_pipe(display, pipe);
3279 
3280 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
3281 		if (IS_ERR(crtc_state))
3282 			return PTR_ERR(crtc_state);
3283 
3284 		if (intel_crtc_needs_modeset(crtc_state))
3285 			pipe = INVALID_PIPE;
3286 	}
3287 
3288 	if (intel_cdclk_can_crawl_and_squash(display,
3289 					     &old_cdclk_state->actual,
3290 					     &new_cdclk_state->actual)) {
3291 		drm_dbg_kms(display->drm,
3292 			    "Can change cdclk via crawling and squashing\n");
3293 	} else if (intel_cdclk_can_squash(display,
3294 					&old_cdclk_state->actual,
3295 					&new_cdclk_state->actual)) {
3296 		drm_dbg_kms(display->drm,
3297 			    "Can change cdclk via squashing\n");
3298 	} else if (intel_cdclk_can_crawl(display,
3299 					 &old_cdclk_state->actual,
3300 					 &new_cdclk_state->actual)) {
3301 		drm_dbg_kms(display->drm,
3302 			    "Can change cdclk via crawling\n");
3303 	} else if (pipe != INVALID_PIPE) {
3304 		new_cdclk_state->pipe = pipe;
3305 
3306 		drm_dbg_kms(display->drm,
3307 			    "Can change cdclk cd2x divider with pipe %c active\n",
3308 			    pipe_name(pipe));
3309 	} else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
3310 					     &new_cdclk_state->actual)) {
3311 		/* All pipes must be switched off while we change the cdclk. */
3312 		ret = intel_modeset_all_pipes_late(state, "CDCLK change");
3313 		if (ret)
3314 			return ret;
3315 
3316 		new_cdclk_state->disable_pipes = true;
3317 
3318 		drm_dbg_kms(display->drm,
3319 			    "Modeset required for cdclk change\n");
3320 	}
3321 
3322 	if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=
3323 	    intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {
3324 		int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);
3325 
3326 		ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
3327 		if (ret)
3328 			return ret;
3329 	}
3330 
3331 	drm_dbg_kms(display->drm,
3332 		    "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3333 		    new_cdclk_state->logical.cdclk,
3334 		    new_cdclk_state->actual.cdclk);
3335 	drm_dbg_kms(display->drm,
3336 		    "New voltage level calculated to be logical %u, actual %u\n",
3337 		    new_cdclk_state->logical.voltage_level,
3338 		    new_cdclk_state->actual.voltage_level);
3339 
3340 	return 0;
3341 }
3342 
3343 void intel_cdclk_update_hw_state(struct intel_display *display)
3344 {
3345 	struct intel_cdclk_state *cdclk_state =
3346 		to_intel_cdclk_state(display->cdclk.obj.state);
3347 	struct intel_crtc *crtc;
3348 
3349 	cdclk_state->active_pipes = 0;
3350 
3351 	for_each_intel_crtc(display->drm, crtc) {
3352 		const struct intel_crtc_state *crtc_state =
3353 			to_intel_crtc_state(crtc->base.state);
3354 		enum pipe pipe = crtc->pipe;
3355 
3356 		if (crtc_state->hw.active)
3357 			cdclk_state->active_pipes |= BIT(pipe);
3358 
3359 		cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state);
3360 		cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
3361 	}
3362 }
3363 
3364 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc)
3365 {
3366 	struct intel_display *display = to_intel_display(crtc);
3367 
3368 	intel_cdclk_update_hw_state(display);
3369 }
3370 
3371 static int intel_compute_max_dotclk(struct intel_display *display)
3372 {
3373 	int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));
3374 	int guardband = intel_cdclk_guardband(display);
3375 	int max_cdclk_freq = display->cdclk.max_cdclk_freq;
3376 
3377 	return ppc * max_cdclk_freq * guardband / 100;
3378 }
3379 
3380 /**
3381  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3382  * @display: display instance
3383  *
3384  * Determine the maximum CDCLK frequency the platform supports, and also
3385  * derive the maximum dot clock frequency the maximum CDCLK frequency
3386  * allows.
3387  */
3388 void intel_update_max_cdclk(struct intel_display *display)
3389 {
3390 	if (DISPLAY_VER(display) >= 30) {
3391 		display->cdclk.max_cdclk_freq = 691200;
3392 	} else if (display->platform.jasperlake || display->platform.elkhartlake) {
3393 		if (display->cdclk.hw.ref == 24000)
3394 			display->cdclk.max_cdclk_freq = 552000;
3395 		else
3396 			display->cdclk.max_cdclk_freq = 556800;
3397 	} else if (DISPLAY_VER(display) >= 11) {
3398 		if (display->cdclk.hw.ref == 24000)
3399 			display->cdclk.max_cdclk_freq = 648000;
3400 		else
3401 			display->cdclk.max_cdclk_freq = 652800;
3402 	} else if (display->platform.geminilake) {
3403 		display->cdclk.max_cdclk_freq = 316800;
3404 	} else if (display->platform.broxton) {
3405 		display->cdclk.max_cdclk_freq = 624000;
3406 	} else if (DISPLAY_VER(display) == 9) {
3407 		u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3408 		int max_cdclk, vco;
3409 
3410 		vco = display->cdclk.skl_preferred_vco_freq;
3411 		drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
3412 
3413 		/*
3414 		 * Use the lower (vco 8640) cdclk values as a
3415 		 * first guess. skl_calc_cdclk() will correct it
3416 		 * if the preferred vco is 8100 instead.
3417 		 */
3418 		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
3419 			max_cdclk = 617143;
3420 		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
3421 			max_cdclk = 540000;
3422 		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
3423 			max_cdclk = 432000;
3424 		else
3425 			max_cdclk = 308571;
3426 
3427 		display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3428 	} else if (display->platform.broadwell)  {
3429 		/*
3430 		 * FIXME with extra cooling we can allow
3431 		 * 540 MHz for ULX and 675 Mhz for ULT.
3432 		 * How can we know if extra cooling is
3433 		 * available? PCI ID, VTB, something else?
3434 		 */
3435 		if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3436 			display->cdclk.max_cdclk_freq = 450000;
3437 		else if (display->platform.broadwell_ulx)
3438 			display->cdclk.max_cdclk_freq = 450000;
3439 		else if (display->platform.broadwell_ult)
3440 			display->cdclk.max_cdclk_freq = 540000;
3441 		else
3442 			display->cdclk.max_cdclk_freq = 675000;
3443 	} else if (display->platform.cherryview) {
3444 		display->cdclk.max_cdclk_freq = 320000;
3445 	} else if (display->platform.valleyview) {
3446 		display->cdclk.max_cdclk_freq = 400000;
3447 	} else {
3448 		/* otherwise assume cdclk is fixed */
3449 		display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
3450 	}
3451 
3452 	display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
3453 
3454 	drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
3455 		display->cdclk.max_cdclk_freq);
3456 
3457 	drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
3458 		display->cdclk.max_dotclk_freq);
3459 }
3460 
3461 /**
3462  * intel_update_cdclk - Determine the current CDCLK frequency
3463  * @display: display instance
3464  *
3465  * Determine the current CDCLK frequency.
3466  */
3467 void intel_update_cdclk(struct intel_display *display)
3468 {
3469 	intel_cdclk_get_cdclk(display, &display->cdclk.hw);
3470 
3471 	/*
3472 	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
3473 	 * Programmng [sic] note: bit[9:2] should be programmed to the number
3474 	 * of cdclk that generates 4MHz reference clock freq which is used to
3475 	 * generate GMBus clock. This will vary with the cdclk freq.
3476 	 */
3477 	if (display->platform.valleyview || display->platform.cherryview)
3478 		intel_de_write(display, GMBUSFREQ_VLV,
3479 			       DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
3480 }
3481 
3482 static int dg1_rawclk(struct intel_display *display)
3483 {
3484 	/*
3485 	 * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
3486 	 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
3487 	 */
3488 	intel_de_write(display, PCH_RAWCLK_FREQ,
3489 		       CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
3490 
3491 	return 38400;
3492 }
3493 
3494 static int cnp_rawclk(struct intel_display *display)
3495 {
3496 	struct drm_i915_private *dev_priv = to_i915(display->drm);
3497 	int divider, fraction;
3498 	u32 rawclk;
3499 
3500 	if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3501 		/* 24 MHz */
3502 		divider = 24000;
3503 		fraction = 0;
3504 	} else {
3505 		/* 19.2 MHz */
3506 		divider = 19000;
3507 		fraction = 200;
3508 	}
3509 
3510 	rawclk = CNP_RAWCLK_DIV(divider / 1000);
3511 	if (fraction) {
3512 		int numerator = 1;
3513 
3514 		rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
3515 							   fraction) - 1);
3516 		if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3517 			rawclk |= ICP_RAWCLK_NUM(numerator);
3518 	}
3519 
3520 	intel_de_write(display, PCH_RAWCLK_FREQ, rawclk);
3521 	return divider + fraction;
3522 }
3523 
3524 static int pch_rawclk(struct intel_display *display)
3525 {
3526 	return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3527 }
3528 
3529 static int vlv_hrawclk(struct intel_display *display)
3530 {
3531 	struct drm_i915_private *dev_priv = to_i915(display->drm);
3532 
3533 	/* RAWCLK_FREQ_VLV register updated from power well code */
3534 	return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
3535 				      CCK_DISPLAY_REF_CLOCK_CONTROL);
3536 }
3537 
3538 static int i9xx_hrawclk(struct intel_display *display)
3539 {
3540 	struct drm_i915_private *i915 = to_i915(display->drm);
3541 
3542 	/* hrawclock is 1/4 the FSB frequency */
3543 	return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
3544 }
3545 
3546 /**
3547  * intel_read_rawclk - Determine the current RAWCLK frequency
3548  * @display: display instance
3549  *
3550  * Determine the current RAWCLK frequency. RAWCLK is a fixed
3551  * frequency clock so this needs to done only once.
3552  */
3553 u32 intel_read_rawclk(struct intel_display *display)
3554 {
3555 	struct drm_i915_private *dev_priv = to_i915(display->drm);
3556 	u32 freq;
3557 
3558 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
3559 		/*
3560 		 * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
3561 		 * "RAWCLK_FREQ defaults to the values for 38.4 and does
3562 		 * not need to be programmed."
3563 		 */
3564 		freq = 38400;
3565 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
3566 		freq = dg1_rawclk(display);
3567 	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3568 		freq = cnp_rawclk(display);
3569 	else if (HAS_PCH_SPLIT(dev_priv))
3570 		freq = pch_rawclk(display);
3571 	else if (display->platform.valleyview || display->platform.cherryview)
3572 		freq = vlv_hrawclk(display);
3573 	else if (DISPLAY_VER(display) >= 3)
3574 		freq = i9xx_hrawclk(display);
3575 	else
3576 		/* no rawclk on other platforms, or no need to know it */
3577 		return 0;
3578 
3579 	return freq;
3580 }
3581 
3582 static int i915_cdclk_info_show(struct seq_file *m, void *unused)
3583 {
3584 	struct intel_display *display = m->private;
3585 
3586 	seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
3587 	seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
3588 	seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
3589 
3590 	return 0;
3591 }
3592 
3593 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
3594 
3595 void intel_cdclk_debugfs_register(struct intel_display *display)
3596 {
3597 	struct drm_minor *minor = display->drm->primary;
3598 
3599 	debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
3600 			    display, &i915_cdclk_info_fops);
3601 }
3602 
3603 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {
3604 	.get_cdclk = bxt_get_cdclk,
3605 	.set_cdclk = bxt_set_cdclk,
3606 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3607 	.calc_voltage_level = xe3lpd_calc_voltage_level,
3608 };
3609 
3610 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3611 	.get_cdclk = bxt_get_cdclk,
3612 	.set_cdclk = bxt_set_cdclk,
3613 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3614 	.calc_voltage_level = rplu_calc_voltage_level,
3615 };
3616 
3617 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
3618 	.get_cdclk = bxt_get_cdclk,
3619 	.set_cdclk = bxt_set_cdclk,
3620 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3621 	.calc_voltage_level = tgl_calc_voltage_level,
3622 };
3623 
3624 static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
3625 	.get_cdclk = bxt_get_cdclk,
3626 	.set_cdclk = bxt_set_cdclk,
3627 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3628 	.calc_voltage_level = ehl_calc_voltage_level,
3629 };
3630 
3631 static const struct intel_cdclk_funcs icl_cdclk_funcs = {
3632 	.get_cdclk = bxt_get_cdclk,
3633 	.set_cdclk = bxt_set_cdclk,
3634 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3635 	.calc_voltage_level = icl_calc_voltage_level,
3636 };
3637 
3638 static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
3639 	.get_cdclk = bxt_get_cdclk,
3640 	.set_cdclk = bxt_set_cdclk,
3641 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3642 	.calc_voltage_level = bxt_calc_voltage_level,
3643 };
3644 
3645 static const struct intel_cdclk_funcs skl_cdclk_funcs = {
3646 	.get_cdclk = skl_get_cdclk,
3647 	.set_cdclk = skl_set_cdclk,
3648 	.modeset_calc_cdclk = skl_modeset_calc_cdclk,
3649 };
3650 
3651 static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
3652 	.get_cdclk = bdw_get_cdclk,
3653 	.set_cdclk = bdw_set_cdclk,
3654 	.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
3655 };
3656 
3657 static const struct intel_cdclk_funcs chv_cdclk_funcs = {
3658 	.get_cdclk = vlv_get_cdclk,
3659 	.set_cdclk = chv_set_cdclk,
3660 	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3661 };
3662 
3663 static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
3664 	.get_cdclk = vlv_get_cdclk,
3665 	.set_cdclk = vlv_set_cdclk,
3666 	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3667 };
3668 
3669 static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
3670 	.get_cdclk = hsw_get_cdclk,
3671 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3672 };
3673 
3674 /* SNB, IVB, 965G, 945G */
3675 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
3676 	.get_cdclk = fixed_400mhz_get_cdclk,
3677 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3678 };
3679 
3680 static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
3681 	.get_cdclk = fixed_450mhz_get_cdclk,
3682 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3683 };
3684 
3685 static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
3686 	.get_cdclk = gm45_get_cdclk,
3687 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3688 };
3689 
3690 /* G45 uses G33 */
3691 
3692 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
3693 	.get_cdclk = i965gm_get_cdclk,
3694 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3695 };
3696 
3697 /* i965G uses fixed 400 */
3698 
3699 static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
3700 	.get_cdclk = pnv_get_cdclk,
3701 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3702 };
3703 
3704 static const struct intel_cdclk_funcs g33_cdclk_funcs = {
3705 	.get_cdclk = g33_get_cdclk,
3706 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3707 };
3708 
3709 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
3710 	.get_cdclk = i945gm_get_cdclk,
3711 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3712 };
3713 
3714 /* i945G uses fixed 400 */
3715 
3716 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
3717 	.get_cdclk = i915gm_get_cdclk,
3718 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3719 };
3720 
3721 static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
3722 	.get_cdclk = fixed_333mhz_get_cdclk,
3723 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3724 };
3725 
3726 static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
3727 	.get_cdclk = fixed_266mhz_get_cdclk,
3728 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3729 };
3730 
3731 static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
3732 	.get_cdclk = i85x_get_cdclk,
3733 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3734 };
3735 
3736 static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
3737 	.get_cdclk = fixed_200mhz_get_cdclk,
3738 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3739 };
3740 
3741 static const struct intel_cdclk_funcs i830_cdclk_funcs = {
3742 	.get_cdclk = fixed_133mhz_get_cdclk,
3743 	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3744 };
3745 
3746 /**
3747  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3748  * @display: display instance
3749  */
3750 void intel_init_cdclk_hooks(struct intel_display *display)
3751 {
3752 	if (DISPLAY_VER(display) >= 30) {
3753 		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3754 		display->cdclk.table = xe3lpd_cdclk_table;
3755 	} else if (DISPLAY_VER(display) >= 20) {
3756 		display->funcs.cdclk = &rplu_cdclk_funcs;
3757 		display->cdclk.table = xe2lpd_cdclk_table;
3758 	} else if (DISPLAY_VERx100(display) >= 1401) {
3759 		display->funcs.cdclk = &rplu_cdclk_funcs;
3760 		display->cdclk.table = xe2hpd_cdclk_table;
3761 	} else if (DISPLAY_VER(display) >= 14) {
3762 		display->funcs.cdclk = &rplu_cdclk_funcs;
3763 		display->cdclk.table = mtl_cdclk_table;
3764 	} else if (display->platform.dg2) {
3765 		display->funcs.cdclk = &tgl_cdclk_funcs;
3766 		display->cdclk.table = dg2_cdclk_table;
3767 	} else if (display->platform.alderlake_p) {
3768 		/* Wa_22011320316:adl-p[a0] */
3769 		if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
3770 			display->cdclk.table = adlp_a_step_cdclk_table;
3771 			display->funcs.cdclk = &tgl_cdclk_funcs;
3772 		} else if (display->platform.alderlake_p_raptorlake_u) {
3773 			display->cdclk.table = rplu_cdclk_table;
3774 			display->funcs.cdclk = &rplu_cdclk_funcs;
3775 		} else {
3776 			display->cdclk.table = adlp_cdclk_table;
3777 			display->funcs.cdclk = &tgl_cdclk_funcs;
3778 		}
3779 	} else if (display->platform.rocketlake) {
3780 		display->funcs.cdclk = &tgl_cdclk_funcs;
3781 		display->cdclk.table = rkl_cdclk_table;
3782 	} else if (DISPLAY_VER(display) >= 12) {
3783 		display->funcs.cdclk = &tgl_cdclk_funcs;
3784 		display->cdclk.table = icl_cdclk_table;
3785 	} else if (display->platform.jasperlake || display->platform.elkhartlake) {
3786 		display->funcs.cdclk = &ehl_cdclk_funcs;
3787 		display->cdclk.table = icl_cdclk_table;
3788 	} else if (DISPLAY_VER(display) >= 11) {
3789 		display->funcs.cdclk = &icl_cdclk_funcs;
3790 		display->cdclk.table = icl_cdclk_table;
3791 	} else if (display->platform.geminilake || display->platform.broxton) {
3792 		display->funcs.cdclk = &bxt_cdclk_funcs;
3793 		if (display->platform.geminilake)
3794 			display->cdclk.table = glk_cdclk_table;
3795 		else
3796 			display->cdclk.table = bxt_cdclk_table;
3797 	} else if (DISPLAY_VER(display) == 9) {
3798 		display->funcs.cdclk = &skl_cdclk_funcs;
3799 	} else if (display->platform.broadwell) {
3800 		display->funcs.cdclk = &bdw_cdclk_funcs;
3801 	} else if (display->platform.haswell) {
3802 		display->funcs.cdclk = &hsw_cdclk_funcs;
3803 	} else if (display->platform.cherryview) {
3804 		display->funcs.cdclk = &chv_cdclk_funcs;
3805 	} else if (display->platform.valleyview) {
3806 		display->funcs.cdclk = &vlv_cdclk_funcs;
3807 	} else if (display->platform.sandybridge || display->platform.ivybridge) {
3808 		display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3809 	} else if (display->platform.ironlake) {
3810 		display->funcs.cdclk = &ilk_cdclk_funcs;
3811 	} else if (display->platform.gm45) {
3812 		display->funcs.cdclk = &gm45_cdclk_funcs;
3813 	} else if (display->platform.g45) {
3814 		display->funcs.cdclk = &g33_cdclk_funcs;
3815 	} else if (display->platform.i965gm) {
3816 		display->funcs.cdclk = &i965gm_cdclk_funcs;
3817 	} else if (display->platform.i965g) {
3818 		display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3819 	} else if (display->platform.pineview) {
3820 		display->funcs.cdclk = &pnv_cdclk_funcs;
3821 	} else if (display->platform.g33) {
3822 		display->funcs.cdclk = &g33_cdclk_funcs;
3823 	} else if (display->platform.i945gm) {
3824 		display->funcs.cdclk = &i945gm_cdclk_funcs;
3825 	} else if (display->platform.i945g) {
3826 		display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3827 	} else if (display->platform.i915gm) {
3828 		display->funcs.cdclk = &i915gm_cdclk_funcs;
3829 	} else if (display->platform.i915g) {
3830 		display->funcs.cdclk = &i915g_cdclk_funcs;
3831 	} else if (display->platform.i865g) {
3832 		display->funcs.cdclk = &i865g_cdclk_funcs;
3833 	} else if (display->platform.i85x) {
3834 		display->funcs.cdclk = &i85x_cdclk_funcs;
3835 	} else if (display->platform.i845g) {
3836 		display->funcs.cdclk = &i845g_cdclk_funcs;
3837 	} else if (display->platform.i830) {
3838 		display->funcs.cdclk = &i830_cdclk_funcs;
3839 	}
3840 
3841 	if (drm_WARN(display->drm, !display->funcs.cdclk,
3842 		     "Unknown platform. Assuming i830\n"))
3843 		display->funcs.cdclk = &i830_cdclk_funcs;
3844 }
3845