xref: /linux/arch/x86/include/asm/microcode.h (revision d8630b67ca1edeea728dbb309b09d239e9db6bdf)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MICROCODE_H
3 #define _ASM_X86_MICROCODE_H
4 
5 #include <asm/msr.h>
6 
7 struct cpu_signature {
8 	unsigned int sig;
9 	unsigned int pf;
10 	unsigned int rev;
11 };
12 
13 struct ucode_cpu_info {
14 	struct cpu_signature	cpu_sig;
15 	void			*mc;
16 };
17 
18 #ifdef CONFIG_MICROCODE
19 void load_ucode_bsp(void);
20 void load_ucode_ap(void);
21 void microcode_bsp_resume(void);
22 bool __init microcode_loader_disabled(void);
23 #else
24 static inline void load_ucode_bsp(void)	{ }
25 static inline void load_ucode_ap(void) { }
26 static inline void microcode_bsp_resume(void) { }
27 static inline bool __init microcode_loader_disabled(void) { return false; }
28 #endif
29 
30 extern unsigned long initrd_start_early;
31 
32 #ifdef CONFIG_CPU_SUP_INTEL
33 /* Intel specific microcode defines. Public for IFS */
34 struct microcode_header_intel {
35 	unsigned int	hdrver;
36 	unsigned int	rev;
37 	unsigned int	date;
38 	unsigned int	sig;
39 	unsigned int	cksum;
40 	unsigned int	ldrver;
41 	unsigned int	pf;
42 	unsigned int	datasize;
43 	unsigned int	totalsize;
44 	unsigned int	metasize;
45 	unsigned int	min_req_ver;
46 	unsigned int	reserved;
47 };
48 
49 struct microcode_intel {
50 	struct microcode_header_intel	hdr;
51 	unsigned int			bits[];
52 };
53 
54 #define DEFAULT_UCODE_DATASIZE		(2000)
55 #define MC_HEADER_SIZE			(sizeof(struct microcode_header_intel))
56 #define MC_HEADER_TYPE_MICROCODE	1
57 #define MC_HEADER_TYPE_IFS		2
58 
59 static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr)
60 {
61 	return hdr->datasize ? : DEFAULT_UCODE_DATASIZE;
62 }
63 
64 extern u32 intel_get_platform_id(void);
65 
66 static inline u32 intel_get_microcode_revision(void)
67 {
68 	u32 rev, dummy;
69 
70 	native_wrmsrq(MSR_IA32_UCODE_REV, 0);
71 
72 	/* As documented in the SDM: Do a CPUID 1 here */
73 	native_cpuid_eax(1);
74 
75 	/* get the current revision from MSR 0x8B */
76 	native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
77 
78 	return rev;
79 }
80 #endif /* !CONFIG_CPU_SUP_INTEL */
81 
82 bool microcode_nmi_handler(void);
83 void microcode_offline_nmi_handler(void);
84 
85 #ifdef CONFIG_MICROCODE_LATE_LOADING
86 DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable);
87 static __always_inline bool microcode_nmi_handler_enabled(void)
88 {
89 	return static_branch_unlikely(&microcode_nmi_handler_enable);
90 }
91 #else
92 static __always_inline bool microcode_nmi_handler_enabled(void) { return false; }
93 #endif
94 
95 #endif /* _ASM_X86_MICROCODE_H */
96