1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 *
5 * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
6 */
7
8 #include <linux/string_helpers.h>
9
10 #include "g4x_dp.h"
11 #include "i915_drv.h"
12 #include "i915_reg.h"
13 #include "intel_audio.h"
14 #include "intel_backlight.h"
15 #include "intel_connector.h"
16 #include "intel_crtc.h"
17 #include "intel_de.h"
18 #include "intel_display_power.h"
19 #include "intel_display_types.h"
20 #include "intel_dp.h"
21 #include "intel_dp_aux.h"
22 #include "intel_dp_link_training.h"
23 #include "intel_dp_test.h"
24 #include "intel_dpio_phy.h"
25 #include "intel_encoder.h"
26 #include "intel_fifo_underrun.h"
27 #include "intel_hdmi.h"
28 #include "intel_hotplug.h"
29 #include "intel_pch_display.h"
30 #include "intel_pps.h"
31 #include "vlv_sideband.h"
32
33 static const struct dpll g4x_dpll[] = {
34 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
35 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
36 };
37
38 static const struct dpll pch_dpll[] = {
39 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
40 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
41 };
42
43 static const struct dpll vlv_dpll[] = {
44 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
45 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
46 };
47
48 static const struct dpll chv_dpll[] = {
49 /* m2 is .22 binary fixed point */
50 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
51 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
52 };
53
vlv_get_dpll(struct drm_i915_private * i915)54 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
55 {
56 return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
57 }
58
g4x_dp_set_clock(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)59 static void g4x_dp_set_clock(struct intel_encoder *encoder,
60 struct intel_crtc_state *pipe_config)
61 {
62 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
63 const struct dpll *divisor = NULL;
64 int i, count = 0;
65
66 if (IS_G4X(dev_priv)) {
67 divisor = g4x_dpll;
68 count = ARRAY_SIZE(g4x_dpll);
69 } else if (HAS_PCH_SPLIT(dev_priv)) {
70 divisor = pch_dpll;
71 count = ARRAY_SIZE(pch_dpll);
72 } else if (IS_CHERRYVIEW(dev_priv)) {
73 divisor = chv_dpll;
74 count = ARRAY_SIZE(chv_dpll);
75 } else if (IS_VALLEYVIEW(dev_priv)) {
76 divisor = vlv_dpll;
77 count = ARRAY_SIZE(vlv_dpll);
78 }
79
80 if (divisor && count) {
81 for (i = 0; i < count; i++) {
82 if (pipe_config->port_clock == divisor[i].dot) {
83 pipe_config->dpll = divisor[i];
84 pipe_config->clock_set = true;
85 break;
86 }
87 }
88 }
89 }
90
intel_dp_prepare(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)91 static void intel_dp_prepare(struct intel_encoder *encoder,
92 const struct intel_crtc_state *pipe_config)
93 {
94 struct intel_display *display = to_intel_display(encoder);
95 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
96 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
97 enum port port = encoder->port;
98 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
99 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
100
101 intel_dp_set_link_params(intel_dp,
102 pipe_config->port_clock,
103 pipe_config->lane_count);
104
105 /*
106 * There are four kinds of DP registers:
107 * IBX PCH
108 * SNB CPU
109 * IVB CPU
110 * CPT PCH
111 *
112 * IBX PCH and CPU are the same for almost everything,
113 * except that the CPU DP PLL is configured in this
114 * register
115 *
116 * CPT PCH is quite different, having many bits moved
117 * to the TRANS_DP_CTL register instead. That
118 * configuration happens (oddly) in ilk_pch_enable
119 */
120
121 /* Preserve the BIOS-computed detected bit. This is
122 * supposed to be read-only.
123 */
124 intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
125
126 /* Handle DP bits in common between all three register formats */
127 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
128 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
129
130 /* Split out the IBX/CPU vs CPT settings */
131
132 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
133 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
134 intel_dp->DP |= DP_SYNC_HS_HIGH;
135 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
136 intel_dp->DP |= DP_SYNC_VS_HIGH;
137 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
138
139 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
140 intel_dp->DP |= DP_ENHANCED_FRAMING;
141
142 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
143 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
144 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
145
146 intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),
147 TRANS_DP_ENH_FRAMING,
148 pipe_config->enhanced_framing ?
149 TRANS_DP_ENH_FRAMING : 0);
150 } else {
151 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
152 intel_dp->DP |= DP_COLOR_RANGE_16_235;
153
154 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
155 intel_dp->DP |= DP_SYNC_HS_HIGH;
156 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
157 intel_dp->DP |= DP_SYNC_VS_HIGH;
158 intel_dp->DP |= DP_LINK_TRAIN_OFF;
159
160 if (pipe_config->enhanced_framing)
161 intel_dp->DP |= DP_ENHANCED_FRAMING;
162
163 if (IS_CHERRYVIEW(dev_priv))
164 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
165 else
166 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
167 }
168 }
169
assert_dp_port(struct intel_dp * intel_dp,bool state)170 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
171 {
172 struct intel_display *display = to_intel_display(intel_dp);
173 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
174 bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;
175
176 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
177 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
178 dig_port->base.base.base.id, dig_port->base.base.name,
179 str_on_off(state), str_on_off(cur_state));
180 }
181 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
182
assert_edp_pll(struct drm_i915_private * dev_priv,bool state)183 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
184 {
185 struct intel_display *display = &dev_priv->display;
186 bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
187
188 INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
189 "eDP PLL state assertion failure (expected %s, current %s)\n",
190 str_on_off(state), str_on_off(cur_state));
191 }
192 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
193 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
194
ilk_edp_pll_on(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)195 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
196 const struct intel_crtc_state *pipe_config)
197 {
198 struct intel_display *display = to_intel_display(intel_dp);
199 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
200 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
201
202 assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
203 assert_dp_port_disabled(intel_dp);
204 assert_edp_pll_disabled(dev_priv);
205
206 drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
207 pipe_config->port_clock);
208
209 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
210
211 if (pipe_config->port_clock == 162000)
212 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
213 else
214 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
215
216 intel_de_write(display, DP_A, intel_dp->DP);
217 intel_de_posting_read(display, DP_A);
218 udelay(500);
219
220 /*
221 * [DevILK] Work around required when enabling DP PLL
222 * while a pipe is enabled going to FDI:
223 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
224 * 2. Program DP PLL enable
225 */
226 if (IS_IRONLAKE(dev_priv))
227 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
228
229 intel_dp->DP |= DP_PLL_ENABLE;
230
231 intel_de_write(display, DP_A, intel_dp->DP);
232 intel_de_posting_read(display, DP_A);
233 udelay(200);
234 }
235
ilk_edp_pll_off(struct intel_dp * intel_dp,const struct intel_crtc_state * old_crtc_state)236 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
237 const struct intel_crtc_state *old_crtc_state)
238 {
239 struct intel_display *display = to_intel_display(intel_dp);
240 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
242
243 assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
244 assert_dp_port_disabled(intel_dp);
245 assert_edp_pll_enabled(dev_priv);
246
247 drm_dbg_kms(display->drm, "disabling eDP PLL\n");
248
249 intel_dp->DP &= ~DP_PLL_ENABLE;
250
251 intel_de_write(display, DP_A, intel_dp->DP);
252 intel_de_posting_read(display, DP_A);
253 udelay(200);
254 }
255
cpt_dp_port_selected(struct drm_i915_private * dev_priv,enum port port,enum pipe * pipe)256 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
257 enum port port, enum pipe *pipe)
258 {
259 struct intel_display *display = &dev_priv->display;
260 enum pipe p;
261
262 for_each_pipe(display, p) {
263 u32 val = intel_de_read(display, TRANS_DP_CTL(p));
264
265 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
266 *pipe = p;
267 return true;
268 }
269 }
270
271 drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",
272 port_name(port));
273
274 /* must initialize pipe to something for the asserts */
275 *pipe = PIPE_A;
276
277 return false;
278 }
279
g4x_dp_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t dp_reg,enum port port,enum pipe * pipe)280 bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
281 i915_reg_t dp_reg, enum port port,
282 enum pipe *pipe)
283 {
284 struct intel_display *display = &dev_priv->display;
285 bool ret;
286 u32 val;
287
288 val = intel_de_read(display, dp_reg);
289
290 ret = val & DP_PORT_EN;
291
292 /* asserts want to know the pipe even if the port is disabled */
293 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
294 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
295 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
296 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
297 else if (IS_CHERRYVIEW(dev_priv))
298 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
299 else
300 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
301
302 return ret;
303 }
304
intel_dp_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)305 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
306 enum pipe *pipe)
307 {
308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
309 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
310 intel_wakeref_t wakeref;
311 bool ret;
312
313 wakeref = intel_display_power_get_if_enabled(dev_priv,
314 encoder->power_domain);
315 if (!wakeref)
316 return false;
317
318 ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
319 encoder->port, pipe);
320
321 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
322
323 return ret;
324 }
325
g4x_dp_get_m_n(struct intel_crtc_state * crtc_state)326 static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
327 {
328 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
329
330 if (crtc_state->has_pch_encoder) {
331 intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);
332 intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);
333 } else {
334 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
335 &crtc_state->dp_m_n);
336 intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,
337 &crtc_state->dp_m2_n2);
338 }
339 }
340
intel_dp_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)341 static void intel_dp_get_config(struct intel_encoder *encoder,
342 struct intel_crtc_state *pipe_config)
343 {
344 struct intel_display *display = to_intel_display(encoder);
345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
346 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
347 u32 tmp, flags = 0;
348 enum port port = encoder->port;
349 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
350
351 if (encoder->type == INTEL_OUTPUT_EDP)
352 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
353 else
354 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
355
356 tmp = intel_de_read(display, intel_dp->output_reg);
357
358 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
359
360 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
361 u32 trans_dp = intel_de_read(display,
362 TRANS_DP_CTL(crtc->pipe));
363
364 if (trans_dp & TRANS_DP_ENH_FRAMING)
365 pipe_config->enhanced_framing = true;
366
367 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
368 flags |= DRM_MODE_FLAG_PHSYNC;
369 else
370 flags |= DRM_MODE_FLAG_NHSYNC;
371
372 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
373 flags |= DRM_MODE_FLAG_PVSYNC;
374 else
375 flags |= DRM_MODE_FLAG_NVSYNC;
376 } else {
377 if (tmp & DP_ENHANCED_FRAMING)
378 pipe_config->enhanced_framing = true;
379
380 if (tmp & DP_SYNC_HS_HIGH)
381 flags |= DRM_MODE_FLAG_PHSYNC;
382 else
383 flags |= DRM_MODE_FLAG_NHSYNC;
384
385 if (tmp & DP_SYNC_VS_HIGH)
386 flags |= DRM_MODE_FLAG_PVSYNC;
387 else
388 flags |= DRM_MODE_FLAG_NVSYNC;
389 }
390
391 pipe_config->hw.adjusted_mode.flags |= flags;
392
393 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
394 pipe_config->limited_color_range = true;
395
396 pipe_config->lane_count =
397 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
398
399 g4x_dp_get_m_n(pipe_config);
400
401 if (port == PORT_A) {
402 if ((intel_de_read(display, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
403 pipe_config->port_clock = 162000;
404 else
405 pipe_config->port_clock = 270000;
406 }
407
408 pipe_config->hw.adjusted_mode.crtc_clock =
409 intel_dotclock_calculate(pipe_config->port_clock,
410 &pipe_config->dp_m_n);
411
412 if (intel_dp_is_edp(intel_dp))
413 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
414
415 intel_audio_codec_get_config(encoder, pipe_config);
416 }
417
418 static void
intel_dp_link_down(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state)419 intel_dp_link_down(struct intel_encoder *encoder,
420 const struct intel_crtc_state *old_crtc_state)
421 {
422 struct intel_display *display = to_intel_display(encoder);
423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
424 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
425 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
426 enum port port = encoder->port;
427
428 if (drm_WARN_ON(display->drm,
429 (intel_de_read(display, intel_dp->output_reg) &
430 DP_PORT_EN) == 0))
431 return;
432
433 drm_dbg_kms(display->drm, "\n");
434
435 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
436 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
437 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
438 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
439 } else {
440 intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
441 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
442 }
443 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
444 intel_de_posting_read(display, intel_dp->output_reg);
445
446 intel_dp->DP &= ~DP_PORT_EN;
447 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
448 intel_de_posting_read(display, intel_dp->output_reg);
449
450 /*
451 * HW workaround for IBX, we need to move the port
452 * to transcoder A after disabling it to allow the
453 * matching HDMI port to be enabled on transcoder A.
454 */
455 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
456 /*
457 * We get CPU/PCH FIFO underruns on the other pipe when
458 * doing the workaround. Sweep them under the rug.
459 */
460 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
461 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
462
463 /* always enable with pattern 1 (as per spec) */
464 intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
465 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
466 DP_LINK_TRAIN_PAT_1;
467 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
468 intel_de_posting_read(display, intel_dp->output_reg);
469
470 intel_dp->DP &= ~DP_PORT_EN;
471 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
472 intel_de_posting_read(display, intel_dp->output_reg);
473
474 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
475 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
476 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
477 }
478
479 msleep(intel_dp->pps.panel_power_down_delay);
480
481 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
482 vlv_pps_port_disable(encoder, old_crtc_state);
483 }
484
g4x_dp_audio_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)485 static void g4x_dp_audio_enable(struct intel_encoder *encoder,
486 const struct intel_crtc_state *crtc_state,
487 const struct drm_connector_state *conn_state)
488 {
489 struct intel_display *display = to_intel_display(encoder);
490 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
491
492 if (!crtc_state->has_audio)
493 return;
494
495 /* Enable audio presence detect */
496 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
497 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
498
499 intel_audio_codec_enable(encoder, crtc_state, conn_state);
500 }
501
g4x_dp_audio_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)502 static void g4x_dp_audio_disable(struct intel_encoder *encoder,
503 const struct intel_crtc_state *old_crtc_state,
504 const struct drm_connector_state *old_conn_state)
505 {
506 struct intel_display *display = to_intel_display(encoder);
507 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
508
509 if (!old_crtc_state->has_audio)
510 return;
511
512 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
513
514 /* Disable audio presence detect */
515 intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE;
516 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
517 }
518
intel_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)519 static void intel_disable_dp(struct intel_atomic_state *state,
520 struct intel_encoder *encoder,
521 const struct intel_crtc_state *old_crtc_state,
522 const struct drm_connector_state *old_conn_state)
523 {
524 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
525
526 intel_dp->link_trained = false;
527
528 /*
529 * Make sure the panel is off before trying to change the mode.
530 * But also ensure that we have vdd while we switch off the panel.
531 */
532 intel_pps_vdd_on(intel_dp);
533 intel_edp_backlight_off(old_conn_state);
534 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
535 intel_pps_off(intel_dp);
536 }
537
g4x_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)538 static void g4x_disable_dp(struct intel_atomic_state *state,
539 struct intel_encoder *encoder,
540 const struct intel_crtc_state *old_crtc_state,
541 const struct drm_connector_state *old_conn_state)
542 {
543 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
544 }
545
vlv_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)546 static void vlv_disable_dp(struct intel_atomic_state *state,
547 struct intel_encoder *encoder,
548 const struct intel_crtc_state *old_crtc_state,
549 const struct drm_connector_state *old_conn_state)
550 {
551 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
552 }
553
g4x_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)554 static void g4x_post_disable_dp(struct intel_atomic_state *state,
555 struct intel_encoder *encoder,
556 const struct intel_crtc_state *old_crtc_state,
557 const struct drm_connector_state *old_conn_state)
558 {
559 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
560 enum port port = encoder->port;
561
562 /*
563 * Bspec does not list a specific disable sequence for g4x DP.
564 * Follow the ilk+ sequence (disable pipe before the port) for
565 * g4x DP as it does not suffer from underruns like the normal
566 * g4x modeset sequence (disable pipe after the port).
567 */
568 intel_dp_link_down(encoder, old_crtc_state);
569
570 /* Only ilk+ has port A */
571 if (port == PORT_A)
572 ilk_edp_pll_off(intel_dp, old_crtc_state);
573 }
574
vlv_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)575 static void vlv_post_disable_dp(struct intel_atomic_state *state,
576 struct intel_encoder *encoder,
577 const struct intel_crtc_state *old_crtc_state,
578 const struct drm_connector_state *old_conn_state)
579 {
580 intel_dp_link_down(encoder, old_crtc_state);
581 }
582
chv_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)583 static void chv_post_disable_dp(struct intel_atomic_state *state,
584 struct intel_encoder *encoder,
585 const struct intel_crtc_state *old_crtc_state,
586 const struct drm_connector_state *old_conn_state)
587 {
588 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
589
590 intel_dp_link_down(encoder, old_crtc_state);
591
592 vlv_dpio_get(dev_priv);
593
594 /* Assert data lane reset */
595 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
596
597 vlv_dpio_put(dev_priv);
598 }
599
600 static void
cpt_set_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,u8 dp_train_pat)601 cpt_set_link_train(struct intel_dp *intel_dp,
602 const struct intel_crtc_state *crtc_state,
603 u8 dp_train_pat)
604 {
605 struct intel_display *display = to_intel_display(intel_dp);
606
607 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
608
609 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
610 case DP_TRAINING_PATTERN_DISABLE:
611 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
612 break;
613 case DP_TRAINING_PATTERN_1:
614 intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;
615 break;
616 case DP_TRAINING_PATTERN_2:
617 intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;
618 break;
619 default:
620 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
621 return;
622 }
623
624 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
625 intel_de_posting_read(display, intel_dp->output_reg);
626 }
627
628 static void
g4x_set_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,u8 dp_train_pat)629 g4x_set_link_train(struct intel_dp *intel_dp,
630 const struct intel_crtc_state *crtc_state,
631 u8 dp_train_pat)
632 {
633 struct intel_display *display = to_intel_display(intel_dp);
634
635 intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
636
637 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
638 case DP_TRAINING_PATTERN_DISABLE:
639 intel_dp->DP |= DP_LINK_TRAIN_OFF;
640 break;
641 case DP_TRAINING_PATTERN_1:
642 intel_dp->DP |= DP_LINK_TRAIN_PAT_1;
643 break;
644 case DP_TRAINING_PATTERN_2:
645 intel_dp->DP |= DP_LINK_TRAIN_PAT_2;
646 break;
647 default:
648 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
649 return;
650 }
651
652 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
653 intel_de_posting_read(display, intel_dp->output_reg);
654 }
655
intel_dp_enable_port(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)656 static void intel_dp_enable_port(struct intel_dp *intel_dp,
657 const struct intel_crtc_state *crtc_state)
658 {
659 struct intel_display *display = to_intel_display(intel_dp);
660
661 /* enable with pattern 1 (as per spec) */
662
663 intel_dp_program_link_training_pattern(intel_dp, crtc_state,
664 DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
665
666 /*
667 * Magic for VLV/CHV. We _must_ first set up the register
668 * without actually enabling the port, and then do another
669 * write to enable the port. Otherwise link training will
670 * fail when the power sequencer is freshly used for this port.
671 */
672 intel_dp->DP |= DP_PORT_EN;
673
674 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
675 intel_de_posting_read(display, intel_dp->output_reg);
676 }
677
intel_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)678 static void intel_enable_dp(struct intel_atomic_state *state,
679 struct intel_encoder *encoder,
680 const struct intel_crtc_state *pipe_config,
681 const struct drm_connector_state *conn_state)
682 {
683 struct intel_display *display = to_intel_display(state);
684 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
685 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
686 u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
687 intel_wakeref_t wakeref;
688
689 if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))
690 return;
691
692 with_intel_pps_lock(intel_dp, wakeref) {
693 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
694 vlv_pps_port_enable_unlocked(encoder, pipe_config);
695
696 intel_dp_enable_port(intel_dp, pipe_config);
697
698 intel_pps_vdd_on_unlocked(intel_dp);
699 intel_pps_on_unlocked(intel_dp);
700 intel_pps_vdd_off_unlocked(intel_dp, true);
701 }
702
703 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
704 unsigned int lane_mask = 0x0;
705
706 if (IS_CHERRYVIEW(dev_priv))
707 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
708
709 vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask);
710 }
711
712 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
713 intel_dp_configure_protocol_converter(intel_dp, pipe_config);
714 intel_dp_check_frl_training(intel_dp);
715 intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
716 intel_dp_start_link_train(state, intel_dp, pipe_config);
717 intel_dp_stop_link_train(intel_dp, pipe_config);
718 }
719
g4x_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)720 static void g4x_enable_dp(struct intel_atomic_state *state,
721 struct intel_encoder *encoder,
722 const struct intel_crtc_state *pipe_config,
723 const struct drm_connector_state *conn_state)
724 {
725 intel_enable_dp(state, encoder, pipe_config, conn_state);
726 intel_edp_backlight_on(pipe_config, conn_state);
727 }
728
vlv_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)729 static void vlv_enable_dp(struct intel_atomic_state *state,
730 struct intel_encoder *encoder,
731 const struct intel_crtc_state *pipe_config,
732 const struct drm_connector_state *conn_state)
733 {
734 intel_edp_backlight_on(pipe_config, conn_state);
735 }
736
g4x_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)737 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
738 struct intel_encoder *encoder,
739 const struct intel_crtc_state *pipe_config,
740 const struct drm_connector_state *conn_state)
741 {
742 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
743 enum port port = encoder->port;
744
745 intel_dp_prepare(encoder, pipe_config);
746
747 /* Only ilk+ has port A */
748 if (port == PORT_A)
749 ilk_edp_pll_on(intel_dp, pipe_config);
750 }
751
vlv_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)752 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
753 struct intel_encoder *encoder,
754 const struct intel_crtc_state *pipe_config,
755 const struct drm_connector_state *conn_state)
756 {
757 vlv_phy_pre_encoder_enable(encoder, pipe_config);
758
759 intel_enable_dp(state, encoder, pipe_config, conn_state);
760 }
761
vlv_dp_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)762 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
763 struct intel_encoder *encoder,
764 const struct intel_crtc_state *pipe_config,
765 const struct drm_connector_state *conn_state)
766 {
767 intel_dp_prepare(encoder, pipe_config);
768
769 vlv_phy_pre_pll_enable(encoder, pipe_config);
770 }
771
chv_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)772 static void chv_pre_enable_dp(struct intel_atomic_state *state,
773 struct intel_encoder *encoder,
774 const struct intel_crtc_state *pipe_config,
775 const struct drm_connector_state *conn_state)
776 {
777 chv_phy_pre_encoder_enable(encoder, pipe_config);
778
779 intel_enable_dp(state, encoder, pipe_config, conn_state);
780
781 /* Second common lane will stay alive on its own now */
782 chv_phy_release_cl2_override(encoder);
783 }
784
chv_dp_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)785 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
786 struct intel_encoder *encoder,
787 const struct intel_crtc_state *pipe_config,
788 const struct drm_connector_state *conn_state)
789 {
790 intel_dp_prepare(encoder, pipe_config);
791
792 chv_phy_pre_pll_enable(encoder, pipe_config);
793 }
794
chv_dp_post_pll_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)795 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
796 struct intel_encoder *encoder,
797 const struct intel_crtc_state *old_crtc_state,
798 const struct drm_connector_state *old_conn_state)
799 {
800 chv_phy_post_pll_disable(encoder, old_crtc_state);
801 }
802
intel_dp_voltage_max_2(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)803 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
804 const struct intel_crtc_state *crtc_state)
805 {
806 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
807 }
808
intel_dp_voltage_max_3(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)809 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
810 const struct intel_crtc_state *crtc_state)
811 {
812 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
813 }
814
intel_dp_preemph_max_2(struct intel_dp * intel_dp)815 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
816 {
817 return DP_TRAIN_PRE_EMPH_LEVEL_2;
818 }
819
intel_dp_preemph_max_3(struct intel_dp * intel_dp)820 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
821 {
822 return DP_TRAIN_PRE_EMPH_LEVEL_3;
823 }
824
vlv_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)825 static void vlv_set_signal_levels(struct intel_encoder *encoder,
826 const struct intel_crtc_state *crtc_state)
827 {
828 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
829 unsigned long demph_reg_value, preemph_reg_value,
830 uniqtranscale_reg_value;
831 u8 train_set = intel_dp->train_set[0];
832
833 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
834 case DP_TRAIN_PRE_EMPH_LEVEL_0:
835 preemph_reg_value = 0x0004000;
836 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
837 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
838 demph_reg_value = 0x2B405555;
839 uniqtranscale_reg_value = 0x552AB83A;
840 break;
841 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
842 demph_reg_value = 0x2B404040;
843 uniqtranscale_reg_value = 0x5548B83A;
844 break;
845 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
846 demph_reg_value = 0x2B245555;
847 uniqtranscale_reg_value = 0x5560B83A;
848 break;
849 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
850 demph_reg_value = 0x2B405555;
851 uniqtranscale_reg_value = 0x5598DA3A;
852 break;
853 default:
854 return;
855 }
856 break;
857 case DP_TRAIN_PRE_EMPH_LEVEL_1:
858 preemph_reg_value = 0x0002000;
859 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
860 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
861 demph_reg_value = 0x2B404040;
862 uniqtranscale_reg_value = 0x5552B83A;
863 break;
864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
865 demph_reg_value = 0x2B404848;
866 uniqtranscale_reg_value = 0x5580B83A;
867 break;
868 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
869 demph_reg_value = 0x2B404040;
870 uniqtranscale_reg_value = 0x55ADDA3A;
871 break;
872 default:
873 return;
874 }
875 break;
876 case DP_TRAIN_PRE_EMPH_LEVEL_2:
877 preemph_reg_value = 0x0000000;
878 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
880 demph_reg_value = 0x2B305555;
881 uniqtranscale_reg_value = 0x5570B83A;
882 break;
883 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
884 demph_reg_value = 0x2B2B4040;
885 uniqtranscale_reg_value = 0x55ADDA3A;
886 break;
887 default:
888 return;
889 }
890 break;
891 case DP_TRAIN_PRE_EMPH_LEVEL_3:
892 preemph_reg_value = 0x0006000;
893 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
894 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
895 demph_reg_value = 0x1B405555;
896 uniqtranscale_reg_value = 0x55ADDA3A;
897 break;
898 default:
899 return;
900 }
901 break;
902 default:
903 return;
904 }
905
906 vlv_set_phy_signal_level(encoder, crtc_state,
907 demph_reg_value, preemph_reg_value,
908 uniqtranscale_reg_value, 0);
909 }
910
chv_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)911 static void chv_set_signal_levels(struct intel_encoder *encoder,
912 const struct intel_crtc_state *crtc_state)
913 {
914 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
915 u32 deemph_reg_value, margin_reg_value;
916 bool uniq_trans_scale = false;
917 u8 train_set = intel_dp->train_set[0];
918
919 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
920 case DP_TRAIN_PRE_EMPH_LEVEL_0:
921 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
922 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
923 deemph_reg_value = 128;
924 margin_reg_value = 52;
925 break;
926 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
927 deemph_reg_value = 128;
928 margin_reg_value = 77;
929 break;
930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
931 deemph_reg_value = 128;
932 margin_reg_value = 102;
933 break;
934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
935 deemph_reg_value = 128;
936 margin_reg_value = 154;
937 uniq_trans_scale = true;
938 break;
939 default:
940 return;
941 }
942 break;
943 case DP_TRAIN_PRE_EMPH_LEVEL_1:
944 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
946 deemph_reg_value = 85;
947 margin_reg_value = 78;
948 break;
949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
950 deemph_reg_value = 85;
951 margin_reg_value = 116;
952 break;
953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
954 deemph_reg_value = 85;
955 margin_reg_value = 154;
956 break;
957 default:
958 return;
959 }
960 break;
961 case DP_TRAIN_PRE_EMPH_LEVEL_2:
962 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
964 deemph_reg_value = 64;
965 margin_reg_value = 104;
966 break;
967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
968 deemph_reg_value = 64;
969 margin_reg_value = 154;
970 break;
971 default:
972 return;
973 }
974 break;
975 case DP_TRAIN_PRE_EMPH_LEVEL_3:
976 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
977 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
978 deemph_reg_value = 43;
979 margin_reg_value = 154;
980 break;
981 default:
982 return;
983 }
984 break;
985 default:
986 return;
987 }
988
989 chv_set_phy_signal_level(encoder, crtc_state,
990 deemph_reg_value, margin_reg_value,
991 uniq_trans_scale);
992 }
993
g4x_signal_levels(u8 train_set)994 static u32 g4x_signal_levels(u8 train_set)
995 {
996 u32 signal_levels = 0;
997
998 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
1000 default:
1001 signal_levels |= DP_VOLTAGE_0_4;
1002 break;
1003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
1004 signal_levels |= DP_VOLTAGE_0_6;
1005 break;
1006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
1007 signal_levels |= DP_VOLTAGE_0_8;
1008 break;
1009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1010 signal_levels |= DP_VOLTAGE_1_2;
1011 break;
1012 }
1013 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1014 case DP_TRAIN_PRE_EMPH_LEVEL_0:
1015 default:
1016 signal_levels |= DP_PRE_EMPHASIS_0;
1017 break;
1018 case DP_TRAIN_PRE_EMPH_LEVEL_1:
1019 signal_levels |= DP_PRE_EMPHASIS_3_5;
1020 break;
1021 case DP_TRAIN_PRE_EMPH_LEVEL_2:
1022 signal_levels |= DP_PRE_EMPHASIS_6;
1023 break;
1024 case DP_TRAIN_PRE_EMPH_LEVEL_3:
1025 signal_levels |= DP_PRE_EMPHASIS_9_5;
1026 break;
1027 }
1028 return signal_levels;
1029 }
1030
1031 static void
g4x_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1032 g4x_set_signal_levels(struct intel_encoder *encoder,
1033 const struct intel_crtc_state *crtc_state)
1034 {
1035 struct intel_display *display = to_intel_display(encoder);
1036 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1037 u8 train_set = intel_dp->train_set[0];
1038 u32 signal_levels;
1039
1040 signal_levels = g4x_signal_levels(train_set);
1041
1042 drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1043 signal_levels);
1044
1045 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
1046 intel_dp->DP |= signal_levels;
1047
1048 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
1049 intel_de_posting_read(display, intel_dp->output_reg);
1050 }
1051
1052 /* SNB CPU eDP voltage swing and pre-emphasis control */
snb_cpu_edp_signal_levels(u8 train_set)1053 static u32 snb_cpu_edp_signal_levels(u8 train_set)
1054 {
1055 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1056 DP_TRAIN_PRE_EMPHASIS_MASK);
1057
1058 switch (signal_levels) {
1059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1061 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1063 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1066 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1069 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1070 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1072 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1073 default:
1074 MISSING_CASE(signal_levels);
1075 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1076 }
1077 }
1078
1079 static void
snb_cpu_edp_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1080 snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1081 const struct intel_crtc_state *crtc_state)
1082 {
1083 struct intel_display *display = to_intel_display(encoder);
1084 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1085 u8 train_set = intel_dp->train_set[0];
1086 u32 signal_levels;
1087
1088 signal_levels = snb_cpu_edp_signal_levels(train_set);
1089
1090 drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1091 signal_levels);
1092
1093 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1094 intel_dp->DP |= signal_levels;
1095
1096 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
1097 intel_de_posting_read(display, intel_dp->output_reg);
1098 }
1099
1100 /* IVB CPU eDP voltage swing and pre-emphasis control */
ivb_cpu_edp_signal_levels(u8 train_set)1101 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
1102 {
1103 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1104 DP_TRAIN_PRE_EMPHASIS_MASK);
1105
1106 switch (signal_levels) {
1107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1108 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1110 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1113 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1114
1115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1116 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1118 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1119
1120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1121 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1123 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1124
1125 default:
1126 MISSING_CASE(signal_levels);
1127 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1128 }
1129 }
1130
1131 static void
ivb_cpu_edp_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1132 ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1133 const struct intel_crtc_state *crtc_state)
1134 {
1135 struct intel_display *display = to_intel_display(encoder);
1136 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1137 u8 train_set = intel_dp->train_set[0];
1138 u32 signal_levels;
1139
1140 signal_levels = ivb_cpu_edp_signal_levels(train_set);
1141
1142 drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1143 signal_levels);
1144
1145 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1146 intel_dp->DP |= signal_levels;
1147
1148 intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
1149 intel_de_posting_read(display, intel_dp->output_reg);
1150 }
1151
1152 /*
1153 * If display is now connected check links status,
1154 * there has been known issues of link loss triggering
1155 * long pulse.
1156 *
1157 * Some sinks (eg. ASUS PB287Q) seem to perform some
1158 * weird HPD ping pong during modesets. So we can apparently
1159 * end up with HPD going low during a modeset, and then
1160 * going back up soon after. And once that happens we must
1161 * retrain the link to get a picture. That's in case no
1162 * userspace component reacted to intermittent HPD dip.
1163 */
1164 static enum intel_hotplug_state
intel_dp_hotplug(struct intel_encoder * encoder,struct intel_connector * connector)1165 intel_dp_hotplug(struct intel_encoder *encoder,
1166 struct intel_connector *connector)
1167 {
1168 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1169 enum intel_hotplug_state state;
1170
1171 if (intel_dp_test_phy(intel_dp))
1172 return INTEL_HOTPLUG_UNCHANGED;
1173
1174 state = intel_encoder_hotplug(encoder, connector);
1175
1176 intel_dp_check_link_state(intel_dp);
1177
1178 /*
1179 * Keeping it consistent with intel_ddi_hotplug() and
1180 * intel_hdmi_hotplug().
1181 */
1182 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
1183 state = INTEL_HOTPLUG_RETRY;
1184
1185 return state;
1186 }
1187
ibx_digital_port_connected(struct intel_encoder * encoder)1188 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
1189 {
1190 struct intel_display *display = to_intel_display(encoder);
1191 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
1192
1193 return intel_de_read(display, SDEISR) & bit;
1194 }
1195
g4x_digital_port_connected(struct intel_encoder * encoder)1196 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
1197 {
1198 struct intel_display *display = to_intel_display(encoder);
1199 u32 bit;
1200
1201 switch (encoder->hpd_pin) {
1202 case HPD_PORT_B:
1203 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
1204 break;
1205 case HPD_PORT_C:
1206 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
1207 break;
1208 case HPD_PORT_D:
1209 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
1210 break;
1211 default:
1212 MISSING_CASE(encoder->hpd_pin);
1213 return false;
1214 }
1215
1216 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;
1217 }
1218
ilk_digital_port_connected(struct intel_encoder * encoder)1219 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
1220 {
1221 struct intel_display *display = to_intel_display(encoder);
1222 u32 bit = display->hotplug.hpd[encoder->hpd_pin];
1223
1224 return intel_de_read(display, DEISR) & bit;
1225 }
1226
g4x_dp_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)1227 static int g4x_dp_compute_config(struct intel_encoder *encoder,
1228 struct intel_crtc_state *crtc_state,
1229 struct drm_connector_state *conn_state)
1230 {
1231 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1232 int ret;
1233
1234 if (HAS_PCH_SPLIT(i915) && encoder->port != PORT_A)
1235 crtc_state->has_pch_encoder = true;
1236
1237 ret = intel_dp_compute_config(encoder, crtc_state, conn_state);
1238 if (ret)
1239 return ret;
1240
1241 g4x_dp_set_clock(encoder, crtc_state);
1242
1243 return 0;
1244 }
1245
g4x_dp_suspend_complete(struct intel_encoder * encoder)1246 static void g4x_dp_suspend_complete(struct intel_encoder *encoder)
1247 {
1248 /*
1249 * TODO: Move this to intel_dp_encoder_suspend(),
1250 * once modeset locking around that is removed.
1251 */
1252 intel_encoder_link_check_flush_work(encoder);
1253 }
1254
intel_dp_encoder_destroy(struct drm_encoder * encoder)1255 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1256 {
1257 intel_dp_encoder_flush_work(encoder);
1258
1259 drm_encoder_cleanup(encoder);
1260 kfree(enc_to_dig_port(to_intel_encoder(encoder)));
1261 }
1262
intel_dp_encoder_reset(struct drm_encoder * encoder)1263 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
1264 {
1265 struct intel_display *display = to_intel_display(encoder->dev);
1266 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1267 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
1268
1269 intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
1270
1271 intel_dp->reset_link_params = true;
1272 intel_dp_invalidate_source_oui(intel_dp);
1273
1274 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1275 vlv_pps_pipe_reset(intel_dp);
1276
1277 intel_pps_encoder_reset(intel_dp);
1278 }
1279
1280 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1281 .reset = intel_dp_encoder_reset,
1282 .destroy = intel_dp_encoder_destroy,
1283 };
1284
g4x_dp_init(struct drm_i915_private * dev_priv,i915_reg_t output_reg,enum port port)1285 bool g4x_dp_init(struct drm_i915_private *dev_priv,
1286 i915_reg_t output_reg, enum port port)
1287 {
1288 struct intel_display *display = &dev_priv->display;
1289 const struct intel_bios_encoder_data *devdata;
1290 struct intel_digital_port *dig_port;
1291 struct intel_encoder *intel_encoder;
1292 struct drm_encoder *encoder;
1293 struct intel_connector *intel_connector;
1294
1295 if (!assert_port_valid(dev_priv, port))
1296 return false;
1297
1298 devdata = intel_bios_encoder_data_lookup(display, port);
1299
1300 /* FIXME bail? */
1301 if (!devdata)
1302 drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",
1303 port_name(port));
1304
1305 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
1306 if (!dig_port)
1307 return false;
1308
1309 dig_port->aux_ch = AUX_CH_NONE;
1310
1311 intel_connector = intel_connector_alloc();
1312 if (!intel_connector)
1313 goto err_connector_alloc;
1314
1315 intel_encoder = &dig_port->base;
1316 encoder = &intel_encoder->base;
1317
1318 intel_encoder->devdata = devdata;
1319
1320 mutex_init(&dig_port->hdcp_mutex);
1321
1322 if (drm_encoder_init(display->drm, &intel_encoder->base,
1323 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
1324 "DP %c", port_name(port)))
1325 goto err_encoder_init;
1326
1327 intel_encoder_link_check_init(intel_encoder, intel_dp_link_check);
1328
1329 intel_encoder->hotplug = intel_dp_hotplug;
1330 intel_encoder->compute_config = g4x_dp_compute_config;
1331 intel_encoder->get_hw_state = intel_dp_get_hw_state;
1332 intel_encoder->get_config = intel_dp_get_config;
1333 intel_encoder->sync_state = intel_dp_sync_state;
1334 intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
1335 intel_encoder->update_pipe = intel_backlight_update;
1336 intel_encoder->suspend = intel_dp_encoder_suspend;
1337 intel_encoder->suspend_complete = g4x_dp_suspend_complete;
1338 intel_encoder->shutdown = intel_dp_encoder_shutdown;
1339 if (IS_CHERRYVIEW(dev_priv)) {
1340 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
1341 intel_encoder->pre_enable = chv_pre_enable_dp;
1342 intel_encoder->enable = vlv_enable_dp;
1343 intel_encoder->disable = vlv_disable_dp;
1344 intel_encoder->post_disable = chv_post_disable_dp;
1345 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
1346 } else if (IS_VALLEYVIEW(dev_priv)) {
1347 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
1348 intel_encoder->pre_enable = vlv_pre_enable_dp;
1349 intel_encoder->enable = vlv_enable_dp;
1350 intel_encoder->disable = vlv_disable_dp;
1351 intel_encoder->post_disable = vlv_post_disable_dp;
1352 } else {
1353 intel_encoder->pre_enable = g4x_pre_enable_dp;
1354 intel_encoder->enable = g4x_enable_dp;
1355 intel_encoder->disable = g4x_disable_dp;
1356 intel_encoder->post_disable = g4x_post_disable_dp;
1357 }
1358 intel_encoder->audio_enable = g4x_dp_audio_enable;
1359 intel_encoder->audio_disable = g4x_dp_audio_disable;
1360
1361 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
1362 (HAS_PCH_CPT(dev_priv) && port != PORT_A))
1363 dig_port->dp.set_link_train = cpt_set_link_train;
1364 else
1365 dig_port->dp.set_link_train = g4x_set_link_train;
1366
1367 if (IS_CHERRYVIEW(dev_priv))
1368 intel_encoder->set_signal_levels = chv_set_signal_levels;
1369 else if (IS_VALLEYVIEW(dev_priv))
1370 intel_encoder->set_signal_levels = vlv_set_signal_levels;
1371 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
1372 intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels;
1373 else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
1374 intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels;
1375 else
1376 intel_encoder->set_signal_levels = g4x_set_signal_levels;
1377
1378 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
1379 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
1380 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
1381 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
1382 } else {
1383 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
1384 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
1385 }
1386
1387 dig_port->dp.output_reg = output_reg;
1388 dig_port->max_lanes = 4;
1389
1390 intel_encoder->type = INTEL_OUTPUT_DP;
1391 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
1392 if (IS_CHERRYVIEW(dev_priv)) {
1393 if (port == PORT_D)
1394 intel_encoder->pipe_mask = BIT(PIPE_C);
1395 else
1396 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
1397 } else {
1398 intel_encoder->pipe_mask = ~0;
1399 }
1400 intel_encoder->cloneable = 0;
1401 intel_encoder->port = port;
1402 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
1403
1404 dig_port->hpd_pulse = intel_dp_hpd_pulse;
1405
1406 if (HAS_GMCH(display)) {
1407 dig_port->connected = g4x_digital_port_connected;
1408 } else {
1409 if (port == PORT_A)
1410 dig_port->connected = ilk_digital_port_connected;
1411 else
1412 dig_port->connected = ibx_digital_port_connected;
1413 }
1414
1415 if (port != PORT_A)
1416 intel_infoframe_init(dig_port);
1417
1418 dig_port->aux_ch = intel_dp_aux_ch(intel_encoder);
1419 if (dig_port->aux_ch == AUX_CH_NONE)
1420 goto err_init_connector;
1421
1422 if (!intel_dp_init_connector(dig_port, intel_connector))
1423 goto err_init_connector;
1424
1425 return true;
1426
1427 err_init_connector:
1428 drm_encoder_cleanup(encoder);
1429 err_encoder_init:
1430 kfree(intel_connector);
1431 err_connector_alloc:
1432 kfree(dig_port);
1433 return false;
1434 }
1435